Manufacturing method of semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure, which is applied to the technical field of semiconductors. According to the method, firstly, a substrate is provided, a plurality of grooves with different opening sizes are formed in the substrate, insulating layers are formed in the grooves, and the surface, facing the substrate, of the top face of the insulating layer in at least one groove is provided with a recess; then, performing an inert ion implantation process on the insulating layer so as to change the density of the insulating layer; and finally, performing at least one planarization treatment process on the substrate. After the insulating layer is formed in the trench, the inert ion implantation process is performed on the insulating layer, so that the film of the insulating layer becomes more compact, the grinding rate of subsequent chemical mechanical grinding is reduced, and the dished recess at the top of the large-size shallow trench isolation is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure. Background Technology

[0002] With the development of large-scale integrated circuit technology, the critical dimensions of semiconductor devices are getting smaller and smaller, and the requirements for the flatness of the wafer surface are also getting higher and higher. As one of the main side effects of chemical mechanical polishing (CMP), the tolerance of advanced processes for the resulting dishing is getting lower and lower.

[0003] In advanced processes, shallow trench isolation (STI) requires higher aspect ratios, making traditional silicon oxide filling methods such as High Aspect Ratio Process (HARP) and High-Density Plasma (HDP) insufficient. Flowable Chemical Vapor Deposition (FCVD) is now necessary due to the increased fluidity of the oxide film formed by FCVD. However, the porous oxide film produced by FCVD typically requires ultraviolet cure (UV cure) and annealing to achieve a denser film and effective electrical isolation between adjacent devices, preventing leakage current. However, due to the inherent limitations of chemical mechanical polishing (CMP), severe dish-shaped depressions inevitably appear in large-area shallow trench isolation regions. (See [reference needed]). Figure 1 As shown. The presence of these dish-shaped depressions may cause leakage current in adjacent devices, thereby affecting the performance of semiconductor devices. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a semiconductor structure, which involves performing an inert ion implantation process on an insulating layer formed in trenches with different opening sizes to make the film of the insulating layer more dense, thereby reducing the polishing rate of subsequent chemical mechanical polishing and reducing the dish-shaped depressions present on the top of large-size shallow trench isolation.

[0005] To address the aforementioned technical problems, the present invention provides a method for fabricating a semiconductor structure, which may include at least the following steps:

[0006] A substrate is provided, on which a plurality of trenches with different opening sizes are formed, an insulating layer is formed in the trenches, and the top surface of the insulating layer in at least one of the trenches has a recess facing the surface of the substrate;

[0007] An inert ion implantation process is performed on the insulating layer to change the density of the insulating layer;

[0008] The substrate undergoes at least one planarization process.

[0009] Furthermore, the inert ion implantation process includes high-temperature helium ion implantation.

[0010] Furthermore, the process for forming the insulating layer includes a flowable chemical vapor deposition process.

[0011] Furthermore, the planarization process includes chemical mechanical polishing, and the substrate undergoes the chemical mechanical polishing at least twice.

[0012] Furthermore, after the insulating layer is formed in the trench, the method further includes:

[0013] Annealing is performed on the substrate.

[0014] Furthermore, the process parameters for the high-temperature helium ion implantation include: an implantation energy range of 6 keV to 10 keV, and an implantation dose range of 3 x 10. 15 ions / cm 2 ~1x10 16 ions / cm 2 The injection temperature range is 0℃~500℃.

[0015] Furthermore, the trench includes: a first trench and a second trench, wherein the opening size of the first trench in the horizontal direction is a first width, and the opening size of the second trench in the horizontal direction is a second width, wherein the first width is greater than the second width, and the surface of the top surface of the insulating layer in the first trench facing the substrate has the recess.

[0016] Furthermore, prior to forming the trench, the method also includes:

[0017] A first hard mask layer is formed on the substrate;

[0018] A second hard mask layer is formed on the first hard mask layer.

[0019] Furthermore, the material of the first hard mask layer includes silicon nitride.

[0020] Furthermore, the material of the insulating layer includes silicon oxide.

[0021] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0022] In a method for fabricating a semiconductor structure provided by the present invention, a substrate is provided, a plurality of trenches with different opening sizes are formed on the substrate, an insulating layer is formed in the trenches, and the top surface of the insulating layer in at least one of the trenches has a recess facing the surface of the substrate; an inert ion implantation process is performed on the insulating layer to change the density of the insulating layer; and at least one planarization process is performed on the substrate.

[0023] In the semiconductor device fabrication method provided by the present invention, a substrate is provided, a plurality of trenches with different opening sizes are formed on the substrate, and an insulating layer is formed in the trenches. Then, an inert ion implantation process is performed on the insulating layer to make the film of the insulating layer more dense, thereby reducing the polishing rate of subsequent chemical mechanical polishing and thus reducing the dish-shaped depressions on the top of the large-size shallow trench isolation. Attached Figure Description

[0024] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0025] Figure 1 This is a schematic diagram of a structure in the prior art where a flowable chemical vapor deposition layer is deposited, and a dish-shaped depression appears after subsequent chemical mechanical polishing.

[0026] Figure 2 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0027] Figures 3a to 3d This is a schematic diagram of the fabrication process of a semiconductor structure fabrication method provided in one embodiment of the present invention.

[0028] The specific reference numerals in the attached figures are as follows:

[0029] 100 - Substrate; 101 - Oxide layer; 102 - First hard mask layer; 103 - Second hard mask layer; 104 - Barrier layer; 105 - Insulating layer; 106 - Trench; 106a - First trench; 106b - Second trench.

[0030] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0031] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0032] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and are only used to facilitate and clarify the illustration of the embodiments of the invention. It is understood that the terms "on," "above," and "over" in this invention should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer. In the embodiments of the invention, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the invention can be arbitrarily combined without conflict.

[0033] As described in the background section, when fabricating shallow trench isolation in advanced processes, flowable chemical vapor deposition with higher fluidity is required to fill the trenches. However, due to the limitations of chemical mechanical polishing (CMP) itself, severe dish-shaped depressions may appear in large-sized shallow trench isolation areas. The presence of these dish-shaped depressions may lead to leakage current in adjacent devices, thereby affecting the performance of semiconductor devices.

[0034] To address the above problems, the present invention proposes an improved solution, namely, by providing a substrate, forming multiple trenches with different opening sizes on the substrate, and then forming an insulating layer in the trenches, performing an inert ion implantation process on the insulating layer to make the film of the insulating layer more dense, reducing the grinding rate of subsequent chemical mechanical polishing, thereby reducing the dish-shaped depressions on the top of the large-size shallow trench isolation.

[0035] refer to Figure 2 As shown, Figure 2 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention; wherein, the method for fabricating the semiconductor structure may include the following steps:

[0036] Step S201: A substrate is provided, and a plurality of trenches with different opening sizes are formed on the substrate. An insulating layer is formed in the trenches, and the top surface of the insulating layer in at least one of the trenches has a recess facing the surface of the substrate.

[0037] Step S202: Perform an inert ion implantation process on the insulating layer to change the density of the insulating layer;

[0038] Step S203: Perform a first chemical mechanical polishing on the substrate;

[0039] Step S204: Perform a second chemical mechanical polishing on the substrate.

[0040] The method for fabricating the semiconductor structure proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention can also be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0041] See Figure 3a In step S201 above, a substrate 100 is first provided. The substrate 100 can be any suitable substrate material known in the art, such as at least one of the following: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors. It also includes multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Alternatively, it can be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz substrate, or a glass substrate. For example, in this embodiment, the substrate 100 is, for example, a silicon wafer.

[0042] Next, an oxide layer 101 is formed on the substrate 100 by thermal oxidation, and then a first hard mask layer 102 is formed on the oxide layer 101 by chemical vapor deposition. Then, a second hard mask layer 103 is formed on the first hard mask layer 102 by chemical vapor deposition. The material of the first hard mask layer 102 includes silicon nitride.

[0043] Then, the second hard mask layer 103, the first hard mask layer 102, the oxide layer 101, and the substrate 100 are sequentially etched by wet etching to form a plurality of trenches 106 with different opening sizes along a direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction). For example, the trenches 106 may include: a first trench 106a and a second trench 106b arranged at intervals along the horizontal direction, wherein the opening size of the first trench 106a in the horizontal direction is a first width, and the opening size of the second trench 106b in the horizontal direction is a second width, and the first width is greater than the second width. Next, a barrier layer 104 is formed on the substrate 100 by atomic layer deposition to cover the bottom and sidewalls of the trenches 106, the sidewalls of the oxide layer 101, the sidewalls of the first hard mask layer 102, and the sidewalls and top surface of the second hard mask layer 103.

[0044] Next, an insulating layer 105 is formed on the substrate 100 using a flowable chemical vapor deposition process to fill the trench 106. Because the gas diffusion efficiency inside the large trench (i.e., the first trench 106a) is significantly reduced, the concentration gradient of reactive gases (such as silane and oxygen) increases in the central region of the trench, for example, the first trench 106a. This uneven distribution causes a decrease in the deposition rate in the central region, resulting in a thinner insulating layer. Therefore, the top surface of the insulating layer 105 within the first trench 106a is recessed downwards towards the surface of the substrate 100. The material of the insulating layer 105 includes silicon oxide. The substrate 100 is then subjected to an annealing process.

[0045] See Figure 3b In step S202 above, an inert ion implantation process is performed on the insulating layer 105. This is because when high-energy inert ions are implanted into the insulating layer, they collide violently with lattice atoms, generating a cascade collision effect. This process breaks the silicon-oxygen bonds in the insulating layer, locally forming an amorphous structure and disrupting the original loose lattice arrangement. The vacancies generated by ion collisions migrate and accumulate during subsequent annealing, while the collisions and compression force interstitial atoms to fill the lattice gaps. This reconstruction significantly reduces the micropore density, resulting in a volume shrinkage rate of 5-8% for the insulating layer. During ion implantation, approximately 90% of the energy is converted into localized heat energy through electron blocking ability, causing the temperature at the impact point to rise instantaneously to 800-1000℃. This temperature far exceeds the glass transition temperature of the insulating layer, triggering local atomic rearrangement and forming a short-range ordered dense network. The inert ions remaining in the lattice gaps generate compressive stress, forcing the interatomic spacing between adjacent atoms to shorten by approximately... The density is directly increased by 3-5%, thus significantly improving the density of the insulating layer 105 after inert ion implantation. The inert ion implantation process includes high-temperature helium ion implantation. The process parameters for high-temperature helium ion implantation include: implantation energy range of 6keV to 10keV, and implantation dose range of 3 x 10. 15 ions / cm 2 ~1x10 16 ions / cm 2 The injection temperature range is 0℃ to 500℃. The higher the injection energy, the lower the subsequent chemical mechanical polishing (CMP) rate; that is, the subsequent CMP rate is inversely proportional to the injection energy. Similarly, the higher the injection dose, the lower the subsequent CMP rate; that is, the subsequent CMP rate is inversely proportional to the injection dose. The substrate 100 is then subjected to annealing.

[0046] See Figure 3c In step S203 above, the substrate 100 is subjected to a first chemical mechanical polishing, with priority given to polishing the insulating layer 105 on the raised portion.

[0047] See Figure 3d In step S204 above, a second chemical mechanical polishing is performed on the substrate 100, which stops at the first hard mask layer 102. Because the insulating layer 105 becomes denser, and the microhardness of a high-density insulating layer can be increased by 20%-40%, polishing particles are more difficult to embed into the surface, significantly reducing mechanical wear efficiency. Densification also reduces the number of grain boundaries and micropores, weakening the fragility of stress concentration points. Densification reduces surface roughness, decreases the actual contact area between the polishing pad and the wafer, and results in a more uniform local pressure distribution, reducing the depth of mechanical scraping. The dense structure hinders the penetration of the active components of the polishing slurry into the material interior. The dense surface is more likely to form a uniform passivation layer, which resists further corrosion from the polishing slurry. Therefore, the polishing rate of the chemical mechanical polishing is reduced, resulting in a decrease in the amount of polishing in the large-size shallow trench isolation area and a reduction in the size of the dish-shaped depression.

[0048] It is understood that in this embodiment, the substrate 100 is subjected to two chemical mechanical polishing processes, but in other embodiments, the number of chemical mechanical polishing processes may be increased or the substrate 100 may be subjected to at least one other planarization process.

[0049] In summary, in the semiconductor structure fabrication method provided by the present invention, a substrate is provided, a plurality of trenches with different opening sizes are formed on the substrate, an insulating layer is formed in the trenches, and the top surface of the insulating layer in at least one of the trenches has a recess facing the surface of the substrate; an inert ion implantation process is performed on the insulating layer to change the density of the insulating layer; and at least one planarization process is performed on the substrate.

[0050] In the semiconductor device fabrication method provided by the present invention, a substrate is provided, a plurality of trenches with different opening sizes are formed on the substrate, and an insulating layer is formed in the trenches. Then, an inert ion implantation process is performed on the insulating layer to make the film of the insulating layer more dense, thereby reducing the polishing rate of subsequent chemical mechanical polishing and thus reducing the dish-shaped depressions on the top of the large-size shallow trench isolation.

[0051] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, on which a plurality of trenches with different opening sizes are formed, an insulating layer is formed in the trenches, and the top surface of the insulating layer in at least one of the trenches has a recess facing the surface of the substrate; An inert ion implantation process is performed on the insulating layer to change the density of the insulating layer; The substrate undergoes at least one planarization process.

2. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The inert ion implantation process includes high-temperature helium ion implantation.

3. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The process for forming the insulating layer includes a flowable chemical vapor deposition process.

4. The method for fabricating a semiconductor structure as described in claim 3, characterized in that, The planarization process includes chemical mechanical polishing, and the substrate undergoes the chemical mechanical polishing at least twice.

5. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, After the insulating layer is formed in the trench, the method further includes: Annealing is performed on the substrate.

6. The method for fabricating a semiconductor structure as described in claim 2, characterized in that, The process parameters for the high-temperature helium ion implantation include: an implantation energy range of 6 keV to 10 keV, and an implantation dose range of 3 x 10. 15 ions / cm 2 ~1x10 16 ions / cm 2 The injection temperature range is 0℃~500℃.

7. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The trench includes a first trench and a second trench. The first trench has a first width in the horizontal direction, and the second trench has a second width in the horizontal direction. The first width is greater than the second width, and the surface of the top surface of the insulating layer in the first trench facing the substrate has the recess.

8. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, Before forming the trench, the method further includes: A first hard mask layer is formed on the substrate; A second hard mask layer is formed on the first hard mask layer.

9. The method for fabricating a semiconductor structure as described in claim 8, characterized in that, The material of the first hard mask layer includes silicon nitride.

10. The method for fabricating a semiconductor structure as described in claim 1, wherein the material of the insulating layer comprises silicon oxide.

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