Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the following steps: providing a substrate; forming a substrate oxide layer on the substrate, and forming a first nitride layer on the substrate oxide layer; etching a part of the first nitride layer and the substrate oxide layer, exposing the surface of the substrate, and forming a first groove; forming a second nitride layer on the groove wall of the first groove and the first nitride layer; etching the second nitride layer on the surface of the substrate and the second nitride layer on the first nitride layer to expose the surface of the substrate and the surface of the first nitride layer, and etching the substrate to form a shallow trench; filling the shallow trench and the first trench to form a shallow trench isolation structure; removing part of the first nitride layer and the second nitride layer in sequence to expose the surface of the shallow trench isolation structure; forming a protective layer on the exposed surface of the shallow trench isolation structure; and sequentially removing the first nitride layer, the substrate oxide layer and the protective layer. The leakage current probability of the device can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Technology

[0002] Shallow trench isolation (STI) is widely used in submicron-level semiconductor processes. STI reduces the area of ​​the isolation region, providing minimal active area intrusion and a flatter surface. However, due to localized stress concentration, the oxide layer in the STI corner region is over-etched during substrate oxide etching, resulting in lateral erosion. Consequently, when the substrate oxide is stripped, the oxide layer in the STI corner region is inadvertently removed preferentially from the trench corner, forming a recessed structure (as shown in the attached figure). Figure 11 (As shown). During the formation of the gate structure, the presence of the recessed structure can lead to overfilling of the polysilicon, resulting in parasitic transistors. The presence of parasitic transistors increases the probability of leakage current in the device. Summary of the Invention

[0003] The purpose of this invention is to provide a method for manufacturing a semiconductor structure and a semiconductor structure, so as to improve the manufacturing yield of shallow trench isolation structures and thereby reduce the probability of leakage current in the device.

[0004] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution: This invention provides a method for manufacturing a semiconductor structure, comprising the following steps: Provide a substrate; A substrate oxide layer is formed on the substrate, and a first nitride layer is formed on the substrate oxide layer; The first nitride layer and the substrate oxide layer are etched to expose the substrate surface and form a first trench; A second nitriding layer is formed on the trench wall of the first trench and on the first nitriding layer; The second nitride layer located on the substrate surface and the second nitride layer located on the first nitride layer are etched to expose the surface of the substrate and the surface of the first nitride layer, and the substrate is etched to form a shallow trench; Fill the shallow trench and the first trench to form a shallow trench isolation structure; Sequentially remove a portion of the first nitrided layer, then remove the second nitrided layer to expose the surface of the shallow trench isolation structure; A protective layer is formed on the exposed surface of the shallow trench isolation structure, wherein the protective layer has amine groups; and The first nitride layer, the substrate oxide layer, and the protective layer are removed sequentially.

[0005] In one embodiment of the present invention, in the step of forming the shallow trench isolation structure, the first trench is filled to form the step portion of the shallow trench isolation structure, and the material of the shallow trench isolation structure is further deposited to form a filling layer on the first nitrided layer and the second nitrided layer.

[0006] In one embodiment of the present invention, before removing the first nitrided layer, the filler layer is removed by grinding until the stepped portion reaches a preset height.

[0007] In one embodiment of the present invention, in the step of removing the second nitride layer, the second nitride layer is wet-etched to form a second trench between the step portion and the substrate oxide layer, exposing the surface of the step portion and the surface of the substrate.

[0008] In one embodiment of the present invention, in the step of forming a protective layer, a reaction layer is formed on the surface of the step portion, and the reaction layer is treated with an organic solvent under a heating environment to form the protective layer.

[0009] In one embodiment of the present invention, the etching solution for removing the first nitride layer is a phosphoric acid solution, the etching solution for removing the substrate oxide layer is a hydrofluoric acid solution, and the etching solution for removing the protective layer is a mixed solution of sulfuric acid and hydrogen peroxide.

[0010] In one embodiment of the present invention, before removing the second nitride layer, a portion of the first nitride layer is removed by wet etching, wherein the etching ratio of the first nitride layer is 50% to 99%.

[0011] In one embodiment of the present invention, the second nitride layer is titanium nitride, and the thickness of the second nitride layer is 5 angstroms to 200 angstroms.

[0012] This invention provides a semiconductor structure, comprising: Substrate; A substrate oxide layer is disposed on the substrate; A first nitride layer is disposed on the substrate oxide layer; A shallow trench isolation structure, wherein a portion of the shallow trench isolation structure is disposed in the substrate, and a portion of the shallow trench isolation structure is located on the substrate; A protective layer covering the exposed surface of the shallow trench isolation structure, wherein the protective layer contains amine groups; and A second trench passes through the substrate oxide layer and the first nitride layer and connects to the surface of the substrate, wherein the second trench is adjacent to the shallow trench isolation structure.

[0013] In one embodiment of the present invention, the shallow trench isolation structure includes a stepped portion located on the substrate, wherein the protective layer covers the surface of the stepped portion.

[0014] As described above, the present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure. Its unexpected technical effect lies in the ability to form a shallow trench isolation structure with a complete surface, avoiding the formation of any depressions on the shallow trench isolation structure or the substrate surface during the shallow trench isolation structure formation process. This improves the molding yield of semiconductor devices in subsequent semiconductor processes and reduces the probability of leakage current in semiconductor devices. The method for manufacturing a semiconductor structure and the semiconductor structure provided by the present invention are particularly suitable for submicron processes and below, and can significantly improve semiconductor process yield.

[0015] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure forming a substrate oxide layer, a first nitride layer, and a photoresist pattern in one embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of the structure forming the first trench in one embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of the structure for forming the second nitride layer in one embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of the structure forming a shallow trench in one embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of the structure forming the filling layer in one embodiment of the present invention.

[0022] Figure 6 This is a schematic diagram of a structure in one embodiment of the present invention with part of the filler layer and part of the first nitriding layer removed.

[0023] Figure 7 This is a schematic diagram of the structure forming the second trench in one embodiment of the present invention.

[0024] Figure 8This is a schematic diagram of the structure forming the protective layer in one embodiment of the present invention.

[0025] Figure 9 This is a schematic diagram of the structure in one embodiment of the present invention after removing the first nitride layer, the substrate oxide layer and the protective layer.

[0026] Figure 10 This is a schematic diagram of a shallow trench isolation structure in one embodiment of the present invention.

[0027] Figure 11 This is an electron microscope image of a shallow trench isolation structure with a recessed structure due to excessive etching in one embodiment of the present invention.

[0028] Figure 12 This is a schematic diagram of a planar structure forming a protective layer in one embodiment of the present invention.

[0029] Figure 13 This is a schematic diagram illustrating the principle of fluoride ion adsorption in the protective layer in one embodiment of the present invention.

[0030] In the figure: 100, substrate; 101, first trench; 102, second nitride layer; 103, shallow trench; 104, filling layer; 105, shallow trench isolation structure; 1051, step portion; 106, second trench; 200, substrate oxide layer; 300, first nitride layer; 400, photoresist pattern; 500, protective layer; 600, recessed structure. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] This invention provides a semiconductor structure and a method for manufacturing the same, wherein the semiconductor structure is a structure for forming a semiconductor device. The semiconductor device can be one or more of the following: Field Effect Transistor (FET), Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), Complementary Metal-Oxide Semiconductor (CMOS), Insulated Gate Bipolar Transistor (IGBT), Fast Recovery Diode (FRD), High Efficiency Diode (HED), Constant Voltage Diode, High Frequency Diode, Light-Emitting Diode (LED), Gate Turn-off Thyristor (GTO), Light Triggered Thyristor (LTT), Thyristor, Charge Coupled Device (CCD image sensor), Digital Signal Processor (DSP), Photo Relay, or Micro Processor.

[0033] Please see Figure 1 As shown, in the semiconductor structure manufacturing method provided by the present invention, a substrate 100 is first provided. In this embodiment, substrate 100 may also refer to a wafer used in semiconductor processing. Furthermore, substrate 100 may include doped and undoped semiconductor or epitaxial semiconductor layers, which may be supported by a substrate of semiconductor or insulating material and other semiconductor structures known to those skilled in the art. Additionally, the term conductor may include semiconductor. Specifically, substrate 100 is, for example, a silicon substrate forming a semiconductor structure. Substrate 100 may include a substrate and a silicon layer disposed on the substrate. The substrate may be, for example, a semiconductor substrate material such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc., and the silicon layer is formed on the substrate.

[0034] Please see Figure 1As shown, in one embodiment of the present invention, a substrate oxide layer 200 is formed on a substrate 100, and a first nitride layer 300 is formed on the substrate oxide layer 200. In this embodiment, silicon oxide is deposited on the substrate 100 by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) to form the substrate oxide layer 200. The present invention does not limit the thickness of the substrate oxide layer 200. Next, silicon nitride material is deposited on the substrate oxide layer 200 by chemical vapor deposition or plasma-enhanced chemical vapor deposition to form the first nitride layer 300. The present invention does not limit the thickness of the first nitride layer 300. In this embodiment, the thickness of the first nitride layer 300 is greater than the thickness of the substrate oxide layer 200. In this embodiment, after the formation of the first nitride layer 300, a photoresist pattern 400 is formed on the first nitride layer 300. Specifically, photoresist is spin-coated onto the first nitride layer 300 to form a photoresist layer, and the photoresist layer is patterned by means of exposure etching to form a photoresist pattern 400. The photoresist pattern 400 is used to help define the maximum width of the shallow trench.

[0035] Please see Figures 1 to 3 As shown, in one embodiment of the present invention, after forming the first nitride layer 300, the first nitride layer 300 and the substrate oxide layer 200 are etched using a photoresist pattern 400 as a mask to expose the surface of the substrate 100 and form a first trench 101. Then, a second nitride layer 102 is formed on the trench walls of the first trench 101 and on the first nitride layer 300. In this embodiment, the first nitride layer 300 and the substrate oxide layer 200 are removed sequentially using dry etching until the surface of the substrate 100 is exposed. The first trench 101 penetrates the first nitride layer 300 and the substrate oxide layer 200 and connects to the surface of the substrate 100. Then, titanium nitride is deposited on the first trench 101 and the first nitride layer 300 by chemical vapor deposition or plasma-enhanced chemical vapor deposition to form the second nitride layer 102. At this time, the second nitride layer 102 covers the sidewalls and bottom walls of the first trench 101 and the top surface of the first nitride layer 300. In this embodiment, the thickness of the second nitride layer 102 is 5~200 angstroms. Specifically, after forming the first trench 101 and before forming the second nitride layer 102, the photoresist pattern 400 is removed by an ashing process.

[0036] Please see Figure 3 and Figure 4As shown, in one embodiment of the present invention, after forming the first trench 101, the second nitride layer 102 located on the first nitride layer 300 and the second nitride layer 102 covering the surface of the substrate 100 are etched away, and a portion of the substrate 100 is etched away to form a shallow trench 103. In this etching step, the bottom of the first trench 101 is deepened, and the original first trench 101 is converted into a through-hole structure. In this embodiment, the second nitride layer 102 and a portion of the substrate 100 are removed by dry etching, and the formed shallow trench 103 is connected to the first trench 101, and the shallow trench 103 is located at the bottom of the first trench 101. In this embodiment, the second nitride layer 102 located on the hole wall of the first trench 101 is retained. Figure 3 and Figure 4 As shown, the first trench 101 shown in this invention has a rectangular cross-section, and under the action of the second nitriding layer 102, it can maintain the surface flatness of the first nitriding layer 300.

[0037] Please see Figure 4 and Figure 5As shown, in one embodiment of the present invention, after forming the shallow trench 103, a shallow trench isolation structure 105 is formed in the first trench 101 and the shallow trench 103, and a filling layer 104 is formed on the second nitride layer 102 and the first nitride layer 300. In this embodiment, the shallow trench 103 and the first trench 101 are sequentially filled by chemical vapor deposition or plasma-enhanced chemical vapor deposition until both the shallow trench 103 and the first trench 101 are filled, forming the shallow trench isolation structure 105. After filling the shallow trench 103, the first trench 101 is continued to be filled, thereby forming a stepped portion 1051 of the shallow trench isolation structure 105. The stepped portion 1051 is the part of the shallow trench isolation structure 105 that is higher than the substrate 100. The portion of the shallow trench isolation structure 105 filled in the shallow trench 103 can be used to isolate the active region in the substrate 100, thereby forming multiple well structures in the substrate 100. After filling the first trench 101, deposition continues to form a thin film structure on the second nitride layer 102 and the first nitride layer 300, thereby forming a filling layer 104. The materials of the shallow trench isolation structure 105 and the filling layer 104 are, for example, tetraethyl orthosilicate (TEOS). It should be noted that the shallow trench isolation structure 105 and the fill layer 104 can also be formed from a material including silicon oxide, silicon dioxide, carbon-doped silicon dioxide, nitrogen-doped silicon dioxide, germanium-doped silicon dioxide, or phosphorus-doped silicon dioxide. The shallow trench isolation structure 105 and the fill layer 104 can be conformally deposited using atmospheric chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sub-atmospheric chemical vapor deposition (SACVD), high-density plasma chemical vapor deposition (HDPCVD), and photo-induced chemical vapor deposition (PDCVD). Those skilled in the art will understand that other insulating materials can also be deposited on the shallow trench 103 and the first trench 101 to achieve the goal of electrically isolating the respective component regions. Furthermore, other known methods can also be used to deposit and form the shallow trench isolation structure 105 and the fill layer 104, as understood by those skilled in the art.

[0038] Please see Figure 5 and Figure 6As shown, in one embodiment of the present invention, after forming the shallow trench isolation structure 105 and the filling layer 104, the filling layer 104 and a portion of the first nitride layer 300 are removed. In this embodiment, after forming the filling layer 104, using the second nitride layer 102 and the first nitride layer 300 as etching stop layers, the filling layer 104 located on the second nitride layer 102 and the first nitride layer 300 is ground by chemical mechanical polishing (CMP), thereby exposing the surfaces of the second nitride layer 102 and the first nitride layer 300. Then, a portion of the first nitride layer 300 is removed by wet etching. In this embodiment, for example, 50% to 99% of the first nitride layer 300 is removed. Specifically, the etching solution used in the wet etching can be a phosphoric acid solution. In this embodiment, during the chemical mechanical polishing process, etching can be stopped when the height of the step portion 1051 reaches a preset height H. The preset height H is set by the designer. During the chemical mechanical polishing (CMP) process, the height of the step portion 1051 can be observed to ensure that the step portion 1051 of the shallow trench isolation structure 105 meets the process requirements at the end of the CMP step, thus avoiding defects. In other embodiments of the present invention, when depositing the first nitride layer 300, the total thickness of the first nitride layer 300 and the substrate oxide layer 200 can be greater than a preset height H, thereby leaving adjustment margin for the shallow trench isolation structure 105 in subsequent processes. In this etching step, most of the first nitride layer 300 is removed first. This protects the surface flatness of the substrate oxide layer 200 and also facilitates the removal of the substrate oxide layer 200 in subsequent processes, allowing for removal as quickly as possible without damaging the shallow trench isolation structure 105.

[0039] Please see Figure 6 and Figure 7 As shown, in one embodiment of the present invention, after removing a portion of the first nitride layer 300, the second nitride layer 102 is removed, exposing a portion of the surface of the substrate 100 and forming a second trench 106. In this embodiment, the second nitride layer 102 is removed by wet etching, wherein the etching solution is a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). The substrate oxide layer 200 and the first nitride layer 300 are connected to form a stacked structure. The second trench 106 is located between the step portion 1051 and the stacked structure, and the second trench 106 has the surface of the substrate 100 as its bottom. The width of the second trench 106 is greater than the critical dimension of the semiconductor structure. The present invention does not limit the specific width of the second trench 106. After removing the second nitride layer 102, space is left for the formation of the protective layer 500 in subsequent processes, so that the protective layer 500 can be completely attached to the surface of the step portion 1051.

[0040] Please see Figure 7 and Figure 8, Figure 12 and Figure 13 As shown, in one embodiment of the present invention, after forming the second trench 106, the surface of the step portion 1051 is treated to form a protective layer 500 on the surface of the step portion 1051. In this embodiment, a reactive layer, such as a chitosan layer, is attached to the surface of the step portion 1051. The chitosan layer is heated and treated in an organic solvent environment at a temperature of, for example, 50°C to 200°C, thereby modifying the chitosan layer and forming the protective layer 500 on the surface of the step portion 1051. The protective layer 500 is a nanocomposite material. Figure 12 As shown, silicon dioxide is linked to the amino groups of chitosan, thereby forming a protective layer 500 on the exposed surface of the step portion 1051. In this embodiment, the organic solvent can be any one of toluene, acetone, and N-methylpyrrolidone, or any mixture of multiple solvents. Since the surface of the step portion 1051 has more -OH groups than the surface of the substrate oxide layer 200, the protective layer 500 is preferentially formed on the surface of the step portion 1051. It should be noted that due to the etching solutions such as phosphoric acid and hydrofluoric acid, the step portion 1051 is under acidic conditions, causing the free amino groups in the chitosan structure to protonate, resulting in a positively charged substance, namely -NH3, appearing on the surface of the nanocomposite material. + .like Figure 13 As shown, under the action of electrostatic adsorption, -NH3 + It can attract F- ions and reduce the etching effect of F- ions on the connection between the step portion 1051 and the substrate 100, thereby protecting the shallow trench isolation structure 105 from excessive etching.

[0041] Please see Figures 8 to 10 As shown, in one embodiment of the present invention, the first nitride layer 300, the substrate oxide layer 200, and the protective layer 500 are removed sequentially. In this embodiment, phosphoric acid is used to remove the residual first nitride layer 300 on the surface of the substrate oxide layer 200. Then, hydrofluoric acid is used to remove the substrate oxide layer 200. Under the protection of the protective layer 500, the corners of the shallow trench isolation structure 105 connecting to the substrate 100 will not experience over-etching. The corners of the shallow trench isolation structure 105 connecting to the substrate 100 are... Figure 9 and Figure 10 The circled area. Next, the protective layer 500 is removed using sulfuric acid and hydrogen peroxide, exposing the surface of the stepped portion 1051, thus forming a shallow groove isolation structure 105 with a complete surface. In this embodiment, the chitosan-modified layer is removed using sulfuric acid and hydrogen peroxide, thereby removing the protective layer 500.

[0042] Please see Figure 10 and Figure 11 As shown, Figure 11 Electron micrograph of the corner of the shallow trench isolation structure 105 showing excessive etching. Figure 10This is a corner structure diagram of the shallow trench isolation structure 105 obtained under the control method provided by the present invention. (See diagram below.) Figure 11 As shown, when an over-etched recessed structure 600 appears at the corner of the shallow trench isolation structure 105, this recessed structure 600 will continue during the formation process of the gate structure and even the formation process of the metal interconnect structure, when depositing the dielectric layer, polysilicon layer, and metal layer. To fill the recessed structure 600, excess polysilicon material or metal material will be added, resulting in parasitic device structures in the original device structure. The shallow trench isolation structure 105 provided by the present invention not only avoids the formation of the recessed structure 600, thereby improving the integrity of the shallow trench isolation structure 105, but also avoids the appearance of parasitic devices that are not required by the design in the semiconductor device, thereby reducing the possibility of leakage current in the device, thus improving the chip manufacturing yield and the wafer yield on a single wafer.

[0043] This invention provides a method for manufacturing a semiconductor structure and the semiconductor structure itself. The method for manufacturing the semiconductor structure includes the following steps: providing a substrate; forming a substrate oxide layer on the substrate and forming a first nitride layer on the substrate oxide layer; etching a portion of the first nitride layer and the substrate oxide layer to expose the substrate surface and form a first trench; forming a second nitride layer on the trench walls and on the first nitride layer; etching the second nitride layer located on the substrate surface and on the first nitride layer to expose the substrate surface and the surface of the first nitride layer, and etching the substrate to form a shallow trench; filling the shallow trench and the first trench to form a shallow trench isolation structure; sequentially removing a portion of the first nitride layer and then removing the second nitride layer to expose the surface of the shallow trench isolation structure; forming a protective layer on the exposed surface of the shallow trench isolation structure; and sequentially removing the first nitride layer, the substrate oxide layer, and the protective layer. The semiconductor structure manufacturing method and semiconductor structure provided by the present invention have the following unexpected technical effects: The present invention can form a shallow trench isolation structure with a complete surface, avoiding the formation of any recessed structure on the shallow trench isolation structure or the substrate surface during the shallow trench isolation structure formation process. This is beneficial to improving the forming yield of semiconductor devices in subsequent semiconductor processes and reducing the probability of leakage current in semiconductor devices. The semiconductor structure manufacturing method and semiconductor structure provided by the present invention are particularly suitable for semiconductor processes at and below the submicron level and can significantly improve semiconductor process yield.

[0044] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: Provide a substrate; A substrate oxide layer is formed on the substrate, and a first nitride layer is formed on the substrate oxide layer; The first nitride layer and the substrate oxide layer are etched to expose the substrate surface and form a first trench; A second nitriding layer is formed on the trench wall of the first trench and on the first nitriding layer; The second nitride layer located on the substrate surface and the second nitride layer located on the first nitride layer are etched to expose the surface of the substrate and the surface of the first nitride layer, and the substrate is etched to form a shallow trench; Fill the shallow trench and the first trench to form a shallow trench isolation structure; Sequentially remove a portion of the first nitrided layer, then remove the second nitrided layer to expose the surface of the shallow trench isolation structure; A protective layer is formed on the exposed surface of the shallow trench isolation structure, wherein the protective layer has amine groups; as well as The first nitride layer, the substrate oxide layer, and the protective layer are removed sequentially.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, In the step of forming the shallow trench isolation structure, the first trench is filled to form the stepped portion of the shallow trench isolation structure, and the material of the shallow trench isolation structure is deposited to form a filling layer on the first nitrided layer and the second nitrided layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, Before removing the first nitrided layer, the filler layer is ground off until the stepped portion reaches a preset height.

4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, In the step of removing the second nitride layer, the second nitride layer is wet-etched to form a second trench between the step portion and the substrate oxide layer, exposing the surface of the step portion and the surface of the substrate.

5. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, In the step of forming the protective layer, a reaction layer is formed on the surface of the step portion, and the reaction layer is treated with an organic solvent under a heating environment to form the protective layer.

6. A method for manufacturing a semiconductor structure according to claim 1 ， Its features are, The etching solution for removing the first nitride layer is a phosphoric acid solution, the etching solution for removing the substrate oxide layer is a hydrofluoric acid solution, and the etching solution for removing the protective layer is a mixed solution of sulfuric acid and hydrogen peroxide.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Before removing the second nitride layer, a portion of the first nitride layer is removed by wet etching, wherein the etching ratio of the first nitride layer is 50% to 99%.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The second nitride layer is titanium nitride, and the thickness of the second nitride layer is 5 angstroms to 200 angstroms.

9. A semiconductor structure, characterized in that, include: Substrate; A substrate oxide layer is disposed on the substrate; A first nitride layer is disposed on the substrate oxide layer; A shallow trench isolation structure, wherein a portion of the shallow trench isolation structure is disposed in the substrate, and a portion of the shallow trench isolation structure is located on the substrate; A protective layer covering the exposed surface of the shallow trench isolation structure, wherein the protective layer has amine groups; as well as A second trench passes through the substrate oxide layer and the first nitride layer and connects to the surface of the substrate, wherein the second trench is adjacent to the shallow trench isolation structure.

10. A semiconductor structure according to claim 9, characterized in that, The shallow trench isolation structure includes a stepped portion located on the substrate, wherein the protective layer covers the surface of the stepped portion.

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