Formation method of semiconductor structure, semiconductor structure and electronic equipment

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure forming method, a semiconductor structure and electronic equipment, and the forming method comprises the steps: providing a to-be-etched layer; forming a first patterned structure on the first process region, and forming a second patterned structure on the second process region; forming a first side wall structure on the side wall of the first graphical structure, and forming a second side wall structure on the side wall of the second graphical structure; the thickness of the formed first side wall structure is different from that of the second side wall structure; etching the to-be-etched layer by taking the first side wall structure and the second side wall structure which are different in thickness as masks, forming a first groove in the first process region, and forming a second groove in the second process region; forming a first conductive layer in the first groove, and forming a second conductive layer in the second groove; the width of the first conductive layer is different from that of the second conductive layer. According to the embodiment of the invention, the differentiated design of the sizes of the conducting layers of different functional modules can be realized.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. Background Technology

[0002] In semiconductor manufacturing, back-end design is crucial for standard cell libraries. Ideally, metal lines and corresponding via sizes can be designed differently based on the requirements of different functional modules. To achieve smaller metal critical dimensions (metal CD), related technologies often utilize spacer-assisted processes, such as Self-aligned Dual Imaging Technique (SADP) and Self-aligned Quadruple Patterning Technique (SAQP). Figure 1 This is a flowchart illustrating SAQP in related technologies, such as... Figure 1 As shown, SAQP produces metalCDs with dimensions much smaller than the limits of photolithography machines through two mandrel / spacer cycles.

[0003] However, the metal CD defined by the relevant technology is consistent across all regions (e.g., Figure 1 As shown, the size of the metal CD is S1 in all regions, which makes it impossible to differentiate the metal wire size for different functional modules. Summary of the Invention

[0004] This application provides a method for forming a semiconductor structure, a semiconductor structure, and an electronic device to at least solve the aforementioned problems existing in the related art.

[0005] To solve the above-mentioned technical problems, the technical solution of this application is as follows:

[0006] According to a first aspect of the embodiments of this application, a method for forming a semiconductor structure is provided, the method comprising:

[0007] A layer to be etched is provided; the layer to be etched includes a first process region and a second process region; the first process region and the second process region have different design requirements for the conductive layer width;

[0008] A first patterned structure is formed on the first process area, and a second patterned structure is formed on the second process area;

[0009] A first sidewall structure is formed on the sidewall of the first patterned structure, and the first patterned structure is removed; a second sidewall structure is formed on the sidewall of the second patterned structure, and the second patterned structure is removed; the thickness of the first sidewall structure and the thickness of the second sidewall structure are different.

[0010] The layer to be etched is etched using a first sidewall structure and a second sidewall structure with different thicknesses as masks, forming a first trench in the first process area and a second trench in the second process area; the width of the first trench is different from the width of the second trench.

[0011] A first conductive layer is formed in the first trench, and a second conductive layer is formed in the second trench; the width of the first conductive layer is different from the width of the second conductive layer.

[0012] In an optional embodiment, the steps of forming a first sidewall structure on the sidewall of the first patterned structure and removing the first patterned structure, and forming a second sidewall structure on the sidewall of the second patterned structure and removing the second patterned structure, include:

[0013] A first sidewall structure is formed on the sidewall of the first patterned structure, and the first patterned structure is removed; a second sidewall structure is formed on the sidewall of the second patterned structure, and the second patterned structure is removed; the thickness of the first sidewall is the same as the thickness of the second sidewall.

[0014] After removing the second graphical structure, the method further includes:

[0015] The thickness of the first sidewall structure is adjusted so that the thickness of the first sidewall structure is less than the thickness of the second sidewall structure, so that the thickness of the first sidewall structure is different from the thickness of the second sidewall structure.

[0016] In an optional embodiment, the etching of the layer to be etched using a first sidewall structure and a second sidewall structure of different thicknesses as masks, forming a first trench in the first process area, and forming a second trench in the second process area, includes:

[0017] Using the modified first sidewall structure and the second sidewall structure as masks, the layer to be etched is etched, forming a first trench in the first process area and a second trench in the second process area; the width of the first trench is smaller than the width of the second trench.

[0018] In an optional embodiment, forming a first conductive layer in the first trench and forming a second conductive layer in the second trench includes:

[0019] A first conductive layer is formed in the first trench, and a second conductive layer is formed in the second trench; the width of the first conductive layer is smaller than the width of the second conductive layer.

[0020] In an optional embodiment, the trimming process includes etching, and the trimming process for the thickness of the first sidewall structure includes:

[0021] The first sidewall structure is subjected to anisotropic etching.

[0022] In an optional embodiment, the anisotropic etching process on the first sidewall structure includes:

[0023] The two sides of the first sidewall structure are simultaneously etched to reduce the thickness of the two sides of the first sidewall structure by a preset thickness.

[0024] Wherein, the difference between the thickness of the second sidewall structure and the thickness of the first sidewall structure after the trimming is a preset number of times the preset thickness, the width of the first conductive layer is the same as the thickness of the first sidewall structure after the trimming, and the width of the second conductive layer is the same as the thickness of the second sidewall structure.

[0025] In an optional embodiment, the layer to be etched includes a substrate, the substrate comprising, from bottom to top, an interlayer dielectric layer, a second mask layer, a core sacrificial layer, and a first mask layer; the forming of a first patterned structure on the first process region and a second patterned structure on the second process region includes:

[0026] Graphicalize the first mask layer;

[0027] Using the patterned first mask layer as a mask, the core sacrificial layer is etched to form the first patterned structure in the first process area and the second patterned structure in the second process area.

[0028] In an optional embodiment, the steps of forming a first sidewall structure on the sidewall of the first patterned structure and removing the first patterned structure, and forming a second sidewall structure on the sidewall of the second patterned structure and removing the second patterned structure, include:

[0029] Remove the first mask layer;

[0030] A sidewall material layer is deposited on the sidewall and top surface of the first patterned structure, the sidewall material layer on the top surface of the first patterned structure is etched back to form the first sidewall structure, and the first patterned structure is removed; and a sidewall material layer is deposited on the sidewall and top surface of the second patterned structure, the sidewall material layer on the top surface of the second patterned structure is etched back to form the second sidewall structure, and the second patterned structure is removed.

[0031] In an optional embodiment, the etching of the layer to be etched using a first sidewall structure and a second sidewall structure of different thicknesses as masks, forming a first trench in the first process area, and forming a second trench in the second process area, includes:

[0032] Using a first sidewall structure and a second sidewall structure of different thicknesses as masks, the second mask layer is etched to form a third patterned structure on the first process area and a fourth patterned structure on the second process area; the thickness of the third patterned structure is different from the thickness of the fourth patterned structure.

[0033] A third sidewall structure is formed on the sidewall of the third patterned structure, and the third patterned structure is removed; a fourth sidewall structure is formed on the sidewall of the fourth patterned structure, and the fourth patterned structure is removed; the thickness of the third sidewall structure is the same as the thickness of the second sidewall.

[0034] Using the third sidewall structure and the fourth sidewall structure as masks, the interlayer dielectric layer is etched to form the first trench in the first process area and the second trench in the second process area.

[0035] In an optional embodiment, the first sidewall structure and the second sidewall structure with different thicknesses are obtained by adjusting the thickness of the first sidewall structure formed on the sidewall of the first patterned structure, and the thickness of the first sidewall structure after adjustment is smaller than the thickness of the second sidewall structure.

[0036] The process of etching the second mask layer using the first and second sidewall structures of different thicknesses as masks to form a third patterned structure on the first process area and a fourth patterned structure on the second process area includes:

[0037] Using the modified first sidewall structure and the second sidewall structure as masks, the second mask layer is etched to form a third patterned structure on the first process area and a fourth patterned structure on the second process area; the thickness of the third patterned structure is less than the thickness of the fourth patterned structure.

[0038] In an optional embodiment, the steps of forming a third sidewall structure on the sidewall of the third patterned structure and removing the third patterned structure, and forming a fourth sidewall structure on the sidewall of the fourth patterned structure and removing the fourth patterned structure, include:

[0039] A sidewall material layer is deposited on the sidewalls and top surface of the third patterned structure, the sidewall material layer on the top surface of the third patterned structure is etched back to form the third sidewall structure, and the third patterned structure is removed; and a sidewall material layer is deposited on the sidewalls and top surface of the fourth patterned structure, the sidewall material layer on the top surface of the fourth patterned structure is etched back to form the fourth sidewall structure, and the fourth patterned structure is removed.

[0040] In an optional embodiment, after forming a third sidewall structure on the sidewall of the third patterned structure and removing the third patterned structure, and after forming a fourth sidewall structure on the sidewall of the fourth patterned structure and removing the fourth patterned structure, the method further includes:

[0041] The thickness of the third side wall structure is adjusted so that the thickness of the adjusted third side wall structure is less than the thickness of the fourth side wall structure.

[0042] The process of etching the interlayer dielectric layer using the third and fourth sidewall structures as masks to form the first trench in the first process area and the second trench in the second process area includes:

[0043] Using the modified third sidewall structure and the fourth sidewall structure as masks, the interlayer dielectric layer is etched to form the first trench in the first process area and the second trench in the second process area.

[0044] In an optional embodiment, the etching of the layer to be etched using a first sidewall structure and a second sidewall structure of different thicknesses as masks, forming a first trench in the first process area, and forming a second trench in the second process area, includes:

[0045] Using a first sidewall structure and a second sidewall structure of different thicknesses as masks, the second mask layer is etched to form a third patterned structure on the first process area and a fourth patterned structure on the second process area; the thickness of the third patterned structure is different from the thickness of the fourth patterned structure.

[0046] The interlayer dielectric layer is etched using the third and fourth patterned structures as masks to form the first trench in the first process region and the second trench in the second process region.

[0047] In an optional embodiment, the first sidewall structure and the second sidewall structure with different thicknesses are obtained by adjusting the thickness of the first sidewall structure formed on the sidewall of the first patterned structure, and the thickness of the first sidewall structure after adjustment is smaller than the thickness of the second sidewall structure.

[0048] The process of etching the second mask layer using the first and second sidewall structures of different thicknesses as masks to form a third patterned structure on the first process area and a fourth patterned structure on the second process area includes:

[0049] Using the modified first sidewall structure and the second sidewall structure as masks, the second mask layer is etched to form a third patterned structure on the first process area and a fourth patterned structure on the second process area; the thickness of the third patterned structure is less than the thickness of the fourth patterned structure.

[0050] In an optional embodiment, the first process region is a low-power standard cell library in the standard cell region, and the second process region is a high-performance standard cell library in the standard cell region.

[0051] In an optional embodiment, the first process area is a standard cell area, and the second process area is a non-standard cell area.

[0052] A second aspect of this application provides a semiconductor structure, which is prepared by the formation method described in any of the above embodiments, the semiconductor structure comprising:

[0053] The layer to be etched includes a first process area and a second process area, and the first process area and the second process area have different design requirements for the conductive layer width.

[0054] A first trench located within the first process area, and a second trench located within the second process area;

[0055] A first conductive layer is located within the first trench, and a second conductive layer is located within the second trench; the thickness of the first conductive layer is different from the width of the second conductive layer.

[0056] In an optional embodiment, the difference between the width of the second conductive layer and the thickness of the first conductive layer is a preset number of times the preset thickness.

[0057] A third aspect of this application provides an electronic device, the electronic device comprising a semiconductor structure as described in any of the above embodiments.

[0058] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects:

[0059] The semiconductor structure formation method provided in this application involves generating first and second sidewall structures of different thicknesses in different process regions. Then, using the first and second sidewall structures of different thicknesses as masks, the layer to be etched is etched, forming a first trench in the first process region and a second trench in the second process region. A first conductive layer is formed in the first trench, and a second conductive layer is formed in the second trench. The widths of the first and second conductive layers are different. This allows for the formation of conductive layers with different widths in different process regions, thus solving the problem that the metal line dimensions in different regions cannot be designed individually due to sidewall auxiliary processes. This enables differentiated design of conductive layer dimensions for different functional modules, allowing for greater design freedom in the conductive layer dimensions of different modules.

[0060] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0061] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.

[0062] Figure 1 This is a flowchart illustrating SAQP in related technologies.

[0063] Figure 2 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment. Figure 1 .

[0064] Figure 3 This is a schematic diagram illustrating a method for forming a semiconductor structure based on SAQP process according to an exemplary embodiment.

[0065] Figure 4 This is a schematic diagram illustrating a method for forming a semiconductor structure based on SADP process according to an exemplary embodiment.

[0066] Figure 5 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment. Figure 2 .

[0067] Figure 6 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment. Figure 3 .

[0068] Figure 7 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment. Figure 4 .

[0069] Figure 8 This is a schematic diagram illustrating the dimensions of wire layers and vias in a low-power standard cell library and a high-performance standard cell library according to an exemplary embodiment.

[0070] Figure 9 This is a schematic diagram illustrating the relationship between Δd and the frequency gain coefficient according to an exemplary embodiment.

[0071] The following is a supplementary explanation of the reference numerals in the accompanying drawings:

[0072] 1-Interlayer dielectric layer, 2-Second mask layer, 3-Core sacrificial layer, 4-First mask layer, 5-First patterned structure, 6-Second patterned structure, 7-First sidewall structure, 8-Second sidewall structure, 9-First sidewall structure after trimming, 10-Third patterned structure, 11-Fourth patterned structure, 12-Third sidewall structure, 13-Fourth sidewall structure, 14-First trench, 15-Second trench, 16-First through hole, 17-Second through hole. Detailed Implementation

[0073] The following provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below in a simplified manner. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances throughout this application. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0074] Additionally, spatial relative terms, such as “below,” “under,” “lower part,” “above,” “upper part,” “front,” “back,” “above,” and similar terms, may be used in this application for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures.

[0075] Figure 2 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment. Figure 1 ,like Figure 2 As shown, the forming method may include:

[0076] S11. Provide a layer to be etched; the layer to be etched includes a first process area and a second process area; the first process area and the second process area have different design requirements for the conductive layer width.

[0077] Optionally, the layer to be etched may include a substrate, the substrate comprising an interlayer dielectric layer, a second mask layer, a core sacrificial layer and a first mask layer stacked sequentially from bottom to top.

[0078] Optionally, the substrate material may include, but is not limited to: silicon, materials comprising silicon, III-V compound semiconductor materials such as gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or another type of semiconductor material capable of generating charge from photons of incident light. Among these, the multi-element semiconductor materials composed of III-V elements include indium phosphide (InP), gallium arsenide (GaAs), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide (InGaAs), or indium gallium arsenide phosphide (InGaAsP). The substrate may also contain several device structures (not shown), which may include one or more of the following: transistor structures, capacitor structures, resistor structures, and inductor structures.

[0079] Optionally, the interlayer dielectric layer is made of a low-k dielectric layer. In other embodiments, the dielectric layer is made of silicon oxide.

[0080] Optionally, the material of the second mask layer includes one or more combinations of silicon oxide, silicon nitride, titanium nitride, titanium oxide, tungsten carbide, silicon carbide, silicon nitride, silicon carbide, aluminum oxide, and aluminum nitride.

[0081] Optionally, the material of the first mask layer includes one or more combinations of silicon oxide, silicon nitride, titanium nitride, titanium oxide, tungsten carbide, silicon carbide, silicon oxycarbide, silicon carbide, aluminum oxide, and aluminum nitride.

[0082] Optionally, the material of the core sacrificial layer is preferably silicon oxide.

[0083] It should be noted that the etched layer includes a first process area and a second process area. This does not mean that the etched layer consists of only two process areas, but rather that they are process areas with different design requirements for the conductive layer width. For example, the first process area may include several process areas, all of which require narrow conductive layer design, while the second process area may include several process areas, all of which are not designed for narrow conductive layers, i.e., they are all designed for wide conductive layers. As another example, both the first and second process areas may include several process areas, all of which are designed for narrow conductive layers, and the first process area has a smaller requirement for conductive layer width than the second process area.

[0084] S13. A first patterned structure is formed on the first process area, and a second patterned structure is formed on the second process area.

[0085] In one embodiment, a first patterned structure can be formed simultaneously on a first process region and a second patterned structure can be formed on a second process region using a first mask layer, thereby improving the formation efficiency of the semiconductor structure and reducing the formation cost of the semiconductor structure.

[0086] In another implementation, the first graphical structure and the second graphical structure may not be generated simultaneously; for example, the first graphical structure and the second graphical structure may be generated sequentially.

[0087] S15. A first sidewall structure is formed on the sidewall of the first patterned structure, and the first patterned structure is removed; a second sidewall structure is formed on the sidewall of the second patterned structure, and the second patterned structure is removed; the thickness of the first sidewall structure and the thickness of the second sidewall structure are different.

[0088] In one implementation, the first sidewall structure and the second patterned structure can be generated simultaneously and uniformly, thereby improving the formation efficiency of the semiconductor structure and reducing its formation cost. In another implementation, the first sidewall structure and the second sidewall structure can be generated at different times; for example, they can be generated sequentially.

[0089] It should be noted that the thickness of the first sidewall structure is different from the thickness of the second sidewall structure. This can mean that the thickness of the first sidewall structure is less than the thickness of the second sidewall structure, or that the thickness of the first sidewall structure is greater than the thickness of the second sidewall structure.

[0090] S17. Using a first sidewall structure and a second sidewall structure of different thicknesses as masks, the layer to be etched is etched to form a first trench in the first process area and a second trench in the second process area; the width of the first trench is different from the width of the second trench.

[0091] In this embodiment, the first sidewall structure and the second sidewall structure with different thicknesses can be used as masks to etch the layer to be etched, so as to form a first trench in the first process area and a second trench in the second process area.

[0092] In one embodiment, a first sidewall structure and a second sidewall structure with different thicknesses can be used as masks to simultaneously etch the layer to be etched, thereby improving the semiconductor structure formation efficiency and reducing the semiconductor structure formation cost. In another embodiment, the layer to be etched may not be etched uniformly. For example, the layer to be etched can be etched first using the first sidewall structure as a mask to form a first trench in the first process area, and then the layer to be etched can be etched using the second sidewall structure as a mask to form a second trench in the second process area. Alternatively, the layer to be etched can be etched first using the second sidewall structure as a mask to form a second trench in the second process area, and then the layer to be etched can be etched using the first sidewall structure as a mask to form a first trench in the first process area.

[0093] It should be noted that the width of the first trench corresponds to the thickness of the first sidewall, and the width of the second trench corresponds to the thickness of the second sidewall. Therefore, the widths of the first trench and the second trench are not the same.

[0094] S19. A first conductive layer is formed in the first trench, and a second conductive layer is formed in the second trench; the width of the first conductive layer is different from the width of the second conductive layer.

[0095] In this embodiment, after obtaining the first trench and the second trench, a first conductive layer can be formed in the first trench, and a second conductive layer can be formed in the second trench. Since the widths of the first trench and the second trench are different, the widths of the first conductive layer and the second conductive layer are also different, resulting in conductive layers of different widths in the first and second process areas. This allows for the formation of conductive layers of different widths in different process areas, thus solving the problem that the metal wire dimensions in different areas introduced by the sidewall auxiliary process cannot be designed individually. This enables differentiated design of conductive layer dimensions for different functional modules, allowing for greater design freedom in the conductive layer dimensions of different modules.

[0096] It should be noted that in step S13 above, the formation of the first patterned structure on the first process area and the formation of the second patterned structure on the second process area can be achieved in various ways, and no specific limitation is made. For example, SADP, SAQP, and other processes can be used.

[0097] Figure 3 This is a schematic diagram illustrating a method for forming a semiconductor structure based on SAQP process according to an exemplary embodiment. Figure 4 This is a schematic diagram illustrating a method for forming a semiconductor structure based on SADP process according to an exemplary embodiment. Figure 3 and Figure 4 The substrate comprises, from bottom to top, an interlayer dielectric layer 1, a second mask layer 2, a core sacrificial layer 3, and a first mask layer 4, stacked sequentially.

[0098] In one implementation, such as Figure 3 and Figure 4 As shown, for SADP and SAQP processes, in step S13 above, forming a first patterned structure on the first process area and a second patterned structure on the second process area may include:

[0099] The first mask layer 4 is graphically represented.

[0100] Using the patterned first mask layer as a mask, the core sacrificial layer 3 is etched to form the first patterned structure 5 in the first process area and the second patterned structure 6 in the second process area.

[0101] In this embodiment, photoresist can be applied over the first mask layer 4, and photolithography exposure can be performed to form a patterned photoresist. The patterned photoresist is then used as a mask to etch the first mask layer 4, forming a patterned first mask layer. After forming the patterned first mask layer, the core sacrificial layer 3 can be etched using the patterned first mask layer as a mask to form a patterned core sacrificial layer (i.e., the first patterned structure 5) in the first process area, and a patterned core sacrificial layer (i.e., the second patterned structure 6) in the second process area. That is, the first mask layer 4 is used as a hard mask to achieve the first pattern definition.

[0102] This embodiment uses the patterned first mask layer as a mask to etch the core sacrificial layer, which can form the same first patterned structure and second patterned structure in the first patterned structure and the second patterned structure. This facilitates the subsequent convenient and accurate generation of the first sidewall structure and the second sidewall result with the same thickness, thereby laying the foundation for accurately forming conductive layers of different widths in different process areas.

[0103] It should be noted that step S15 above can be implemented in various ways, and no specific limitation is made. For example, it can be implemented using processes such as SADP and SAQP.

[0104] In one embodiment, for SADP and SAQP processes, in step S15 above, the formation of a first sidewall structure on the sidewall of the first patterned structure and the removal of the first patterned structure, and the formation of a second sidewall structure on the sidewall of the second patterned structure and the removal of the second patterned structure, may include:

[0105] Remove the first mask layer 4.

[0106] A sidewall material layer is deposited on the sidewall and top surface of the first patterned structure 5, and the sidewall material layer on the top surface of the first patterned structure is etched back to form the first sidewall structure 7, and the first patterned structure 5 is removed; and a sidewall material layer is deposited on the sidewall and top surface of the second patterned structure 6, and the sidewall material layer on the top surface of the second patterned structure 6 is etched back to form the second sidewall structure 8, and the second patterned structure 6 is removed.

[0107] In this embodiment, after forming the first patterned structure 5 and the second patterned structure 6, the first mask layer 4 can be removed, and a sidewall material layer can be deposited on the sidewalls and top surface of the first patterned structure 5. The sidewall material layer on the top surface of the first patterned structure 5 is then etched back until the first patterned structure is exposed to form the first sidewall structure 7, and the first patterned structure 5 is then removed. Similarly, a sidewall material layer can be deposited on the sidewalls and top surface of the second patterned structure 6, and the sidewall material layer on the top surface of the second patterned structure 6 is then etched back until the second patterned structure is exposed to form the second sidewall structure 8, and the second patterned structure 6 is then removed.

[0108] In one embodiment, the processes of forming the first sidewall structure 7 and the second sidewall structure 8 can be performed simultaneously. In another embodiment, the processes of forming the first sidewall structure 7 and the second sidewall structure 8 can also be performed non-simultaneously; for example, the first sidewall structure 7 and the second sidewall structure 8 can be formed sequentially.

[0109] Optionally, an atomic layer deposition process can be used to deposit sidewall material layers on the sidewalls and top surface of the first patterned structure 5, and on the sidewalls and top surface of the second patterned structure 6.

[0110] Optionally, the material of the sidewall material layer may include at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, or boron carbonitride.

[0111] Therefore, by depositing sidewall material layers on the sidewalls and top surface of the patterned structure, sidewalls of consistent thickness can be accurately formed in the first and second process zones, thus laying the foundation for accurately forming conductive layers of different widths in different process zones.

[0112] In an optional embodiment, in step S15 above, forming a first sidewall structure on the sidewall of the first patterned structure and removing the first patterned structure, and forming a second sidewall structure on the sidewall of the second patterned structure and removing the second patterned structure, may include:

[0113] A first sidewall structure is formed on the sidewall of the first patterned structure, and the first patterned structure is removed; a second sidewall structure is formed on the sidewall of the second patterned structure, and the second patterned structure is removed; the thickness of the first sidewall is the same as the thickness of the second sidewall.

[0114] Accordingly, after removing the second graphical structure, the method further includes:

[0115] The thickness of the first sidewall structure is adjusted so that the thickness of the first sidewall structure is less than the thickness of the second sidewall structure, so that the thickness of the first sidewall structure is different from the thickness of the second sidewall structure.

[0116] In this embodiment, a first sidewall structure and a second sidewall structure of the same thickness can be formed on the sidewalls of the first and second patterned structures. It should be noted that "the thickness of the first sidewall is the same as the thickness of the second sidewall" can mean that the thickness of the first sidewall and the thickness of the second sidewall are completely equal. Alternatively, "the thickness of the first sidewall is the same as the thickness of the second sidewall" can mean that the deviation between the thicknesses of the first and second sidewalls is less than a preset thickness threshold. This preset thickness threshold can be set according to actual business needs and is not specifically limited thereto.

[0117] In this embodiment of the application, for the first process area that requires a narrow conductive layer design, the thickness of the first sidewall structure can be adjusted after the first sidewall structure is generated, so that the thickness of the adjusted first sidewall structure is less than the thickness of the second sidewall structure, thereby the thickness of the first sidewall structure and the thickness of the second sidewall structure are different.

[0118] It should be noted that the second process area can also be a process area requiring a narrow conductive layer design. When both the first and second process areas are designed for narrow conductive layers, the first and second sidewall structures can be modified to different degrees according to the required conductive layer width, resulting in different thicknesses for the first and second sidewall structures. Conversely, if the second process area requires a narrow conductive layer design while the first process area does not, only the thickness of the second sidewall structure needs modification. Therefore, by modifying the process, conductive layers of different widths can be obtained in different process areas, thus solving the problem of not being able to design the metal wire dimensions of different areas independently due to the sidewall auxiliary process. This enables differentiated design of conductive layer dimensions for different functional modules, allowing for greater design freedom in the conductive layer dimensions of different modules.

[0119] In an optional embodiment, in step S17 above, the etching of the layer to be etched using the first sidewall structure and the second sidewall structure with different thicknesses as masks to form a first trench in the first process area and a second trench in the second process area may include:

[0120] Using the modified first sidewall structure and the second sidewall structure as masks, the layer to be etched is etched, forming a first trench in the first process area and a second trench in the second process area; the width of the first trench is smaller than the width of the second trench.

[0121] In this embodiment, the modified first sidewall structure and the second sidewall structure can be used as masks to etch the layer to be etched, so as to form a first trench in the first process area and a second trench in the second process area.

[0122] In one embodiment, the modified first sidewall structure and the second sidewall structure can be used as masks to simultaneously etch the layer to be etched, thereby improving the semiconductor structure formation efficiency and reducing the semiconductor structure formation cost. In another embodiment, the layer to be etched may not be etched simultaneously. For example, the modified first sidewall structure can be used as a mask to first etch the layer to be etched, forming a first trench in the first process area, and then the second sidewall structure can be used as a mask to etch the layer to be etched, forming a second trench in the second process area. Alternatively, the second sidewall structure can be used as a mask to first etch the layer to be etched, forming a second trench in the second process area, and then the modified first sidewall structure can be used as a mask to etch the layer to be etched, forming a first trench in the first process area.

[0123] It should be noted that the width of the first trench corresponds to the thickness of the first sidewall, and the width of the second trench corresponds to the thickness of the second sidewall. Therefore, the width of the first trench is smaller than the width of the second trench.

[0124] In an optional embodiment, in step S19 above, forming a first conductive layer in the first trench and forming a second conductive layer in the second trench may include:

[0125] A first conductive layer is formed in the first trench, and a second conductive layer is formed in the second trench; the width of the first conductive layer is smaller than the width of the second conductive layer.

[0126] In this embodiment, after obtaining the first trench and the second trench, a first conductive layer can be formed in the first trench, and a second conductive layer can be formed in the second trench. Since the width of the first trench is smaller than the width of the second trench, the width of the first conductive layer is also smaller than the width of the second conductive layer, resulting in conductive layers of different widths in the first and second process areas. This allows for the formation of conductive layers of different widths in different process areas, thus solving the problem of not being able to design the metal wire dimensions for different areas introduced by the sidewall auxiliary process independently. This enables differentiated design of conductive layer dimensions for different functional modules, allowing for greater design flexibility in the conductive layer dimensions of different modules.

[0127] In an optional embodiment, the trimming process includes etching, and the trimming process for the thickness of the first sidewall structure includes:

[0128] Anisotropic etching is performed on the first sidewall structure 7 so that the thickness of the first sidewall structure after etching is less than the thickness of the second sidewall structure 8.

[0129] In this embodiment, the finishing process may include an etching process, in which the first sidewall structure 7 is anisotropically etched to make the thickness of the etched first sidewall structure less than the thickness of the second sidewall structure 8. This allows the thickness of the first sidewall structure to decrease at the same rate in all directions, improving the uniformity of the subsequently formed conductive layer. This ensures that the subsequently formed conductive layer meets process requirements and allows for more flexible and free design of the conductive layer.

[0130] In one exemplary embodiment, the trimming process is a dry etching process. More specifically, the trimming process can be an isotropic dry etching process. For example, the trimming process is performed under conditions of a pressure of 5 mTorr to 20 mTorr, a power supply of 700 W to 800 W, a carbon tetrafluoride gas flow rate of 125 sccm to 225 sccm, and without the use of a bias voltage. In alternative embodiments, the trimming process can use another fluorine-containing gas (e.g., SF6, CH2F2, CHF3, and / or C2F6), an oxygen-containing gas, a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, or other suitable gases, and / or plasma, and / or combinations thereof.

[0131] In a specific embodiment, the anisotropic etching process performed on the first sidewall structure described above may include:

[0132] The first sidewall structure 7 is simultaneously etched on both sides to reduce the thickness of both sides of the first sidewall structure 7 by a predetermined thickness.

[0133] Wherein, the difference between the thickness of the second sidewall structure 8 and the thickness of the first sidewall structure 9 after the trimming is a preset number of times the preset thickness, the width of the first conductive layer is the same as the thickness of the first sidewall structure 9 after the trimming, and the width of the second conductive layer is the same as the thickness of the second sidewall structure.

[0134] In this embodiment, etching can be performed on both sides of the first sidewall structure 7 simultaneously. For example, the two sides of the first sidewall structure 7 can be etched according to the above-described isotropic dry etching process so that the thickness of both sides of the first sidewall structure can be reduced by a preset thickness at the same time.

[0135] Assuming the preset thickness is Δd, the thickness of the second side wall structure 8 and the first side wall structure 7 is S1, and the thickness of the first side wall structure 9 after the trimming is S2, then S2 = S1 - preset multiple × Δd.

[0136] It should be noted that the preset thickness Δd and the preset quantity multiple are set according to actual business needs, and no specific limitation is made. For example, if the preset quantity multiple is 2 times, that is, S2 = S1 - 2Δd, then the thickness of both sides of the first side wall structure 7 is reduced by half of the preset thickness.

[0137] Therefore, various directional etchings can be performed on both sides of the first sidewall structure through the trimming process, so that both sides of the first sidewall structure reduce the thickness at the same rate, thereby further improving the operability of the subsequently formed metal layer, enabling the subsequently formed metal layer to meet the process requirements, and making the design of the metal layer more flexible and free.

[0138] It should be noted that step S19 above can be implemented in various ways, and no specific limitation is made. For example, it can be implemented using SADP or SAQP processes.

[0139] Figure 5 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment. Figure 2 ,like Figure 5 As shown, for the SAQP process, in step S17 above, the etching of the layer to be etched using the first sidewall structure and the second sidewall structure with different thicknesses as masks, forming a first trench in the first process area and a second trench in the second process area, may include:

[0140] S171-1. Using a first sidewall structure and a second sidewall structure of different thicknesses as masks, the second mask layer is etched to form a third patterned structure on the first process area and a fourth patterned structure on the second process area; the thickness of the third patterned structure is different from the thickness of the fourth patterned structure.

[0141] S171-3. A third sidewall structure is formed on the sidewall of the third patterned structure, and the third patterned structure is removed; a fourth sidewall structure is formed on the sidewall of the fourth patterned structure, and the fourth patterned structure is removed; the thickness of the third sidewall structure is the same as the thickness of the second sidewall.

[0142] S171-5. Using the third sidewall structure and the fourth sidewall structure as masks, etch the interlayer dielectric layer to form the first trench in the first process area and the second trench in the second process area.

[0143] Optionally, continue as follows Figure 3 As shown, in step S171-1 above, after obtaining the first sidewall structure 7 and the second sidewall structure 8 with different thicknesses, the first sidewall structure 7 can be transferred to form a third patterned structure 10 in the first process area, and the second sidewall structure 8 can be transferred to form a fourth patterned structure 11 in the second process area. Specifically, transferring the first sidewall structure 7 to form the third patterned structure 10 in the first process area may include: etching the second mask layer 2 using the first sidewall structure 7 as a mask to form the third patterned structure 10 in the first process area. Specifically, transferring the second sidewall structure 8 to form the fourth patterned structure 11 in the second process area may include: etching the second mask layer 2 using the second sidewall structure 8 as a mask to form the fourth patterned structure 11 in the second process area.

[0144] Since the thickness of the first sidewall structure 7 is different from the thickness of the second sidewall structure 8, the thickness of the third patterned structure 10 is also different from the thickness of the fourth patterned structure 11. For example, when the difference between the thickness of the second sidewall structure 8 and the thickness of the first sidewall structure 7 is a preset multiple of a preset thickness, the difference between the thickness of the fourth patterned structure 11 and the thickness of the third patterned structure 10 is also a preset multiple of a preset thickness. More specifically, when S2 = S1 - 2Δd, the difference between the thickness of the fourth patterned structure 11 and the thickness of the third patterned structure 10 is also 2Δd.

[0145] Optionally, in steps S171-3 above, in one embodiment, the third sidewall structure 12 and the fourth sidewall structure 13 can be generated simultaneously, with the thickness of the third sidewall structure being the same as the thickness of the fourth sidewall structure, thereby improving the semiconductor structure formation efficiency and reducing the semiconductor structure formation cost. In another embodiment, the third sidewall structure 12 and the fourth sidewall structure 13 can be generated at different times; for example, the third sidewall structure 12 and the fourth sidewall structure 13 can be generated sequentially.

[0146] It should be noted that the statement that the third side wall structure 12 and the fourth side wall structure 13 have the same thickness can mean that the thicknesses of the third side wall structure 12 and the fourth side wall structure 13 are exactly equal. Alternatively, it can mean that the deviation between the third side wall structure 12 and the fourth side wall structure 13 is less than a preset thickness threshold. This preset thickness threshold can be set according to actual business needs and is not specifically limited thereto.

[0147] Optionally, for the SAQP process, in steps S171-5 above, the interlayer dielectric layer 1 can be etched using the third sidewall structure 12 and the fourth sidewall structure 13 as masks, forming a plurality of first trenches 14 in the first process area and a plurality of second trenches 15 in the second process area.

[0148] Since the third patterned structure 10 and the fourth patterned structure 11 are removed, and the interlayer dielectric layer 1 is etched using the three-sidewall structure 12 and the fourth sidewall structure 13 as masks, the width of the etched first trench 14 corresponds to the width of the third patterned structure 10, and the width of the etched second trench 15 corresponds to the width of the fourth patterned structure 11. Therefore, the width of the first trench 14 is smaller than the width of the second trench 15. More specifically, when S2 = S1 - 2Δd, the difference between the width of the second trench 15 and the width of the first trench 14 is also 2Δd.

[0149] It should be noted that the embodiments of this application do not specifically limit the number of sidewalls and trenches.

[0150] Therefore, by using the first and second sidewall structures of different thicknesses as masks to etch the layer to be etched, trenches of different widths can be formed in different process areas, so that metal layers of different widths can be obtained in different process areas. This solves the problem that the metal layer size in different areas introduced by the sidewall auxiliary process cannot be designed separately, realizes the differentiated design of the metal layer size of different functional modules, and makes the design of the metal layer size of different modules more flexible.

[0151] In an optional embodiment, in step S171-1 above, the etching of the second mask layer using the first sidewall structure and the second sidewall structure with different thicknesses as masks to form a third patterned structure on the first process area and a fourth patterned structure on the second process area may include:

[0152] Using the modified first sidewall structure 9 and the second sidewall structure 8 as masks, the second mask layer 2 is etched to form a third patterned structure 10 on the first process area and a fourth patterned structure 11 on the second process area; the thickness of the third patterned structure 10 is less than the thickness of the fourth patterned structure 11.

[0153] In this embodiment, after obtaining the trimmed first sidewall structure 9 and the second sidewall structure 8, the trimmed first sidewall structure 9 can be used as a mask to etch the second mask layer 2, forming a third patterned structure 10 on the first process area. The second sidewall structure 8 can be used as a mask to etch the second mask layer 2, forming a fourth patterned structure 11 on the second process area.

[0154] Since the thickness of the first sidewall structure 9 after the trimming process is less than the thickness of the second sidewall structure 8, the thickness of the third patterned structure 10 is also less than the thickness of the fourth patterned structure 11. For example, when the difference between the thickness of the second sidewall structure 8 and the thickness of the first sidewall structure 9 after the trimming process is a preset multiple of a preset thickness, the difference between the thickness of the fourth patterned structure 11 and the thickness of the third patterned structure 10 is also a preset multiple of a preset thickness. More specifically, when S2 = S1 - 2Δd, the difference between the thickness of the fourth patterned structure 11 and the thickness of the third patterned structure 10 is also 2Δd.

[0155] In an optional embodiment, for the SAQP process, in steps S171-3 above, forming a third sidewall structure on the sidewall of the third patterned structure and removing the third patterned structure, and forming a fourth sidewall structure on the sidewall of the fourth patterned structure and removing the fourth patterned structure, may include:

[0156] A sidewall material layer is deposited on the sidewalls and top surface of the third patterned structure 10, the sidewall material layer on the top surface of the third patterned structure 10 is etched back to form the third sidewall structure 12, and the third patterned structure 10 is removed; and a sidewall material layer is deposited on the sidewalls and top surface of the fourth patterned structure 11, the sidewall material layer on the top surface of the fourth patterned structure 11 is etched back to form the fourth sidewall structure 13, and the fourth patterned structure 11 is removed.

[0157] In this embodiment, after obtaining the third patterned structure 10 and the fourth patterned structure 11, a sidewall material layer can be deposited on the sidewalls and top surface of the first patterned structure 10. The sidewall material layer on the top surface of the third patterned structure 10 is then etched back until the first patterned structure is exposed to form the third sidewall structure 12, and the third patterned structure 10 is then removed. Similarly, a sidewall material layer is deposited on the sidewalls and top surface of the fourth patterned structure 11. The sidewall material layer on the top surface of the fourth patterned structure 11 is then etched back until the fourth patterned structure is exposed to form the fourth sidewall structure 13, and the fourth patterned structure 11 is then removed.

[0158] In one embodiment, the processes of forming the third side wall structure 12 and the fourth side wall structure 13 can be performed simultaneously. In another embodiment, the processes of forming the third side wall structure and the fourth side wall structure can also be performed non-simultaneously; for example, the third side wall structure 12 and the fourth side wall structure 13 can be formed sequentially.

[0159] Optionally, an atomic layer deposition process can be used to deposit sidewall material layers on the sidewalls and top surface of the third patterned structure, and on the sidewalls and top surface of the fourth patterned structure.

[0160] Optionally, the material of the sidewall material layer may include at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, or boron carbonitride.

[0161] Therefore, by depositing sidewall material layers on the sidewalls and top surface of the patterned structure, sidewalls of consistent thickness can be accurately formed in the first and second process zones, thus laying the foundation for accurately forming conductive layers of different widths in different process zones.

[0162] Figure 6 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment. Figure 3 ,like Figure 6As shown, for SAQP, after forming a third sidewall structure on the sidewall of the third patterned structure and removing the third patterned structure in steps S171-3 above, and after forming a fourth sidewall structure on the sidewall of the fourth patterned structure and removing the fourth patterned structure, the above method may further include:

[0163] S171-4. The thickness of the third side wall structure is adjusted so that the thickness of the adjusted third side wall structure is less than the thickness of the fourth side wall structure.

[0164] In this embodiment, for the SAQP process, the trimming process used in this application is not limited to one step; multiple trimming processes can be used to achieve the design of multiple conductive layers in multiple regions. Based on this, for the first process area requiring narrow metal line design, after forming the third sidewall structure 12 and the fourth sidewall structure 13, the thickness of the third sidewall structure 12 can be trimmed so that the thickness of the trimmed third sidewall structure is less than the thickness of the fourth sidewall structure 13. Alternatively, the thicknesses of the third and fourth sidewall structures can be trimmed so that the thickness of the trimmed third sidewall structure is less than the thickness of the trimmed fourth sidewall structure. Optionally, the third sidewall structure 12 can be subjected to anisotropic etching so that the thickness of the etched third sidewall structure is less than the thickness of the fourth sidewall structure 13. Furthermore, etching can be performed on both sides of the third sidewall structure 12 simultaneously to reduce the thickness of both sides of the third sidewall structure by a preset thickness; wherein the difference between the thickness of the fourth sidewall structure 13 and the thickness of the trimmed third sidewall structure is a preset number of times the preset thickness.

[0165] In this embodiment, the finishing process may include an etching process, in which the third sidewall structure 12 is anisotropically etched to make the thickness of the etched third sidewall structure less than the thickness of the fourth sidewall structure. This allows the thickness of the third sidewall structure 12 to decrease at the same rate in all directions, improving the uniformity of the subsequently formed conductive layer, ensuring that the subsequently formed metal layer meets process requirements, and allowing for more flexible and free design of the metal layer.

[0166] In one exemplary embodiment, the trimming process is a dry etching process. More specifically, the trimming process can be the isotropic dry etching process described above.

[0167] Therefore, various directional etchings can be performed on both sides of the third sidewall structure through the trimming process, so that both sides of the third sidewall structure reduce the thickness at the same rate, thereby further improving the operability of the subsequently formed metal layer, enabling the subsequently formed metal layer to meet the process requirements, and making the design of the metal layer more flexible and free; in addition, multiple trimming processes can realize the design of multiple conductive layers in multiple regions, thereby further improving the design flexibility of the conductive layer.

[0168] Accordingly, continue as Figure 6 As shown, in steps S171-5 above, the etching of the interlayer dielectric layer using the third sidewall structure and the fourth sidewall structure as masks to form the first trench in the first process area and the second trench in the second process area may include:

[0169] Using the modified third sidewall structure and the fourth sidewall structure as masks, the interlayer dielectric layer is etched to form the first trench in the first process area and the second trench in the second process area.

[0170] In one embodiment, the modified third sidewall structure and the fourth sidewall structure can be used as masks to etch the same pair of interlayer dielectric layers, thereby improving the semiconductor structure formation efficiency and reducing the semiconductor structure formation cost. In another embodiment, the interlayer dielectric layers may not be etched uniformly. For example, the modified third sidewall structure can be used as a mask to first etch the interlayer dielectric layer, forming a first trench in the first process area, and then the fourth sidewall structure can be used as a mask to etch the interlayer dielectric layer, forming a second trench in the second process area. Alternatively, the fourth sidewall structure can be used as a mask to first etch the layer to be etched, forming a first trench in the second process area, and then the modified third sidewall structure can be used as a mask to etch the layer to be etched, forming a second trench in the first process area.

[0171] Figure 7 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment. Figure 4 ,like Figure 7 As shown, in another embodiment, for the SADP process, in step S17 above, the etching of the layer to be etched using a first sidewall structure and a second sidewall structure of different thicknesses as masks, forming a first trench in the first process area and a second trench in the second process area, may include:

[0172] S173-1. Using a first sidewall structure and a second sidewall structure of different thicknesses as masks, the second mask layer is etched to form a third patterned structure on the first process area and a fourth patterned structure on the second process area; the thickness of the third patterned structure is different from the thickness of the fourth patterned structure.

[0173] S173-3. Using the third patterned structure and the fourth patterned structure as masks, the interlayer dielectric layer is etched to form the first trench in the first process region and the second trench in the second process region.

[0174] In this embodiment, continue as follows Figure 4 As shown, in step S173-1 above, for the SADP process, after obtaining the first sidewall structure 7 and the second sidewall structure 8 with different thicknesses, the first sidewall structure 7 can be transferred to form a third patterned structure 10 in the first process area, and the second sidewall structure 8 can be transferred to form a fourth patterned structure 11 in the second process area. Specifically, transferring the first sidewall structure 7 to form the third patterned structure 10 in the first process area can include: etching the second mask layer 2 using the first sidewall structure 7 as a mask to form the third patterned structure 10 in the first process area. Specifically, transferring the second sidewall structure 8 to form the fourth patterned structure 11 in the second process area can include: etching the second mask layer 2 using the second sidewall structure 8 as a mask to form the fourth patterned structure 11 in the second process area.

[0175] Optionally, for SADP, in steps S173-3 above, the third patterned structure 10 can be used as a mask to etch the interlayer dielectric layer 1 to form the first trench in the first process area, while the fourth patterned structure 11 can be used as a mask to etch the interlayer dielectric layer 1 to form the second trench 15 in the second process area. In other embodiments, the first trench 14 and the second trench 15 can also be formed sequentially.

[0176] Since the interlayer dielectric layer is etched using the third patterned structure 10 and the fourth patterned structure 11 as masks, the width of the etched first trench 14 corresponds to the width of the third patterned structure 10, and the width of the etched second trench 15 corresponds to the width of the fourth patterned structure 11. Therefore, the width of the first trench 14 is smaller than the width of the second trench 15. For example, the difference between the thickness of the third patterned structure 10 and the thickness of the fourth patterned structure 11 is also a preset multiple of the preset thickness. More specifically, when S2 = S1 - 2Δd, the difference between the width of the second trench 15 and the width of the first trench 14 is also 2Δd.

[0177] Therefore, for the SADP process, the layer to be etched can be etched by using the modified first sidewall structure and the second sidewall structure as a mask, forming trenches of different widths in different process areas. This allows for the subsequent obtaining of conductive layers of different widths in different process areas, thereby solving the problem that the conductive layer size in different areas cannot be designed separately due to the sidewall auxiliary process. This enables differentiated design of conductive layer size for different functional modules, making the design of conductive layer size for different modules more flexible.

[0178] In an optional embodiment, in step S173-1 above, the etching of the second mask layer using the first sidewall structure and the second sidewall structure with different thicknesses as masks to form a third patterned structure on the first process area and a fourth patterned structure on the second process area may include:

[0179] Using the modified first sidewall structure and the second sidewall structure as masks, the second mask layer is etched to form a third patterned structure on the first process area and a fourth patterned structure on the second process area; the thickness of the third patterned structure is less than the thickness of the fourth patterned structure.

[0180] Optionally, continue as follows Figure 4 As shown, in step S173-1 above, for the SADP process, after obtaining the trimmed first sidewall structure 9 and the second sidewall structure 8, the first sidewall structure 7 can be transferred to form a third patterned structure 10 in the first process area, and the second sidewall structure 8 can be transferred to form a fourth patterned structure 11 in the second process area. Specifically, transferring the first sidewall structure 7 to form the third patterned structure 10 in the first process area may include: etching the second mask layer 2 using the trimmed first sidewall structure 9 as a mask to form the third patterned structure 10 in the first process area. Specifically, transferring the second sidewall structure 8 to form the fourth patterned structure 11 in the second process area may include: etching the second mask layer 2 using the second sidewall structure 8 as a mask to form the fourth patterned structure 11 in the second process area.

[0181] Since the thickness of the first sidewall structure 9 after the trimming process is less than the thickness of the second sidewall structure 8, the thickness of the third patterned structure 10 is also less than the thickness of the fourth patterned structure 11. For example, when the difference between the thickness of the second sidewall structure 8 and the thickness of the first sidewall structure 9 after the trimming process is a preset multiple of a preset thickness, the difference between the thickness of the fourth patterned structure 11 and the thickness of the third patterned structure 10 is also a preset multiple of a preset thickness. More specifically, when S2 = S1 - 2Δd, the difference between the thickness of the fourth patterned structure 11 and the thickness of the third patterned structure 10 is also 2Δd.

[0182] In an optional embodiment, step S19, forming a first conductive layer in the first trench and a second conductive layer in the second trench, may include: forming a conductive material layer in the first trench, the second trench, and on the layer to be etched; planarizing the conductive material layer until the surface of the layer to be etched is exposed, thereby forming the first and second conductive layers. Exemplarily, the conductive layer may be a metal wire layer.

[0183] In related technologies, due to the limitations of SAQP and SADP processes, the critical dimensions of the conductive layers defined in different regions are entirely determined by the thickness of the first sidewall. Therefore, the dimensions of the conductor layers (e.g., metal lines) in the design of the low-power standard cell library (LP) in the standard cell (STC) region determine the dimensions of the metal lines in the high-performance standard cell library (HP) in the STC region, thus limiting the dimensions of the metal lines and their corresponding vias in the HP cell library layout design. However, using the formation method provided in this application embodiment, the low-power standard cell library (LP) can be used as the first process region, and the high-performance standard cell library (HP) as the second process region. Then, using the above formation method, a first trench is formed in the low-power standard cell library (LP), and a second trench is formed in the high-performance standard cell library (HP). A first conductive layer is formed in the first trench, and a second conductive layer is formed in the second trench. This allows the low-power standard cell library (LP) to form a narrow-sized conductive layer, while the high-performance standard cell library (HP) can form a wide-sized conductive layer.

[0184] Figure 8 This is a schematic diagram illustrating the dimensions of the wire layers and vias in a low-power standard cell library and a high-performance standard cell library according to an exemplary embodiment, such as... Figure 8 As shown in Figure a, taking the thickness of the first and second sidewall structures as S1, and the thickness of the first sidewall structure after trimming as S2, with S2 = S1 - 2Δd as an example, the width of the first conductive layer finally formed by the low-power standard cell library (LP) remains S1 - 2Δd, and the width of the corresponding first via 16 is also S1 - 2Δd. The width of the second conductive layer formed by the high-performance standard cell library (HP) can be expanded by 2Δd, i.e., it can be S1. At the same time, the corresponding second via 17 can also be expanded by 2Δd, widening from S1 - 2Δd to S1, thereby reducing resistance and improving the performance of the high-performance standard cell library (HP).

[0185] Since the size of the via is limited by the minimum metal CD, the formation method provided in this application increases the metal CD of the HP region to S1, thereby increasing the size of the corresponding via from the original (S1-2Δd) to S1, thereby reducing the downstream resistance and improving the performance of the high-performance standard cell library. Figure 9 This is a schematic diagram illustrating the relationship between Δd and the frequency gain coefficient according to an exemplary embodiment, such as... Figure 9 As shown, since S2+2Δd=S1, the larger Δd is, the larger S1 is in HP, the larger the corresponding via size is, and the larger the frequency gain coefficient is. At a certain node, increasing the CD of a single-layer via by 2nm can achieve a 1% frequency boost.

[0186] This application embodiment can also implement the design of the dimensions of the wide and narrow conductive layers in the STC region and other non-STC regions. In this embodiment, the STC region can be used as the first process region and the non-STC region as the second process region, so that a narrower metal layer is formed in the STC region and a wider metal layer is formed in the non-STC region. For example, the non-STC region can be a static random access memory (SRAM) region.

[0187] The following explanation, using the SAQP process as an example and a single-stage repair of the sidewall structure as an example, provides an overall description of the above-mentioned formation method:

[0188] Continue as Figure 3 As shown, the method for forming the SAQP-based semiconductor structure may include:

[0189] 1) Provide a layer to be etched; the layer to be etched includes a first process region and a second process region; the first process region and the second process region have different design requirements for the conductive layer width. The layer to be etched includes a substrate, the substrate including an interlayer dielectric layer 1, a second mask layer 2, a core sacrificial layer 3 and a first mask layer 4 stacked sequentially from bottom to top.

[0190] 2) Pattern the first mask layer 4; using the patterned first mask layer as a mask, etch the core sacrificial layer 3 to form the first patterned structure 5 in the first process area and the second patterned structure 6 in the second process area.

[0191] 3) Remove the first mask layer 4; deposit a sidewall material layer on the sidewall and top surface of the first patterned structure 5, etch back the sidewall material layer on the top surface of the first patterned structure to form the first sidewall structure 7, and remove the first patterned structure 5; and deposit a sidewall material layer on the sidewall and top surface of the second patterned structure 6, etch back the sidewall material layer on the top surface of the second patterned structure to form the second sidewall structure 8, and remove the second patterned structure 6.

[0192] 4) The thickness of the first side wall structure 7 is adjusted so that the thickness of the adjusted first side wall structure 9 is less than the thickness of the second side wall structure 8.

[0193] Specifically, the first sidewall structure 7 can be anisotropically etched to make the thickness of the etched first sidewall structure less than the thickness of the second sidewall structure 8. For example, the thickness of the etched first sidewall structure 9 is S1-2Δd, and the thickness of the second sidewall structure 8 is S1.

[0194] The anisotropic etching process performed on the first sidewall structure 7 includes:

[0195] The first sidewall structure 7 is simultaneously etched on both sides to reduce the thickness of both sides of the first sidewall structure 7 by a preset thickness. The difference between the thickness of the second sidewall structure 8 and the thickness of the first sidewall structure 9 after the trimming is a preset number of times the preset thickness. The width of the first conductive layer is the same as the thickness of the first sidewall structure after the trimming, and the width of the second conductive layer is the same as the thickness of the second sidewall structure.

[0196] 5) Using the modified first sidewall structure 9 and the second sidewall structure 8 as masks, etch the second mask layer to form a third patterned structure 10 on the first process area and a fourth patterned structure 11 on the second process area; the thickness of the third patterned structure 10 is less than the thickness of the fourth patterned structure 11. For example, the thickness of the third patterned structure 10 is S1-2Δd, and the thickness of the fourth patterned structure 11 is S1.

[0197] 6) A third sidewall structure 12 is formed on the sidewall of the third patterned structure 10, and the third patterned structure 10 is removed; a fourth sidewall structure 13 is formed on the sidewall of the fourth patterned structure 11, and the fourth patterned structure 11 is removed; the thickness of the third sidewall structure 12 is the same as the thickness of the fourth sidewall structure 13. For example, the thickness of the third sidewall structure 12 and the thickness of the fourth sidewall structure 13 are both S1.

[0198] 7) Using the third sidewall structure 12 and the fourth sidewall structure 13 as masks, the interlayer dielectric layer 1 is etched to form the first trench 14 in the first process area and the second trench 15 in the second process area.

[0199] 8) A first conductive layer (not shown) is formed in the first trench 14, and a second conductive layer (not shown) is formed in the second trench 15; the width of the first conductive layer is smaller than the width of the second conductive layer.

[0200] The following explanation, using the SAQP process as an example and citing multiple modifications to the sidewall structure, provides a comprehensive overview of the aforementioned formation method:

[0201] Continue as Figure 3 As shown, the method for forming the SAQP-based semiconductor structure may include:

[0202] 1) Provide a layer to be etched; the layer to be etched includes a first process region and a second process region; the first process region and the second process region have different design requirements for the conductive layer width. The layer to be etched includes a substrate, the substrate including an interlayer dielectric layer 1, a second mask layer 2, a core sacrificial layer 3 and a first mask layer 4 stacked sequentially from bottom to top.

[0203] 2) Pattern the first mask layer 4; using the patterned first mask layer as a mask, etch the core sacrificial layer 3 to form the first patterned structure 5 in the first process area and the second patterned structure 6 in the second process area.

[0204] 3) Remove the first mask layer 4; deposit a sidewall material layer on the sidewall and top surface of the first patterned structure 5, etch back the sidewall material layer on the top surface of the first patterned structure to form the first sidewall structure 7, and remove the first patterned structure 5; and deposit a sidewall material layer on the sidewall and top surface of the second patterned structure 6, etch back the sidewall material layer on the top surface of the second patterned structure to form the second sidewall structure 8, and remove the second patterned structure 6.

[0205] 4) The thickness of the first side wall structure 7 is adjusted so that the thickness of the adjusted first side wall structure 9 is less than the thickness of the second side wall structure 8.

[0206] 5) Using the modified first sidewall structure 9 and the second sidewall structure 8 as masks, the second mask layer 2 is etched to form a third patterned structure 10 on the first process area and a fourth patterned structure 11 on the second process area; the thickness of the third patterned structure 10 is less than the thickness of the fourth patterned structure 11.

[0207] 6) A third sidewall structure 12 is formed on the sidewall of the third patterned structure 10, and the third patterned structure 10 is removed; a fourth sidewall structure 13 is formed on the sidewall of the fourth patterned structure 11, and the fourth patterned structure 11 is removed; the thickness of the third sidewall structure 12 is the same as the thickness of the second sidewall structure 8.

[0208] 7) The thickness of the third side wall structure 12 is adjusted so that the thickness of the adjusted third side wall structure is less than the thickness of the fourth side wall structure 13.

[0209] 8) Using the modified third sidewall structure and the fourth sidewall structure as masks, etch the interlayer dielectric layer 1 to form the first trench in the first process area and the second trench in the second process area.

[0210] 9) A first conductive layer is formed in the first trench, and a second conductive layer is formed in the second trench; the width of the first conductive layer is smaller than the width of the second conductive layer.

[0211] The following explanation, using the SADP process as an example and a single-stage repair of the sidewall structure as an example, provides an overall description of the above-mentioned formation method:

[0212] Continue as Figure 4 As shown, the method for forming the SADP-based semiconductor structure may include:

[0213] 1) Provide a layer to be etched; the layer to be etched includes a first process region and a second process region; the first process region and the second process region have different design requirements for the conductive layer width. The layer to be etched includes a substrate, the substrate including an interlayer dielectric layer 1, a second mask layer 2, a core sacrificial layer 3 and a first mask layer 4 stacked sequentially from bottom to top.

[0214] 2) Pattern the first mask layer 4; using the patterned first mask layer as a mask, etch the core sacrificial layer 3 to form the first patterned structure 5 in the first process area and the second patterned structure 6 in the second process area.

[0215] 3) Remove the first mask layer 4; deposit a sidewall material layer on the sidewall and top surface of the first patterned structure 5, etch back the sidewall material layer on the top surface of the first patterned structure 5 to form the first sidewall structure 7, and remove the first patterned structure 5; and deposit a sidewall material layer on the sidewall and top surface of the second patterned structure 6, etch back the sidewall material layer on the top surface of the second patterned structure 6 to form the second sidewall structure 8, and remove the second patterned structure 6.

[0216] 4) The thickness of the first side wall structure 7 is adjusted so that the thickness of the adjusted first side wall structure 9 is less than the thickness of the second side wall structure 8.

[0217] 5) Using the modified first sidewall structure 9 and the second sidewall structure 8 as masks, the second mask layer 2 is etched to form a third patterned structure 10 on the first process area and a fourth patterned structure 11 on the second process area; the thickness of the third patterned structure 10 is less than the thickness of the fourth patterned structure 11.

[0218] 6) Using the third patterned structure 10 and the fourth patterned structure 11 as masks, the interlayer dielectric layer 1 is etched to form the first trench 14 in the first process area and the second trench 15 in the second process area.

[0219] 7) A first conductive layer is formed in the first trench, and a second conductive layer is formed in the second trench; the width of the first conductive layer is smaller than the width of the second conductive layer.

[0220] This application embodiment also provides a conductor structure, wherein the semiconductor structure is prepared by the above-described forming method, and the semiconductor structure includes:

[0221] The layer to be etched includes a first process area and a second process area, and the first process area and the second process area have different design requirements for the conductive layer width.

[0222] A first trench located within the first process area, and a second trench located within the second process area;

[0223] A first conductive layer is located within the first trench, and a second conductive layer is located within the second trench; the thickness of the first conductive layer is different from the width of the second conductive layer.

[0224] Optionally, the difference between the width of the second conductive layer and the thickness of the first conductive layer is a preset number of times the preset thickness.

[0225] Therefore, it is possible to obtain metal layers of different widths in different process regions of semiconductor structures, thereby solving the problem that the metal line size of different regions introduced by the sidewall auxiliary process cannot be designed separately, realizing the differentiated design of metal line size of different functional modules, and making the design of metal line size of different modules more flexible.

[0226] It should be noted that the above-described semiconductor structure and the above-described formal method are based on the same inventive concept.

[0227] This application also provides an electronic device, which includes the semiconductor structure described in any of the above embodiments.

[0228] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0229] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A layer to be etched is provided; the layer to be etched includes a first process region and a second process region; the first process region and the second process region have different design requirements for the conductive layer width; A first patterned structure is formed on the first process area, and a second patterned structure is formed on the second process area; A first sidewall structure is formed on the sidewall of the first patterned structure, and the first patterned structure is removed; a second sidewall structure is formed on the sidewall of the second patterned structure, and the second patterned structure is removed; the thickness of the first sidewall structure and the thickness of the second sidewall structure are different. The layer to be etched is etched using a first sidewall structure and a second sidewall structure with different thicknesses as masks, forming a first trench in the first process area and a second trench in the second process area; the width of the first trench is different from the width of the second trench. A first conductive layer is formed in the first trench, and a second conductive layer is formed in the second trench; the width of the first conductive layer is different from the width of the second conductive layer.

2. The forming method according to claim 1, characterized in that, The steps of forming a first sidewall structure on the sidewall of the first patterned structure and removing the first patterned structure, and forming a second sidewall structure on the sidewall of the second patterned structure and removing the second patterned structure, include: A first sidewall structure is formed on the sidewall of the first patterned structure, and the first patterned structure is removed; a second sidewall structure is formed on the sidewall of the second patterned structure, and the second patterned structure is removed; the thickness of the first sidewall is the same as the thickness of the second sidewall. After removing the second graphical structure, the method further includes: The thickness of the first sidewall structure is adjusted so that the thickness of the first sidewall structure is less than the thickness of the second sidewall structure, so that the thickness of the first sidewall structure is different from the thickness of the second sidewall structure.

3. The forming method according to claim 2, characterized in that, The etching process, using a first sidewall structure and a second sidewall structure of different thicknesses as masks, to etch the layer to be etched, forms a first trench in the first process area and a second trench in the second process area, including: Using the modified first sidewall structure and the second sidewall structure as masks, the layer to be etched is etched, forming a first trench in the first process area and a second trench in the second process area; the width of the first trench is smaller than the width of the second trench.

4. The forming method according to any one of claims 1 to 3, characterized in that, The step of forming a first conductive layer in the first trench and forming a second conductive layer in the second trench includes: A first conductive layer is formed in the first trench, and a second conductive layer is formed in the second trench; the width of the first conductive layer is smaller than the width of the second conductive layer.

5. The forming method according to claim 2, characterized in that, The finishing process includes etching, and the finishing process for the thickness of the first sidewall structure includes: The first sidewall structure is subjected to anisotropic etching.

6. The forming method according to claim 5, characterized in that, The anisotropic etching process performed on the first sidewall structure includes: The two sides of the first sidewall structure are simultaneously etched to reduce the thickness of the two sides of the first sidewall structure by a preset thickness. Wherein, the difference between the thickness of the second sidewall structure and the thickness of the first sidewall structure after the trimming is a preset number of times the preset thickness, the width of the first conductive layer is the same as the thickness of the first sidewall structure after the trimming, and the width of the second conductive layer is the same as the thickness of the second sidewall structure.

7. The forming method according to any one of claims 1 to 3, characterized in that, The layer to be etched includes a substrate, which includes, from bottom to top, an interlayer dielectric layer, a second mask layer, a core sacrificial layer, and a first mask layer stacked sequentially. The process of forming a first patterned structure on the first process area and forming a second patterned structure on the second process area includes: Graphicalize the first mask layer; Using the patterned first mask layer as a mask, the core sacrificial layer is etched to form the first patterned structure in the first process area and the second patterned structure in the second process area.

8. The forming method according to claim 7, characterized in that, The steps of forming a first sidewall structure on the sidewall of the first patterned structure and removing the first patterned structure, and forming a second sidewall structure on the sidewall of the second patterned structure and removing the second patterned structure, include: Remove the first mask layer; A sidewall material layer is deposited on the sidewall and top surface of the first patterned structure, the sidewall material layer on the top surface of the first patterned structure is etched back to form the first sidewall structure, and the first patterned structure is removed; and a sidewall material layer is deposited on the sidewall and top surface of the second patterned structure, the sidewall material layer on the top surface of the second patterned structure is etched back to form the second sidewall structure, and the second patterned structure is removed.

9. The forming method according to claim 7, characterized in that, The etching process, using a first sidewall structure and a second sidewall structure of different thicknesses as masks, to etch the layer to be etched, forming a first trench in the first process area and a second trench in the second process area, includes: Using a first sidewall structure and a second sidewall structure of different thicknesses as masks, the second mask layer is etched to form a third patterned structure on the first process area and a fourth patterned structure on the second process area; the thickness of the third patterned structure is different from the thickness of the fourth patterned structure. A third sidewall structure is formed on the sidewall of the third patterned structure, and the third patterned structure is removed; a fourth sidewall structure is formed on the sidewall of the fourth patterned structure, and the fourth patterned structure is removed; the thickness of the third sidewall structure is the same as the thickness of the second sidewall. Using the third sidewall structure and the fourth sidewall structure as masks, the interlayer dielectric layer is etched to form the first trench in the first process area and the second trench in the second process area.

10. The forming method according to claim 9, characterized in that, The first sidewall structure and the second sidewall structure with different thicknesses are obtained by adjusting the thickness of the first sidewall structure formed on the sidewall of the first patterned structure. The thickness of the first sidewall structure after adjustment is smaller than the thickness of the second sidewall structure. The process of etching the second mask layer using the first and second sidewall structures of different thicknesses as masks to form a third patterned structure on the first process area and a fourth patterned structure on the second process area includes: Using the modified first sidewall structure and the second sidewall structure as masks, the second mask layer is etched to form a third patterned structure on the first process area and a fourth patterned structure on the second process area; the thickness of the third patterned structure is less than the thickness of the fourth patterned structure.

11. The forming method according to claim 9, characterized in that, The process of forming a third sidewall structure on the sidewall of the third patterned structure and removing the third patterned structure, and forming a fourth sidewall structure on the sidewall of the fourth patterned structure and removing the fourth patterned structure, includes: A sidewall material layer is deposited on the sidewalls and top surface of the third patterned structure, the sidewall material layer on the top surface of the third patterned structure is etched back to form the third sidewall structure, and the third patterned structure is removed; and a sidewall material layer is deposited on the sidewalls and top surface of the fourth patterned structure, the sidewall material layer on the top surface of the fourth patterned structure is etched back to form the fourth sidewall structure, and the fourth patterned structure is removed.

12. The forming method according to claim 9, characterized in that, After forming a third sidewall structure on the sidewall of the third patterned structure and removing the third patterned structure, and after forming a fourth sidewall structure on the sidewall of the fourth patterned structure and removing the fourth patterned structure, the method further includes: The thickness of the third sidewall structure is adjusted so that the thickness of the adjusted third sidewall structure is less than the thickness of the fourth sidewall structure; the step of etching the interlayer dielectric layer using the third and fourth sidewall structures as masks to form the first trench in the first process area and the second trench in the second process area includes: Using the modified third sidewall structure and the fourth sidewall structure as masks, the interlayer dielectric layer is etched to form the first trench in the first process area and the second trench in the second process area.

13. The forming method according to claim 7, characterized in that, The etching process, using a first sidewall structure and a second sidewall structure of different thicknesses as masks, to etch the layer to be etched, forming a first trench in the first process area and a second trench in the second process area, includes: Using a first sidewall structure and a second sidewall structure of different thicknesses as masks, the second mask layer is etched to form a third patterned structure on the first process area and a fourth patterned structure on the second process area; the thickness of the third patterned structure is different from the thickness of the fourth patterned structure. The interlayer dielectric layer is etched using the third and fourth patterned structures as masks to form the first trench in the first process region and the second trench in the second process region.

14. The forming method according to claim 13, characterized in that, The first sidewall structure and the second sidewall structure with different thicknesses are obtained by adjusting the thickness of the first sidewall structure formed on the sidewall of the first patterned structure. The thickness of the first sidewall structure after adjustment is smaller than the thickness of the second sidewall structure. The process of etching the second mask layer using the first and second sidewall structures of different thicknesses as masks to form a third patterned structure on the first process area and a fourth patterned structure on the second process area includes: Using the modified first sidewall structure and the second sidewall structure as masks, the second mask layer is etched to form a third patterned structure on the first process area and a fourth patterned structure on the second process area; the thickness of the third patterned structure is less than the thickness of the fourth patterned structure.

15. The forming method according to any one of claims 1 to 3, characterized in that, The first process area is a low-power standard cell library in the standard cell area, and the second process area is a high-performance standard cell library in the standard cell area.

16. The forming method according to any one of claims 1 to 3, characterized in that, The first process area is a standard unit area, and the second process area is a non-standard unit area.

17. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the formation method according to any one of claims 1 to 16, and the semiconductor structure comprises: The layer to be etched includes a first process area and a second process area, and the first process area and the second process area have different design requirements for the conductive layer width. A first trench located within the first process area, and a second trench located within the second process area; A first conductive layer is located within the first trench, and a second conductive layer is located within the second trench; the thickness of the first conductive layer is different from the width of the second conductive layer.

18. The semiconductor structure according to claim 17, characterized in that, The difference between the width of the second conductive layer and the thickness of the first conductive layer is a preset number of times the preset thickness.

19. An electronic device, characterized in that, The electronic device includes the semiconductor structure as described in claim 17 or 18.

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