Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method of the semiconductor device, multiple layers of metal wires are arranged on a semiconductor substrate, the metal wires are used for being connected with a device structure formed on the semiconductor substrate, different layers of metal wires are electrically connected through contact holes, and gaps of each layer of metal wires are filled with dielectric layers. The multi-layer metal wiring comprises top layer metal; the composite passivation layer is coated on the top-layer metal and sequentially comprises a silicon-rich silicon oxide layer, a high-density plasma chemical vapor deposition oxide layer, a ground plasma enhanced chemical vapor deposition oxide layer and a silicon nitride layer from bottom to top; the total thickness of the silicon-rich silicon oxide layer, the high-density plasma chemical vapor deposition oxide layer and the ground plasma enhanced chemical vapor deposition oxide layer is greater than or equal to the thickness of the top metal. According to the invention, the damage to the semiconductor device can be reduced, the cracking problem can be avoided, and the reliability of the device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, and more specifically, to a semiconductor device and a method for manufacturing the semiconductor device. Background Technology

[0002] In integrated circuit manufacturing, after the downstream metal wiring is completed, a passivation layer is formed to protect the upstream semiconductor devices from external environmental corrosion and electrical interference, thereby ensuring long-term stable operation of the devices and optimizing their electrical performance and lifespan.

[0003] As the thickness of the top metal increases and the integration density of devices improves, composite passivation layer structures, including high-density plasma chemical vapor deposition (HDP CVD) technology, are widely used to ensure intermetallic filling. However, HDP CVD relies on high-energy ion bombardment to fill the gaps. High-energy ions can easily penetrate the surface structure and damage the underlying semiconductor device, causing reliability risks such as leakage and performance drift. On the other hand, due to its own stress characteristics, the nitride layer is prone to stress concentration in non-flat areas, leading to cracking. This damages the barrier and protection function of the passivation layer, allowing external contaminants to enter the device and ultimately affecting the stability and lifespan of the device, making it difficult to meet the application requirements of high-reliability semiconductor devices. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a semiconductor device and a method for manufacturing a semiconductor device, which can not only reduce the damage to the semiconductor device caused by plasma generated by high-density plasma chemical vapor deposition, but also avoid the cracking problem caused by stress in non-flat or stepped areas of traditional passivation layers, thus helping to improve device reliability.

[0005] In a first aspect, embodiments of this application provide a semiconductor device, including: a semiconductor substrate, multilayer metal wiring, multilayer dielectric layers, and a composite passivation layer; A multilayer metal wiring is provided on the semiconductor substrate. The metal wiring is used to connect device structures formed on the semiconductor substrate. Different layers of metal wiring are electrically connected through contact holes. The gaps between each layer of metal wiring are filled by the dielectric layer. The multilayer metal wiring includes a top metal layer. The composite passivation layer is coated on the top metal. The composite passivation layer comprises, from bottom to top: a silicon-rich silicon oxide layer, a high-density plasma chemical vapor deposition oxide layer, a polished plasma-enhanced chemical vapor deposition oxide layer, and a silicon nitride layer. The total thickness of the silicon-rich silicon oxide layer, the high-density plasma chemical vapor deposition oxide layer, and the polished plasma-enhanced chemical vapor deposition oxide layer in the composite passivation layer is greater than or equal to the thickness of the top metal.

[0006] In one optional embodiment, the thickness of the top layer metal is between 0.9 μm and 4 μm.

[0007] In one optional embodiment, the silicon-rich silicon oxide layer is deposited on the top metal by plasma-enhanced chemical vapor deposition, and the thickness of the silicon-rich silicon oxide layer is between 300 Å and 600 Å.

[0008] In one optional embodiment, the high-density plasma chemical vapor deposition oxide layer is deposited on the silicon-rich silicon oxide layer, and the thickness of the high-density plasma chemical vapor deposition oxide layer is between 0.9 μm and 1.1 μm.

[0009] In one optional embodiment, the polished plasma-enhanced chemical vapor deposition oxide layer is deposited on the high-density plasma-enhanced chemical vapor deposition oxide layer, and the thickness of the polished plasma-enhanced chemical vapor deposition oxide layer is between 0 and 2 μm; wherein, the thickness of the plasma-enhanced chemical vapor deposition oxide layer before polishing is greater than or equal to 1 μm.

[0010] In one optional embodiment, the silicon nitride layer is deposited on the polished plasma-enhanced chemical vapor deposition oxide layer by a plasma-enhanced chemical vapor deposition process, and the thickness of the silicon nitride layer is between 0.3 μm and 1 μm.

[0011] In one optional embodiment, the dielectric layer includes silicon-rich silicon oxide, a high-density plasma chemical vapor deposition oxide layer, and a plasma-enhanced chemical vapor deposition oxide layer.

[0012] In one optional embodiment, the semiconductor substrate is made of single-crystal silicon or a compound semiconductor, wherein the compound semiconductor is SiC or GaAs; And / or, the material of the top layer metal is aluminum, copper, or an aluminum-copper alloy.

[0013] Secondly, embodiments of this application also provide a method for manufacturing a semiconductor device, comprising: Multiple dielectric layers are sequentially formed on a semiconductor substrate. A metal layer is formed in each dielectric layer by physical vapor deposition. The metal layer is patterned into metal wiring by photolithography. Contact holes are formed in the dielectric layers to connect the metal wiring layers. The metal wiring includes a top metal layer. A composite passivation layer is formed on the top metal; wherein, the composite passivation layer comprises, from bottom to top: a silicon-rich silicon oxide layer, a high-density plasma chemical vapor deposition oxide layer, a polished plasma-enhanced chemical vapor deposition oxide layer, and a silicon nitride layer, wherein the total thickness of the silicon-rich silicon oxide layer, the high-density plasma chemical vapor deposition oxide layer, and the polished plasma-enhanced chemical vapor deposition oxide layer in the composite passivation layer is greater than or equal to the thickness of the top metal.

[0014] In one optional embodiment, the step of forming a composite passivation layer on the top metal includes: A silicon-rich silicon oxide layer is deposited on the surface of the top metal and dielectric layer using a plasma-enhanced chemical vapor deposition process, so that the silicon-rich silicon oxide layer covers the top metal, and the thickness of the silicon-rich silicon oxide layer is between 300 Å and 600 Å. An oxide layer is deposited on the silicon-rich silicon oxide layer using a high-density plasma chemical vapor deposition (PDCVD) process to obtain a high-density plasma chemical vapor deposition oxide layer with a thickness between 0.9 μm and 1.1 μm. A silicon dioxide layer is deposited on the high-density plasma chemical vapor deposition oxide layer using a plasma-enhanced chemical vapor deposition process to obtain a plasma-enhanced chemical vapor deposition oxide layer, wherein the initial thickness of the plasma-enhanced chemical vapor deposition oxide layer is greater than or equal to 1 μm. The plasma-enhanced chemical vapor deposition oxide layer is subjected to chemical mechanical polishing so that the thickness of the polished plasma-enhanced chemical vapor deposition oxide layer is between 0 and 2 μm. A silicon nitride layer is deposited on a polished plasma-enhanced chemical vapor deposition oxide layer using a plasma-enhanced chemical vapor deposition process. The thickness of the silicon nitride layer is between 0.3 μm and 1 μm.

[0015] The semiconductor device and its manufacturing method provided in this application construct a multilayer dielectric layer and metal wiring with a specific structure on a semiconductor substrate, and form a composite passivation layer composed of a silicon-rich silicon oxide layer, a high-density plasma chemical vapor deposition oxide layer, a polished plasma-enhanced chemical vapor deposition oxide layer, and a silicon nitride layer. The total thickness of the specific oxide layer in the composite passivation layer is controlled to be no less than the thickness of the top metal layer. On the one hand, the characteristics of the silicon-rich silicon oxide layer can be used to repair metal etching damage and buffer stress. The excellent gap filling ability of the high-density plasma chemical vapor deposition oxide layer ensures the metal gap filling effect. The polished plasma-enhanced chemical vapor deposition oxide layer and silicon nitride layer further improve passivation protection, effectively reducing the damage of plasma generated by high-density plasma chemical vapor deposition to semiconductor devices. On the other hand, the reasonable layer thickness design avoids the cracking problem caused by stress in non-flat or stepped areas of the traditional passivation layer, significantly improving device reliability.

[0016] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figure 2 This is one of the process schematic diagrams of a semiconductor device provided in an embodiment of this application; Figure 3 This is a second schematic diagram of the process of a semiconductor device provided in an embodiment of this application; Figure 4 This is a third schematic diagram of the process of a semiconductor device provided in an embodiment of this application; Figure 5 This is the fourth schematic diagram of the process of a semiconductor device provided in the embodiments of this application; Figure 6 Fifth schematic diagram of the process of a semiconductor device provided in the embodiments of this application; Figure 7 A flowchart illustrating a method for manufacturing a semiconductor device as provided in this application embodiment; Figure 8This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0019] Figure reference numerals: 101-Semiconductor substrate; 201-Dielectric layer; 301-Metal wiring; 302-Top metal; 303-Contact hole; 401-Silicon-rich silicon oxide layer; 402-High-density plasma chemical vapor deposition oxide layer; 403-Polished plasma-enhanced chemical vapor deposition oxide layer; 404-Silicon nitride layer. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0021] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. Figure 1 As shown in the figure, the semiconductor device provided in the embodiments of this application includes: a semiconductor substrate 101, a multilayer metal wiring 301, a multilayer dielectric layer 201, and a composite passivation layer; A multilayer metal wiring 301 is provided on a semiconductor substrate 101. The metal wiring 301 is used to connect device structures formed on the semiconductor substrate 101. Different layers of metal wiring 301 are electrically connected through contact holes 303. The gap between each layer of metal wiring 301 is filled by a dielectric layer 201. The multilayer metal wiring 301 includes a top metal layer 302. A composite passivation layer is coated on the top metal 302. The composite passivation layer includes, from bottom to top, a silicon-rich silicon oxide layer 401, a high-density plasma chemical vapor deposition oxide layer 402, a polished plasma-enhanced chemical vapor deposition oxide layer 403, and a silicon nitride layer 404. The total thickness of the silicon-rich silicon oxide layer 401, the high-density plasma chemical vapor deposition oxide layer 402, and the polished plasma-enhanced chemical vapor deposition oxide layer 403 in the composite passivation layer is greater than or equal to the thickness of the top metal 302.

[0022] Specifically, such as Figure 2As shown, the semiconductor substrate 101 is the base used to support the various structures of the semiconductor device and is the basic carrier for semiconductor device manufacturing. In an optional embodiment, the semiconductor substrate 101 needs to have good semiconductor properties and structural stability to ensure the formation of subsequent layers and the realization of device functions. Optionally, the semiconductor substrate 101 is made of single-crystal silicon or compound semiconductor, with the compound semiconductor being SiC or GaAs. For example, a single-crystal silicon substrate can be selected as the semiconductor substrate, as single-crystal silicon has excellent electrical properties and mature processing technology compatibility; a compound semiconductor substrate, such as a silicon carbide (SiC) substrate or a gallium arsenide (GaAs) substrate, can also be selected. Among these, silicon carbide substrates are suitable for high-temperature, high-frequency, and high-power semiconductor device applications, while gallium arsenide substrates have advantages in the fields of radio frequency devices and optoelectronic devices.

[0023] The multilayer dielectric layer 201 is an insulating layer structure formed on the semiconductor substrate 101 to isolate different metal wirings 301 and provide structural support. Exemplarily, the gaps between each metal wiring 301 are filled by the dielectric layer 201. The multilayer dielectric layer 201 can possess good insulation, flatness, and gap-filling capability to achieve electrical isolation between the metal wirings 301 and ensure the stability of the overall device structure. Optionally, the multilayer dielectric layer 201 can adopt a composite dielectric layer structure, with each dielectric layer 201 including silicon-rich silicon oxide (SRO), a high-density plasma chemical vapor deposition (HDP CVD) oxide layer, and a plasma-enhanced chemical vapor deposition (PECVD) oxide layer. Here, the silicon-rich silicon oxide layer 401 can enhance the adhesion between the dielectric layer 201 and the metal layer, the high-density plasma chemical vapor deposition oxide layer 402 can effectively fill the gaps in the dielectric layer 201, and the plasma-enhanced chemical vapor deposition oxide layer can optimize the flatness and insulation performance of the dielectric layer 201. During the formation process, multiple dielectric layers 201 can be formed sequentially through multiple deposition and planarization processes. The thickness of each dielectric layer 201 can be determined according to the device design requirements, and is generally controlled in the range of hundreds of nanometers to several micrometers.

[0024] Optionally, the metal wiring 301 is a metal line formed within the dielectric layer 201 through photolithography and etching processes, used to connect various structures of the semiconductor device and transmit electrical signals. Specifically, the metal wiring 301 has good conductivity, low resistance, and a regular pattern structure to ensure efficient transmission of electrical signals and effective connection between various device structures, such as the metal wiring 301 used to connect device structures formed on the semiconductor substrate 101. For example, the width and spacing of the metal wiring 301 are determined according to the device integration requirements. In high-integration devices, the width and spacing of the metal wiring 301 can be controlled within the range of tens to hundreds of nanometers. The routing and distribution of the metal wiring 301 need to be based on the circuit design of the semiconductor device to ensure that the predetermined electrical connection between active devices such as transistors, resistors, and capacitors and passive devices can be achieved. In the multilayer dielectric layer 201 structure, metal wiring 301 is formed within each dielectric layer 201. The metal wiring 301 of different layers is electrically connected through contact holes 303 formed subsequently, together forming the electrical transmission network of the device.

[0025] It should be noted that a metal layer is formed within the dielectric layer 201 using a physical vapor deposition process. This metal layer is used for subsequent etching of the metal wiring 301. Specifically, the metal layer needs to possess good conductivity, processability, and stability to ensure that the subsequently formed metal wiring 301 can effectively transmit electrical signals and operate reliably for a long period. For example, an aluminum metal layer can be used, as aluminum has low resistivity and mature processing technology, and its cost is relatively low, making it suitable for semiconductor devices with low to medium performance requirements. Alternatively, a copper metal layer or an aluminum-copper alloy layer can be used. Copper has lower resistivity than aluminum and superior conductivity, making it suitable for high-performance, highly integrated devices. The aluminum-copper alloy layer, while maintaining the processing advantages of aluminum, enhances the metal layer's resistance to electromigration and mechanical strength by adding copper, thus extending the device's lifespan.

[0026] In this process, the metal wiring pattern 301 is transferred to the surface of the metal layer using photolithography, and then the metal wiring 301 is formed through etching. Here, the photolithography process needs to have high resolution and pattern transfer accuracy to achieve fine patterning of the metal wiring 301 and meet the requirements of high device integration. During the etching process, the etching rate and etching time must be precisely controlled to avoid over-etching that damages the dielectric layer 201 or incomplete etching that results in residual metal wiring 301.

[0027] Furthermore, such as Figure 2As shown, the top metal 302 is the uppermost metal line in the metal wiring 301, and is the outermost structure of the metal wiring 301 system, directly contacting the subsequently formed composite passivation layer. Optionally, the top metal 302 needs to have sufficient thickness and structural integrity to withstand the process influences during the formation of the subsequent composite passivation layer and ensure good contact with the passivation layer. For example, the thickness S1 of the top metal 302 is designed to be 0.9µm~4µm. This thickness range of S1 can meet the current carrying capacity requirements of the device for the top metal 302, and also adapt to the coverage and protection requirements of the subsequent composite passivation layer. The material of the top metal 302 can be the same as other layers of metal wiring 301, such as aluminum, or copper with better performance, or an aluminum-copper alloy, depending on the requirements. During the formation process, by adjusting the physical vapor deposition process parameters, the uniformity and density of the thickness of the top metal 302 are ensured, avoiding incomplete coverage of the subsequent passivation layer due to uneven thickness or defects.

[0028] Optionally, the contact hole 303 is a hole-like structure formed in the dielectric layer 201 to achieve electrical connection between different layers of metal wiring 301. Specifically, the contact hole 303 can have precise positional accuracy, suitable aperture and good conductive filling effect to ensure reliable electrical connection between different layers of metal wiring 301. For example, when forming the contact hole 303, the pattern of the contact hole 303 is first defined on the dielectric layer 201 by photolithography. Then, the dielectric layer 201 is etched by dry etching to form the contact hole 303. The diameter of the contact hole 303 is determined according to the spacing of the metal wiring 301 and the connection requirements, and is generally in the range of several hundred nanometers. After etching, a barrier layer, such as titanium or titanium nitride, and a seed layer, such as a copper seed layer, are deposited on the inner wall of the contact hole 303 and the surface of the dielectric layer 201 by physical vapor deposition or chemical vapor deposition. The barrier layer can prevent metal atoms from diffusing into the dielectric layer 201, and the seed layer provides a basis for subsequent metal filling. Finally, the contact hole 303 is filled with metal, such as copper, by electroplating and planarization is performed to form a good electrical connection between the contact hole 303 and the upper and lower metal wiring 301.

[0029] Furthermore, the composite passivation layer is a multilayer composite structure that coats the top metal 302 of the semiconductor device to protect the semiconductor device and optimize its performance. From bottom to top, it includes: a silicon-rich silicon oxide layer 401, a high-density plasma-enhanced chemical vapor deposition oxide layer 402, a polished plasma-enhanced chemical vapor deposition oxide layer 403, and a silicon nitride layer 404. This can solve the defect problems of traditional passivation layers, such as HDP CVD damage and nitride layer cracking. The layers work synergistically, as detailed below: like Figure 3As shown, the silicon-rich silicon oxide layer 401 refers to a silicon oxide thin film layer rich in silicon elements, serving as the bottom layer of the composite passivation layer, and is formed on the surface of the top metal 302 and the dielectric layer 201 through a plasma-enhanced chemical vapor deposition (PECVD) process. In an optional embodiment, the silicon-rich silicon oxide layer 401 needs to possess good adhesion, stress buffering capacity, and metal damage repair function to enhance the bonding force between subsequent layers and the top metal 302, alleviate interlayer stress, and repair etching damage generated during the patterning process of the top metal 302. For example, the silicon content in the silicon-rich silicon oxide layer 401 is slightly higher than that in ordinary silicon oxide, and its refractive index and dielectric constant also differ from those of ordinary silicon oxide. This compositional characteristic makes its coefficient of thermal expansion closer to that of the metal layer, effectively buffering the thermal stress between the subsequent deposited layers and the metal layer; at the same time, the deposition process of the silicon-rich silicon oxide layer 401 can fill the tiny pits and defects on the surface of the top metal 302 caused by etching, achieving metal damage repair and ensuring the integrity of the surface of the top metal 302.

[0030] Furthermore, the thickness S2 of the silicon-rich silicon oxide layer 401 can be controlled between 300 Å and 600 Å. This thickness S2 can meet the above functional requirements without increasing the overall cost and process complexity of the device due to excessive thickness.

[0031] like Figure 4 As shown, the high-density plasma chemical vapor deposition (PDCVD) oxide layer 402 refers to a thin film of silicon oxide formed on the silicon-rich silicon oxide layer 401 by a PDCVD process. It is an important gap-filling and insulating layer in the composite passivation layer. In an optional embodiment, the PDCVD oxide layer 402 needs to have good gap-filling integrity, insulation, and structural stability to achieve complete filling of the gaps in the top metal 302 and ensure the insulating protection effect of the passivation layer. For example, in scenarios where the gap width of the top metal 302 is several hundred nanometers, the PDCVD oxide layer 402 can completely fill the gaps without voids or pores, effectively preventing external moisture and ions from entering the device through the gaps.

[0032] Furthermore, the thickness S3 of the high-density plasma chemical vapor deposition oxide layer 402 can be controlled between 0.9 μm and 1.1 μm. This thickness S3 ensures complete coverage of the silicon-rich silicon oxide layer 401 and sufficient filling of the gaps, while also cooperating with the subsequent plasma-enhanced chemical vapor deposition oxide layer to meet the design requirements for the total thickness of the composite passivation layer. Preferably, the thickness S3 of the high-density plasma chemical vapor deposition oxide layer 402 is approximately 1 μm.

[0033] like Figure 6As shown, the polished plasma-enhanced chemical vapor deposition oxide layer 403 is a silicon dioxide layer that has undergone chemical mechanical polishing, and it is a key layer in the composite passivation layer for achieving a planarized surface. Specifically, the polished plasma-enhanced chemical vapor deposition oxide layer 403 possesses good planarity, uniform thickness, and a complete structure to ensure the uniform deposition of the subsequent silicon nitride layer 404 and the overall protective effect of the passivation layer. For example, the surface roughness of the polished oxide layer needs to be controlled within a few nanometers to ensure that the silicon nitride layer 404 can uniformly cover its surface and avoid uneven thickness of the silicon nitride layer 404 due to surface irregularities.

[0034] Furthermore, the thickness S4b of the plasma-enhanced chemical vapor deposition oxide layer 403 after grinding can be controlled between 0 and 2 μm according to the device design requirements. If the initial thickness of the initial deposition is large, the grinding amount can be appropriately increased to make the remaining thickness close to the lower limit, so as to reduce the overall thickness of the device. If it is necessary to enhance the insulation performance, a thicker oxide layer can be retained. At the same time, the grinding process should avoid excessive grinding, which may expose or damage the underlying high-density plasma-enhanced chemical vapor deposition oxide layer 402, and ensure the integrity of each layer structure.

[0035] In the embodiments of this application, such as Figure 5 As shown, before grinding, a silicon dioxide layer is deposited on the high-density plasma chemical vapor deposition oxide layer 402 using a plasma-enhanced chemical vapor deposition process to obtain a plasma-enhanced chemical vapor deposition oxide layer 4031. The initial thickness S4a of the plasma-enhanced chemical vapor deposition oxide layer 4031 is greater than or equal to 1 μm.

[0036] The silicon dioxide layer is a thin film mainly composed of silicon dioxide, formed on the high-density plasma-enhanced chemical vapor deposition (PDCVD) oxide layer 402 using plasma-enhanced chemical vapor deposition (PECVD). It represents an initial morphology. Due to its good flatness and sufficient thickness margin, the silicon dioxide layer provides a foundation for subsequent polishing processes, while further enhancing the insulation performance and structural integrity of the composite passivation layer. For example, the initial thickness S4a of the silicon dioxide layer is set to be greater than or equal to 1 μm. This thickness margin ensures that surface protrusions and defects can be removed during subsequent polishing, resulting in a flat polished surface. Simultaneously, it ensures that the remaining oxide layer thickness after polishing meets the insulation and protection requirements. Because the gap-filling capability of plasma-enhanced chemical vapor deposition is weaker than that of high-density plasma-enhanced chemical vapor deposition, tiny cracks may form on the surface of the silicon dioxide layer during deposition. However, practical experience has shown that these tiny cracks do not affect the electrical performance of the chip or the protective effect of the passivation layer, requiring no additional treatment.

[0037] Furthermore, the plasma-enhanced chemical vapor deposition oxide layer 4031 is subjected to chemical mechanical polishing to control the thickness S4b of the polished plasma-enhanced chemical vapor deposition oxide layer 403 to be between 0 and 2 μm.

[0038] Chemical mechanical polishing (CMP) refers to a process that combines chemical etching and mechanical polishing to planarize the surface of a plasma-enhanced chemical vapor deposition (PECVD) oxide layer. This process requires high-precision thickness control and excellent planarization to precisely control the oxide layer thickness after polishing, ensuring the oxide surface meets the flatness requirements of subsequent device processes. For example, a dedicated polishing pad and slurry are used. The slurry contains silicon oxide abrasive particles and a chemical etchant. The abrasive particles mechanically remove protrusions from the oxide layer surface, while the chemical etchant reacts with the oxide layer, making surface substances easier to remove. The thickness change during polishing is monitored in real time, and polishing is stopped when the oxide layer thickness reaches 0-2 μm. After polishing, the device surface must be cleaned to remove residual polishing slurry and abrasive particles, preventing contamination of subsequent processes.

[0039] like Figure 1 As shown, the silicon nitride layer 404 is a thin film layer mainly composed of silicon nitride, formed on the polished plasma-enhanced chemical vapor deposition oxide layer 403 by a plasma-enhanced chemical vapor deposition process. It is the outermost protective structure of the composite passivation layer. Here, the silicon nitride layer 404 has excellent barrier properties, moisture resistance, and mechanical strength to prevent external ions, such as sodium ions and heavy metal ions, from penetrating the device, preventing water vapor and moisture from corroding the device, and providing mechanical protection against external force damage during subsequent packaging and use. For example, when depositing the silicon nitride layer 404, silane and ammonia are selected as the reaction gases. Under plasma activation, a chemical reaction occurs to generate silicon nitride, and the deposition temperature is controlled at 300℃~450℃ to ensure the compactness of the silicon nitride layer 404. Furthermore, the thickness S5 of the silicon nitride layer 404 can be set between 0.3um and 1um. Preferably, the thickness S5 of the silicon nitride layer 404 is set to 0.5um. This thickness S5 can achieve good barrier and protection functions, and can also avoid the risk of cracking caused by increased interlayer stress due to excessive thickness S5.

[0040] Among them, the total thickness (S2+S3+S4b) of the silicon-rich silicon oxide layer 401, the high-density plasma chemical vapor deposition oxide layer 402, and the polished plasma-enhanced chemical vapor deposition oxide layer 403 in the composite passivation layer is greater than or equal to the thickness S1 of the top metal 302, which can ensure that the composite passivation layer completely covers the top metal 302, effectively relieves stress, and achieves comprehensive protection.

[0041] In an optional embodiment, this thickness relationship can be precisely controlled according to the actual thickness of the top metal 302 to ensure that the composite passivation layer fully covers and protects the top metal 302. For example, if the thickness S1 of the top metal 302 is 0.9 μm, the thickness S2 of the silicon-rich oxide layer 401 can be 400 Å (0.04 μm), the thickness S3 of the high-density plasma chemical vapor deposition oxide layer 402 can be 1 μm, and the thickness S4b of the polished plasma-enhanced chemical vapor deposition oxide layer 403 can be 0.1 μm, the total thickness of the three is 0.04 μm + 1 μm + 0.1 μm = 1.14 μm, which is greater than the thickness S1 of the top metal 302 (0.9 μm); if the thickness S1 of the top metal 302 is 4 μm, the thickness S2 of the silicon-rich oxide layer 401 can be 600 Å (0.06 μm), the thickness S3 of the high-density plasma chemical vapor deposition oxide layer 402 can be 1 μm, and the thickness S4b of the polished plasma-enhanced chemical vapor deposition oxide layer 402 ... The thickness S3 can be 1.1µm, and the thickness S4b of the polished plasma-enhanced chemical vapor deposition oxide layer 403 can be 2µm. The total thickness of the three is 0.06µm + 1.1µm + 2µm = 3.16µm. At this point, the thickness S4b of the polished plasma-enhanced chemical vapor deposition oxide layer 403 can be appropriately increased to 2.84µm, so that the total thickness reaches 0.06µm + 1.1µm + 2.84µm = 4µm, which is equal to the thickness S1 (4µm) of the top metal 302. Through this thickness matching design, the edge of the top metal can be exposed due to the passivation layer being too thin, or the thickness being insufficient to resist external corrosion and relieve stress, thus ensuring the long-term reliability of the device.

[0042] This application embodiment constructs a multilayer dielectric layer and metal wiring with a specific structure on a semiconductor substrate, forming a composite passivation layer composed of a silicon-rich silicon oxide layer, a high-density plasma chemical vapor deposition (PDCVD) oxide layer, a polished PDCVD oxide layer, and a silicon nitride layer. The total thickness of the specific oxide layer in the composite passivation layer is controlled to be no less than the thickness of the top metal layer. On the one hand, the characteristics of the silicon-rich silicon oxide layer can be used to repair metal etching damage and buffer stress. The excellent gap-filling ability of the PDCVD oxide layer ensures the metal gap filling effect. The polished PDCVD oxide layer and silicon nitride layer further improve passivation protection, effectively reducing the damage to semiconductor devices caused by plasma generated during PDCVD. On the other hand, the reasonable layer thickness design avoids the cracking problem caused by stress in non-flat or stepped areas of the traditional passivation layer, significantly improving device reliability.

[0043] Secondly, such as Figure 7 As shown, this application provides a method for manufacturing a semiconductor device, including: S701. Multiple dielectric layers are sequentially formed on a semiconductor substrate. A metal layer is formed in each dielectric layer by physical vapor deposition. The metal layer is patterned into metal wiring by photolithography. Contact holes are formed in the dielectric layers to connect the metal wiring layers. The metal wiring includes the top metal layer. S702. A composite passivation layer is formed on the top metal; wherein, the composite passivation layer comprises, from bottom to top, a silicon-rich silicon oxide layer, a high-density plasma chemical vapor deposition oxide layer, a polished plasma-enhanced chemical vapor deposition oxide layer, and a silicon nitride layer, and the total thickness of the silicon-rich silicon oxide layer, the high-density plasma chemical vapor deposition oxide layer, and the polished plasma-enhanced chemical vapor deposition oxide layer in the composite passivation layer is greater than or equal to the thickness of the top metal.

[0044] In one optional embodiment, step S702 specifically includes: A silicon-rich silicon oxide layer is deposited on the surface of the top metal and dielectric layer using a plasma-enhanced chemical vapor deposition process, so that the silicon-rich silicon oxide layer covers the top metal, and the thickness of the silicon-rich silicon oxide layer is between 300 Å and 600 Å. An oxide layer is deposited on the silicon-rich silicon oxide layer using a high-density plasma chemical vapor deposition (PDCVD) process to obtain a high-density plasma chemical vapor deposition oxide layer with a thickness between 0.9 μm and 1.1 μm. A silicon dioxide layer is deposited on the high-density plasma chemical vapor deposition oxide layer using a plasma-enhanced chemical vapor deposition process to obtain a plasma-enhanced chemical vapor deposition oxide layer, wherein the initial thickness of the plasma-enhanced chemical vapor deposition oxide layer is greater than or equal to 1 μm. The plasma-enhanced chemical vapor deposition oxide layer is subjected to chemical mechanical polishing so that the thickness of the polished plasma-enhanced chemical vapor deposition oxide layer is between 0 and 2 μm. A silicon nitride layer is deposited on a polished plasma-enhanced chemical vapor deposition oxide layer using a plasma-enhanced chemical vapor deposition process. The thickness of the silicon nitride layer is between 0.3 μm and 1 μm.

[0045] Here, the description of the manufacturing method for semiconductor devices can be found above. Figures 1 to 6 The semiconductor device described herein can achieve the same technical effect, and will not be elaborated further.

[0046] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 8 As shown, the electronic device 800 includes a processor 810, a memory 820, and a bus 830.

[0047] The memory 820 stores machine-readable instructions executable by the processor 810. When the electronic device 800 is running, the processor 810 and the memory 820 communicate via the bus 830. When the machine-readable instructions are executed by the processor 810, they can perform the operations described above. Figure 7 The steps of the semiconductor device manufacturing method in the illustrated method embodiment can be found in the method embodiment for specific implementation, and will not be repeated here.

[0048] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 7 The steps of the semiconductor device manufacturing method in the illustrated method embodiment can be found in the method embodiment for specific implementation, and will not be repeated here.

[0049] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0050] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0051] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0052] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0053] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0054] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate, multilayer metal wiring, multilayer dielectric layer and composite passivation layer; A multilayer metal wiring is provided on the semiconductor substrate. The metal wiring is used to connect device structures formed on the semiconductor substrate. Different layers of metal wiring are electrically connected through contact holes. The gaps between each layer of metal wiring are filled by the dielectric layer. The multilayer metal wiring includes a top metal layer. The composite passivation layer is coated on the top metal. The composite passivation layer comprises, from bottom to top: a silicon-rich silicon oxide layer, a high-density plasma chemical vapor deposition oxide layer, a polished plasma-enhanced chemical vapor deposition oxide layer, and a silicon nitride layer. The total thickness of the silicon-rich silicon oxide layer, the high-density plasma chemical vapor deposition oxide layer, and the polished plasma-enhanced chemical vapor deposition oxide layer in the composite passivation layer is greater than or equal to the thickness of the top metal.

2. The semiconductor device according to claim 1, characterized in that, The thickness of the top layer metal is between 0.9µm and 4µm.

3. The semiconductor device according to claim 1, characterized in that, The silicon-rich silicon oxide layer is deposited on the top metal using a plasma-enhanced chemical vapor deposition process, and the thickness of the silicon-rich silicon oxide layer is between 300 Å and 600 Å.

4. The semiconductor device according to claim 3, characterized in that, The high-density plasma chemical vapor deposition oxide layer is deposited on the silicon-rich silicon oxide layer, and the thickness of the high-density plasma chemical vapor deposition oxide layer is between 0.9 μm and 1.1 μm.

5. The semiconductor device according to claim 4, characterized in that, The polished plasma-enhanced chemical vapor deposition oxide layer is deposited on the high-density plasma-enhanced chemical vapor deposition oxide layer, and the thickness of the polished plasma-enhanced chemical vapor deposition oxide layer is between 0 and 2 μm; wherein, the thickness of the plasma-enhanced chemical vapor deposition oxide layer before polishing is greater than or equal to 1 μm.

6. The semiconductor device according to claim 5, characterized in that, The silicon nitride layer is deposited on the polished plasma-enhanced chemical vapor deposition oxide layer by a plasma-enhanced chemical vapor deposition process, and the thickness of the silicon nitride layer is between 0.3 μm and 1 μm.

7. The semiconductor device according to claim 1, characterized in that, The dielectric layer includes silicon-rich silicon oxide, a high-density plasma chemical vapor deposition oxide layer, and a plasma-enhanced chemical vapor deposition oxide layer.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor substrate is made of single-crystal silicon or a compound semiconductor, wherein the compound semiconductor is SiC or GaAs; And / or, the material of the top layer metal is aluminum, copper, or an aluminum-copper alloy.

9. A method for manufacturing a semiconductor device, characterized in that, include: Multiple dielectric layers are sequentially formed on a semiconductor substrate. A metal layer is formed in each dielectric layer by physical vapor deposition. The metal layer is patterned into metal wiring by photolithography. Contact holes are formed in the dielectric layers to connect the metal wiring layers. The metal wiring includes a top metal layer. A composite passivation layer is formed on the top metal; wherein, the composite passivation layer comprises, from bottom to top: a silicon-rich silicon oxide layer, a high-density plasma chemical vapor deposition oxide layer, a polished plasma-enhanced chemical vapor deposition oxide layer, and a silicon nitride layer, wherein the total thickness of the silicon-rich silicon oxide layer, the high-density plasma chemical vapor deposition oxide layer, and the polished plasma-enhanced chemical vapor deposition oxide layer in the composite passivation layer is greater than or equal to the thickness of the top metal.

10. The method according to claim 9, characterized in that, The step of forming a composite passivation layer on the top metal includes: A silicon-rich silicon oxide layer is deposited on the surface of the top metal and dielectric layer using a plasma-enhanced chemical vapor deposition process, so that the silicon-rich silicon oxide layer covers the top metal, and the thickness of the silicon-rich silicon oxide layer is between 300 Å and 600 Å. An oxide layer is deposited on the silicon-rich silicon oxide layer using a high-density plasma chemical vapor deposition (PDCVD) process to obtain a high-density plasma chemical vapor deposition oxide layer with a thickness between 0.9 μm and 1.1 μm. A silicon dioxide layer is deposited on the high-density plasma chemical vapor deposition oxide layer using a plasma-enhanced chemical vapor deposition process to obtain a plasma-enhanced chemical vapor deposition oxide layer, wherein the initial thickness of the plasma-enhanced chemical vapor deposition oxide layer is greater than or equal to 1 μm. The plasma-enhanced chemical vapor deposition oxide layer is subjected to chemical mechanical polishing so that the thickness of the polished plasma-enhanced chemical vapor deposition oxide layer is between 0 and 2 μm. A silicon nitride layer is deposited on a polished plasma-enhanced chemical vapor deposition oxide layer using a plasma-enhanced chemical vapor deposition process. The thickness of the silicon nitride layer is between 0.3 μm and 1 μm.

Images