Semiconductor structure, forming method, electronic device and electronic device

Abstract

The invention discloses a semiconductor structure, a forming method, an electronic device and an electronic device.The semiconductor structure comprises a substrate and a first metal layer formed on the substrate, the first metal layer comprises a first metal part and a second metal part, and the first metal part and the second metal part are electrically connected; the high-resistance device is formed on the second metal part; the second metal layer is formed on the high-resistance device, the second metal layer is electrically connected with the first metal part through the first metal through hole, and the second metal layer is electrically connected with the high-resistance device through the second metal through hole; and the dielectric layer is formed between the metal layer and the high-resistance device and is used for isolating the metal layer from the high-resistance device, and the metal layer comprises a first metal layer and a second metal layer. The heat generated by the high-resistance device can be conducted upwards through the second metal part, the first metal part, the first metal through hole and the second metal layer in sequence, and the heat is prevented from spreading to the lower layer to affect the overall performance of the lower layer device and the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for forming it, an electronic device, and an electronic apparatus. Background Technology

[0002] In semiconductor manufacturing processes, the resistive structure formed by high-resistor (HiR) layers can divide voltage and limit current, and is therefore widely used in analog circuits. Due to the high resistance of HiR, a large amount of heat is generated during chip operation. This heat accumulates and radiates, affecting the performance of underlying transistors and other devices, potentially causing a drift in the critical voltage and thus impacting the normal operation of the chip. Summary of the Invention

[0003] This application provides a semiconductor structure, a method for forming it, an electronic device, and an electronic apparatus that can conduct heat generated by high-resistivity devices upwards, preventing heat from accumulating around and spreading downwards, thus avoiding impact on the performance of lower-layer devices and the overall semiconductor structure. The technical solution of this application is as follows:

[0004] On one hand, this application provides a semiconductor structure, including:

[0005] Base,

[0006] A first metal layer is formed on the substrate, the first metal layer includes a first metal portion and a second metal portion, the first metal portion and the second metal portion being electrically connected;

[0007] A high-resistance device, wherein the high-resistance device is formed on the second metal portion;

[0008] A second metal layer is formed on the high-resistivity device. The second metal layer is electrically connected to the first metal portion through a first metal via and to the high-resistivity device through a second metal via.

[0009] A dielectric layer is formed between the metal layer and the high-resistivity device to isolate the metal layer and the high-resistivity device; the metal layer includes a first metal layer and a second metal layer.

[0010] The heat generated by the high-resistivity device is conducted sequentially through the second metal part, the first metal part, the first metal via, and the second metal layer.

[0011] In an optional embodiment, the semiconductor structure further includes a pad metal layer formed on the second metal layer, the pad metal layer being electrically connected to the second metal layer through a third metal via;

[0012] The heat generated by the high-resistivity device is conducted sequentially through the second metal part, the first metal part, the first metal via, the second metal layer, the third metal via, and the pad metal layer.

[0013] In an optional embodiment, the first metal portion and the second metal portion are connected to form at least one U-shaped structure.

[0014] In an optional embodiment, the dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is formed between the first metal layer and the high-resistivity device, and the second dielectric layer is formed between the second metal layer and the high-resistivity device; the first dielectric layer is used to isolate the first metal layer and the high-resistivity device, and the second dielectric layer is used to isolate the second metal layer and the high-resistivity device.

[0015] The first dielectric layer includes a first dielectric structure and a second dielectric structure. The first dielectric structure is formed on the first metal portion, and the second dielectric structure is formed on the second metal portion. The first metal via penetrates the first dielectric structure and the second dielectric layer, and the first metal via exposes the surface of the first metal portion. The second metal via penetrates the second dielectric layer, and the second metal via exposes the surface of the high-resistivity device.

[0016] In an optional embodiment, the second metal layer includes at least one metal layer.

[0017] In an optional embodiment, the substrate includes a device layer and a third metal layer stacked sequentially from bottom to top, the third metal layer being formed between the first metal layer and the device layer, and the third metal layer being electrically connected to the first metal layer and the device layer, respectively.

[0018] In an alternative embodiment, the device layer includes a transistor, and the third metal layer includes at least one metal layer.

[0019] On the other hand, a method for forming a semiconductor structure is also provided, including:

[0020] Provide a base

[0021] Based on a preset pattern, a first metal layer is formed on the substrate. The first metal layer includes a first metal portion and a second metal portion, and the first metal portion and the second metal portion are electrically connected.

[0022] A high-resistivity device is formed above the second metal portion;

[0023] A second metal layer and a second metal via are formed above the high-resistivity device, and a first metal via is formed on the first metal portion; the first metal via exposes the surface of the first metal portion, the second metal via exposes the surface of the high-resistivity device, the second metal layer is electrically connected to the first metal portion through the first metal via, and the second metal layer is electrically connected to the high-resistivity device through the second metal via.

[0024] A dielectric layer is formed between the metal layer and the high-resistivity device, the dielectric layer being used to isolate the metal layer and the high-resistivity device, the metal layer comprising the first metal layer and the second metal layer;

[0025] The heat generated by the high-resistivity device is conducted sequentially through the second metal part, the first metal part, the first metal via, and the second metal layer.

[0026] In an optional embodiment, the method further includes:

[0027] A pad metal layer and a third metal via are formed on the second metal layer. The third metal via exposes the surface of the second metal layer, and the pad metal layer is electrically connected to the second metal layer through the third metal via.

[0028] The heat generated by the high-resistivity device is conducted sequentially through the second metal part, the first metal part, the first metal via, the second metal layer, the third metal via, and the pad metal layer.

[0029] In an optional embodiment, forming a first metal layer on the substrate based on a preset pattern includes:

[0030] Using the preset pattern as a mask, etching is performed on the substrate to form the first metal portion and the second metal portion, and the first metal portion and the second metal portion are connected to form at least one U-shaped structure;

[0031] The first metal portion and the second metal portion are used as the first metal layer.

[0032] In an optional embodiment, the dielectric layer includes a first dielectric layer and a second dielectric layer, and forming a high-resistivity device over the second metal portion includes:

[0033] A first dielectric layer is formed on the first metal layer, the first dielectric layer being used to isolate the first metal layer and the high-resistivity device; the first dielectric layer includes a first dielectric structure and a second dielectric structure, the first dielectric structure being formed on the first metal portion and the second dielectric structure being formed on the second metal portion;

[0034] The high-resistivity device is formed within the second dielectric structure;

[0035] Accordingly, forming a second metal layer and a second metal via above the high-resistivity device, and forming a first metal via on the first metal portion, includes:

[0036] A second dielectric layer is formed on the high-resistivity device, the second dielectric layer being used to isolate the second metal layer and the high-resistivity device;

[0037] A second metal layer is formed on the second dielectric layer, and a second metal via is formed through the second dielectric layer, and a first metal via is formed through the first dielectric structure and the second dielectric layer.

[0038] In an optional embodiment, the substrate includes a device layer and a third metal layer stacked sequentially from bottom to top, and the formation of the first metal layer on the substrate based on a preset pattern includes:

[0039] Based on the preset pattern, the first metal layer is formed on the third metal layer, and the third metal layer is electrically connected to the first metal layer and the device layer respectively.

[0040] On the other hand, an electronic device is also provided, which includes any of the semiconductor structures described in the embodiments of this application.

[0041] On the other hand, an electronic device is also provided, which includes the electronic devices described in the embodiments of this application.

[0042] The semiconductor structure provided in this application includes a substrate, a first metal layer formed on the substrate, wherein the first metal layer includes a first metal portion and a second metal portion, and the first metal portion and the second metal portion are electrically connected; a high-resistance device formed on the second metal portion, and a second metal layer formed on the high-resistance device, wherein the second metal layer is electrically connected to the first metal portion through a first metal via, and the second metal layer is electrically connected to the high-resistance device through a second metal via; and a dielectric layer formed between the metal layer and the high-resistance device, the dielectric layer being used to isolate the metal layer and the high-resistance device, the metal layer including the first metal layer and the second metal layer; wherein the heat generated by the high-resistance device is conducted sequentially through the second metal portion, the first metal portion, the first metal via, and the second metal layer. Thus, in the metal layer below the high-resistivity device, two metal parts (the first metal part and the second metal part) corresponding to the covered and uncovered areas of the high-resistivity device are electrically connected. The metal part corresponding to the uncovered area (i.e., the first metal part) is electrically connected to the metal layer above the metal layer where the metal part is located through a metal via. This allows the heat generated by the high-resistivity device to be conducted upward through the two metal parts, the metal via, and the upper metal layer, ensuring heat dissipation and effectively preventing heat from radiating downward, which could affect the performance of the lower device and the overall semiconductor structure, thereby ensuring the normal operation of the semiconductor structure. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0045] Figure 2 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0046] Figure 3 This is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0047] Figure 4 This is a top view schematic diagram of another semiconductor structure provided in the embodiments of this application;

[0048] Figure 5 This is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0049] Figure 6This is a top view schematic diagram of another semiconductor structure provided in the embodiments of this application;

[0050] Figure 7 This is a schematic flowchart of a method for forming a semiconductor structure provided in an embodiment of this application;

[0051] Figure 8 This is a schematic diagram of a process for forming a first metal layer provided in an embodiment of this application.

[0052] The following is a supplementary explanation of the reference numerals in the accompanying drawings:

[0053] 10 - Substrate; 20 - First metal layer; 210 - First metal portion; 220 - Second metal portion; 30 - High-resistivity device; 40 - Dielectric layer; 50 - Second metal layer; 60 - Pad metal layer; 70 - First metal via; 80 - Second metal via; 90 - Third metal via. Detailed Implementation

[0054] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0055] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe specific objects or a sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0056] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0057] In semiconductor back-end of line (BEOL) process technology, high-resistance (HiR) devices are used to form resistive structures. These structures can divide voltage and limit current, and are therefore widely used in analog circuits, such as radio frequency (RF) circuits. Due to the high resistance of HiR devices, they generate a significant amount of heat when current is applied to the chip, which then radiates to the surroundings and downwards. Metal-oxide-semiconductor (MOS) transistors and other devices are typically located below the HiR device. This radiated heat can affect the performance of the devices beneath the HiR, potentially causing a drift in the critical voltage and thus impacting chip functionality.

[0058] Based on this, this application proposes a semiconductor structure and a heat dissipation design. In the metal layer below the high-resistivity device, two metal parts corresponding to the covered and uncovered areas of the high-resistivity device are electrically connected. The metal part corresponding to the uncovered area is electrically connected to the metal layer above the metal layer through a metal via. This allows the heat generated by the high-resistivity device to be conducted upward through the two metal parts, the metal via, and the upper metal layer, ensuring heat dissipation and effectively preventing heat from radiating downwards, which could affect the performance of the lower device and the overall semiconductor structure, thereby ensuring the normal operation of the semiconductor structure.

[0059] Please see Figures 1-6This application provides a semiconductor structure including a substrate 10, a first metal layer 20, a high-resistivity device 30, a second metal layer 50, and a dielectric layer 40. The first metal layer 20 is formed on the substrate and includes a first metal portion 210 and a second metal portion 220, which are electrically connected. The high-resistivity device 30 is formed on the second metal portion 220. The second metal layer 50 is formed on the high-resistivity device 30 and is electrically connected to the first metal portion 210 through a first metal via 70 and to the high-resistivity device 30 through a second metal via 80. The dielectric layer 40 is formed between the metal layers and the high-resistivity device 30 to isolate them. The metal layers include the first metal layer 20 and the second metal layer 50.

[0060] In one specific embodiment, the first metal portion 210 is the portion of the metal structure in the first metal layer 20 that is not covered by the high-resistivity device 30, and the second metal portion 220 is the portion of the metal structure in the first metal layer 20 that is covered by the high-resistivity device 30. The first metal portion 210 and the second metal portion 220 form the metal structure of the first metal layer 20. A first metal via 70 is used to achieve an electrical connection between the second metal layer 50 and the first metal portion 210. The number of first metal vias 70 can be set according to actual application requirements; specifically, at least one first metal via 70 is provided. Without affecting the semiconductor's operating performance, the heat dissipation effect increases with the increase in the number of first metal vias 70.

[0061] In one specific embodiment, the second metal layer 50 can be electrically connected to both ends of the high-resistance device 30 through two second metal vias 80. The high-resistance device 30 can be made of at least one of tantalum nitride, titanium nitride, silicon chromium, aluminum nitride, etc. Specifically, the high-resistance device 30 can be a one-layer or multi-layer thin film structure made of the above materials. Optionally, during the process of forming the vias between the metal layers, vias that enable electrical connection between the metal layers and the high-resistance device 30 can also be formed simultaneously, thereby connecting the high-resistance device 30 and the metal layers to form a resistive structure. For example, during the process of forming the via between the first metal layer 20 and the second metal layer 50, vias between the high-resistance device 30 and the second metal layer 50 can also be formed simultaneously.

[0062] In some embodiments, during the back-end processes of semiconductor devices, metal interconnect structures can be formed on a semiconductor substrate as needed. These metal interconnect structures may include multiple metal layers. The aforementioned metal interconnect structure may include the first metal layer 20 and the second metal layer 50. Optionally, the first metal layer 20 may be a lower or middle metal layer in the metal interconnect structure, and the second metal layer 50 may be a metal layer located above the first metal layer 20. Specifically, the second metal layer 50 includes at least one metal layer. In the case where the second metal layer 50 includes multiple metal layers, the lowest metal layer in the second metal layer 50 is adjacent to the first metal layer 20, and this lowest metal layer is electrically connected to the first metal portion 210 through a first metal via 70 and electrically connected to the high-resistance device 30 through a second metal via 80.

[0063] In practical applications, in the aforementioned metal interconnect structure, each metal layer includes a trench structure, and vias are present between adjacent metal layers. The trench structure and vias can be used in subsequent processing steps to fill the trench structure and vias with metal material to form a conductive structure, thereby enabling interconnection between metal layers. Optionally, trench structures and vias can be formed by forming a dielectric layer on a semiconductor substrate and then performing patterned etching on the dielectric layer using photoresist and / or a hard mask. In some exemplary embodiments, trench structures and vias can be obtained through all-in-one etching (AIO). AIO refers to a process that completes via etching, photoresist removal, and trench etching in the same step, reducing pattern defects generated during the formation of trench structures and vias and significantly accelerating the processing efficiency of semiconductor structures.

[0064] In one specific embodiment, the first metal layer 20 includes a first trench structure, wherein the trench structures corresponding to the first metal portion 210 and the second metal portion 220 are connected, thereby electrically connecting the first metal portion 210 and the second metal portion 220 formed after filling the trench structure with metal material. The second metal layer 50 includes a second trench structure, and the second trench structure, the first through-hole, and the second through-hole can be formed simultaneously using an integrated etching process. The first through-hole is a through-hole between the first metal portion 210 and the second metal layer 50, exposing the surface of the first metal portion 210, and the second through-hole is a through-hole between the second metal layer 50 and the high-resistivity device 30, exposing the surface of the high-resistivity device 30. Furthermore, metal material is filled into the second trench structure, the first through-hole, and the second through-hole to form the second metal layer, the first metal through-hole, and the second metal through-hole, respectively, so that the second metal layer 50 is electrically connected to the first metal portion 210 through the first metal through-hole 70 and to the high-resistivity device 30 through the second metal through-hole 80.

[0065] In the above embodiments, based on the thermal conductivity of the metal material, during operation, the heat generated by the high-resistivity device 30 can be conducted through the metal portion (i.e., the second metal portion) covered by the area where the high-resistivity device 30 is located in the lower metal layer to another metal portion (i.e., the first metal portion) connected to this metal portion but not covered by the area where the high-resistivity device 30 is located. Then, it is conducted to the upper metal layer through a metal via connected to this other metal portion. In other words, the heat generated by the high-resistivity device 30 is conducted sequentially through the second metal portion 220, the first metal portion 210, the first metal via 70, and the second metal layer 50, thereby achieving a good heat dissipation effect and effectively dissipating heat from the area around the high-resistivity device 30 to the upper layer, preventing heat from diffusing to the lower layer and affecting the performance of the lower-layer devices. Simultaneously, heat dissipation is achieved through the metal interconnect structure in the semiconductor structure, realizing the effective utilization of the semiconductor structure and improving the rationality of the heat dissipation design.

[0066] In an optional embodiment, the connection between the first metal portion 210 and the second metal portion 220 can form at least one U-shaped structure.

[0067] In one specific embodiment, the first metal portion 210 and the second metal portion 220 can be connected in various ways. The number of connections, the positions of the connections, and the connection structures can be set according to actual application requirements. Optionally, in addition to the connection between the first metal portion 210 and the second metal portion 220, adjacent sub-parts included in each of the first metal portion 210 and the second metal portion 220 can also be connected.

[0068] In one exemplary embodiment, such as Figure 1 and Figure 2 As shown, the first metal portion 210 and the second metal portion 220 are connected to form a U-shaped structure, and only one connection is formed between the first metal portion 210 and the second metal portion 220; in an exemplary embodiment, as Figure 3 and Figure 4 As shown, the first metal portion 210 and the second metal portion 220 are connected to form two U-shaped structures, and two connections are formed between the first metal portion 210 and the second metal portion 220; in an exemplary embodiment, as Figure 5 and Figure 6 As shown, based on the connection formed between the first metal portion 210 and the second metal portion 220, the adjacent sub-parts included in the second metal portion 220 are also connected, so that the first metal portion 210 and the second metal portion 220 are connected to form a serpentine structure. The above... Figures 1-6 In the three embodiments shown, the heat dissipation effect on the high-resistivity device 30 in the corresponding semiconductor structure is gradually enhanced.

[0069] In an optional embodiment, the semiconductor structure further includes a pad metal layer 60 formed on the second metal layer 50, and the pad metal layer 60 is electrically connected to the second metal layer 50 through a third metal via 90.

[0070] In one specific embodiment, the pad metal layer 60 is used to form pads, thereby enabling connection with external circuitry such as printed circuit boards. Optionally, the pad metal layer 60 is made of at least one of aluminum, nickel, copper, tungsten, titanium, silver, and gold; for example, the pad metal layer 60 is made of aluminum, a lower-cost metal.

[0071] In practical applications, the pad metal layer 60 needs to be isolated from the metal interconnect structure. Specifically, an isolation layer is formed on top of the uppermost metal layer in the metal interconnect structure, and the pad metal layer 60 is formed on the isolation layer. Optionally, the isolation layer is made of at least one of silicon oxide, silicon nitride, and aluminum oxide.

[0072] In the above embodiments, the heat generated by the high-resistivity device 30 can be conducted sequentially through the second metal portion 220, the first metal portion 210, the first metal via 70, the second metal layer 50, the third metal via 90, and the pad metal layer 60, thereby dissipating the heat inside the semiconductor structure to the outside of the semiconductor structure, achieving effective heat dissipation, and ensuring the performance of the semiconductor structure.

[0073] In an optional embodiment, the dielectric layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer is formed between the first metal layer 20 and the high-resistivity device 30, and the second dielectric layer is formed between the second metal layer 50 and the high-resistivity device 30. The first dielectric layer is used to isolate the first metal layer 20 and the high-resistivity device 30, and the second dielectric layer is used to isolate the second metal layer 50 and the high-resistivity device 30. The first dielectric layer includes a first dielectric structure and a second dielectric structure. The first dielectric structure is formed on the first metal portion 210, and the second dielectric structure is formed on the second metal portion 220. A first metal via 70 penetrates the first dielectric structure and the second dielectric layer, exposing the surface of the first metal portion 210. A second metal via 80 penetrates the second dielectric layer, exposing the surface of the high-resistivity device 30.

[0074] Specifically, since capacitance is generated between different metal layers, this increases circuit power consumption and signal delay. To eliminate this adverse effect, in the metal interconnect structure, adjacent metal layers can be separated by a dielectric layer to achieve electrical isolation between them. The dielectric layer is typically formed using materials with low or ultra-low dielectric constants, such as silicon oxide, silicon nitride, or germanium-silicon-carbon. The high-resistivity device 30 is formed on the second dielectric structure within the first dielectric layer, so that the region where the high-resistivity device 30 is located covers the region where the second metal portion 220 corresponding to the second dielectric structure is located, but does not cover the region where the first metal portion 210 corresponding to the first dielectric structure is located.

[0075] In some embodiments, the substrate 10 may include a device layer (not shown) and a third metal layer (not shown) stacked sequentially from bottom to top, the third metal layer being formed between the first metal layer 20 and the device layer, and the third metal layer being electrically connected to the first metal layer 20 and the device layer respectively.

[0076] In one specific embodiment, the third metal layer may include at least one metal layer. The third metal layer may be located between the device layer and the first metal layer 20. Specifically, the third metal layer may be a portion of the metal interconnect structure located at the bottom of the aforementioned metal interconnect structure. The third metal layer is formed on the device layer, the first metal layer 20 is formed on the third metal layer, and a second metal layer 50, including at least one metal layer, is formed on the first metal layer 20. In this case, the first metal layer 20 is one of the metal layers located in the middle of the aforementioned metal interconnect structure. The third metal layer is electrically connected to the first metal layer 20 and the device layer through corresponding metal vias, which may be formed in the dielectric layer between the two layers.

[0077] In one specific embodiment, a semiconductor device is formed in the device layer. Optionally, the semiconductor device formed in the device layer can be an active device or a passive device. Specifically, active components can include, but are not limited to, transistors, and passive components can include, but are not limited to, at least one of capacitors, resistors, or inductors.

[0078] In the embodiments described in this specification, the aforementioned metal interconnect structure is formed on the device layer. In the integrated circuit, the aforementioned metal interconnect structure is used to connect various semiconductor devices in the device layer, thereby realizing the circuit function. Specifically, the functions realized by the metal interconnect structure include, but are not limited to, signal transmission, power and ground connection, component interconnection, signal isolation, and layout and routing. To realize the above functions, the metal interconnect structure typically includes multiple metal layers. Optionally, the material of the metal layers is at least one of copper, aluminum, nickel, tungsten, titanium, silver, and gold. The materials of different metal layers can be the same or different.

[0079] In some embodiments, the substrate 10 may further include a substrate structure (not shown), which can be obtained by processing a semiconductor wafer. Optionally, the semiconductor wafer includes, but is not limited to, a silicon wafer, a silicon-on-insulator wafer, etc. Optionally, the processing of the semiconductor wafer includes, but is not limited to, oxidation, photolithography, etching, thin film deposition, etc.

[0080] The semiconductor structure provided in this application includes a substrate, a first metal layer formed on the substrate, wherein the first metal layer includes a first metal portion and a second metal portion, and the first metal portion and the second metal portion are electrically connected; a high-resistance device formed on the second metal portion; a second metal layer formed on the high-resistance device, wherein the second metal layer is electrically connected to the first metal portion through a first metal via, and the second metal layer is electrically connected to the high-resistance device through a second metal via; and a dielectric layer formed between the metal layer and the high-resistance device, the dielectric layer being used to isolate the metal layer and the high-resistance device, the metal layer including the first metal layer and the second metal layer; wherein the heat generated by the high-resistance device is conducted sequentially through the second metal portion, the first metal portion, the first metal via, and the second metal layer. Thus, in the metal layer below the high-resistivity device, two metal portions corresponding to the covered and uncovered areas of the high-resistivity device are electrically connected. The metal portion corresponding to the uncovered area is electrically connected to the metal layer above it via a metal via. Based on the excellent thermal conductivity of the metal material, the heat generated by the high-resistivity device can be conducted through the metal portion covered by the high-resistivity device in the lower metal layer to another metal portion connected to it but not covered by the high-resistivity device. The heat is then conducted upwards through the metal via connected to this other metal portion to the upper metal layer, effectively preventing impact on the lower device and ensuring the normal operation of the semiconductor structure. Furthermore, heat can be discharged to the outside of the semiconductor structure via the metal via between the upper metal layer and the packaging pad metal layer, achieving excellent heat dissipation.

[0081] This application also provides a method for forming a semiconductor structure, which can be used to form the semiconductor structure provided in the foregoing embodiments. The method for forming the semiconductor structure provided in this disclosure will be described in detail below. It should be noted that the parts that are the same as or corresponding to those in the foregoing embodiments can be referred to the description of the foregoing embodiments, and will not be repeated hereafter.

[0082] Please see Figure 7 , Figure 7 This is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this application. The method includes:

[0083] S701: Provides a substrate.

[0084] S703: Based on a preset pattern, a first metal layer is formed on the substrate.

[0085] In one specific embodiment, the first metal layer 20 includes a first metal portion 210 and a second metal portion 220, which are electrically connected. The aforementioned preset pattern defines a pattern for forming a first trench structure of the first metal layer 20. For example, the preset pattern may define the connectivity between the trench structures forming the first metal portion 210 and the second metal portion 220.

[0086] Optionally, the formation of the first metal layer 20 on the substrate 10 based on a preset pattern may include forming a dielectric layer on the substrate 10 and forming a photoresist and / or a hard mask above the dielectric layer for patterned etching.

[0087] Specifically, the above-mentioned patterned etching process may include: forming a first patterned photoresist layer on a dielectric layer; using the first patterned photoresist layer as a mask, etching the dielectric layer to form a first trench structure, and removing the first patterned photoresist layer; filling the first trench structure with metal material to form a metal filling structure, thereby obtaining a first metal layer 20. Specifically, the above-mentioned preset pattern is defined in the first patterned photoresist layer.

[0088] In practical applications, during the formation of a metal layer, an integrated etching process can be used to simultaneously obtain the trench structure and the vias communicating with the trench structure. Then, metal material is filled into the trench structure and the vias to obtain the metal layer and the metal vias. These metal vias are used to achieve electrical connection between the metal layer and the underlying structure. For example, during the formation of the first metal layer 20, an integrated etching process can be used to simultaneously obtain the first trench structure and the vias communicating with the first trench structure. Then, metal material is filled into the first trench structure and the vias to obtain the first metal layer 20 and the metal vias. These metal vias are used to achieve electrical connection between the first metal layer 20 and the substrate 10.

[0089] Optionally, after forming the first trench structure and the vias communicating with a portion of the first trench structure, conductive metal can be deposited in the opening areas of the first trench structure and the vias until it overflows and covers the upper surface of the dielectric layer. This planarizes the conductive metal until its top surface is flush with the upper surface of the dielectric layer, forming the first metal layer 20 and the metal vias for electrically connecting the first metal layer 20 to the substrate 10. Specifically, the deposition process can be performed using physical vapor deposition, chemical vapor deposition, electrochemical plating, or other deposition techniques. For example, when the conductive metal is copper, physical vapor deposition can be used. The planarization of the conductive metal can be achieved using techniques such as chemical mechanical polishing (CMP).

[0090] In one specific embodiment, before depositing the conductive metal, a barrier layer (not shown) and a seed layer (not shown) can be sequentially formed on the inner surfaces of the first trench structure and the via. Then, the conductive metal is deposited on the seed layer until it overflows and covers the surface of the dielectric layer. Specifically, the barrier layer can be made of titanium nitride, and it can prevent the conductive metal from diffusing, thereby improving electromigration. The barrier layer can be formed using physical vapor deposition. The seed layer is made of the same material as the conductive metal, and it can enhance the adhesion between the conductive metal and the barrier layer. The seed layer can be formed using sputtering or chemical vapor deposition.

[0091] In some embodiments, before performing the patterning etching process described above, an oxide hard mask layer can be formed on the substrate 10, and after filling with metal material, the remaining oxide hard mask layer can be removed. Specifically, the oxide hard mask layer can be made of silicon oxynitride, and this oxide hard mask layer is used to protect the dielectric layer during the formation of the semiconductor structure.

[0092] In an optional embodiment, Figure 8 This is a schematic diagram of a process for forming a first metal layer provided in an embodiment of this application, such as... Figure 8 As shown, forming a first metal layer on a substrate based on a preset pattern may include:

[0093] S801: Using a preset pattern as a mask, etching is performed on the substrate to form a first metal part and a second metal part.

[0094] In one specific embodiment, the aforementioned preset pattern may include at least one U-shaped pattern. During the etching process, the aforementioned at least one U-shaped pattern is defined in the first patterned photoresist layer. After the etching process, the trench structures corresponding to the first metal portion 210 and the second metal portion 220 are connected to form at least one U-shaped structure, allowing the subsequent connection of the first metal portion 210 and the second metal portion 220 to form at least one U-shaped structure. The specific pattern can be set according to actual application requirements. For example, the preset pattern may include one U-shaped pattern or multiple U-shaped patterns. Furthermore, the preset pattern may also be a serpentine pattern, making the formed first trench structure serpentine.

[0095] S803: The first metal portion and the second metal portion are used as the first metal layer.

[0096] In an optional embodiment, the substrate 10 may include a device layer (not shown) and a third metal layer (not shown) stacked sequentially from bottom to top. Correspondingly, the formation of the first metal layer on the substrate based on a preset pattern may include:

[0097] Based on a preset pattern, a first metal layer is formed on the third metal layer.

[0098] Specifically, the third metal layer is electrically connected to the first metal layer 20 and the device layer through corresponding metal vias. The formation of the first metal layer on the third metal layer based on the preset pattern can include forming a photoresist and / or a hard mask on the third metal layer for patterned etching to form the first metal layer. The specific implementation method can be found in the detailed steps of forming the first metal layer on the substrate based on the preset pattern described above, and will not be repeated here.

[0099] S705: A high-resistivity device is formed above the second metal part.

[0100] In one specific embodiment, a dielectric layer 40 is further formed between the first metal layer 20 and the high-resistivity device 30, and between the second metal layer 50 and the high-resistivity device 30. Specifically, the dielectric layer 40 is used to isolate the first metal layer 20 and the high-resistivity device 30, and to isolate the second metal layer 50 and the high-resistivity device 30.

[0101] In an optional embodiment, forming a high-resistivity device above the second metal portion may include:

[0102] A first dielectric layer is formed on the first metal layer;

[0103] A high-resistivity device is formed on the second dielectric structure.

[0104] In one specific embodiment, the dielectric layer 40 includes a first dielectric layer and a second dielectric layer. A dielectric material is deposited on the first metal layer 20 to form a first dielectric layer covering the first metal layer 20. The first dielectric layer includes a first dielectric structure and a second dielectric structure. The first dielectric structure is formed on the first metal portion 210, and the second dielectric structure is formed on the second metal portion 220. Optionally, a thin-film resistive material layer is deposited on the second dielectric structure, and the thin-film resistive material layer is patterned and etched to form a high-resistivity device 30, such that the area where the high-resistivity device 30 is formed covers the area where the second metal portion 220 is located, but does not cover the area where the first metal portion 210 is located. The resistive material can be at least one of tantalum nitride, titanium nitride, silicon chromium, aluminum nitride, etc., and the high-resistivity device 30 can be formed by deposition processes such as chemical vapor deposition, physical vapor deposition, and electrochemical plating.

[0105] S707: A second metal layer and a second metal via are formed above the high-resistivity device, and a first metal via is formed on the first metal portion.

[0106] In an optional embodiment, forming a second metal layer and a second metal via above the high-resistivity device, and forming a first metal via on the first metal portion, may include:

[0107] A second dielectric layer is formed on the high-resistivity device;

[0108] A second metal layer is formed on the second dielectric layer, and a second metal via is formed through the second dielectric layer, and a first metal via is formed through the first dielectric structure and the second dielectric layer.

[0109] In one specific embodiment, a dielectric material is deposited on the high-resistivity device 30 to form a second dielectric layer, and then a second metal layer 50 is formed on the second dielectric layer. Specifically, the second metal layer 50 may include a second trench structure. Optionally, a photoresist and / or a hard mask can be formed above the second dielectric layer for patterned etching to simultaneously obtain the second trench structure and vias communicating with the second trench structure, and then the photoresist layer is removed. Specifically, using the second patterned photoresist layer as a mask, an integrated etching process is used to simultaneously form the second trench structure and a first via and a second via communicating with the second trench structure; wherein, the first via is a via between the first metal portion 210 and the second metal layer 50, and the first via exposes the surface of the first metal portion 210; the second via is a via between the second metal layer 50 and the high-resistivity device 30, and the second via exposes the surface of the high-resistivity device 30. The second patterned photoresist layer defines a pattern for forming the second trench structure, the first via, and the second via.

[0110] Specifically, the detailed implementation of forming the second metal layer, the first metal via, and the second metal via can be found in the detailed steps of forming the first metal layer on the substrate based on the preset pattern, which will not be repeated here.

[0111] In an optional embodiment, the above method may further include:

[0112] A pad metal layer and a third metal via are formed on the second metal layer.

[0113] Optionally, an isolation layer can be formed on the uppermost metal layer of the metal interconnect structure, and a pad metal layer 60 can be formed on the isolation layer, thereby isolating the pad metal layer 60 from the metal interconnect structure.

[0114] Specifically, a dielectric layer can be deposited on the second metal layer 50, and the dielectric layer can be etched until the surface of the second metal layer 50 is exposed to form a via. Conductive metal is deposited in the opening region of the via to form the third metal via 90. Then, a pad metal layer 60 is formed on the dielectric layer on which the third metal via 90 is formed. If the second metal layer 50 includes multiple metal layers, the pad metal layer 60 and the third metal via 90 are formed on the uppermost metal layer in the multiple metal layers, so that the pad metal layer 60 is electrically connected to the uppermost metal layer through the third metal via 90.

[0115] In the above embodiments, the heat generated by the high-resistivity device 30 can be conducted to the outside of the semiconductor structure through the second metal portion 220, the first metal portion 210, the first metal via 70, the second metal layer 50, the third metal via 90 and the pad metal layer 60 in sequence.

[0116] The semiconductor structure formed by the above method has two metal parts electrically connected in the metal layer below the high-resistivity device, corresponding to the covered and uncovered areas of the high-resistivity device. The metal part corresponding to the uncovered area (i.e., the first metal part) is electrically connected to the metal layer above the metal layer through a metal via. This allows the heat generated by the high-resistivity device to be conducted upward through the two metal parts, the metal via, and the upper metal layer. Furthermore, the heat can be discharged to the outside of the semiconductor structure through the metal via between the upper metal layer and the packaging pad metal layer, achieving a good heat dissipation effect, effectively avoiding affecting the performance of the lower device, and thus ensuring the normal operation of the semiconductor structure.

[0117] This application also provides an electronic device, including any of the semiconductor structures described in this application.

[0118] This application also provides an electronic device, which includes any of the electronic components described in the preceding embodiments of this application. The electronic device can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigator, camera, camcorder, voice recorder, MP3, MP4, PSP, etc., or it can be an intermediate product with the semiconductor structure described above, such as a device motherboard with the electronic component. The use of the electronic component in this electronic device improves the working performance of the electronic device accordingly.

[0119] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base, A first metal layer is formed on the substrate, the first metal layer includes a first metal portion and a second metal portion, the first metal portion and the second metal portion being electrically connected; A high-resistance device, wherein the high-resistance device is formed on the second metal portion; A second metal layer is formed on the high-resistivity device. The second metal layer is electrically connected to the first metal portion through a first metal via and to the high-resistivity device through a second metal via. A dielectric layer is formed between the metal layer and the high-resistivity device to isolate the metal layer and the high-resistivity device; the metal layer includes a first metal layer and a second metal layer. The heat generated by the high-resistivity device is conducted sequentially through the second metal part, the first metal part, the first metal via, and the second metal layer.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a pad metal layer, which is formed on the second metal layer and electrically connected to the second metal layer through a third metal via. The heat generated by the high-resistivity device is conducted sequentially through the second metal part, the first metal part, the first metal via, the second metal layer, the third metal via, and the pad metal layer.

3. The semiconductor structure according to claim 1, characterized in that, The first metal portion and the second metal portion are connected to form at least one U-shaped structure.

4. The semiconductor structure according to claim 1, characterized in that, The dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is formed between the first metal layer and the high-resistivity device, and the second dielectric layer is formed between the second metal layer and the high-resistivity device; the first dielectric layer is used to isolate the first metal layer and the high-resistivity device, and the second dielectric layer is used to isolate the second metal layer and the high-resistivity device. The first dielectric layer includes a first dielectric structure and a second dielectric structure. The first dielectric structure is formed on the first metal portion, and the second dielectric structure is formed on the second metal portion. The first metal via penetrates the first dielectric structure and the second dielectric layer, and the first metal via exposes the surface of the first metal portion. The second metal via penetrates the second dielectric layer, and the second metal via exposes the surface of the high-resistivity device.

5. The semiconductor structure according to claim 1, wherein the second metal layer comprises at least one metal layer.

6. The semiconductor structure according to claim 1, characterized in that, The substrate includes a device layer and a third metal layer stacked sequentially from bottom to top. The third metal layer is formed between the first metal layer and the device layer, and is electrically connected to the first metal layer and the device layer, respectively.

7. The semiconductor structure according to claim 6, characterized in that, The device layer includes transistors, and the third metal layer includes at least one metal layer.

8. A method for forming a semiconductor structure, characterized in that, include: Provide a base Based on a preset pattern, a first metal layer is formed on the substrate. The first metal layer includes a first metal portion and a second metal portion, and the first metal portion and the second metal portion are electrically connected. A high-resistivity device is formed above the second metal portion; A second metal layer and a second metal via are formed above the high-resistivity device, and a first metal via is formed on the first metal portion; the first metal via exposes the surface of the first metal portion, the second metal via exposes the surface of the high-resistivity device, the second metal layer is electrically connected to the first metal portion through the first metal via, and the second metal layer is electrically connected to the high-resistivity device through the second metal via. A dielectric layer is formed between the metal layer and the high-resistivity device, the dielectric layer being used to isolate the metal layer and the high-resistivity device, the metal layer comprising the first metal layer and the second metal layer; The heat generated by the high-resistivity device is conducted sequentially through the second metal part, the first metal part, the first metal via, and the second metal layer.

9. The method according to claim 8, characterized in that, The method further includes: A pad metal layer and a third metal via are formed on the second metal layer. The third metal via exposes the surface of the second metal layer, and the pad metal layer is electrically connected to the second metal layer through the third metal via. The heat generated by the high-resistivity device is conducted sequentially through the second metal part, the first metal part, the first metal via, the second metal layer, the third metal via, and the pad metal layer.

10. The method according to claim 8, characterized in that, The step of forming a first metal layer on the substrate based on a preset pattern includes: Using the preset pattern as a mask, etching is performed on the substrate to form the first metal portion and the second metal portion, and the first metal portion and the second metal portion are connected to form at least one U-shaped structure; The first metal portion and the second metal portion are used as the first metal layer.

11. The method according to claim 8, characterized in that, The dielectric layer includes a first dielectric layer and a second dielectric layer, and forming a high-resistivity device over the second metal portion includes: A first dielectric layer is formed on the first metal layer, the first dielectric layer being used to isolate the first metal layer and the high-resistivity device; the first dielectric layer includes a first dielectric structure and a second dielectric structure, the first dielectric structure being formed on the first metal portion and the second dielectric structure being formed on the second metal portion; The high-resistivity device is formed on the second dielectric structure; Accordingly, forming a second metal layer and a second metal via above the high-resistivity device, and forming a first metal via on the first metal portion, includes: A second dielectric layer is formed on the high-resistivity device, the second dielectric layer being used to isolate the second metal layer and the high-resistivity device; A second metal layer is formed on the second dielectric layer, and a second metal via is formed through the second dielectric layer, and a first metal via is formed through the first dielectric structure and the second dielectric layer.

12. The method according to claim 8, characterized in that, The substrate includes a device layer and a third metal layer stacked sequentially from bottom to top, and the step of forming the first metal layer on the substrate based on a preset pattern includes: Based on the preset pattern, the first metal layer is formed on the third metal layer, and the third metal layer is electrically connected to the first metal layer and the device layer respectively.

13. An electronic device, characterized in that, The electronic device includes the semiconductor structure as described in any one of claims 1 to 7.

14. An electronic device, characterized in that, Including the electronic device as described in claim 13.

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