Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, and the semiconductor structure comprises a structural layer which is provided with an interconnection region; the laminated structure is located on the structural layer and comprises an interval dielectric layer and an ultra-low K dielectric layer which are stacked in the first direction, and the first direction is the thickness direction of the structural layer; the low-K dielectric layer penetrates through the laminated structure along the first direction; the conductive channel penetrates through the low-K dielectric layer in the first direction and is connected with the interconnection area, in the second direction, the size of the interval dielectric layer is smaller than that of the ultra-low-K dielectric layer to form a recess, and the recess is filled with the low-K dielectric layer to form a protrusion so that the interval dielectric layer, the ultra-low-K dielectric layer and the low-K dielectric layer can form an interlocking structure; the second direction is perpendicular to the first direction. According to the semiconductor structure, the interval dielectric layer, the ultralow-K dielectric layer and the low-K dielectric layer form a concave-convex interlocking structure, so that the overall mechanical strength of the dielectric layers is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] As semiconductor devices become increasingly miniaturized and their integration density continues to rise, the parasitic effects of resistance / capacitance in circuit connections are causing increasingly severe RC delay. RC delay has a growing impact on device speed. Currently, the RC delay phenomenon can be mitigated by using materials with low dielectric constants (Low K) to reduce parasitic capacitance.

[0003] However, as the dielectric constant decreases, the mechanical strength of the dielectric layer weakens, making it prone to delamination, cracking, or peeling during subsequent etching and polishing processes, leading to device failure. Therefore, the industry faces a conformal challenge in 28nm and below nodes, especially in 14nm and below nodes, where it is difficult to simultaneously achieve both "low K value" and "high mechanical strength". Summary of the Invention

[0004] In view of the above problems, there is a need to propose a semiconductor structure and its manufacturing method.

[0005] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0006] A structural layer having interconnection regions;

[0007] A stacked structure, located on the structural layer, includes a spacer dielectric layer and an ultra-low K dielectric layer stacked along a first direction, wherein the first direction is the thickness direction of the structural layer;

[0008] A low-k dielectric layer extends through the stacked structure along the first direction; and

[0009] A conductive channel extends along the first direction through the low-k dielectric layer and connects to the interconnect region.

[0010] In this configuration, along the second direction, the size of the spacer dielectric layer is smaller than the size of the ultra-low-k dielectric layer, forming a recess. The low-k dielectric layer fills the recess, forming a protrusion, so that the spacer dielectric layer, the ultra-low-k dielectric layer, and the low-k dielectric layer form an interlocking structure.

[0011] The second direction is perpendicular to the first direction.

[0012] Optionally, there may be multiple ultra-low K dielectric layers, with the spacer dielectric layer located between two adjacent ultra-low K dielectric layers, and / or there may be multiple spacer dielectric layers and multiple ultra-low K dielectric layers, with the multiple spacer dielectric layers and multiple ultra-low K dielectric layers stacked alternately.

[0013] Optionally, the low-k dielectric layer is also located on the stacked structure.

[0014] Optionally, a protective layer is also included, located between the stacked structure and the low-k dielectric layer.

[0015] According to another aspect of this disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0016] A stacked structure is formed on a structural layer having interconnection regions, the stacked structure comprising a spacer dielectric layer and an ultra-low K dielectric layer stacked along a first direction, the first direction being the thickness direction of the structural layer;

[0017] The stacked structure is etched to form a first groove;

[0018] A low-k dielectric layer is formed within the first groove;

[0019] Etching the low-k dielectric layer to form a second groove; and

[0020] A conductive channel is formed in the second groove, and the conductive channel is connected to the interconnect region.

[0021] In this process, along the second direction, the etching rate of the spacer dielectric layer is greater than the etching rate of the ultra-low-k dielectric layer, so as to form a recess at the sidewall of the first groove. The low-k dielectric layer forms a protrusion at the recess so that the spacer dielectric layer, the ultra-low-k dielectric layer, and the low-k dielectric layer constitute an interlocking structure.

[0022] The second direction is perpendicular to the first direction.

[0023] Optionally, the step of forming a low-k dielectric layer within the first groove includes:

[0024] The reaction chamber is supplied with plasma-form oxygen free radicals and plasma-form silicon-, oxygen-, carbon-, and hydrogen-containing precursors.

[0025] The oxygen free radicals react with the silicon-, oxygen-, carbon-, and hydrogen-containing precursor to generate a flowable low-k dielectric layer, which is then deposited within the first groove; and

[0026] The low-k dielectric layer is solidified.

[0027] Optionally, the low-k dielectric layer is also located on the stacked structure, and the chemical mechanical polishing of the conductive filling layer used to form the conductive channel stops on the low-k dielectric layer on the stacked structure.

[0028] Optionally, before forming the low-k dielectric layer, a protective layer is further formed on the inner surface of the first groove.

[0029] The low-k dielectric layer is separated from the stacked structure by the protective layer.

[0030] Optionally, the carbon content in the spacer layer is less than the carbon content in the ultra-low K dielectric layer, so that the etching rate of the spacer layer along the second direction is greater than the etching rate of the ultra-low K dielectric layer.

[0031] Optionally, in the steps of the first groove and the second groove, the photoresist is patterned through the fully transparent and semi-transparent portions of the halftone mask to form a photomask, and the underlying structure is etched through the photomask so that the lower width of a portion of the first groove and the second groove is smaller than the upper width.

[0032] One of the above technical solutions has the following unexpected technical effect:

[0033] By stacking spacer dielectric layers, ultra-low-k dielectric layers, and low-k dielectric layers that penetrate the stacked structure on a structural layer with interconnect regions, and in a second direction perpendicular to the thickness of the structural layer, the size of the spacer dielectric layer is smaller than that of the ultra-low-k dielectric layer to form a recess, and the low-k dielectric layer fills the recess to form a protrusion, so that the spacer dielectric layer, ultra-low-k dielectric layer, and low-k dielectric layer form an interlocking structure. This composite dielectric layer interlocking structure can improve the overall mechanical strength of the dielectric layer. During etching, polishing, and other processes, the improved overall mechanical strength of the dielectric layer makes it less prone to damage. Furthermore, due to the presence of the ultra-low-k and low-k dielectric layers, the dielectric constant is kept within a low range. Therefore, this technical solution reduces the parasitic capacitance of the device while ensuring the mechanical strength of the device.

[0034] In some alternative embodiments, plasma oxygen radicals and plasma-containing silicon, oxygen, carbon, and hydrogen precursors are provided to the reaction chamber. Since the oxygen in the reaction chamber exists as oxygen plasma rather than oxygen gas, excessively high temperatures are not required during the reaction, and the oxidation of carbon elements in the ultra-low K dielectric layer can be prevented.

[0035] In some alternative embodiments, a protective layer separates the low-k dielectric layer from the stacked structure, thereby preventing the carbon in the ultra-low-k dielectric layer from being oxidized during the formation of the low-k dielectric layer.

[0036] In some alternative embodiments, the low-k dielectric layer is also located on the stacked structure. Since the dielectric constant of the low-k dielectric layer is greater than that of the ultra-low-k dielectric layer, the mechanical strength of the low-k dielectric layer is also greater than that of the ultra-low-k dielectric layer. When performing chemical mechanical polishing on the conductive filling layer, stopping on the low-k dielectric layer above the stacked structure can protect the stacked structure below it from damage.

[0037] In some alternative embodiments, when forming the first and second grooves, the photoresist is first patterned through the fully transparent and semi-transparent portions of a halftone mask to form a photomask, and the underlying structure is etched through the photomask, so that the lower width of some of the first and second grooves is smaller than the upper width. Compared with the case where the upper and lower widths are the same as the upper width, this solution can increase the proportion of the ultra-low K dielectric layer and further reduce the overall dielectric constant of the dielectric layer.

[0038] It should be noted that the above general description and the following detailed description are exemplary and explanatory only and do not limit this disclosure. Attached Figure Description

[0039] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which: Figure 1 A schematic diagram illustrating the trends of interconnect delay and gate delay in semiconductor devices in related technologies is shown. Figures 2 to 9 A cross-sectional structural schematic diagram of the formation process of a semiconductor structure for interconnection technology according to an embodiment of the present disclosure is shown; Figure 10 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure is shown.

[0040] Explanation of reference numerals in the attached figures: 101-Substrate; 102-Interconnect region; 110-Metal layer; 120-Barrier layer; 130-Stacked structure; 131-Spacer dielectric layer; 132-Ultra-low K dielectric layer; 140-First hard mask layer; 150-First photolithography mask; 152-Second photolithography mask; 160-First groove; 161-Recess; 170-Protective layer; 180-Low K dielectric layer; 181-Bump; 191-Stress buffer layer; 192-Second hard mask layer; 201-Second groove; 210-Conductive filler layer; 211 and 212-Conductive channels; 10-Interlayer dielectric layer. Detailed Implementation

[0041] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0042] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.

[0043] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0044] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0045] This application may be presented in various forms, some of which will be described below.

[0046] Figure 1 This diagram illustrates the trends of interconnect delay and gate delay in semiconductor devices in related technologies. The horizontal axis represents the gate width in nanometers (nm); the left vertical axis represents the gate delay time in picoseconds (ps); the right vertical axis represents the interconnect delay time in picoseconds (ps); the solid curve represents the trend of interconnect delay with gate width; and the dashed curve represents the trend of gate delay with gate width.

[0047] See Figure 1As semiconductor devices become increasingly miniaturized and integration density increases, gate widths shrink, leading to a decrease in gate delay time. However, parasitic effects caused by resistance and capacitance in circuit interconnects result in increasingly severe interconnect delay, also known as resistive-capacitive delay (RC delay), which limits device operating speed. The trend of RC delay is opposite to that of gate delay; higher integration density results in a larger RC delay. In related technologies, RC delay can be mitigated by using copper to fabricate interconnect structures to reduce line resistance and by selecting materials with low dielectric constants (Low K) to reduce parasitic capacitance.

[0048] When the gate width is at nodes such as 45nm, 60nm, and 90nm, a carbon-doped dielectric layer and interconnect metal are formed in the back-end process steps of semiconductor devices. The dielectric constant of the carbon-doped dielectric layer is k=3±0.1, and the Young's modulus E of the carbon-doped dielectric layer is approximately 13GPa. The Young's modulus E characterizes the mechanical strength of the dielectric layer; the smaller the value, the lower the mechanical strength.

[0049] When the gate width is at nodes such as 22nm and 28nm, a carbon-doped porous dielectric layer and interconnect metal are formed in the back-end process steps of the semiconductor device. Due to the increased porosity in the carbon-doped porous dielectric layer, the dielectric constant decreases accordingly. The dielectric constant k = 2.5 ± 0.1, and the Young's modulus E of the carbon-doped porous dielectric layer is approximately 7.5 GPa. The material of the carbon-doped porous dielectric layer belongs to low-k dielectric materials (as referred to in this disclosure, low-k dielectric materials are dielectric materials with a dielectric constant K less than 4 and greater than or equal to 2.2).

[0050] As the gate width decreases further, simply increasing the porosity of the dielectric layer to reduce the dielectric constant, such as by using ultra-low-k dielectric materials (ultra-low-k dielectric materials, as referred to in this disclosure, are dielectric materials with a dielectric constant K less than 2.2), will result in insufficient mechanical strength of the dielectric layer, leading to damage during etching, polishing, and other processes. Therefore, to ensure sufficient mechanical strength of the dielectric layer when the gate width is less than 14 nm, it is necessary to use dielectric materials with higher dielectric constants to achieve higher mechanical strength.

[0051] When the gate width is at nodes such as 5nm, 7nm, 10nm and 14nm, a carbon-doped high-density dielectric layer and interconnect metal are formed in the back-end process steps of semiconductor devices. Since the carbon-doped high-density dielectric layer is very dense, its Young's modulus E is about 20Gpa, so its mechanical strength is relatively large. However, the dielectric constant k of the carbon-doped high-density dielectric layer is about 2.8, which is higher than that of the carbon-doped porous dielectric layer, thus increasing the RC delay.

[0052] In view of the above problems, this disclosure proposes a new semiconductor structure and a method for manufacturing the same.

[0053] Figures 2 to 9 A cross-sectional schematic diagram of the formation process of a semiconductor structure for interconnection technology according to an embodiment of the present disclosure is shown.

[0054] See Figure 2 A semiconductor structure with interconnect regions 102 is provided. This semiconductor structure includes a substrate 101 and one or more interlayer dielectric layers on the substrate 101, as well as metal interconnect layers between the interlayer dielectric layers. Conductive plugs are formed within the interlayer dielectric layers. Inductors, memory cells, through-silicon vias, etc., may also be formed within the interlayer dielectric layers. Figure 2 In the diagram, only one metal layer 110 on the substrate 101 is shown. The material of the metal layer 110 is, for example, copper. The interconnect region 102 may be located on the metal layer 110, or on structures such as conductive plugs, inductors, memory cells, and through-silicon vias.

[0055] In some other embodiments, the semiconductor structure having interconnect regions 102 may also be a substrate 101 and an epitaxial layer on the substrate 101. The interconnect regions 102 may be doped regions, through-silicon vias, etc., located within the substrate 101 or the epitaxial layer, or on the surface of the substrate 101 or the epitaxial layer. The interconnect regions 102 may also be transistor gates, resistors, capacitors, memory cells, etc., located on the surface of the substrate or the epitaxial layer.

[0056] Further, a stacked structure 130 is formed on the metal layer 110 of the structural layer, wherein the stacked structure 130 includes a spacer dielectric layer 131 and an ultra-low k dielectric layer 132 stacked along a first direction, which is the thickness direction of the structural layer. In this embodiment, there are two ultra-low k dielectric layers 132, with the spacer dielectric layer 131 sandwiched between two adjacent ultra-low k dielectric layers 132. In some optional embodiments, the spacer dielectric layer 131 is located at the bottom layer of the stacked structure 130, and the ultra-low k dielectric layer 132 is located on the spacer dielectric layer 131. In other optional embodiments, both the spacer dielectric layer 131 and the ultra-low k dielectric layer 132 are multiple layers and are stacked alternately on top of each other.

[0057] The spacer dielectric layer 131 is made of a carbon-doped oxide layer. In some embodiments, the spacer dielectric layer 131 is a low-carbon oxide layer with a carbon content lower than that in the ultra-low-K dielectric layer 132. The ultra-low-K dielectric layer 132 is made of a porous dielectric material, including one or a combination of Si-based porous dielectric materials, C-based porous dielectric materials, and organic polymer porous dielectric materials. Si-based porous dielectric materials include, for example, silica aerogel, nanoporous silica, and microporous silica. C-based porous dielectric materials include, for example, porous diamond materials. Organic polymer porous dielectric materials include, for example, polyimide porous materials, polyethylene porous materials, and polysilazane porous materials. The material of the ultra-low-K dielectric layer 132 can also be one or a combination of SiO2, porous SiO2H, carbon, carbon aerogel, and oxide aerogel. In this embodiment, the dielectric constant K of the ultra-low-K dielectric layer 132 is not greater than 2.2. Preferably, the dielectric constant K of the ultra-low-K dielectric layer 132 is not greater than 2.

[0058] In some preferred embodiments, a barrier layer 120 is further formed between the metal layer 110 and the stacked structure 130 to prevent metal elements in the metal layer 110 from diffusing into the stacked structure 130, wherein the material of the barrier layer 120 includes SICN.

[0059] In some other preferred embodiments, a first hard mask layer 140, such as an oxide layer, is also deposited on the stacked structure 130.

[0060] Furthermore, a first photomask 150 is formed on the stacked structure 130, such as... Figure 2 As shown.

[0061] In this step, for example, photoresist is first coated on the first hard mask layer 140, and then the photoresist is patterned through the fully transparent and semi-transparent portions of the halftone mask to form the first photomask 150, wherein, Figure 2 The two on the left and in the middle are formed using a fully transparent pattern; the left half of the one on the right is formed using a semi-transparent pattern. See also Figure 2 and Figure 3 The first photolithography mask 150 is the etching position of the first groove 160 in the subsequent steps. The left half of the first photolithography mask 150 on the right side is also the etching position of the first groove 160. However, due to the obstruction of the first photolithography mask 150, the etching depth is small.

[0062] Furthermore, the etched stacked structure 130 forms the first groove 160, such as Figure 3 As shown.

[0063] In this step, the first photomask 150 is etched together to remove it. Along the second direction, the etching rate of the spacer dielectric layer 131 is greater than the etching rate of the ultra-low K dielectric layer 132, to form a recess 161, or indentation structure, at the sidewall of the first groove 160, wherein the second direction is perpendicular to the first direction. The first groove 160 can be a trench structure or a via structure, and its location corresponds to the interconnect region 102. There are multiple first grooves 160, wherein, due to... Figure 3 The first photomask 150 corresponding to the left half of the rightmost first groove 160 is formed by a semi-transparent pattern, so that the lower width of the first groove 160 is smaller than the upper width.

[0064] Furthermore, a protective layer 170 is formed on the surface of the semiconductor structure, such as... Figure 4 As shown, the protective layer 170 covers the inner surface of the first groove 160 and the first hard mask layer 140.

[0065] In this step, for example, an organometallic compound OMCTS (octamethylcyclotetrasiloxane) is used as a reactant to form the protective layer 170. This reaction does not involve oxygen, but the final protective layer 170 is made of silicon oxide. This is to prevent oxygen from oxidizing the carbon in the ultra-low K dielectric layer 132 during the reaction. The material of the protective layer 170 is not limited to silicon oxide, but also includes substances such as silicon nitride. In some other embodiments, the protective layer 170 may not be formed.

[0066] Furthermore, a low-k dielectric layer 180 is formed, such as... Figure 5 As shown, the low-K dielectric layer 180 is located above the stacked structure 130, covering the protective layer 170 and filling the first groove 160. The low-K dielectric layer 180 forms a protrusion 181 at the groove.

[0067] In this step, firstly, distal plasma is used to provide plasma-form oxygen radicals and plasma-form silicon-, oxygen-, carbon-, and hydrogen-containing precursors into the reaction chamber. Then, the oxygen radicals react with the silicon-, oxygen-, carbon-, and hydrogen-containing precursors to generate a flowable low-k dielectric layer 180, which is deposited within the first groove 160 and above the stacked structure 130. Finally, ultraviolet irradiation or annealing cures the flowable low-k dielectric layer 180. The reaction in the chamber is oxygen-free to prevent oxygen from oxidizing the carbon in the ultra-low-k dielectric layer 132 during the reaction. A protective layer 170 is used to protect the stacked structure 130 in this step, separating the low-k dielectric layer 180 from the stacked structure.

[0068] The low-k dielectric layer 180 is made of materials such as silicon dioxide doped with elements like fluorine, carbon, and hydrogen, amorphous carbon, or organic polymers. In this embodiment, the low-k dielectric layer 180 is deposited using processes including but not limited to FCVD / ALD / HARP / HDP / spin-coating, and the materials include but are not limited to porous SiCOH (BD2), non-porous SiCO (BD1), and oxides, with a dielectric constant K of approximately 2.8. The adjacent areas of the spacer dielectric layer 131, the ultra-low-k dielectric layer 132, and the low-k dielectric layer 180 have an interlocking structure with uneven surfaces, thereby improving the overall mechanical strength of the dielectric layer. In subsequent etching and polishing processes, the improved overall mechanical strength of the dielectric layer makes it less prone to damage, further ensuring product performance. Furthermore, since the dielectric constant K of the ultra-low-k dielectric layer 132 is not greater than 2, controlling the proportion of the ultra-low-k dielectric layer 132 ensures that the overall dielectric constant k of the composite dielectric layer is not greater than 2.3, or even less than 2.2 or lower.

[0069] Furthermore, a stress buffer layer 191 and a second hard mask layer 192 are formed on the low-k dielectric layer 180, such as... Figure 6 As shown, the material of the buffer layer 191 includes, for example, one or a combination of an oxide layer, a TEOS layer, and a TIN layer, and the second hard mask layer 192 is, for example, an oxide layer. In some other embodiments, the buffer layer 191 and the second hard mask layer 192 may not be formed.

[0070] Furthermore, a second photomask 152 is formed on the second hard mask layer 192, such as... Figure 6 As shown.

[0071] In this step, for example, photoresist is first coated on the second hard mask layer 192, and then the photoresist is patterned through the fully transparent and semi-transparent portions of the halftone mask to form the second photomask 152. Figure 6 The two on the left and in the middle are formed using a fully transparent pattern; the left half of the one on the right is formed using a semi-transparent pattern. See also Figure 6 and Figure 7 The area between the second photolithography mask 152 is the etching position of the second groove 201 in the subsequent steps. The corresponding position of the left half of the second photolithography mask 152 on the right is also the etching position of the second groove 201, but the etching depth is smaller due to the obstruction of the second photolithography mask 152.

[0072] Further, the second hard mask layer 192, buffer layer 191, low-k dielectric layer 180, and barrier layer 120 are etched to form the second groove 201, as shown. Figure 7As shown, in this step, the second photomask 152 is etched together to remove it. The second groove 201 can be a trench structure or a through-hole structure. The second groove 201 corresponds to the position of the first groove 160, and along the second direction, the size of the second groove 201 is smaller than that of the first groove 160. Figure 7 The upper and lower sections of the second groove 201 on the left side are basically the same width. The second photomask 152 corresponding to the left half of the second groove 201 on the right side is formed by a semi-transparent pattern, so that the lower section of the second groove 201 in this part is narrower than the upper section.

[0073] Furthermore, a conductive fill layer 210 is formed covering the second hard mask layer 192, and the conductive fill layer 210 also fills the second groove 201, such as... Figure 8 As shown, the material of the conductive filling layer 210 is, for example, copper.

[0074] Further, the conductive filling layer 210 is ground, and the remaining conductive filling layer 210 filling the second groove forms conductive channels 211 and 212, as shown. Figure 9 As shown, conductive channels 211 and 212 are connected to interconnect regions 102 on the metal layer 110.

[0075] In this step, the chemical mechanical polishing of the conductive filler layer 210 stops on the low-K dielectric layer 180 on the stacked structure 130 to prevent the ultra-low-K dielectric layer 132, which is softer and has lower mechanical strength, from being polished and damaged.

[0076] In this embodiment, along the second direction, the width of the ultra-low K dielectric layer 132 can be preset according to the layout of the subsequent metal lines. For example, between the conductive channels 211 and 212, the width of the ultra-low K dielectric layer 132 can account for up to 70%, thereby making the overall dielectric constant K of the dielectric layer lower.

[0077] Figure 10 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure is shown.

[0078] See Figure 10 The semiconductor structure formed using the above manufacturing method includes: a structural layer with interconnect regions 102, an interlayer dielectric layer 10, and conductive channels 211 and 212. The structural layer includes a substrate 101 and a metal layer 110. The interlayer dielectric layer 10 is located on the metal layer 110. The conductive channels 211 and 212 penetrate the interlayer dielectric layer 10 and are connected to the interconnect regions 102 on the metal layer 110. In the back-end processes of the semiconductor device, multiple metal layers 110 and interlayer dielectric layers 10 are stacked alternately.

[0079] In this embodiment, the specific structure of the interlayer dielectric layer 10 can be referred to Figure 9The description includes, for example, a stacked structure 130 and a low-k dielectric layer 180. The stacked structure 130 is located on a structural layer and includes a spacer dielectric layer 131 and an ultra-low-k dielectric layer 132 stacked along a first direction, which is the thickness direction of the structural layer. The low-k dielectric layer 180 is located on the stacked structure 130 and extends through the stacked structure 130 along the first direction. Conductive channels 211 and 212 extend through the low-k dielectric layer 180 along the first direction and are connected to the interconnect region 102. In a second direction perpendicular to the first direction, the spacer dielectric layer 131 is smaller than the ultra-low-k dielectric layer 132, forming a recess. The low-k dielectric layer 180 fills the recess, forming a protrusion, so that the spacer dielectric layer 131, the ultra-low-k dielectric layer 132, and the low-k dielectric layer 180 form an interlocking structure to increase the mechanical strength of the interlayer dielectric layer 10.

[0080] In some optional embodiments, there are multiple ultra-low-k dielectric layers 132, with spacer dielectric layers 131 located between adjacent ultra-low-k dielectric layers 132, and / or multiple spacer dielectric layers 131 and multiple ultra-low-k dielectric layers 132, with the multiple spacer dielectric layers 131 and multiple ultra-low-k dielectric layers 132 stacked alternately. In each interlayer dielectric layer 10, along the first direction, the number of interlocking structures increases with the increase in the number of stacked spacer dielectric layers 131 and ultra-low-k dielectric layers 132.

[0081] In some alternative embodiments, the semiconductor structure further includes a protective layer 170 located between the stacked structure 130 and the low-k dielectric layer 180.

[0082] In this embodiment, the interlayer dielectric layer 10 is a composite structure, including a spacer dielectric layer 131, an ultra-low K dielectric layer 132, and a low K dielectric layer 180. The total dielectric constant K is no greater than 2.3, and the Young's modulus E can reach about 12 GPa. It can ensure the mechanical strength of the dielectric layer through the interlocking structure with concave and convex shapes, and can also control the dielectric constant K below 2.3. Therefore, it can effectively reduce RCDelay and improve device speed and reliability.

[0083] As described above, these embodiments of the present disclosure do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present disclosure, thereby enabling those skilled in the art to make good use of the present disclosure and modifications based on it. The scope of protection of this disclosure should be determined by the scope defined by the claims and their equivalents.

Claims

1. A semiconductor structure, comprising: A structural layer having interconnection regions; A stacked structure, located on the structural layer, includes a spacer dielectric layer and an ultra-low K dielectric layer stacked along a first direction, wherein the first direction is the thickness direction of the structural layer; A low-k dielectric layer extends through the stacked structure along the first direction; as well as A conductive channel extends along the first direction through the low-k dielectric layer and connects to the interconnect region. In this configuration, along the second direction, the size of the spacer dielectric layer is smaller than the size of the ultra-low-k dielectric layer, forming a recess. The low-k dielectric layer fills the recess, forming a protrusion, so that the spacer dielectric layer, the ultra-low-k dielectric layer, and the low-k dielectric layer form an interlocking structure. The second direction is perpendicular to the first direction.

2. The semiconductor structure according to claim 1, wherein, The number of ultra-low k dielectric layers is multiple, and the spacer dielectric layer is located between two adjacent ultra-low k dielectric layers. And / or there are multiple spacer layers and multiple ultra-low K dielectric layers, with the spacer layers and the ultra-low K dielectric layers stacked alternately.

3. The semiconductor structure according to claim 1, wherein, The low-K dielectric layer is also located on the stacked structure.

4. The semiconductor structure according to claim 1 further includes a protective layer located between the stacked structure and the low-k dielectric layer.

5. A method for manufacturing a semiconductor structure, comprising: A stacked structure is formed on a structural layer having interconnection regions, the stacked structure comprising a spacer dielectric layer and an ultra-low K dielectric layer stacked along a first direction, the first direction being the thickness direction of the structural layer; The stacked structure is etched to form a first groove; A low-k dielectric layer is formed within the first groove; The low-k dielectric layer is etched to form a second groove; as well as A conductive channel is formed in the second groove, and the conductive channel is connected to the interconnect region. In this process, along the second direction, the etching rate of the spacer dielectric layer is greater than the etching rate of the ultra-low-k dielectric layer, so as to form a recess at the sidewall of the first groove. The low-k dielectric layer forms a protrusion at the recess so that the spacer dielectric layer, the ultra-low-k dielectric layer, and the low-k dielectric layer constitute an interlocking structure. The second direction is perpendicular to the first direction.

6. The manufacturing method according to claim 5, wherein, The step of forming a low-k dielectric layer in the first groove includes: The reaction chamber is supplied with plasma-form oxygen free radicals and plasma-form silicon-, oxygen-, carbon-, and hydrogen-containing precursors. The oxygen free radicals react with the silicon-, oxygen-, carbon-, and hydrogen-containing precursor to generate a flowable low-k dielectric layer, which is then deposited within the first groove; and The low-k dielectric layer is solidified.

7. The manufacturing method according to claim 5, wherein, The low-k dielectric layer is also located on the stacked structure, and the chemical mechanical polishing of the conductive filling layer used to form the conductive channel stops on the low-k dielectric layer on the stacked structure.

8. The manufacturing method according to claim 5, further comprising forming a protective layer on the inner surface of the first groove before forming the low-k dielectric layer. in, The low-K dielectric layer is separated from the stacked structure by the protective layer.

9. The manufacturing method according to any one of claims 5 to 8, wherein, The carbon content in the spacer dielectric layer is less than the carbon content in the ultra-low K dielectric layer, so that the etching rate of the spacer dielectric layer along the second direction is greater than the etching rate of the ultra-low K dielectric layer.

10. The manufacturing method according to any one of claims 5 to 8, wherein, In the steps of the first groove and the second groove, the photoresist is patterned through the fully transparent and semi-transparent portions of the halftone mask to form a photomask, and the underlying structure is etched through the photomask so that the lower width of a portion of the first groove and the second groove is smaller than the upper width.

Images