Voltage sampling circuit and LED driving chip

Abstract

The application belongs to the technical field of electronic circuits, and provides a voltage sampling circuit and an LED driving chip. The voltage sampling circuit comprises a current output module, a voltage sampling module and a buffer module; the voltage sampling module is connected with the current output module and the buffer module respectively, a common end of the voltage sampling module, the current output module and the buffer module is a first node, and the voltage sampling module is further used for being connected with sampling points of n LED channels, wherein n is a natural number greater than zero. The voltage sampling module can identify the lowest sampling point voltage in the n sampling point voltages, and through a feedback loop between the voltage sampling module and the first node, the voltage at the first node becomes a second voltage related to the lowest sampling point voltage, and finally the lowest sampling point voltage is output through the processing of the buffer module, so that more accurate sampling of the lowest sampling point voltage is realized, and then the LED driving chip can make an accurate response to ensure the normal work of the n LED channels.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic circuits, and particularly relates to a voltage sampling circuit and an LED driving chip. BACKGROUND

[0002] In electronic devices using DCDC (Direct Current to Direct Current) switching power supplies, LED (Light-Emitting Diode) driving chips for driving electronic screens have been widely applied. In order to achieve high-precision performance of the LED driving chip, the voltage sampling precision of each LED channel should be improved.

[0003] The lowest sampling point voltage sampling circuit is used for sampling the voltages of a plurality of LED channels and outputting the lowest sampling point voltage in the plurality of LED channels; the LED driving chip adjusts its output voltage according to the lowest sampling point voltage to ensure that the plurality of LED channels can work normally. However, the lowest sampling point voltage output by the traditional lowest sampling point voltage sampling circuit is insufficient in precision, which causes the LED driving chip to be unable to make accurate responses. SUMMARY

[0004] Embodiments of the application provide a voltage sampling circuit and an LED driving chip, which can solve the problem of insufficient precision of the lowest sampling point voltage output by the traditional lowest sampling point voltage sampling circuit, which causes the LED driving chip to be unable to make accurate responses.

[0005] In a first aspect, embodiments of the application provide a voltage sampling circuit, comprising a current output module, a voltage sampling module and a buffer module; the voltage sampling module is connected with the current output module and the buffer module respectively, a common end of the voltage sampling module, the current output module and the buffer module is a first node, and the voltage sampling module is further used for being connected with sampling points of n LED channels, wherein n is a natural number greater than zero;

[0006] The current output module is used for outputting a first current to the first node, so that the voltage at the first node becomes a first voltage; the voltage sampling module is used for outputting a second current to the first node according to the first voltage and the lowest sampling point voltage in the n sampling point voltages collected, so that the voltage at the first node becomes a second voltage; and the buffer module is used for outputting a target voltage according to the second voltage, and the target voltage is the lowest sampling point voltage.

[0007] In a possible implementation manner of the first aspect, the current output module comprises a first current source, an input end of the first current source receives a power supply voltage, and output ends of the first current source are connected with the voltage sampling module and the buffer module respectively.

[0008] The first current source is configured to output a first current to the first node, so that a voltage at the first node becomes a first voltage.

[0009] In a possible implementation of the first aspect, the voltage sampling module includes n voltage sampling units, which are respectively connected to the current output module and the buffer module, and are further configured to be connected to sampling points of the n LED channels correspondingly.

[0010] The target voltage sampling unit is configured to output a second current to the first node according to the first voltage and the lowest sampling point voltage, so that a voltage at the first node becomes a second voltage; wherein the target voltage sampling unit is a unit receiving the lowest sampling point voltage among the n voltage sampling units.

[0011] In a possible implementation of the first aspect, the voltage sampling unit includes a sampling tube and a shunt sub-unit, a source of the sampling tube is connected to the shunt sub-unit, the current output module and the buffer module respectively, a gate of the sampling tube is configured to be connected to a sampling point of an LED channel, and a drain of the sampling tube is connected to the shunt sub-unit.

[0012] For the target voltage sampling unit, the sampling tube outputs a third current under the action of the first voltage and the lowest sampling point voltage; the shunt sub-unit is configured to provide a fourth current, and output a second current to the first node according to the third current and the fourth current, so that a voltage at the first node becomes a second voltage; wherein the fourth current is equal to 1 / n times of the first current, and the second voltage is equal to a sum of the lowest sampling point voltage and a gate-source voltage of the sampling tube.

[0013] In a possible implementation of the first aspect, the shunt sub-unit includes a first transistor, a second current source and a third current source, a gate of the first transistor is connected to an output end of the second current source, an input end of the third current source and a drain of the sampling tube respectively, a drain of the first transistor is connected to a source of the sampling tube, the current output module and the buffer module respectively, an input end of the second current source receives a power supply voltage, and a source of the first transistor and an output end of the third current source are both grounded.

[0014] The second current source is configured to output a first bias current; and the third current source is configured to output a second bias current; wherein the fourth current is a difference between the second bias current and the first bias current.

[0015] In a possible implementation manner of the first aspect, the buffer module comprises an input unit, an intermediate stage unit and an output unit, the input unit is connected with the current output module, the voltage sampling module, the output unit and the intermediate stage unit respectively, and the intermediate stage unit is connected with the output unit;

[0016] The input unit is configured to output fifth and sixth currents according to the second and third voltages; the intermediate stage unit is configured to output a fourth voltage according to the fifth and sixth currents; and the output unit is configured to output the third and target voltages according to the fourth voltage.

[0017] In a possible implementation manner of the first aspect, the input unit comprises a fourth current source, a second transistor and a third transistor, a source of the second transistor is connected with a source of the third transistor and an output terminal of the fourth current source respectively, an input terminal of the fourth current source receives a power supply voltage, a gate of the third transistor is connected with the current output module and the voltage sampling module respectively, for receiving a second voltage, a gate of the second transistor is connected with the output unit, for receiving a third voltage, a drain of the third transistor is connected with the intermediate stage unit, and a drain of the second transistor is connected with the intermediate stage unit.

[0018] In a possible implementation manner of the first aspect, the intermediate stage unit comprises a fifth current source, a sixth current source, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, an input terminal of the fifth current source and an input terminal of the sixth current source both receive a power supply voltage, an output terminal of the fifth current source is connected with a drain of the fourth transistor and the output unit respectively, for outputting a fourth voltage, a gate of the fourth transistor and a gate of the fifth transistor receive a bias voltage, a source of the fourth transistor is connected with the input unit and a drain of the sixth transistor respectively, for receiving a fifth current, an output terminal of the sixth current source is connected with a drain of the fifth transistor, a gate of the sixth transistor and a gate of the seventh transistor respectively, a source of the fifth transistor is connected with the input unit and a drain of the seventh transistor respectively, for receiving a sixth current, and a source of the sixth transistor and a source of the seventh transistor are both grounded.

[0019] In a possible implementation manner of the first aspect, the output unit comprises a seventh current source, an eighth transistor and a ninth transistor, a drain of the eighth transistor receives a power supply voltage, a gate of the eighth transistor is connected with the intermediate stage unit and is configured to receive the fourth voltage, sources of the eighth transistor and the ninth transistor are connected with the input unit and the input of the seventh current source respectively and are configured to output a third voltage, a gate of the ninth transistor is connected with the drain of the ninth transistor and the input of the seventh current source, a common terminal of the gate of the ninth transistor, the drain of the ninth transistor and the input of the seventh current source is a second node configured to output a target voltage, and an output terminal of the seventh current source is grounded; wherein the target voltage is equal to the second voltage minus a gate-source voltage of the ninth transistor; and the ninth transistor has the same size as the sampling transistor.

[0020] In a second aspect, the embodiments of the present application provide an LED driving chip, comprising the voltage sampling circuit in any of the first aspect.

[0021] In a third aspect, the embodiments of the present application provide an electronic device, comprising the driving chip in any of the second aspect.

[0022] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0023] The embodiments of the present application provide a voltage sampling circuit, comprising a current output module, a voltage sampling module and a buffer module; the voltage sampling module is connected with the current output module and the buffer module respectively, a common terminal of the voltage sampling module, the current output module and the buffer module is a first node, and the voltage sampling module is further configured to be connected with sampling points of n LED channels. Wherein, n is a natural number greater than zero.

[0024] The current output module is configured to output a first current to the first node, so that the voltage at the first node becomes a first voltage. The voltage sampling module is configured to output a second current to the first node according to the first voltage and the lowest sampling point voltage in the n collected sampling point voltages, so that the voltage at the first node becomes a second voltage. The buffer module is configured to output a target voltage according to the second voltage, and the target voltage is the lowest sampling point voltage.

[0025] The voltage sampling module can identify the lowest sampling point voltage in the n sampling points, and through the feedback loop between the voltage sampling module and the first node, the voltage at the first node becomes the second voltage related to the lowest sampling point voltage. Finally, the lowest sampling point voltage is output through the processing of the buffer module, which realizes more accurate sampling of the lowest sampling point voltage, and further ensures that the LED driving chip can make accurate response to ensure the normal work of the n LED channels.

[0026] In conclusion, the voltage sampling circuit provided by the embodiments of the present application solves the problem of insufficient precision of the lowest sampling point voltage output by the conventional lowest sampling point voltage sampling circuit, which causes the LED driving chip to fail to make accurate response.

[0027] It can be understood that the beneficial effects of the second aspect to the third aspect can be referred to the related description in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0029] Figure 1 is a schematic diagram of a conventional lowest sampling point voltage sampling circuit;

[0030] Figure 2 is a schematic diagram of a voltage sampling circuit provided by an embodiment of the present application;

[0031] Figure 3 is a schematic diagram of a voltage sampling circuit provided by another embodiment of the present application;

[0032] Figure 4 is a schematic diagram of a voltage sampling circuit provided by an embodiment of the present application;

[0033] Figure 5 is a schematic diagram of a voltage sampling circuit provided by another embodiment of the present application;

[0034] Figure 6 is a schematic diagram of a voltage sampling circuit provided by another embodiment of the present application.

[0035] In the figure: 10, voltage sampling circuit; 11, current output module; 12, voltage sampling module; 121, voltage sampling unit; 1211, shunt sub-unit; 13, buffer module; 131, input unit; 132, intermediate stage unit; 133, output unit. DETAILED DESCRIPTION

[0036] In the following description, specific details such as specific system structures, techniques, etc. are presented in order to thoroughly understand the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits and methods are omitted in order not to obscure the description of the present application with unnecessary details.

[0037] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0038] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0039] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0040] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0041] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0042] Figure 1 The schematic diagram of a traditional lowest sampling point voltage sampling circuit is shown. Figure 1 As shown, the lowest sampling point voltage sampling circuit is connected to the sampling points S1, S2, ..., Sn of n LED channels respectively, and is used to sample the voltage V at the n sampling points. HRADROOM1 V HRADROOM2 ,……,V HRADROOMn Data is collected, and the voltage V at n sampling points is used as the basis for the data acquisition. HRADROOM1 V HRADROOM2 ,……,V HRADROOMnOutput minimum sampling point voltage V HRADROOMmin Where n is a natural number greater than zero. The comparator circuit in the LED driver chip uses the reference voltage and the lowest sampling point voltage V... HRADROOMmin A comparison signal is output to the BOOST circuit. The BOOST circuit adjusts its output voltage V based on the comparison signal. BOOST_OUT This is to ensure that all n LED channels can function properly.

[0043] However, the lowest sampling point voltage V output by the traditional lowest sampling point voltage sampling circuit HRADROOMmin Insufficient precision causes the BOOST circuit in the LED driver chip to fail to respond accurately, thus affecting the operation of n LED channels.

[0044] To address the problem that traditional minimum sampling point voltage sampling circuits produce insufficient accuracy in their output minimum sampling point voltage, leading to inaccurate responses from LED driver chips, this application provides a voltage sampling circuit, such as... Figure 2 As shown, the voltage sampling circuit 10 includes a current output module 11, a voltage sampling module 12, and a buffer module 13. The voltage sampling module 12 is connected to both the current output module 11 and the buffer module 13. The common terminal of the voltage sampling module 12, the current output module 11, and the buffer module 13 is the first node A1. The voltage sampling module 12 is also used to connect to the sampling points S1, S2, ..., Sn of n LED channels. Here, n is a natural number greater than zero.

[0045] The current output module 11 is used to output a first current to the first node A1, so that the voltage at the first node A1 becomes a first voltage. The voltage sampling module 12 is used to sample the voltages V at n sampling points based on the first voltage. HRADROOM1 V HRADROOM2 ,……,V HRADROOMn The lowest sampling point voltage V HRADROOMmin A second current is output to the first node A1, causing the voltage at the first node A1 to change to the second voltage. Buffer module 13 is used to output the target voltage V based on the second voltage. M Target voltage V M The lowest sampling point voltage V HRADROOMmin .

[0046] Voltage sampling module 12 can identify the voltage V at n sampling points. HRADROOM1 V HRADROOM2 ,……,V HRADROOMn The lowest sampling point voltage V HRADROOMmin And through the feedback loop between the voltage sampling module 12 and the first node A1, the voltage at the first node A1 is made to be the same as the voltage at the lowest sampling point V. HRADROOMminThe relevant second voltage is finally processed by buffer module 13 to output the lowest sampling point voltage V. HRADROOMmin This achieves a more accurate minimum sampling point voltage V. HRADROOMmin The sampling ensures that the LED driver chip can make an accurate response, thereby guaranteeing the normal operation of n LED channels.

[0047] In summary, the voltage sampling circuit 10 provided in this application embodiment solves the problem that the accuracy of the lowest sampling point voltage output by the traditional lowest sampling point voltage sampling circuit is insufficient, which causes the LED driver chip to be unable to make an accurate response.

[0048] like Figure 3 As shown, the voltage sampling module 12 includes n voltage sampling units 121, which are respectively connected to the current output module 11 and the buffer module 13. The n voltage sampling units 121 are also used to connect to the sampling points S1, S2, ..., Sn of the n LED channels.

[0049] Specifically, the target voltage sampling unit is used to sample the first voltage and the lowest sampling point voltage V. HRADROOMmin A second current is output to the first node A1, causing the voltage at the first node A1 to become the second voltage. The target voltage sampling unit is the lowest sampling point voltage V among the n voltage sampling units 121. HRADROOMmin The unit.

[0050] like Figure 4 As shown, the voltage sampling unit 121 includes a sampling transistor and a shunt subunit 1211. The source of the sampling transistor is connected to the shunt subunit 1211, the current output module 11, and the buffer module 13, respectively. The gate of the sampling transistor is connected to the sampling point of the LED channel, and the drain of the sampling transistor is connected to the shunt subunit 1211. It should be noted that the sampling transistor in the first voltage sampling unit 121 is represented by Mc1, and its gate is connected to the sampling point S1 of the first LED channel to collect the sampling point voltage V. HRADROOM1 The sampling tube in the second voltage sampling unit 121 is represented by Mc2, and its gate is used to connect to the sampling point S2 of the second LED channel to collect the sampling point voltage V. HRADROOM2 Similarly, the sampling tube in the nth voltage sampling unit 121 is represented by Mcn, and its gate is used to connect to the sampling point Sn of the nth LED channel to collect the sampling point voltage V. HRADROOMn .

[0051] Specifically, for the target voltage sampling unit, the sampling tube is at the first voltage and the lowest sampling point voltage V. HRADROOMminunder the action of the first current source CS1, the voltage at the first node A1 becomes the first voltage. The first current source CS1 is configured to output the first current to the first node A1, so that the voltage at the first node A1 becomes the first voltage. HRADROOMmin The sum of the gate-source voltage of the sampling tube.

[0052] As shown in Figure 4 The current output module 11 includes a first current source CS1, and an input end of the first current source CS1 receives a power supply voltage VDD, and output ends of the first current source CS1 are connected with the voltage sampling module 12 and the buffer module 13 respectively.

[0053] Specifically, the first current source CS1 is configured to output the first current to the first node, so that the voltage at the first node A1 becomes the first voltage.

[0054] As shown in Figure 5 The shunt unit 1211 includes a first transistor M1, a second current source CS2 and a third current source CS3, a gate of the first transistor M1 is connected with an output end of the second current source CS2, an input end of the third current source CS3 and a drain of the sampling tube respectively, a drain of the first transistor M1 is connected with a source of the sampling tube, the current output module 11 and the buffer module 13 respectively, an input end of the second current source CS2 receives the power supply voltage VDD, and a source of the first transistor M1 and an output end of the third current source CS3 are grounded. It should be noted that for the first voltage sampling unit 121, the gate of the first transistor M1 is connected with the output end of the second current source CS2, the input end of the third current source CS3 and the drain of the Mc1 tube respectively, and the drain of the first transistor M1 is connected with the source of the Mc1 tube, the current output module 11 and the buffer module 13 respectively; for the second voltage sampling unit 121, the gate of the first transistor M1 is connected with the output end of the second current source CS2, the input end of the third current source CS3 and the drain of the Mc2 tube respectively, and the drain of the first transistor M1 is connected with the source of the Mc2 tube, the current output module 11 and the buffer module 13 respectively; and so on, for the nth voltage sampling unit 121, the gate of the first transistor M1 is connected with the output end of the second current source CS2, the input end of the third current source CS3 and the drain of the Mcn tube respectively, and the drain of the first transistor M1 is connected with the source of the Mcn tube, the current output module 11 and the buffer module 13 respectively.

[0055] Specifically, the second current source CS2 is configured to output the first bias current IB1. The third current source CS3 is configured to output the second bias current IB2. The fourth current is the difference between the second bias current IB2 and the first bias current IB1, i.e. IB2-IB1. Since the fourth current is equal to 1 / n times of the first current, the first current is n*(IB2-IB1).

[0056] As shown in Figure 3 , the buffer module 13 includes an input unit 131, an intermediate stage unit 132 and an output unit 133. The input unit 131 is connected with the current output module 11, the voltage sampling module 12, the output unit 133 and the intermediate stage unit 132 respectively. The intermediate stage unit 132 is connected with the output unit 133.

[0057] Specifically, the input unit 131 is configured to output a fifth current and a sixth current according to the second voltage and the third voltage. The intermediate stage unit 132 is configured to output a fourth voltage according to the fifth current and the sixth current. The output unit 133 is configured to output the third voltage and a target voltage V M .

[0058] As shown in Figure 6 , the input unit 131 includes a fourth current source CS4, a second transistor M2 and a third transistor M3. The source of the second transistor M2 is connected with the source of the third transistor M3 and the output of the fourth current source CS4 respectively. The input of the fourth current source CS4 receives a power voltage VDD. The gate of the third transistor M3 is connected with the current output module 11 and the voltage sampling module 12 respectively, for receiving the second voltage. The gate of the second transistor M2 is connected with the output unit 133, for receiving the third voltage. The drain of the third transistor M3 is connected with the intermediate stage unit 132. The drain of the second transistor M2 is connected with the intermediate stage unit 132.

[0059] Specifically, the fourth current source CS4 is configured to provide a bias current. The second transistor M2 is configured to convert the third voltage into the fifth current. The third transistor M3 is configured to convert the second voltage into the sixth current.

[0060] As shown in Figure 6As shown, the intermediate stage unit 132 includes a fifth current source CS5, a sixth current source CS6, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7, the input terminals of the fifth current source CS5 and the sixth current source CS6 both receive the power supply voltage VDD, the output terminal of the fifth current source CS5 is connected with the drain of the fourth transistor M4 and the output unit 133 respectively, for outputting a fourth voltage, the gate of the fourth transistor M4 and the gate of the fifth transistor M5 receive a bias voltage VB, the source of the fourth transistor M4 is connected with the input unit 131 and the drain of the sixth transistor M6 respectively, for receiving a fifth current, the output terminal of the sixth current source CS6 is connected with the drain of the fifth transistor M5, the gate of the sixth transistor M6 and the gate of the seventh transistor M7 respectively, the source of the fifth transistor M5 is connected with the input unit 131 and the drain of the seventh transistor M7 respectively, for receiving a sixth current, and the source of the sixth transistor M6 and the source of the seventh transistor M7 are both grounded.

[0061] Specifically, the fifth current source CS5 and the sixth current source CS6 are used to provide bias currents. The current of the branch where the fourth transistor M4 is located is affected by the fifth current output by the input unit 131, and the current of the branch where the fifth transistor M5 is located is affected by the sixth current output by the input unit 131. Under the action of the fifth current and the sixth current, the fourth voltage is finally formed at the output terminal of the fifth current source CS5.

[0062] As shown in the figure, Figure 6 The output unit 133 includes a seventh current source CS7, an eighth transistor M8 and a ninth transistor M9. The drain of the eighth transistor M8 receives the power supply voltage VDD, the gate of the eighth transistor M8 is connected with the intermediate stage unit 132, for receiving the fourth voltage, the source of the eighth transistor M8 is connected with the input unit 131 and the source of the ninth transistor M9 respectively, for outputting a third voltage, the common terminal of the source of the eighth transistor M8, the input unit 131 and the source of the ninth transistor M9 is a third node A3, the gate of the ninth transistor M9 is connected with the drain of the ninth transistor M9 and the input terminal of the seventh current source CS7 respectively, the common terminal of the gate of the ninth transistor M9, the drain of the ninth transistor M9 and the input terminal of the seventh current source CS7 is a second node A2, for outputting a target voltage V M , and the output terminal of the seventh current source CS7 is grounded. Wherein, the target voltage V M is equal to the second voltage minus the gate-source voltage of the ninth transistor M9; the size of the ninth transistor M9 is the same as that of the sampling tube. Since the size of the ninth transistor M9 is the same as that of the sampling tube, the gate-source voltage of the ninth transistor M9 is equal to the gate-source voltage of the sampling tube; and since the second voltage is equal to the sum of the lowest sampling point voltage V HRADROOMmin and the gate-source voltage of the sampling tube, the target voltage V Mthe lowest sampling point voltage V HRADROOMmin .

[0063] Specifically, the seventh current source CS7 is configured to provide a bias current. The eighth transistor M8 generates a current according to the fourth voltage, which affects the current of the branch where the eighth transistor M8 is located, and finally outputs the third voltage at the third node A3 and the target voltage V M . It should be noted that the third voltage is equal to the second voltage.

[0064] The working principle of the present application will be described in detail according to Figure 5 and Figure 6 .

[0065] As shown in Figure 5 , the present application has n sampling tubes, which are Mc1 tube, Mc2 tube, …, Mcn tube.

[0066] The gate of the Mc1 tube, the gate of the Mc2 tube, …, and the gate of the Mcn tube are configured to be connected with the sampling points S1, S2, …, and Sn of the n LED channels, so as to collect the n sampling point voltages V HRADROOM1 , V HRADROOM2 , …, and V HRADROOMn . The drain of the Mc1 tube, the drain of the Mc2 tube, …, and the drain of the Mcn tube are connected with the n shunt sub-units 1211.

[0067] The shunt sub-unit 1211 is configured to provide a fourth current, the second current source CS2 inside the shunt sub-unit 1211 provides a first bias current IB1, and the third current source CS3 provides a second bias current IB2, the second bias current IB2 being greater than the first bias current IB1, and the two bias currents are configured to limit the current flowing through the sampling tube; wherein the fourth current is IB2-IB1.

[0068] The current bias at the first node A1 is a first current, so that the voltage at the first node A1 becomes a first voltage, wherein the first current is n*(IB2-IB1).

[0069] Suppose that the n sampling point voltages V HRADROOM1 , V HRADROOM2 , …, and V HRADROOMn are all the same, then the current of the branch where each voltage sampling unit 121 is located is the same, which is IB2-IB1, so that the feedback loop between the voltage sampling module 12 and the first node A1 does not work. However, in the actual collection process, the n sampling point voltages V HRADROOM1 , V HRADROOM2 , …, and V HRADROOMn are not the same, and suppose that the first voltage sampling unit 121 receives the lowest sampling point voltage V HRADROOMminTherefore, the gate-source voltage of transistor Mc1 is the largest, and the current flowing through transistor Mc1 is the largest current among the n branches, i.e., the third current. After configuring the value of the fourth current, since the third current is greater than the fourth current, the branch containing the first voltage sampling unit 121 will output a second current to the first node A1, making the voltage at the first node A1 the second voltage. The second current is the difference between the third and fourth currents, and the second voltage is the voltage V at the lowest sampling point. HRADROOMmin The sum of the gate-source voltages of the Mc1 transistor.

[0070] like Figure 6 As shown, the second voltage at the first node A1 is transmitted to the third node A3 via a folded cascode buffer, i.e., buffer module 13. The third voltage equals the second voltage. The second voltage minus the gate-source voltage of the ninth transistor M9 outputs the high-precision target voltage V from the second node A2. M That is, the voltage V at the lowest sampling point HRADROOMmin It should be noted that the dimensions of the n sampling transistors are the same as the dimensions of the ninth transistor M9. If the lowest sampling point voltage V... HRADROOMmin If the value is too low, it will affect the working state of the comparator circuit in the LED driver chip. Alternatively, the second node A2 can be used to measure the lowest sampling point voltage V. HRADROOMmin The voltage is raised, specifically the gate-source voltage of the ninth transistor M9, so that the comparator circuit can utilize the raised lowest sampling point voltage V. HRADROOMmin When making the comparison, it is important to note that the reference voltage terminal of the comparator circuit should be increased by adding a gate-source voltage that matches the ninth transistor M9.

[0071] In summary, the voltage sampling module 12 in this application can identify the voltage V at n sampling points. HRADROOM1 V HRADROOM2 ,……,V HRADROOMn The lowest sampling point voltage V HRADROOMmin And through the feedback loop between the voltage sampling module 12 and the first node A1, the voltage at the first node A1 is made to be the same as the voltage at the lowest sampling point V. HRADROOMmin The relevant second voltage is finally processed by buffer module 13 to output the lowest sampling point voltage V. HRADROOMmin This achieves a more accurate minimum sampling point voltage V. HRADROOMmin The sampling ensures that the LED driver chip can make an accurate response, thereby guaranteeing the normal operation of n LED channels.

[0072] This application also provides an LED driver chip, including the voltage sampling circuit described above. Because the LED driver chip provided in this application includes the voltage sampling circuit described above, it has the advantage of high response accuracy.

[0073] The electronic device provided by the embodiments of the present application can be any electronic device containing the LED driving chip.

[0074] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0075] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A voltage sampling circuit, characterized by, The current output module, the voltage sampling module and the buffer module are connected with each other, and the common end of the voltage sampling module, the current output module and the buffer module is a first node; the voltage sampling module is further connected with the sampling points of n LED channels, wherein n is a natural number greater than zero; The current output module is configured to output a first current to the first node, so that the voltage at the first node becomes a first voltage; the voltage sampling module is configured to output a second current to the first node according to the first voltage and the lowest sampling point voltage in the collected n sampling point voltages, so that the voltage at the first node becomes a second voltage; and the buffer module is configured to output a target voltage according to the second voltage, wherein the target voltage is the lowest sampling point voltage. The voltage sampling module includes n voltage sampling units, and each voltage sampling unit is connected with the current output module and the buffer module; and each voltage sampling unit is further connected with the sampling points of the n LED channels. The target voltage sampling unit is configured to output a second current to the first node according to the first voltage and the lowest sampling point voltage, so that the voltage at the first node becomes a second voltage; wherein the target voltage sampling unit is a unit receiving the lowest sampling point voltage among the n voltage sampling units. The voltage sampling unit includes a sampling tube and a shunt sub-unit; the source of the sampling tube is connected with the shunt sub-unit, the current output module and the buffer module; the gate of the sampling tube is connected with the sampling point of the LED channel; and the drain of the sampling tube is connected with the shunt sub-unit. For the target voltage sampling unit, the sampling tube outputs a third current under the action of the first voltage and the lowest sampling point voltage; the shunt sub-unit is configured to provide a fourth current, and output a second current to the first node according to the third current and the fourth current, so that the voltage at the first node becomes a second voltage; wherein the fourth current is equal to 1 / n times of the first current, and the second voltage is equal to the sum of the lowest sampling point voltage and the gate-source voltage of the sampling tube.

2. The voltage sampling circuit of claim 1, wherein, The current output module includes a first current source, the input end of the first current source receives a power supply voltage, and the output end of the first current source is connected with the voltage sampling module and the buffer module. The first current source is configured to output a first current to the first node, so that the voltage at the first node becomes a first voltage.

3. The voltage sampling circuit of claim 1, wherein, The shunt sub-unit includes a first transistor, a second current source and a third current source; the gate of the first transistor is connected with the output end of the second current source, the input end of the third current source and the drain of the sampling tube; the drain of the first transistor is connected with the source of the sampling tube, the current output module and the buffer module; the input end of the second current source receives a power supply voltage; and the source of the first transistor and the output end of the third current source are grounded. The second current source is configured to output a first bias current. The third current source is configured to output a second bias current; wherein the fourth current is a difference between the second bias current and the first bias current.

4. The voltage sampling circuit of claim 1, wherein, The buffer module comprises an input unit, an intermediate unit and an output unit, the input unit is connected with the current output module, the voltage sampling module, the output unit and the intermediate unit respectively, and the intermediate unit is connected with the output unit; The input unit is configured to output a fifth current and a sixth current according to the second voltage and a third voltage; the intermediate unit is configured to output a fourth voltage according to the fifth current and the sixth current; and the output unit is configured to output the third voltage and the target voltage according to the fourth voltage.

5. The voltage sampling circuit of claim 4, wherein, The input unit comprises a fourth current source, a second transistor and a third transistor, the source of the second transistor is connected with the source of the third transistor and the output terminal of the fourth current source respectively, the input terminal of the fourth current source receives a power voltage, the gate of the third transistor is connected with the current output module and the voltage sampling module respectively, and is configured to receive a second voltage, the gate of the second transistor is connected with the output unit, and is configured to receive a third voltage, the drain of the third transistor is connected with the intermediate unit, and the drain of the second transistor is connected with the intermediate unit.

6. The voltage sampling circuit of claim 4, wherein, The intermediate unit comprises a fifth current source, a sixth current source, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, the input terminal of the fifth current source and the input terminal of the sixth current source both receive a power voltage, the output terminal of the fifth current source is connected with the drain of the fourth transistor and the output unit respectively, and is configured to output a fourth voltage, the gate of the fourth transistor and the gate of the fifth transistor receive a bias voltage, the source of the fourth transistor is connected with the input unit and the drain of the sixth transistor respectively, and is configured to receive a fifth current, the output terminal of the sixth current source is connected with the drain of the fifth transistor, the gate of the sixth transistor and the gate of the seventh transistor respectively, the source of the fifth transistor is connected with the input unit and the drain of the seventh transistor respectively, and is configured to receive a sixth current, and the source of the sixth transistor and the source of the seventh transistor are both grounded.

7. The voltage sampling circuit of claim 4, wherein, The output unit comprises a seventh current source, an eighth transistor and a ninth transistor, the drain of the eighth transistor receives a power voltage, the gate of the eighth transistor is connected with the intermediate unit, and is configured to receive a fourth voltage, the source of the eighth transistor is connected with the input unit and the source of the ninth transistor respectively, and is configured to output a third voltage, the gate of the ninth transistor is connected with the drain of the ninth transistor and the input terminal of the seventh current source respectively, the common terminal of the gate of the ninth transistor, the drain of the ninth transistor and the input terminal of the seventh current source is a second node, and is configured to output a target voltage, and the output terminal of the seventh current source is grounded; wherein the target voltage is equal to the second voltage minus the gate-source voltage of the ninth transistor; and the ninth transistor has the same size as the sampling transistor.

8. An LED driver chip, characterized in that, The voltage sampling circuit according to any one of claims 1 to 7. The voltage sampling circuit according to any one of claims 1 to 7.

Images