Digital transceiver link self-checking method and device, medium and nuclear magnetic resonance spectrometer

Abstract

The invention discloses a digital transceiver link self-checking method and device, a medium and a nuclear magnetic resonance spectrometer, and the digital transceiver link comprises an FPGA module, a transmitting link and a receiving link, and the method comprises the steps: controlling the transmitting link and the receiving link to be switched to a self-checking channel when the digital transceiver link self-checking is started, a digital transceiver link forms a receiving and transmitting closed loop; controlling a digital-to-analog converter in the transmitting link to output a fixed-frequency continuous wave and controlling an analog-to-digital converter in the receiving link to obtain a signal to be measured, and obtaining the measurement amplitude of the signal to be measured according to a phase-locked amplification algorithm; and self-checking the link of the digital transceiver according to the measurement amplitude. Therefore, link self-inspection of a transmitting link and a receiving link is completed through a receiving and transmitting closed loop formed by the FPGA module based on a digital transceiver link in combination with a phase-locked amplification algorithm, so that high-precision digital receiving and transmitting link integrated self-inspection can be realized without adding any additional hardware circuit.

Description

Technical Field

[0001] This invention relates to the field of digital transceiver technology, and in particular to a self-testing method for a digital transceiver link, a computer-readable storage medium, a self-testing device for a digital transceiver link, and a nuclear magnetic resonance spectrometer. Background Technology

[0002] The digital transceiver is a core component of an NMR spectrometer, primarily responsible for the generation, transmission, reception, and digitization of radio frequency excitation signals. Therefore, testing the digital transceiver link is essential. Conventional transmitter testing methods involve adding a detector and a power detection analog-to-digital converter (ADC) at the hardware level. By setting different transmit gains, the ADC acquires the signal power output from the detector and calculates whether the acquired value matches the control gain, thus checking if the transmit link is functioning correctly. For receiver link testing, the transmitter needs to provide a known signal to the receiver, setting different receive gains. After the receiver acquires and quantizes the signal, peak-and-valley finding is used to confirm the amplitude of the acquired signal, and then calculating whether this amplitude matches the receive control gain. However, the problem with these technologies is that NMR spectrometers require high precision in digital transceiver gain control. Detection and peak-and-valley finding methods have limited measurement accuracy and are unsuitable for high-precision gain control testing scenarios. Furthermore, the hardware design of detectors and ADC circuits is complex. Summary of the Invention

[0003] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, the first objective of this invention is to propose a self-testing method for a digital transceiver link that can achieve high-precision integrated self-testing of the digital transceiver link without adding any additional hardware circuitry.

[0004] A second objective of this invention is to provide a computer-readable storage medium.

[0005] The third objective of this invention is to provide a self-testing device for a digital transceiver link.

[0006] The fourth objective of this invention is to provide a nuclear magnetic resonance spectrometer.

[0007] To achieve the above objectives, a first aspect of the present invention proposes a self-testing method for a digital transceiver link, wherein the digital transceiver link includes an FPGA (Field-Programmable Gate Array) module, a transmit link, and a receive link. The method includes: when initiating a self-test of the digital transceiver link, controlling the transmit link and the receive link to switch to the self-test channel, so that the digital transceiver link forms a transmit-receive closed loop; controlling the digital-to-analog converter in the transmit link to output a fixed-frequency continuous wave and controlling the analog-to-digital converter in the receive link to acquire the signal under test, and acquiring the measured amplitude of the signal under test according to a lock-in amplification algorithm; and performing a self-test on the digital transceiver link based on the measured amplitude. According to the self-testing method of the digital transceiver link of the present invention, when the self-test of the digital transceiver link is initiated, the transmitting link and the receiving link are switched to the self-test channel, forming a transmit-receive closed loop in the digital transceiver link. Then, the digital-to-analog converter in the transmitting link is controlled to output a fixed-frequency continuous wave, and the analog-to-digital converter in the receiving link is controlled to acquire the signal under test. The measured amplitude of the signal under test is obtained according to the lock-in amplification algorithm, and the digital transceiver link is self-tested based on the measured amplitude. Thus, by using an FPGA module based on the transmit-receive closed loop formed by the digital transceiver link and the lock-in amplification algorithm, the self-testing of the transmitting and receiving links is completed, thereby achieving high-precision integrated self-testing of the digital transceiver link without adding any additional hardware circuitry.

[0008] In addition, the self-testing method for the digital transceiver link according to the above embodiments of the present invention may also have the following additional technical features:

[0009] According to one embodiment of the present invention, the self-test method of the digital transceiver link is performed by three concurrent processes of the FPGA module, which respectively execute the output of a fixed frequency continuous wave by the digital-to-analog converter, the acquisition of the signal under test by the analog-to-digital converter, and the acquisition of the measurement amplitude of the signal under test according to the lock-in amplification algorithm.

[0010] According to one embodiment of the present invention, obtaining the measured amplitude of a signal under test based on a lock-in amplification algorithm includes: generating two orthogonal reference signals of the same frequency; obtaining the in-phase component and the quadrature component of the signal under test based on the signal under test and the reference signals of the same frequency; and obtaining the measured amplitude of the signal under test based on the in-phase component and the quadrature component of the signal under test.

[0011] According to one embodiment of the present invention, the same-frequency reference signal is generated by the direct digital frequency synthesizer of the FPGA module.

[0012] According to one embodiment of the present invention, both the transmit link and the receive link include amplifiers and / or attenuators; the digital transceiver link is self-tested based on the measured amplitude, including: initializing the channel gain of the digital transceiver link and obtaining the real-time measured amplitude of the signal under test; obtaining the default link AMP value, and performing a default link self-test on the digital transceiver link based on the real-time measured amplitude of the signal under test and the default link AMP value.

[0013] According to one embodiment of the present invention, the transmit link includes multiple amplifiers and / or attenuators; the digital transceiver link is self-tested based on the measured amplitude, including: sequentially controlling the multiple amplifiers and / or attenuators of the transmit link to operate for a preset time to obtain the corresponding real-time measured amplitude of the signal under test; and performing a transmit gain self-test on the digital transceiver link based on the corresponding real-time measured amplitude of the signal under test and the default link AMP value.

[0014] According to one embodiment of the present invention, the receiving link includes multiple amplifiers and / or attenuators; the digital transceiver link is self-tested based on the measured amplitude, including: sequentially controlling the multiple amplifiers and / or attenuators of the receiving link to operate for a preset time to obtain the corresponding real-time measured amplitude of the signal under test; and performing a receive gain self-test on the digital transceiver link based on the corresponding real-time measured amplitude of the signal under test and the default link AMP value.

[0015] According to one embodiment of the present invention, a self-test of a digital transceiver link based on measured amplitude includes: increasing the attenuation value of the attenuator step by step and obtaining measured amplitude; obtaining the attenuation magnitude of the attenuator at each step compared to the previous step based on the measured amplitude of each step and the measured amplitude of the previous step; and performing a self-test on each step of the attenuator based on the attenuation magnitude. According to another embodiment of the present invention, the self-test method for the digital transceiver link further includes: acquiring the self-test result of the digital transceiver link self-test and feeding it back to a host computer as calibration parameters for the amplifier and / or attenuator, wherein the self-test result includes the gain value of the amplifier and / or attenuator.

[0016] To achieve the above objectives, a computer-readable storage medium is provided in the second aspect of the present invention, which stores a self-test program for a digital transceiver link, which, when executed by a processor, implements the aforementioned self-test method for a digital transceiver link.

[0017] According to embodiments of the present invention, a computer-readable storage medium can achieve high-precision integrated self-testing of a digital transceiver link without adding any additional hardware circuitry by executing a self-test program for a digital transceiver link stored thereon.

[0018] To achieve the above objectives, a third aspect of the present invention provides a self-testing device for a digital transceiver link, wherein the digital transceiver link includes an FPGA module, a transmit link, and a receive link. The device includes: a closed-loop module, used to control the transmit link and the receive link to switch to the self-test channel when the digital transceiver link self-test is initiated, so that the digital transceiver link forms a transmit-receive closed loop; a measurement module, used to control the digital-to-analog converter in the transmit link to output a fixed-frequency continuous wave and control the analog-to-digital converter in the receive link to acquire the signal under test, and to acquire the measured amplitude of the signal under test according to a lock-in amplification algorithm; and a self-testing module, used to perform a self-test of the digital transceiver link based on the measured amplitude.

[0019] According to an embodiment of the present invention, a self-testing device for a digital transceiver link, when initiating a self-test, controls the transmitting link and the receiving link to switch to the self-test channel via a closed-loop module, forming a transmit-receive closed loop in the digital transceiver link. Then, a measurement module controls the digital-to-analog converter in the transmitting link to output a fixed-frequency continuous wave and controls the analog-to-digital converter in the receiving link to acquire the signal under test. The measured amplitude of the signal under test is obtained according to a lock-in amplification algorithm. Finally, the self-testing module performs a self-test of the digital transceiver link based on the measured amplitude. Thus, by using an FPGA module based on the transmit-receive closed loop formed by the digital transceiver link and a lock-in amplification algorithm, the self-testing of the transmitting and receiving links is completed, thereby achieving high-precision integrated self-testing of the digital transceiver link without the need for any additional hardware circuitry.

[0020] In addition, the self-testing device for the digital transceiver link according to the above embodiments of the present invention may also have the following additional technical features:

[0021] According to one embodiment of the present invention, the transmit link includes a first-stage transmit amplifier, a first-stage transmit attenuator, a second-stage transmit amplifier, and a second-stage transmit attenuator, and the receive link includes a first-stage receive amplifier, a first-stage receive attenuator, a second-stage receive amplifier, and a second-stage receive attenuator.

[0022] To achieve the above objectives, the nuclear magnetic resonance spectrometer proposed in the fourth aspect of the present invention includes the self-testing device for the digital transceiver link of the foregoing embodiments.

[0023] According to the vehicle of the present invention, by adopting the aforementioned self-testing device for digital transceiver links, high-precision integrated self-testing of digital transceiver links can be achieved without adding any additional hardware circuits.

[0024] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0025] Figure 1 This is a flowchart illustrating a self-testing method for a digital transceiver link according to an embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram of a process for obtaining the measured amplitude of a signal under test according to a lock-in amplification algorithm according to an embodiment of the present invention;

[0027] Figure 3 This is a flowchart illustrating the process of performing a self-test on the default link of a digital transceiver based on the measured amplitude, according to an embodiment of the present invention.

[0028] Figure 4 This is a schematic diagram illustrating the process of performing a self-test on the transmission link of a digital transceiver based on the measured amplitude according to an embodiment of the present invention.

[0029] Figure 5 This is a schematic diagram illustrating the process of performing a self-test on the receiving link of a digital transceiver based on the measured amplitude according to an embodiment of the present invention.

[0030] Figure 6 This is a flowchart illustrating the self-test process for each setting of the attenuator according to an embodiment of the present invention.

[0031] Figure 7 A block diagram of a self-testing device for a digital transceiver link according to an embodiment of the present invention;

[0032] Figure 8 This is a block diagram of a nuclear magnetic resonance spectrometer according to an embodiment of the present invention. Detailed Implementation

[0033] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0034] The following describes, with reference to the accompanying drawings, a self-testing method for a digital transceiver link, a computer-readable storage medium, a self-testing device for a digital transceiver link, and a nuclear magnetic resonance spectrometer according to embodiments of the present invention.

[0035] Figure 1 This is a flowchart illustrating a self-testing method for a digital transceiver link according to an embodiment of the present invention.

[0036] Specifically, in some embodiments of the present invention, the digital transceiver link includes an FPGA module, a transmit link, and a receive link, as shown in the reference. Figure 1 As shown, the self-testing method for a digital transceiver link includes:

[0037] S110 controls the transmission link and the receiving link to switch to the self-test channel when the digital transceiver link self-test is started, so that the digital transceiver link forms a closed loop for transmission and reception.

[0038] It is understood that, in this embodiment of the present invention, the digital transceiver link includes an FPGA module, a transmit link, and a receive link, wherein the FPGA module is used for the digital processing of the self-test signal, the transmit link is used for the generation and transmission of the self-test signal, and the receive link is used for the reception of the self-test signal.

[0039] Specifically, in the above embodiments of the present invention, the FPGA module controls the transmission link and the receiving link to switch to the self-test channel, so that the digital transceiver link forms a closed-loop transmission and reception mechanism. This ensures that the digital transceiver link is not interfered with by other irrelevant signals during self-testing. At the same time, the self-test signal is generated and output by the transmission link, then received by the receiving link, and digitized by the FPGA module. In this way, the self-test signal can cover all components of the digital transceiver link, so as to complete the self-test of the entire digital transceiver link.

[0040] S120 controls the digital-to-analog converter in the transmission link to output a fixed-frequency continuous wave and controls the analog-to-digital converter in the receiving link to acquire the signal under test, and obtains the measured amplitude of the signal under test according to the lock-in amplification algorithm.

[0041] It is understood that in this embodiment of the present invention, the digital-to-analog converter in the transmitting link is controlled to output a continuous wave at a fixed frequency, and the analog-to-digital converter in the receiving link is controlled to acquire the signal under test. The measured amplitude of the signal under test is obtained according to the lock-in amplification algorithm, so as to perform self-testing on the digital transceiver link based on the measured amplitude.

[0042] Optionally, in some embodiments of the present invention, three concurrent processes of the FPGA module respectively execute the output of a fixed-frequency continuous wave by a digital-to-analog converter, the acquisition of the signal under test by an analog-to-digital converter, and the acquisition of the measurement amplitude of the signal under test according to a lock-in amplification algorithm.

[0043] Specifically, in this embodiment of the present invention, based on the multi-process concurrency characteristics of the FPGA module, the FPGA module uses a first process to control the digital-to-analog converter in the transmission link to output a fixed-frequency continuous wave (an intermediate frequency signal with a frequency of f0), uses a second process to control the receiving link to receive the aforementioned fixed-frequency continuous wave, and controls the analog-to-digital converter in the receiving link to convert it into a digital signal as the signal to be measured. At the same time, the FPGA module uses a third process to synchronously run a lock-in amplification algorithm to obtain the measured amplitude of the signal to be measured.

[0044] S130, perform a self-test on the digital transceiver link based on the measured amplitude.

[0045] It is understood that in this embodiment of the present invention, the normality of the digital transceiver link is determined based on the measured amplitude of the signal under test. For example, the gain coefficients of each component of the digital transceiver link are adjusted sequentially using the control variable method. Then, the measured amplitude of the signal under test is compared with the expected signal amplitude to determine whether each component in the digital transceiver link is normal, thereby achieving high-precision integrated self-testing of the digital transceiver link. The expected signal amplitude refers to the theoretical signal amplitude calculated based on the current gain coefficient of each component.

[0046] Furthermore, in some embodiments of the present invention, reference is made to... Figure 2 As shown, the measured amplitude of the signal under test is obtained according to the lock-in amplification algorithm, including:

[0047] S210 generates two orthogonal reference signals with the same frequency.

[0048] It is understandable that we assume the expression of the signal to be measured is:

[0049]

[0050] Where Vs(t) is the signal to be measured, V sig Let ω be the amplitude of the signal to be measured, and ω0 be the frequency of the signal to be measured. The phase of the signal to be measured is denoted as .

[0051] Specifically, in this embodiment of the invention, two orthogonal reference signals with the same frequency are generated by firmware:

[0052]

[0053] Where Vr(t) is the first reference signal of the same frequency, V r Let ω0 be the amplitude of the first reference signal at the same frequency, and let ω0 be the frequency of the first reference signal at the same frequency (which is the same as the frequency of the signal under test). The phase of the first reference signal at the same frequency.

[0054]

[0055] Where Vr′(t) is the second reference signal of the same frequency, V r ω0 is the amplitude of the second reference signal (which is the same as the amplitude of the first reference signal), and ω0 is the frequency of the second reference signal (which is the same as the frequency of the signal under test). The phase of the second reference signal at the same frequency (is the same as the phase of the first reference signal at the same frequency).

[0056] S220: Based on the signal to be measured and the reference signal at the same frequency, obtain the in-phase component and quadrature component of the signal to be measured.

[0057] Specifically, in this embodiment of the invention, after the signal under test is digitized by the analog-to-digital converter, it is mixed (multiplied) with two reference signals, and the sum-frequency component is filtered out by a digital filter to obtain the in-phase component I and the quadrature component Q as follows:

[0058]

[0059] Where I(t) is the in-phase component, V sig V represents the amplitude of the aforementioned signal to be measured. r The amplitude of the aforementioned same-frequency reference, The phase of the aforementioned signal to be measured, The phase of the aforementioned reference signal at the same frequency.

[0060]

[0061] Where Q(t) is the orthogonal component, V sig V represents the amplitude of the aforementioned signal to be measured. r The amplitude of the aforementioned same-frequency reference, The phase of the aforementioned signal to be measured, The phase of the aforementioned reference signal at the same frequency.

[0062] Optionally, in some embodiments of the present invention, frequency deviation errors of the transceiver link can be checked in a timely manner by comparing the consistency of the transceiver link signal frequencies, thereby ensuring the correctness of the self-test.

[0063] S230: Obtain the measured amplitude of the signal under test based on the in-phase and quadrature components of the signal under test.

[0064] Specifically, in this embodiment of the invention, the amplitude V of the signal under test at a certain frequency is accurately calculated based on the in-phase and quadrature components. sig And the relative phase Pha between the measured signal and the reference signal:

[0065]

[0066] Among them, V sig Let I(t) be the amplitude of the signal under test at a certain frequency, I(t) be the in-phase component, Q(t) be the quadrature component, and V be the amplitude of the signal under test at a certain frequency. r The amplitude is the same as the aforementioned reference value.

[0067]

[0068] Where Pha is the relative phase between the signal to be measured and the reference signal, I(t) is the in-phase component, and Q(t) is the quadrature component.

[0069] Furthermore, in some embodiments of the present invention, the same-frequency reference signal is generated by the direct digital frequency synthesizer of the FPGA module.

[0070] It is understood that direct digital frequency synthesizers can directly generate high-precision, high-stability analog waveforms with flexible control over frequency and phase. In this embodiment of the invention, a high-precision in-frequency reference signal is generated by the direct digital frequency synthesizer of the FPGA module to accurately obtain the measurement amplitude of the signal under test, thereby achieving high-precision self-testing of the digital transceiver link. Furthermore, in some embodiments of the invention, both the transmit and receive links include amplifiers and / or attenuators, with reference... Figure 3 As shown, based on the measured amplitude, a self-test is performed on the digital transceiver link, including:

[0071] S310 initializes the channel gain of the digital transceiver link and acquires the real-time measured amplitude of the signal under test.

[0072] It is understood that in this embodiment of the present invention, the channel gain of the digital transceiver link is initialized by the FPGA module (i.e., the transceiver channel gain is controlled to the default value, the amplifier is bypassed, and the attenuator is not attenuated), and the amplitude AMP0 measured at this time is recorded as the real-time measured amplitude of the signal under test, so as to determine whether the default link of the digital transceiver is normal.

[0073] S320 obtains the default link AMP value and performs a default link self-test on the digital transceiver link based on the real-time measured amplitude of the signal under test and the default link AMP value.

[0074] It is understood that in this embodiment of the present invention, the default link self-test of the digital transceiver link is realized by comparing the real-time measured amplitude of the signal under test with the default link AMP value. For example, when the difference between the real-time measured amplitude of the signal under test (such as the aforementioned AMP0) and the default link AMP value is less than or equal to a preset threshold, the default link is judged to be normal. Conversely, when the difference between the real-time measured amplitude of the signal under test (such as the aforementioned AMP0) and the default link AMP value is greater than the threshold, the default link is judged to be abnormal. Here, the default link AMP value refers to the expected AMP value when the digital transceiver is the default link.

[0075] Furthermore, in some embodiments of the present invention, the transmit link includes multiple amplifiers and / or attenuators, referencing... Figure 4 As shown, the self-test of the digital transceiver link based on the measured amplitude also includes:

[0076] S410 sequentially controls the operation of multiple amplifiers and / or attenuators in the transmission link for a preset time to obtain the corresponding real-time measurement amplitude of the signal under test.

[0077] It is understood that, in this embodiment of the present invention, the FPGA module sequentially controls multiple amplifiers and / or attenuators of the transmission link to operate for a preset time in order to obtain the corresponding real-time measured amplitude of the signal under test. For example, when controlling one amplifier of the transmission link to operate for a preset time (the attenuator of the transmission link does not attenuate, and the other amplifiers of the transmission link are bypassed), the corresponding real-time measured amplitude of the signal under test after being amplified by the amplifier of the transmission link is obtained. Or, for example, when controlling one attenuator of the transmission link to operate for a preset time (the amplifier of the transmission link is bypassed, and the other attenuators of the transmission link do not attenuate), the corresponding real-time measured amplitude of the signal under test after being attenuated by the attenuator of the transmission link is obtained.

[0078] It should be noted that in the above embodiments of the present invention, since the lock-in amplification algorithm steps are mixing, filtering, and modulus calculation, the iteration time of the digital filter depends on the filter time constant. Therefore, the preset time should correspond to the time constant. The larger the time constant, the longer the preset time, the longer the total self-test time of the digital transceiver link, and the higher the detection accuracy. The preset time can be set according to the test accuracy requirements.

[0079] The S420 performs a transmit gain self-test on the digital transceiver link based on the real-time measured amplitude of the signal under test and the default link AMP value.

[0080] Specifically, in this embodiment of the invention, the transmit gain self-test of the digital transceiver link can be achieved by comparing the corresponding real-time measured amplitude of the signal under test with the default link AMP value. Taking the self-test of the first amplifier of the transmit link as an example: the first amplifier of the transmit link is controlled by the FPGA module (assuming the amplification gain is 20dB and the corresponding amplitude amplification factor is 10) to work for a preset time (the attenuator of the transmit link does not attenuate, and the other amplifiers of the transmit link are bypassed), and the amplitude AMP1 measured at this time is recorded as the corresponding real-time measured amplitude of the signal under test after being amplified by the first amplifier of the transmit link. Then, when the corresponding real-time measured amplitude AMP1 of the signal under test after being amplified by the first amplifier of the transmit link meets the condition (AMP1 = AMP * 10), the first amplifier of the transmit link is judged to be normal; otherwise, the first amplifier of the transmit link is judged to be abnormal. In addition, the self-test process of the other amplifiers of the transmit link is the same as the self-test process of the first amplifier of the transmit link, and will not be described again here.

[0081] Furthermore, since the transmit attenuator is adjustable within a fixed attenuation range, in this embodiment of the invention, the attenuator of the transmit link is self-tested by setting an attenuation gradient. Taking the self-test of the first attenuator of the transmit link as an example: the first attenuator of the transmit link is controlled by the FPGA module to operate for a preset time (the amplifier of the transmit link is bypassed, and other attenuators in the transmit link do not attenuate). The attenuation value of the first attenuator of the transmit link is set to 0.5dB, and the amplitude AMP2_1 measured at this time is recorded as the corresponding real-time measured amplitude of the signal under test after being attenuated (0.5dB) by the first attenuator of the transmit link. Then, when the real-time measured amplitude AMP2_1 corresponding to the signal under test after being attenuated (0.5dB) by the first attenuator of the transmit link meets the condition (AMP2_1 = AMP0 / 1.059), it is determined that the 0.5dB setting of the first attenuator of the transmit link is normal; otherwise, it is determined that the first attenuator of the transmit link is not attenuated. If the 0.5dB setting of the first attenuator in the transmission link is abnormal, then the attenuation value of the first attenuator in the transmission link is set to 1dB. The amplitude measured at this time, AMP2_2, is recorded as the real-time measured amplitude of the signal under test after attenuation (1dB) by the first attenuator in the transmission link. Then, when the real-time measured amplitude AMP2_2 after attenuation (1dB) by the first attenuator in the transmission link meets the condition (AMP2_2 = AMP2_1 / 1.059), the 1dB setting of the first attenuator in the transmission link is judged to be normal. Otherwise, the 1dB setting of the first attenuator in the transmission link is judged to be abnormal. And so on. By detecting all attenuation settings of the first attenuator in the transmission link with a gradient of 0.5dB, the self-test of the first attenuator in the transmission link is completed. In addition, the self-test process of the other attenuators in the transmission link is the same as that of the first attenuator in the transmission link, and will not be described in detail here.

[0082] It should be noted that, in some embodiments of the present invention, in the process of determining whether the real-time measured amplitude and the default link AMP value of the signal under test meet the corresponding conditions, a certain error may be allowed according to the requirements of self-test accuracy.

[0083] Therefore, in the above embodiments of the present invention, the FPGA module sequentially performs self-tests on multiple amplifiers and / or attenuators in the transmission link to achieve self-testing of the transmission gain of the digital transceiver link.

[0084] Furthermore, in some embodiments of the present invention, the receive link includes multiple amplifiers and / or attenuators, referencing... Figure 5 As shown, the self-test of the digital transceiver link based on the measured amplitude also includes:

[0085] S510 sequentially controls the operation of multiple amplifiers and / or attenuators in the receiving link for a preset time to obtain the corresponding real-time measurement amplitude of the signal under test.

[0086] It is understood that, in this embodiment of the present invention, the control method of the amplifier of the receiving link and the method of obtaining the real-time measured amplitude of the signal under test are the same as those of the amplifier of the transmitting link and the method of obtaining the real-time measured amplitude of the signal under test. Similarly, the control method of the attenuator of the receiving link and the method of obtaining the real-time measured amplitude of the signal under test are the same as those of the attenuator of the transmitting link and the method of obtaining the real-time measured amplitude of the signal under test. These will not be repeated here.

[0087] The S520 performs a receive gain self-test on the digital transceiver link based on the real-time measured amplitude of the signal under test and the default link AMP value.

[0088] It is understood that, in this embodiment of the present invention, the self-test process of the amplifier in the receiving link is the same as that of the amplifier in the receiving link, and the self-test process of the attenuator in the receiving link is the same as that of the attenuator in the aforementioned transmitting link, and will not be described again here.

[0089] Therefore, in the above embodiments of the present invention, the FPGA module sequentially performs self-tests on multiple amplifiers and / or attenuators in the receiving link to achieve self-testing of the receiving gain of the digital transceiver link.

[0090] Optionally, in some embodiments of the present invention, reference is made to... Figure 6 As shown, based on the measured amplitude, a self-test is performed on the digital transceiver link, including:

[0091] S610, gradually increases the attenuation value of the attenuator and obtains the measured amplitude.

[0092] It is understood that in this embodiment of the present invention, if the attenuator is normal, the attenuation amplitude of the corresponding real-time measured amplitude remains unchanged when the attenuation value of the attenuator is increased step by step. For example, when the attenuator attenuates by 0.5dB, the corresponding measured amplitude AMP2_1 is 1 / 1.059 of the measured amplitude AMP0 of the default link (without attenuation) (AMP2_1 = AMP0 / 1.059), and when the attenuator attenuates by 1dB, the corresponding measured amplitude AMP2_2 is 1 / 1.059 of the measured amplitude AMP2_1 of the attenuator attenuation of 0.5dB (AMP2_2 = AMP2_1 / 1.059). By increasing the attenuation value of the attenuator step by step and obtaining the measured amplitude, it is convenient to calculate and obtain the attenuation amplitude of the attenuator at each step compared to the previous step.

[0093] S620 obtains the attenuation magnitude of the attenuator at each gear compared to the previous gear based on the measured amplitude of each gear and the measured amplitude of the previous gear.

[0094] It is understood that, in this embodiment of the present invention, the attenuation amplitude of the attenuator at each gear is obtained by comparing the measured amplitude of each gear with the measured amplitude of the previous gear, so as to facilitate self-testing of each gear of the attenuator based on the attenuation amplitude.

[0095] The S630 performs a self-test on each setting of the attenuator based on the attenuation amplitude.

[0096] It is understood that in this embodiment of the present invention, a self-test is performed on each gear of the attenuator by comparing the preset attenuation amplitude with the attenuation amplitude of the attenuator at each gear compared to the previous gear. If the attenuation amplitude of the attenuator at a gear compared to the previous gear is equal to the preset attenuation amplitude, it indicates that the gear of the attenuator is normal; otherwise, it indicates that the gear of the attenuator is abnormal. Similarly, when comparing the preset attenuation amplitude with the attenuation amplitude of the attenuator at each gear compared to the previous gear, a certain error can be allowed according to the requirements of self-test accuracy.

[0097] Therefore, by performing self-tests on each setting of the attenuator using the above method, not only can the self-test judgment standard value of each setting of the attenuator be set to a uniform value, instead of setting a value for each setting, simplifying the self-test process, but it can also intuitively show which setting(s) has a larger error, and the error value of each setting will not be affected by the superposition of errors of other settings. At the same time, the self-test data can be saved as calibration parameters, thereby enabling precise error compensation for each setting of the attenuator.

[0098] Furthermore, in some embodiments of the present invention, the self-testing method of the digital transceiver link further includes: acquiring the self-test result of the digital transceiver link self-test and feeding it back to the host computer as calibration parameters for the amplifier and / or attenuator, wherein the self-test result includes the gain value of the amplifier and / or attenuator.

[0099] It is understood that, in this embodiment of the present invention, after the digital transceiver link self-test is completed, the self-test result of the digital transceiver link self-test is fed back to the host computer as calibration parameters for the amplifier and / or attenuator, so that the tester can debug and repair the digital transceiver link and perform error compensation for the amplifier and / or attenuator according to the calibration parameters.

[0100] In summary, the self-testing method for a digital transceiver link according to embodiments of the present invention, when initiating a self-test of the digital transceiver link, controls the transmitting link and the receiving link to switch to the self-test channel, forming a transmit-receive closed loop in the digital transceiver link. Then, it controls the digital-to-analog converter in the transmitting link to output a fixed-frequency continuous wave and controls the analog-to-digital converter in the receiving link to acquire the signal under test. The measured amplitude of the signal under test is obtained according to a lock-in amplification algorithm. Based on the measured amplitude, the digital transceiver link is controlled to perform a self-test. Thus, by using an FPGA module based on the transmit-receive closed loop formed by the digital transceiver link and combining it with a lock-in amplification algorithm, the self-testing of the transmitting and receiving links is completed. Therefore, high-precision integrated self-testing of the digital transceiver link can be achieved without adding any additional hardware circuitry.

[0101] Based on the self-testing method for digital transceiver links in the foregoing embodiments of the present invention, the present invention also proposes a computer-readable storage medium storing a self-testing program for a digital transceiver link, which, when executed by a processor, implements the self-testing method for digital transceiver links described in the foregoing embodiments of the present invention.

[0102] It should be understood that specific embodiments of the computer-readable storage medium of the present invention can be found in the specific embodiments of the self-test method of the digital transceiver link described in the foregoing embodiments of the present invention, and will not be repeated here to reduce redundancy.

[0103] In summary, the computer-readable storage medium according to embodiments of the present invention can achieve high-precision integrated self-testing of digital transceiver links by executing the self-test program of the digital transceiver link stored thereon, without adding any additional hardware circuitry.

[0104] Figure 7 This is a block diagram of a self-testing device for a digital transceiver link according to an embodiment of the present invention.

[0105] Specifically, in some embodiments of the present invention, reference is made to Figure 7 As shown, the self-testing device 100 of the digital transceiver link includes: a closed-loop module 10, a measurement module 20, and a self-testing module 30.

[0106] The closed-loop module 10 is used to control the transmission link and the receiving link to switch to the self-test channel when the digital transceiver link self-test is started, so that the digital transceiver link forms a transmission-reception closed loop; the measurement module 20 is used to control the digital-to-analog converter in the transmission link to output a fixed frequency continuous wave and control the analog-to-digital converter in the receiving link to acquire the signal under test, and to acquire the measured amplitude of the signal under test according to the phase-locked amplification algorithm; the self-test module 30 is used to perform a self-test on the digital transceiver link according to the measured amplitude.

[0107] Furthermore, the measurement module 20 is specifically used to generate two orthogonal reference signals of the same frequency; obtain the in-phase component and quadrature component of the signal under test based on the signal under test and the reference signals of the same frequency; and obtain the measured amplitude of the signal under test based on the in-phase component and quadrature component of the signal under test.

[0108] Furthermore, the self-test module 30 is specifically used to initialize the channel gain of the digital transceiver link and obtain the real-time measured amplitude of the signal under test; obtain the default link AMP value, and perform a default link self-test on the digital transceiver link based on the real-time measured amplitude of the signal under test and the default link AMP value.

[0109] Furthermore, the self-test module 30 is specifically used to sequentially control the preset operating time of multiple amplifiers and / or attenuators of the transmission link to obtain the corresponding real-time measured amplitude of the signal under test; and to perform a self-test of the transmission gain of the digital transceiver link based on the corresponding real-time measured amplitude of the signal under test and the default link AMP value.

[0110] Furthermore, the self-test module 30 is specifically used to sequentially control the preset operating time of multiple amplifiers and / or attenuators in the receiving link to obtain the corresponding real-time measured amplitude of the signal under test; and to perform a receive gain self-test on the digital transceiver link based on the corresponding real-time measured amplitude of the signal under test and the default link AMP value.

[0111] Furthermore, the self-test module 30 is specifically used to: increase the attenuation value of the attenuator step by step and obtain the measured amplitude; obtain the attenuation amplitude of the attenuator at each level compared to the previous level based on the measured amplitude of each level and the measured amplitude of the previous level; and perform a self-test on each level of the attenuator based on the attenuation amplitude.

[0112] Furthermore, the self-test module 30 is specifically used to acquire the self-test results of the digital transceiver link self-test and feed them back to the host computer as calibration parameters for the amplifier and / or attenuator. The self-test results include the gain values ​​of the amplifier and / or attenuator.

[0113] Furthermore, in some embodiments of the present invention, the transmit link includes a first-stage transmit amplifier, a first-stage transmit attenuator, a second-stage transmit amplifier, and a second-stage transmit attenuator; the receive link includes a first-stage receive amplifier, a first-stage receive attenuator, a second-stage receive amplifier, and a second-stage receive attenuator.

[0114] It should be understood that the specific implementation of the self-testing device for the digital transceiver link of the present invention can be found in the specific implementation of the self-testing method for the digital transceiver link described in the foregoing embodiments of the present invention. To reduce redundancy, it will not be described again here.

[0115] In summary, the self-testing device for a digital transceiver link according to an embodiment of the present invention, through a closed-loop module, controls the transmitting link and the receiving link to switch to the self-test channel when the digital transceiver link self-test is initiated, thus forming a transmit-receive closed loop in the digital transceiver link. Furthermore, the measurement module controls the digital-to-analog converter in the transmitting link to output a fixed-frequency continuous wave and controls the analog-to-digital converter in the receiving link to acquire the signal under test, and obtains the measured amplitude of the signal under test according to a lock-in amplification algorithm. Finally, the self-testing module performs a self-test of the digital transceiver link based on the measured amplitude. Therefore, by using an FPGA module based on the transmit-receive closed loop formed by the digital transceiver link and a lock-in amplification algorithm, the self-testing of the transmitting and receiving links is completed, thereby achieving high-precision integrated self-testing of the digital transceiver link without adding any additional hardware circuitry.

[0116] Figure 8 This is a block diagram of a nuclear magnetic resonance spectrometer according to an embodiment of the present invention.

[0117] Specifically, in some embodiments of the present invention, reference is made to Figure 8 As shown, the nuclear magnetic resonance spectrometer 1000 includes the self-testing device 100 of the digital transceiver link in the above embodiment of the present invention.

[0118] It should be understood that the specific implementation of the nuclear magnetic resonance spectrometer 1000 of the present invention can be found in the specific implementation of the self-test device of the digital transceiver link in the foregoing embodiments of the present invention. To reduce redundancy, it will not be described again here.

[0119] In summary, the nuclear magnetic resonance spectrometer according to the embodiments of the present invention, by employing the aforementioned self-testing device for the digital transceiver link, can achieve high-precision integrated self-testing of the digital transceiver link without adding any additional hardware circuitry.

[0120] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0121] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0122] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0123] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0124] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0125] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0126] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0127] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A self-testing method for a digital transceiver link, characterized in that, The digital transceiver link includes an FPGA module, a transmit link, and a receive link; the method includes: When the digital transceiver link self-test is initiated, the transmitting link and the receiving link are controlled to switch to the self-test channel, so that the digital transceiver link forms a closed loop for transmitting and receiving. The system controls the digital-to-analog converter in the transmitting link to output a fixed-frequency continuous wave and controls the analog-to-digital converter in the receiving link to acquire the signal under test, and obtains the measured amplitude of the signal under test according to the lock-in amplification algorithm. The digital transceiver link is self-tested based on the measured amplitude.

2. The self-testing method for a digital transceiver link according to claim 1, characterized in that, The three concurrent processes of the FPGA module respectively execute the following steps: the digital-to-analog converter outputs a fixed-frequency continuous wave, the analog-to-digital converter acquires the signal under test, and the phase-locked amplification algorithm is used to acquire the measured amplitude of the signal under test.

3. The self-testing method for a digital transceiver link according to claim 1, characterized in that, The step of obtaining the measured amplitude of the signal under test according to the lock-in amplification algorithm includes: Generate two orthogonal, same-frequency reference signals; Based on the signal under test and the reference signal at the same frequency, obtain the in-phase component and quadrature component of the signal under test; The measured amplitude of the signal under test is obtained based on the in-phase and quadrature components of the signal under test.

4. The self-testing method for a digital transceiver link according to claim 3, characterized in that, The same-frequency reference signal is generated by the direct digital frequency synthesizer of the FPGA module.

5. The self-testing method for a digital transceiver link according to claim 1, characterized in that, Both the transmit link and the receive link include amplifiers and / or attenuators; The step of performing a self-test on the digital transceiver link based on the measured amplitude includes: Initialize the channel gain of the digital transceiver link and obtain the real-time measured amplitude of the signal under test; Obtain the default link AMP value, and perform a default link self-test on the digital transceiver link based on the real-time measured amplitude of the signal under test and the default link AMP value.

6. The self-testing method for a digital transceiver link according to claim 5, characterized in that, The transmit link includes multiple amplifiers and / or attenuators; The step of controlling the digital transceiver link to perform a self-test based on the measured amplitude includes: The multiple amplifiers and / or attenuators of the transmission link are controlled to operate for a preset time in sequence in order to obtain the corresponding real-time measured amplitude of the signal under test; Based on the real-time measured amplitude of the signal under test and the default link AMP value, a transmit gain self-test is performed on the digital transceiver link.

7. The self-testing method for a digital transceiver link according to claim 5, characterized in that, The receiving link includes multiple amplifiers and / or attenuators; The step of performing a self-test on the digital transceiver link based on the measured amplitude includes: The multiple amplifiers and / or attenuators of the receiving link are controlled to operate for a preset time in sequence in order to obtain the corresponding real-time measured amplitude of the signal under test; Based on the real-time measured amplitude of the signal under test and the default link AMP value, the digital transceiver link is subjected to a receive gain self-test.

8. The self-testing method for a digital transceiver link according to claim 5, characterized in that, The step of performing a self-test on the digital transceiver link based on the measured amplitude includes: The attenuation value of the attenuator is increased step by step to obtain the measured amplitude; Based on the measured amplitude of each gear and the measured amplitude of the previous gear, the attenuation amplitude of the attenuator in each gear is obtained compared to the previous gear. The attenuator performs a self-test for each setting based on the attenuation amplitude.

9. The self-testing method for a digital transceiver link according to claim 5, characterized in that, The method further includes: The self-test results of the digital transceiver link self-test are obtained and fed back to the host computer as calibration parameters for the amplifier and / or attenuator. The self-test results include the gain values ​​of the amplifier and / or attenuator.

10. A computer-readable storage medium, characterized in that, It stores a self-test program for a digital transceiver link, which, when executed by a processor, implements the self-test method for a digital transceiver link as described in any one of claims 1-9.

11. A self-testing device for a digital transceiver link, characterized in that, The digital transceiver link includes an FPGA module, a transmit link, and a receive link; the device includes: The closed-loop module is used to control the transmit link and the receive link to switch to the self-test channel when the digital transceiver link self-test is started, so that the digital transceiver link forms a transmit-receive closed loop; The measurement module is used to control the digital-to-analog converter in the transmitting link to output a fixed-frequency continuous wave and to control the analog-to-digital converter in the receiving link to acquire the signal under test, and to acquire the measured amplitude of the signal under test according to the lock-in amplification algorithm; The self-test module is used to perform a self-test of the digital transceiver link based on the measured amplitude.

12. The self-testing device for a digital transceiver link according to claim 11, characterized in that, The transmit link includes a first-stage transmit amplifier, a first-stage transmit attenuator, a second-stage transmit amplifier, and a second-stage transmit attenuator; the receive link includes a first-stage receive amplifier, a first-stage receive attenuator, a second-stage receive amplifier, and a second-stage receive attenuator.

13. A nuclear magnetic resonance spectrometer, characterized in that, The nuclear magnetic resonance spectrometer includes a digital transceiver link and a self-testing device for the digital transceiver link as described in claim 11 or 12.

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