PCB structure compatible with multiple data transmission modes and surface mounting method
By introducing a series circuit design of port expansion chips and resistor modules into the PCB structure, the problem of insufficient communication ports of the main chip is solved, compatibility with multiple USB data transmission schemes is achieved, costs are reduced, and signal integrity and design flexibility are improved.
Patent Information
- Application Number
- CN202511184963.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-22
- Publication Date
- 2025-11-14
AI Technical Summary
In existing technologies, the insufficient number of communication ports on the main chip makes it impossible to simultaneously meet the needs of multiple functional modules, resulting in limited design space, signal integrity issues, and restricted flexibility.
The PCB structure is compatible with multiple data transmission methods. Through the layout design of port expansion chips and multiple resistor modules, communication between the main chip and multiple functional modules is realized. This includes the connection between the total port of the port expansion chip and the functional modules, and the optimization of the signal transmission path by using the series circuit of the resistor modules.
By occupying only one USB port on the main chip, it is compatible with multiple USB data transmission schemes, reduces surface mount costs, reduces useless branches, and improves signal integrity and design flexibility.
Smart Images
Figure CN120957321A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of PCB manufacturing technology, specifically to a PCB structure compatible with multiple data transmission methods and a surface mount method. Background Technology
[0002] In the research and development of electronic products, to meet the diverse needs of different customer groups, it is often necessary to develop multiple product models under the same technology platform. Taking new energy vehicles and mobile phones as examples, different models of products have significant differences in functionality and price. This differentiated functional requirement necessitates corresponding adjustments to the hardware design. However, in conventional design practice, to reduce production costs and simplify management processes, a compatible design strategy is often adopted, which involves reserving all possible functions in a single hardware design. During the production stage, depending on the different product models, only the circuit devices corresponding to the required functions are installed, while the devices corresponding to unnecessary functions are left unmounted.
[0003] While this compatible design reduces costs to some extent, it also brings a series of problems. First, because multiple functions need to be reserved, design space often becomes tight, making it difficult to arrange them reasonably. Second, when multiple functions are integrated into the same design, signal integrity issues are prone to occur, which can affect product performance and reliability. Furthermore, the number of communication ports on the main chip may not be sufficient to simultaneously meet the needs of all reserved functional modules, thus limiting the flexibility and scalability of the design. Summary of the Invention
[0004] In view of this, this application proposes a PCB structure and surface mount method that are compatible with multiple data transmission methods, in order to solve the problem in the related technology that the insufficient number of communication ports of the main chip makes it impossible to simultaneously meet the needs of all reserved functional modules.
[0005] The first aspect of this application proposes a PCB structure compatible with multiple data transmission methods. The PCB structure includes a PCB back side and a PCB front side. The PCB back side is provided with a first resistor module, a second resistor module, and a port expansion chip. The PCB front side is provided with a third resistor module, a fourth resistor module, a main chip, a first functional module, and a second functional module.
[0006] The main chip is connected to the main port of the port expansion chip through the first resistor module. The first expansion port of the port expansion chip is connected to the first functional module, and the second expansion port is connected to the second functional module. The main chip is connected to the first functional module through the third resistor module and the second resistor module, and the main chip is connected to the second functional module through the third resistor module and the fourth resistor module.
[0007] This application embodiment, through a port expansion chip and multiple resistors, can achieve compatibility with three USB data transmission schemes while occupying only one USB port of the main chip, minimizing useless branches on the line and having the least impact on signal integrity.
[0008] In this embodiment, the first resistor module includes a first resistor and a second resistor, and the total ports of the port expansion chip include a positive total port and a negative total port;
[0009] The positive signal port of the main chip is connected to the positive total port of the port expansion chip through the first resistor, and the negative signal port of the main chip is connected to the negative total port of the port expansion chip through the second resistor.
[0010] In this embodiment, the second resistor module includes a fifth resistor and a sixth resistor, the third resistor module includes a third resistor and a fourth resistor, and the fourth resistor module includes a seventh resistor and an eighth resistor; the first expansion port includes a first positive expansion port and a first negative expansion port; the second expansion port includes a second positive expansion port and a second negative expansion port.
[0011] The positive signal port of the main chip is connected to the first positive expansion port through the first series circuit of the third resistor and the sixth resistor, and the negative signal port of the main chip is connected to the first negative expansion port through the second series circuit of the fourth resistor and the fifth resistor.
[0012] The positive signal port of the main chip is connected to the second positive expansion port through the third series circuit of the third resistor and the eighth resistor, and the negative signal port of the main chip is connected to the second negative expansion port through the fourth series circuit of the fourth resistor and the seventh resistor.
[0013] In this embodiment of the application, the first resistor at a first position on the reverse side of the PCB and the third resistor at a second position on the front side of the PCB overlap each other, and the second resistor at a third position on the reverse side of the PCB and the fourth resistor at a fourth position on the front side of the PCB overlap each other.
[0014] A first via is deployed on the pad at the second position, and the positive signal port of the main chip is connected to the first resistor through the first via and a signal line; a second via is deployed on the pad at the fourth position, and the negative signal port of the main chip is connected to the second resistor through the second via and a signal line.
[0015] In this embodiment of the application, a third through hole is deployed on the connection path between the sixth resistor on the reverse side of the PCB and the first positive expansion port, and a fourth through hole is deployed on the connection path between the fifth resistor on the reverse side of the PCB and the first negative expansion port; a fifth through hole at the same position as the third through hole and a sixth through hole at the same position as the fourth through hole are deployed on the front side of the PCB.
[0016] The first positive expansion port is connected to the positive port of the first functional module through the third through hole and the fifth through hole; the first negative expansion port is connected to the negative port of the first functional module through the fourth through hole and the sixth through hole.
[0017] In this embodiment of the application, a seventh through hole is deployed on the connection path between the seventh resistor and the second negative expansion port on the front side of the PCB, and an eighth through hole is deployed on the connection path between the eighth resistor and the second positive expansion port on the front side of the PCB; a ninth through hole at the same position as the seventh through hole and a tenth through hole at the same position as the eighth through hole are deployed on the back side of the PCB.
[0018] The second negative expansion port is connected to the negative port of the second functional module through the seventh through hole and the ninth through hole; the second positive expansion port is connected to the positive port of the second functional module through the eighth through hole and the tenth through hole.
[0019] In this embodiment of the application, the fifth resistor and the sixth resistor on the reverse side of the PCB are arranged in parallel to each other, and the seventh resistor and the eighth resistor on the front side of the PCB are arranged in parallel to each other; the first deployment direction of the fifth resistor and the sixth resistor is perpendicular to the second deployment direction of the seventh resistor and the eighth resistor;
[0020] The pad position of the fifth resistor on the reverse side of the PCB partially overlaps with the pad position of the seventh resistor on the front side of the PCB; the pad position of the sixth resistor on the reverse side of the PCB partially overlaps with the pad position of the eighth resistor on the front side of the PCB; the fifth resistor and the seventh resistor are connected to the fourth resistor through vias on their corresponding overlapping pads; the sixth resistor and the eighth resistor are connected to the third resistor through vias on their corresponding overlapping pads.
[0021] The second aspect of this application provides a method for surface mount technology (SMT) of a PCB structure, wherein the PCB structure is the PCB structure compatible with multiple data transmission methods described in the first aspect above; the SMT method includes:
[0022] The third and fourth resistors on the front side of the PCB, and the fifth and sixth resistors on the back side of the PCB, are solidly mounted; the seventh and eighth resistors on the front side of the PCB, and the first, second, and port expansion chips on the back side of the PCB are loosely mounted, so that the main chip can communicate with the first functional module through the first signal line and the second signal line; the first signal line refers to the series circuit formed by the third and sixth resistors; the second signal line refers to the series circuit formed by the fourth and fifth resistors.
[0023] In this embodiment of the application, the patching method includes:
[0024] The third, fourth, seventh, and eighth resistors on the front side of the PCB are physically mounted; the first, second, fifth, sixth resistors, and the port expansion chip on the back side of the PCB are not mounted, so that the main chip can communicate with the second functional module through the third and fourth signal lines; the third signal line refers to the series circuit formed by the third and eighth resistors; the fourth signal line refers to the series circuit formed by the fourth and seventh resistors.
[0025] In this embodiment of the application, the patching method includes:
[0026] The first resistor, the second resistor, and the port expansion chip on the reverse side of the PCB are physically mounted; the fifth resistor and the sixth resistor on the reverse side of the PCB, and the third resistor, the fourth resistor, the seventh resistor, and the eighth resistor on the front side of the PCB are loosely mounted, so that the main chip can be connected to the first functional module through the first expansion port of the port expansion chip, and to the second functional module through the second expansion port of the port expansion chip.
[0027] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0028] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:
[0029] Figure 1 This illustration shows a schematic diagram of a PCB structure compatible with multiple data transmission methods according to an embodiment of this application;
[0030] Figure 2 A schematic diagram of another PCB structure compatible with multiple data transmission methods provided in an embodiment of this application is shown;
[0031] Figure 3 A perspective view of the reverse side of the PCB in an embodiment of this application is shown;
[0032] Figure 4 This illustration shows a perspective view of the front side of the PCB in a PCB structure provided in an embodiment of this application;
[0033] Figure 5 A schematic diagram of the resistor pads and vias deployed on the pads provided in an embodiment of this application is shown.
[0034] Figure 6 This illustration shows a superimposed perspective view of the reverse side and the front side of a PCB provided in an embodiment of this application;
[0035] Figure 7 A schematic diagram of the deployment of the fifth, sixth, seventh, and eighth resistors provided in an embodiment of this application is shown;
[0036] Figure 8 This illustration shows a schematic diagram of the signal transmission path in a PCB structure that only supports communication between the main chip and the first functional module, according to an embodiment of this application.
[0037] Figure 9 This illustration shows a schematic diagram of the signal transmission path in a PCB structure that only supports communication between the main chip and the second functional module, according to an embodiment of this application.
[0038] Figure 10 This illustration shows a schematic diagram of the signal transmission path in a PCB structure that simultaneously supports communication between the main chip and the first functional module and the second functional module, according to an embodiment of this application. Detailed Implementation
[0039] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.
[0040] It should be noted that, unless otherwise stated, the technical or scientific terms used in this application shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application pertains.
[0041] The technical scenarios involved in the embodiments of this application are described below.
[0042] To meet the diverse needs of different customers during the R&D process of electronic products, multiple models often need to be produced on the same platform, each with different functions and prices, such as new energy vehicles and mobile phones. Different functions require different hardware designs. Typically, to save production and management costs, a compatible design is used to implement all functions in the same design. During production, components for unnecessary functions are simply mounted on different models. This approach can lead to problems such as insufficient design space, signal integrity issues when integrating multiple functions, and insufficient communication ports on the main chip to accommodate multiple functional modules. USB ports are commonly used data transmission ports in electronic products and have widespread compatibility requirements.
[0043] This application provides a circuit and PCB design method that is compatible with three USB data transmission schemes simultaneously. By using only one USB port of the main chip, a unique layout and routing design is used to be compatible with three USB data transmission schemes simultaneously. Regardless of which scheme is used alone, the surface mount cost is relatively low, the useless branches on the line are shortest, and the impact on signal integrity is minimal.
[0044] This embodiment provides a PCB structure compatible with multiple data transmission methods. Figure 1 This is a schematic diagram of a PCB structure compatible with multiple data transmission methods according to an embodiment of this application, such as... Figure 1 As shown:
[0045] The PCB structure includes a PCB back side and a PCB front side; the PCB back side is equipped with a first resistor module, a second resistor module and a port expansion chip; the PCB front side is equipped with a third resistor module, a fourth resistor module, a main chip, a first functional module and a second functional module.
[0046] The main chip is connected to the main port of the port expansion chip through the first resistor module. The first expansion port of the port expansion chip is connected to the first functional module, and the second expansion port is connected to the second functional module. The main chip is connected to the first functional module through the third resistor module and the second resistor module, and the main chip is connected to the second functional module through the third resistor module and the fourth resistor module.
[0047] In this embodiment, the connection between the various ports / modules is implemented using USB differential wiring. In USB communication, differential signal transmission technology is used for data transmission wiring. Differential signal transmission transmits signals through a pair of wires (called a differential pair), where one wire, USB_UP_DP, transmits a positive signal, and the other wire, USB_UP_DM, transmits a negative signal (inverted signal).
[0048] In this embodiment, the main chip can be understood as a System-on-Chip (SOC), which integrates a processor (CPU), memory (such as RAM, ROM), input / output interfaces (such as USB, UART, SPI, etc.), analog circuits (such as ADC, DAC), and other functional modules onto a single chip. This highly integrated design significantly reduces the system's size and power consumption. In this embodiment, the main chip provides one USB communication port, supporting single-duplex data processing modes for receiving, storing, or outputting data.
[0049] In this embodiment, the port expansion chip can be understood as a USB HUB chip. Its function is to expand one USB port into multiple USB ports. The signals transmitted by multiple functional modules connected to the multiple expansion ports are processed by the chip and then communicate with the SOC through the lumped port. In this embodiment, one port is expanded into two USB ports.
[0050] In the embodiments of this application, the specific functions of the first functional module and the second functional module can be set according to the actual situation, and no specific limitation is made here. For example, the first functional module can be a function module for reading and writing FT cards, and the second functional module can be a wireless gateway function module.
[0051] This embodiment of the application enables communication between the main chip and the first functional module through the third and second resistor modules, communication between the main chip and the second functional module through the third and fourth resistor modules, and simultaneous communication between the main chip and both functional modules through the first resistor module and the port expansion module. This PCB structure, through reasonable circuit layout and resistor module configuration, combined with the function of the port expansion chip, achieves compatibility with three USB data transmission schemes while occupying only one USB port on the SOC. This design not only improves port utilization but also optimizes signal transmission performance, meeting the flexibility of different functional requirements.
[0052] In some specific embodiments, such as Figure 2 As shown: the first resistor module includes a first resistor R1 and a second resistor R2; the total ports of the port expansion chip include a positive total port and a negative total port; the positive signal port USB_UP_DP of the main chip is connected to the positive total port of the port expansion chip through the first resistor R1; and the negative signal port USB_UP_DM of the main chip is connected to the negative total port of the port expansion chip through the second resistor R2.
[0053] In some specific embodiments, such as Figure 2As shown: the second resistor module includes a fifth resistor R5 and a sixth resistor R6; the third resistor module includes a third resistor R3 and a fourth resistor R4; the fourth resistor module includes a seventh resistor R7 and an eighth resistor R8; the first expansion port (i.e. Figure 2 The "Extension Port 1" in the text includes a first positive extension port and a first negative extension port; the second extension port (i.e. Figure 2 The “Extension Port 2” in the text includes a second positive extension port and a second negative extension port.
[0054] The positive signal port USB_UP_DP of the main chip is connected to the first positive expansion port through a first series circuit of the third resistor R3 and the sixth resistor R6. The negative signal port USB_UP_DM of the main chip is connected to the first negative expansion port through a second series circuit of the fourth resistor R4 and the fifth resistor R5. The positive signal port USB_UP_DP of the main chip is connected to the second positive expansion port through a third series circuit of the third resistor R3 and the eighth resistor R8. The negative signal port USB_UP_DM of the main chip is connected to the second negative expansion port through a fourth series circuit of the fourth resistor R4 and the seventh resistor R7.
[0055] In some specific embodiments, the first resistor R1 at a first position on the reverse side of the PCB and the third resistor R3 at a second position on the front side of the PCB overlap each other, and the second resistor R2 at a third position on the reverse side of the PCB and the fourth resistor R4 at a fourth position on the front side of the PCB overlap each other.
[0056] A first via is deployed on the pad at the second position, and the positive signal port of the main chip is connected to the first resistor R1 through the first via and a signal line; a second via is deployed on the pad at the fourth position, and the negative signal port of the main chip is connected to the second resistor through the second via and a signal line.
[0057] In the embodiments of this application, Figure 3 This is a perspective view of the reverse side of the PCB. Figure 4 This is a perspective view of the front of the PCB. Figure 3 and Figure 4 It can be seen that the first resistor R1 is located at the same position on the reverse side of the PCB as the third resistor R3 is located at the same position on the front side of the PCB. Each resistor includes two pads (e.g., ...). Figure 5 (in "a1"), one of the pads has a via deployed (e.g. Figure 5 (as shown in "a2"). Any resistor in one layer of a circuit board can be connected to resistors or other components in other layers of circuit boards through vias on its pads.
[0058] In this embodiment, by placing the first resistor R1 and the third resistor R3 at the same position on the back and front of the PCB respectively, and deploying through holes, the communication path between the main chip and the first resistor R1 and the third resistor R3 is shortened, thereby reducing signal attenuation, maintaining signal strength and quality, and improving signal integrity.
[0059] In some specific embodiments, a third through hole is deployed on the connection path between the sixth resistor R6 on the reverse side of the PCB and the first positive expansion port, and a fourth through hole is deployed on the connection path between the fifth resistor R5 on the reverse side of the PCB and the first negative expansion port; a fifth through hole at the same position as the third through hole and a sixth through hole at the same position as the fourth through hole are deployed on the front side of the PCB.
[0060] The first positive expansion port is connected to the positive port of the first functional module through the third through hole and the fifth through hole; the first negative expansion port is connected to the negative port of the first functional module through the fourth through hole and the sixth through hole.
[0061] In this embodiment, by deploying a third via on the connection path between the sixth resistor R6 and the first positive expansion port, and a fourth via on the connection path between the fifth resistor R5 and the first negative expansion port, the first positive expansion port can establish a connection with the first functional module through the third and fourth vias. Figure 6 As shown: the fifth resistor R5 and the sixth resistor R6 are connected to the T-BOX respectively.
[0062] This application embodiment utilizes vias deployed on both the reverse and front sides of the PCB, allowing signals to reach the positive and negative ports of the functional module from the expansion port via the shortest path. Shorter signal paths reduce signal delay, attenuation, and reflection, thereby improving signal integrity.
[0063] In some specific embodiments, a seventh through hole is deployed on the connection path between the seventh resistor R7 and the second negative expansion port on the front side of the PCB, and an eighth through hole is deployed on the connection path between the eighth resistor R8 and the second positive expansion port on the front side of the PCB; a ninth through hole at the same position as the seventh through hole and a tenth through hole at the same position as the eighth through hole are deployed on the back side of the PCB.
[0064] The second negative expansion port is connected to the negative port of the second functional module through the seventh through hole and the ninth through hole; the second positive expansion port is connected to the positive port of the second functional module through the eighth through hole and the tenth through hole.
[0065] In this embodiment, the second positive expansion port and the second negative expansion port are located on the reverse side of the PCB, and the second functional module is located on the front side of the PCB. When the second positive expansion port and the second negative expansion port establish a communication connection with the second functional module, through holes need to be deployed on the circuit board. By deploying the seventh through hole on the connection path between the seventh resistor R7 and the second negative expansion port, the communication path between the expansion port and the functional module can be greatly shortened, thereby reducing signal delay, attenuation and reflection, so as to improve signal integrity.
[0066] In some specific embodiments, the fifth resistor and the sixth resistor on the reverse side of the PCB are arranged in parallel with each other, for example... Figure 7 As shown in "b2"; the seventh resistor and the eighth resistor on the front side of the PCB are arranged in parallel to each other, for example... Figure 7 As shown in "b1"; the first deployment direction of the fifth resistor and the sixth resistor is perpendicular to the second deployment direction of the seventh resistor and the eighth resistor;
[0067] The pad position of the fifth resistor R5 on the reverse side of the PCB partially overlaps with the pad position of the seventh resistor R7 on the front side of the PCB. Similarly, the pad position of the sixth resistor R6 on the reverse side of the PCB partially overlaps with the pad position of the eighth resistor R8 on the front side of the PCB. Figure 6 As shown; the fifth resistor R5 and the seventh resistor R7 are connected to the fourth resistor R4 through vias on the corresponding overlapping pads; the sixth resistor R6 and the eighth resistor R8 are connected to the third resistor R3 through vias on the corresponding overlapping pads.
[0068] In this embodiment, the fifth resistor R5 and the sixth resistor R6 are deployed at a 45-degree angle to the horizontal line, and the seventh resistor R7 and the eighth resistor R8 are deployed at a 45-degree angle to the horizontal line. This deployment method causes the pads on the other end of the multiple resistors connected to the port expansion chip to overlap on the back and front of the PCB and be connected through the through holes on the pads. They are also connected to the third resistor R3 and the fourth resistor R4 on the front of the PCB through USB differential lines. This method minimizes the branch length when R3 / R4 selects either R5 / R6 or R7 / R8 communication paths.
[0069] In some specific embodiments, under the premise of meeting the manufacturing process, R5 / R6 and R7 / R8 need to be as close as possible to the USBHUB chip, so that the wiring length between R5 / R6 and USB HUB chip expansion port 1, and between R7 / R8 and USB HUB chip expansion port 2 is infinitely short. This design makes the branch on the path shortest when the USB HUB communicates with both CV-BOX and T-BOX at the same time (i.e. R5 / R6 / R7 / R8 are not attached).
[0070] This application embodiment can simultaneously support three USB data transmission schemes by occupying only one USB port of the SOC through a unique layout and routing design. Regardless of which scheme is used alone, the surface mount cost is relatively low, the useless branches on the line are shortest, and the impact on signal integrity is minimal.
[0071] Corresponding to the above-mentioned PCB structure compatible with multiple data transmission methods, this application embodiment also provides a PCB structure mounting method. The method includes:
[0072] The third resistor R3 and the fourth resistor R4 on the front side of the PCB, and the fifth resistor R5 and the sixth resistor R6 on the back side of the PCB are solidly mounted; the seventh resistor R7 and the eighth resistor R8 on the front side of the PCB, and the first resistor R1, the second resistor R2 and the USB HUB port expansion chip on the back side of the PCB are not mounted, so that the main chip SOC can communicate with the first functional module through the first signal line and the second signal line; the first signal line refers to the series circuit formed by the third resistor R3 and the sixth resistor R6; the second signal line refers to the series circuit formed by the fourth resistor R4 and the fifth resistor R5.
[0073] In this embodiment, the above-mentioned surface mount method only supports the first function (e.g., CV-BOX), that is, communication between the main chip and the first functional module; the main chip SOC communicates with the first functional module through multiple resistors R3 / R4 / R5 / R6 and corresponding USB differential lines and vias. In this scheme, R3 / R4 / R5 / R6 are actually mounted, while R1 / R2 / R7 / R8 and port expansion chips are mounted without mounting. Figure 8 As shown.
[0074] In some specific embodiments, the patching method includes:
[0075] The third resistor R3, the fourth resistor R4, the seventh resistor R7, and the eighth resistor R8 on the front side of the PCB are mounted solidly; the first resistor R1, the second resistor R2, the fifth resistor R5, the sixth resistor R6, and the USB hub port expansion chip on the back side of the PCB are mounted without mounting, so that the main chip SOC can communicate with the second functional module through the third signal line and the fourth signal line; the third signal line refers to the series circuit formed by the third resistor R3 and the eighth resistor R8; the fourth signal line refers to the series circuit formed by the fourth resistor R4 and the seventh resistor R7.
[0076] In this embodiment, the above-mentioned surface mount method only supports the second function (e.g., T-BOX), that is, communication between the main chip and the second function module; the main chip SOC communicates with the second function module through multiple resistors R3 / R4 / R7 / R8 and corresponding USB differential lines and vias. In this scheme, R3 / R4 / R7 / R8 are actually mounted, while R1 / R2 / R5 / R6 and the port expansion chip are only mounted. Figure 9 As shown.
[0077] In some specific embodiments, the patching method includes:
[0078] The first resistor R1, the second resistor R2, and the USB hub port expansion chip on the reverse side of the PCB are solidly mounted; the fifth resistor R5 and the sixth resistor R6 on the reverse side of the PCB, and the third resistor R3, the fourth resistor R4, the seventh resistor R7, and the eighth resistor R8 on the front side of the PCB are loosely mounted, so that the main chip SOC can connect to the first functional module through the first expansion port of the USB hub port expansion chip, and to the second functional module through the second expansion port of the USB hub port expansion chip, as shown below. Figure 10 As shown.
[0079] In this embodiment, the surface mount method described above simultaneously supports the functions of the first functional module CV-BOX and the second functional module T-BOX. That is, when the main chip SOC communicates with both the CV-BOX and T-BOX simultaneously, and only occupies one USB port on the SOC: the main chip SOC communicates with the lumped port of the port expansion chip USB HUB chip through multiple resistors R1 / R2 and corresponding USB differential lines and vias. The port expansion chip USB HUB communicates with the first functional module CV-BOX and the second functional module T-BOX respectively through expansion ports 1 and 2 and corresponding USB differential lines and vias. This allows the main chip SOC to communicate with both the first functional module CV-BOX and the second functional module T-BOX simultaneously using only one USB port. In this scheme, R1 / R2 and the port expansion chip USB HUB chip are actually mounted, while R3 / R4 / R5 / R6 / R7 / R8 are not mounted.
[0080] This application embodiment can simultaneously support three USB data transmission schemes by occupying only one USB port of the SOC through a unique layout and routing design. Regardless of which scheme is used alone, the surface mount cost is relatively low, the useless branches on the line are shortest, and the impact on signal integrity is minimal.
[0081] It should be noted that:
[0082] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known structures and techniques have not been shown in detail so as not to obscure the understanding of this specification.
[0083] Similarly, it should be understood that, in order to simplify this application and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of this application, various features of this application are sometimes grouped together in a single embodiment, figure, or description thereof. However, this disclosure should not be construed as reflecting a schematic diagram in which the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.
[0084] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.
[0085] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A PCB structure compatible with multiple data transmission methods, characterized in that, The PCB structure includes a PCB back side and a PCB front side; the PCB back side is equipped with a first resistor module, a second resistor module, and a port expansion chip; the PCB front side is equipped with a third resistor module, a fourth resistor module, a main chip, a first functional module, and a second functional module. The main chip is connected to the main port of the port expansion chip through the first resistor module. The first expansion port of the port expansion chip is connected to the first functional module, and the second expansion port is connected to the second functional module. The main chip is connected to the first functional module through the third resistor module and the second resistor module, and the main chip is connected to the second functional module through the third resistor module and the fourth resistor module.
2. The PCB structure compatible with multiple data transmission methods according to claim 1, characterized in that, The first resistor module includes a first resistor and a second resistor, and the total ports of the port expansion chip include a positive total port and a negative total port; The positive signal port of the main chip is connected to the positive total port of the port expansion chip through the first resistor, and the negative signal port of the main chip is connected to the negative total port of the port expansion chip through the second resistor.
3. The PCB structure compatible with multiple data transmission methods according to claim 2, characterized in that, The second resistor module includes a fifth resistor and a sixth resistor; the third resistor module includes a third resistor and a fourth resistor; the fourth resistor module includes a seventh resistor and an eighth resistor; the first expansion port includes a first positive expansion port and a first negative expansion port; the second expansion port includes a second positive expansion port and a second negative expansion port. The positive signal port of the main chip is connected to the first positive expansion port through the first series circuit of the third resistor and the sixth resistor, and the negative signal port of the main chip is connected to the first negative expansion port through the second series circuit of the fourth resistor and the fifth resistor. The positive signal port of the main chip is connected to the second positive expansion port through the third series circuit of the third resistor and the eighth resistor, and the negative signal port of the main chip is connected to the second negative expansion port through the fourth series circuit of the fourth resistor and the seventh resistor.
4. The PCB structure compatible with multiple data transmission methods according to claim 3, characterized in that, The first resistor at a first position on the reverse side of the PCB overlaps with the third resistor at a second position on the front side of the PCB, and the second resistor at a third position on the reverse side of the PCB overlaps with the fourth resistor at a fourth position on the front side of the PCB. A first via is deployed on the pad at the second position, and the positive signal port of the main chip is connected to the first resistor through the first via and a signal line; a second via is deployed on the pad at the fourth position, and the negative signal port of the main chip is connected to the second resistor through the second via and a signal line.
5. The PCB structure compatible with multiple data transmission methods according to claim 4, characterized in that, A third through-hole is deployed on the connection path between the sixth resistor and the first positive expansion port on the reverse side of the PCB, and a fourth through-hole is deployed on the connection path between the fifth resistor and the first negative expansion port on the reverse side of the PCB; a fifth through-hole and a sixth through-hole are deployed on the front side of the PCB at the same position as the third through-hole. The first positive expansion port is connected to the positive port of the first functional module through the third through hole and the fifth through hole; the first negative expansion port is connected to the negative port of the first functional module through the fourth through hole and the sixth through hole.
6. The PCB structure compatible with multiple data transmission methods according to claim 5, characterized in that, A seventh through hole is deployed on the connection path between the seventh resistor and the second negative expansion port on the front side of the PCB, and an eighth through hole is deployed on the connection path between the eighth resistor and the second positive expansion port on the front side of the PCB; a ninth through hole and a tenth through hole are deployed on the back side of the PCB at the same position as the seventh through hole. The second negative expansion port is connected to the negative port of the second functional module through the seventh through hole and the ninth through hole; the second positive expansion port is connected to the positive port of the second functional module through the eighth through hole and the tenth through hole.
7. The PCB structure compatible with multiple data transmission methods according to claim 6, characterized in that, The fifth and sixth resistors on the reverse side of the PCB are arranged in parallel to each other, and the seventh and eighth resistors on the front side of the PCB are arranged in parallel to each other; the first deployment direction of the fifth and sixth resistors is perpendicular to the second deployment direction of the seventh and eighth resistors. The pad position of the fifth resistor on the reverse side of the PCB partially overlaps with the pad position of the seventh resistor on the front side of the PCB; the pad position of the sixth resistor on the reverse side of the PCB partially overlaps with the pad position of the eighth resistor on the front side of the PCB; the fifth resistor and the seventh resistor are connected to the fourth resistor through vias on their corresponding overlapping pads; the sixth resistor and the eighth resistor are connected to the third resistor through vias on their corresponding overlapping pads.
8. A method for mounting a PCB structure, characterized in that, The PCB structure is the PCB structure compatible with multiple data transmission methods as described in any one of claims 1 to 7; the surface mount method includes: The third and fourth resistors on the front side of the PCB, and the fifth and sixth resistors on the back side of the PCB, are solidly mounted; the seventh and eighth resistors on the front side of the PCB, and the first, second, and port expansion chips on the back side of the PCB are loosely mounted, so that the main chip can communicate with the first functional module through the first signal line and the second signal line; the first signal line refers to the series circuit formed by the third and sixth resistors; the second signal line refers to the series circuit formed by the fourth and fifth resistors.
9. The method according to claim 8, characterized in that, The patching method includes: The third, fourth, seventh, and eighth resistors on the front side of the PCB are physically mounted; the first, second, fifth, sixth resistors, and the port expansion chip on the back side of the PCB are not mounted, so that the main chip can communicate with the second functional module through the third and fourth signal lines; the third signal line refers to the series circuit formed by the third and eighth resistors; the fourth signal line refers to the series circuit formed by the fourth and seventh resistors.
10. The method according to claim 8 or 9, characterized in that, The patching method includes: The first resistor, the second resistor, and the port expansion chip on the reverse side of the PCB are physically mounted; the fifth resistor and the sixth resistor on the reverse side of the PCB, and the third resistor, the fourth resistor, the seventh resistor, and the eighth resistor on the front side of the PCB are loosely mounted, so that the main chip can be connected to the first functional module through the first expansion port of the port expansion chip, and to the second functional module through the second expansion port of the port expansion chip.