An embedded laminated chip package structure and its packaging method, integrated circuit board

Abstract

To overcome the problem of insufficient heat dissipation performance in existing chip packaging, this invention provides an embedded stacked chip packaging structure and its packaging method, as well as an integrated circuit board. The embedded stacked chip packaging structure includes multiple stacked layers, each layer including a core board body and a first chip. The core board body has mounting holes, and the first chip is embedded in the mounting holes. The multiple first chips are stacked in a stepped staggered manner, so that a first stepped surface is formed on one side of the multiple first chips, and a second stepped surface is formed on the other side of the multiple first chips. The first stepped surface abuts against the inner wall of one side of the mounting hole, and a cutout is formed between the second stepped surface and the inner wall of the other side of the mounting hole. The first chip has at least one first pad at the position of the second stepped surface, and the first pads of two adjacent first chips are connected to each other by leads.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging structure technology, specifically relating to an embedded stacked chip packaging structure and its packaging method, and an integrated circuit board. Background Technology

[0002] With the rapid development of consumer electronics, the Internet of Things, and artificial intelligence, electronic devices are evolving rapidly towards integration, miniaturization, and high performance. This trend places increasingly stringent demands on chip packaging technology, requiring not only higher integration to support complex functions but also ensuring stable operation and good performance within a limited space.

[0003] In traditional chip packaging solutions, chips are typically mounted directly onto a circuit board using a planar layout. However, the functionality of a single chip is often limited. To achieve the complex functions required by electronic devices, a large number of chips must be arranged side-by-side on the circuit board. This layout directly leads to a significant increase in the circuit board area, making it difficult to meet the current urgent needs of electronic devices for miniaturization and thinner designs, and severely restricting the development of electronic devices towards higher integration levels.

[0004] To address the issues of low integration and large space occupation inherent in traditional planar layouts, the industry has proposed a three-dimensional stacked chip packaging solution. This solution significantly improves chip integration per unit space by stacking multiple chips vertically, thus alleviating the space pressure caused by planar layouts to some extent.

[0005] However, existing three-dimensional stacked architectures still have many problems that urgently need to be solved:

[0006] Firstly, heat dissipation is a significant issue. With a three-dimensional stacked architecture, multiple chips are concentrated on top of the substrate, leading to a substantial increase in heat generation per unit space. Currently used substrate materials have poor heat dissipation properties, failing to dissipate the large amount of heat generated during chip operation in a timely manner. This results in elevated chip operating temperatures, severely impacting chip stability and lifespan, and potentially causing equipment failure.

[0007] Secondly, encapsulating adhesive further exacerbates the heat dissipation problem. In existing three-dimensional stacked architectures, electrical connections between different chips need to be achieved through leads. To protect these electrical connection points from the influence of the external environment, encapsulating adhesive is required. However, encapsulating adhesive is also a poor heat dissipator. Its presence not only hinders the heat transfer path but also creates new thermal resistance between the chip and the external environment, further reducing the heat dissipation efficiency of the entire encapsulation structure and making the heat dissipation problem even more severe.

[0008] In summary, neither traditional planar layouts nor three-dimensional stacked architectures in existing technologies can adequately balance key performance indicators such as integration density, heat dissipation performance, and space occupancy. Therefore, a new chip packaging technology is urgently needed to solve these problems. Summary of the Invention

[0009] To address the problem of insufficient heat dissipation performance in existing chip packaging, this invention provides an embedded stacked chip packaging structure and its packaging method.

[0010] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows:

[0011] On one hand, the present invention provides an embedded stacked chip packaging structure, including multiple stacked layers, each layer including a core board body and a first chip. The core board body has mounting holes, and the first chip is embedded in the mounting holes. The multiple first chips are stacked in a stepped staggered manner, so that a first stepped surface is formed on one side of the multiple first chips, and a second stepped surface is formed on the other side of the multiple first chips. The first stepped surface abuts against the inner wall of one side of the mounting hole, and a cutout is formed between the second stepped surface and the inner wall of the other side of the mounting hole. The first chip has at least one first pad at the position of the second stepped surface. The first pads of two adjacent first chips are connected to each other by a lead wire. A first circuit pattern is provided on the outer side of the outermost core board body, and a second pad is provided on the outer side of one of the outermost first chips. The first circuit pattern extends to the surface of the first chip and is electrically connected to the second pad.

[0012] Optionally, one side of the inner wall of the plurality of mounting holes is staggered in a stepped manner to fit with the first stepped surface of the plurality of first chips, and the other side of the inner wall of the plurality of mounting holes is flush with each other. The hollow portion is filled with an encapsulating adhesive layer, which includes an epoxy resin layer and a thermally conductive layer. The epoxy resin layer covers the second stepped surface and the lead wire, and the thermally conductive layer fills the area in the hollow portion where no epoxy resin layer is provided.

[0013] Optionally, a prepreg adhesive layer is provided between two adjacent layers, and the prepreg adhesive layer has clearance holes at the positions corresponding to the cutouts.

[0014] Optionally, a second circuit pattern is provided on the surface of the inner core board body, and a third circuit pattern is provided on the outer side of the outermost core board body. The embedded stacked chip packaging structure is provided with multiple electrical connection holes, which penetrate multiple core board bodies and electrically connect two or more of the first circuit pattern, multiple second circuit patterns, and the third circuit pattern.

[0015] Optionally, the embedded stacked chip package structure further includes a second chip, which is located on the outer side of the outermost core board body and is electrically connected to the first circuit pattern.

[0016] Optionally, the embedded stacked chip package structure further includes a first heat sink and a second heat sink. The first heat sink is located on the outer side of one of the outermost first chips, and the second heat sink is located on the outer side of another of the outermost first chips. The second heat sink extends to the cutout portion and abuts against the thermally conductive layer.

[0017] In another aspect, the present invention provides an integrated circuit board, including the embedded stacked chip package structure described above.

[0018] Furthermore, the present invention provides a packaging method for the embedded stacked chip packaging structure as described above, comprising the following operations:

[0019] Step 1: Multiple layers and multiple prepreg adhesive layers are alternately stacked and pressed together to obtain a laminate. The inner walls of one side of the multiple mounting holes are staggered in a stepped manner to fit with the first stepped surface of the multiple first chips. The inner walls of the other side of the multiple mounting holes are flush with each other. A second stepped surface is formed on the other side of the multiple first chips. A hollow part is formed between the second stepped surface and the inner wall of the other side of the multiple mounting holes. The prepreg adhesive layer has a clearance hole corresponding to the position of the hollow part.

[0020] Step 2: Create a first circuit pattern on the outer surface of the laminate, and electrically connect the first circuit pattern to the second pad.

[0021] Step 3: Perform wire bonding operations between multiple first pads on the second step surface of the cutout section;

[0022] Step 4: Seal the cut-out part to form a sealing adhesive layer.

[0023] Optionally, step 2 further includes: creating connecting holes in the laminate, masking the cutout portion, depositing and electroplating a seed layer on the hole wall and the surface of the laminate to form an electrical connection hole in the connecting hole, and forming a copper layer on the surface of the laminate.

[0024] The copper layer on the outer side of the outermost layer is etched to obtain the first circuit pattern, and the copper layer on the outer side of the other outermost layer is etched to obtain the third circuit pattern.

[0025] Remove the mask from the cutout area after etching is complete.

[0026] Optionally, step 4 includes:

[0027] The hollowed-out portion is injection molded with epoxy resin to cover the second stepped surface and the lead wire, thus obtaining an epoxy resin layer. The hollowed-out portion is further filled with thermally conductive silver paste, and after curing, a thermally conductive layer is obtained.

[0028] The first heat sink is installed on the outer side of the outermost first chip, and the second heat sink is installed on the outer side of the other outermost first chip.

[0029] The embedded stacked chip packaging structure provided by the present invention combines a multi-layer board structure with a multi-chip stacking method, in which multiple first chips are embedded one-to-one in multiple core board bodies. This method simplifies the chip packaging process and can use lamination to form multiple first chips and multiple core board bodies into a whole. Since multiple first chips are stacked and embedded in multiple core board bodies, the space occupied in the horizontal and vertical directions can be effectively reduced, and the integration level can be improved. At the same time, the stacked first chips have heat dissipation surfaces on both sides of the thickness direction of the embedded stacked chip packaging structure, which can effectively improve the heat dissipation area and heat dissipation efficiency. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the embedded stacked chip packaging structure provided by the present invention;

[0031] Figure 2 This is a schematic diagram of the structural changes in steps 1 to 4 provided by the present invention.

[0032] The reference numerals in the accompanying drawings are as follows:

[0033] 1. Layer; 11. Core board body; 111. Mounting hole; 12. First chip; 121. First pad; 122. Lead; 13. First stepped surface; 14. Second stepped surface; 15. Second pad; 16. Cutout; 2. Prepreg adhesive layer; 3. Electrical connection hole; 3a. Communicating hole; 4. Encapsulating adhesive layer; 41. Epoxy resin layer; 42. Thermally conductive layer; 5. First circuit pattern; 6. Third circuit pattern; 7. Second chip; 8. First heat sink; 9. Second heat sink. Detailed Implementation

[0034] To make the technical problems solved, the technical solutions, and the beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0035] See Figure 1As shown, this embodiment of the invention provides an embedded stacked chip packaging structure, including multiple stacked layers 1. Each layer 1 includes a core board body 11 and a first chip 12. The core board body 11 has mounting holes 111, and the first chip 12 is embedded in the mounting holes 111. The multiple first chips 12 are stacked in a stepped, staggered manner, such that a first stepped surface 13 is formed on one side of the multiple first chips 12, and a second stepped surface 14 is formed on the other side of the multiple first chips 12. The first stepped surface 13 abuts against the inner wall of one side of the mounting hole 111. A cutout 16 is formed between the second stepped surface 14 and the inner wall of the other side of the mounting hole 111. The first chip 12 is provided with at least one first pad 121 at the position of the second stepped surface 14. The first pads 121 of two adjacent first chips 12 are connected to each other by a lead wire 122. A first circuit pattern 5 is provided on the outer side of the outermost core board body 11. A second pad 15 is provided on the outer side of one of the outermost first chips 12. The first circuit pattern 5 extends to the surface of the first chip 12 and is electrically connected to the second pad.

[0036] In the embedded stacked chip packaging structure, a combination of multi-layer board 1 structure and multi-chip stacking method is adopted, in which multiple first chips 12 are embedded one-to-one in multiple core board bodies 11. This method can simplify the chip packaging process. Multiple first chips 12 and multiple core board bodies 11 can be formed into a whole by lamination. Since multiple first chips 12 are stacked and embedded in multiple core board bodies 11, the space occupied in the horizontal and vertical directions can be effectively reduced, and the integration level can be improved. At the same time, the stacked first chips 12 have heat dissipation surfaces on both sides of the thickness direction of the embedded stacked chip packaging structure, which can effectively improve the heat dissipation area and heat dissipation efficiency.

[0037] The outer surfaces of the multiple first chips 12 after being stacked remain flush with the surface of the core board body 11. The first circuit pattern 5 can be electrically connected to the second pad 15 to realize the electrical lead-out of the multiple first chips 12. The first circuit pattern 5 can be further electrically connected to the second chip 7, which helps to maintain the surface flatness. At the same time, this electrical connection process is combined with the circuit etching process of the multilayer board process, reducing the process flow.

[0038] In one embodiment, in the same layer 1, the two side surfaces of the first chip 12 are flush with the two side surfaces of the core board body 11 to ensure the consistency of the thickness of the layer 1, which facilitates subsequent pressing operations and avoids deformation caused by inconsistent thickness; and the two outermost first chips 12 have surfaces exposed on the core board body 11, which helps to improve heat dissipation.

[0039] In one embodiment, the inner walls of one side of the plurality of mounting holes 111 are staggered in a stepped manner to fit against the first stepped surface 13 of the plurality of first chips 12. The inner walls of the other side of the plurality of mounting holes 111 are flush with each other. A second stepped surface 14 is formed on the other side of the plurality of first chips 12. The hollow portion 16 is filled with an encapsulating adhesive layer 4. The encapsulating adhesive layer 4 includes an epoxy resin layer 41 and a thermally conductive layer 42. The epoxy resin layer 41 covers the second stepped surface 14 and the lead wire 122. The thermally conductive layer 42 fills the area in the hollow portion 16 where the epoxy resin layer 41 is not provided.

[0040] By setting the epoxy resin layer 41, the first pad 121 and the lead 122 can be well protected, avoiding the corrosion problem of the first pad 121 and the lead 122 by external moisture. The thermal conductive layer 42 can provide an efficient channel for heat transfer, solving the problem of insufficient thermal conductivity of the core board body 11 itself. The thermal conductive layer 42 can quickly dissipate the heat generated by the first chip 12 during operation, significantly improving the heat dissipation problem of the three-dimensional stacked architecture. The epoxy resin layer 41 covering the second stepped surface 14 can prevent short circuits between chips caused by contact of the thermal conductive layer 42, improving heat dissipation performance while ensuring circuit safety, and further optimizing the stability and service life of chip operation.

[0041] In one embodiment, the thermally conductive layer 42 is obtained by curing a thermally conductive paste, the thermally conductive paste being selected from thermally conductive silver paste.

[0042] It should be noted that, compared with the existing method of embedding copper blocks, the use of thermally conductive paste has fluidity when filling the hollow part 16, which can better adapt to the non-flat surfaces such as epoxy resin layer 41 and hollow part 16, and improve heat conduction efficiency. The method of embedding copper blocks will inevitably form gaps at the contact surface, especially when in contact with non-flat surfaces such as hollow part 16, the gaps formed will significantly affect the heat conduction efficiency.

[0043] In one embodiment, a prepreg adhesive layer 2 is provided between two adjacent layers 1, and the prepreg adhesive layer 2 has a clearance hole at the position corresponding to the cutout portion 16.

[0044] The prepreg adhesive layer 2 provides stable structural support after curing, ensuring the stability and reliability of the entire encapsulation structure. The clearance holes allow the thermally conductive paste to directly facilitate heat transfer between adjacent layers 1, preventing the prepreg adhesive layer 2 from becoming an obstacle to heat conduction. Simultaneously, the clearance holes ensure that the thermally conductive paste can fully fill the cutouts 16, further improving heat transfer efficiency.

[0045] In one embodiment, a second circuit pattern is provided on the surface of the inner core board body 11, and a third circuit pattern 6 is provided on the outer side of the outermost core board body 11. The embedded stacked chip packaging structure is provided with a plurality of electrical connection holes 3, which penetrate the plurality of core board bodies 11 and electrically connect two or more of the first circuit pattern 5, the plurality of second circuit patterns and the third circuit pattern 6.

[0046] This design not only simplifies the circuit connection path but also enhances the integration and flexibility of the internal circuitry within the chip package structure. Electrical connection hole 3, serving as a channel for electrical signal transmission, ensures efficient and stable connections between various circuit patterns. Simultaneously, the electrical connections of multi-layered circuit patterns achieved through electrical connection hole 3 optimize current distribution, reduce signal loss and interference during transmission, and improve the overall circuit performance.

[0047] In one embodiment, the embedded stacked chip package structure further includes a second chip 7, which is located on the outer side of the outermost core board body 11. The second chip 7 is electrically connected to the first circuit pattern 5. Under the same operating conditions, the heat generated by the second chip 7 is greater than the heat generated by the first chip 12.

[0048] By placing the second chip 7, which generates more heat, on the outer surface of the core board body 11, while embedding the first chip 12, which generates relatively less heat, within the core board body 11, the spatial layout of the packaging structure can be effectively utilized to optimize thermal management. Placing the second chip 7, which generates more heat, on the outer layer makes heat dissipation easier, such as using heat sinks, fans, or other heat dissipation devices, effectively dissipating the heat generated by the second chip 7 and preventing overheating from affecting chip performance. Simultaneously, the first chip 12, which generates less heat, is embedded within the core board body 11 and is protected by it, reducing interference from the external environment and improving the chip's stability and reliability. This design, which rationally arranges the chips based on their heat generation, not only improves the overall heat dissipation efficiency of the packaging structure but also ensures stable chip operation and extends the chip's lifespan.

[0049] In one embodiment, the embedded stacked chip package structure further includes a first heat sink 8 and a second heat sink 9. The first heat sink 8 is located on the outer side of one of the outermost first chips 12, and the second heat sink 9 is located on the outer side of the other of the outermost first chips 12. The second heat sink 9 extends to the cutout portion 16 and abuts against the thermally conductive layer.

[0050] This dual-sided heat dissipation method effectively reduces the operating temperature of the first chip 12 and significantly improves the heat dissipation efficiency of the entire package structure. Furthermore, extending the second heat sink 9 to the cutout portion 16 and contacting the thermally conductive layer facilitates the further dissipation of heat from inside the package structure. Through the excellent thermal conductivity of the thermally conductive layer, heat can be quickly transferred to the second heat sink 9 and dissipated to the external environment via the second heat sink 9.

[0051] Thanks to the synergistic effect of the first heat sink 8 and the second heat sink 9, the heat of the embedded stacked first chip 12 can be dissipated more quickly, thereby extending the service life of the first chip 12 and enhancing the stability and reliability of the system.

[0052] In one embodiment, the core board body 11 is a polyimide sheet, the first circuit pattern 5, the second circuit pattern and the third circuit pattern 6 are all copper circuits, and the prepreg adhesive layer 2 is a polypropylene layer.

[0053] Another embodiment of the present invention provides an integrated circuit board including the embedded stacked chip package structure described above.

[0054] like Figure 2 As shown, another embodiment of the present invention provides a packaging method for the embedded stacked chip package structure as described above, including the following operations:

[0055] Step 1: Multiple layers 1 and multiple prepreg adhesive layers 2 are alternately stacked and pressed together to obtain a laminate. The inner walls of one side of the multiple mounting holes 111 are staggered in a stepped manner to fit with the first stepped surface 13 of the multiple first chips 12. The inner walls of the other side of the multiple mounting holes 111 are flush with each other. A second stepped surface 14 is formed on the other side of the multiple first chips 12. A hollow portion 16 is formed between the second stepped surface 14 and the inner walls of the other side of the multiple mounting holes 111. The prepreg adhesive layer 2 has a clearance hole corresponding to the position of the hollow portion 16.

[0056] Step 2: Create the first circuit pattern 5 on the outer surface of the laminate, so that the first circuit pattern 5 is electrically connected to the second pad 15.

[0057] Step 3: Perform wire bonding operations between multiple first pads 121 at the second stepped surface 14 of the cutout portion 16;

[0058] Step 4: Encapsulate the cutout portion 16 to form an encapsulating adhesive layer 4.

[0059] The encapsulation method of the embedded multilayer chip packaging structure combines the multilayer board 1 lamination process with multi-chip stacking, achieving a high degree of integration of the chip packaging structure. During the packaging process, each layer of board 1 is tightly bonded to the prepreg adhesive layer 2 through a precise lamination process, ensuring stable connections between layers. A first circuit pattern 5 is formed on the outer surface of the laminate, completing the electrical connection between the first chip 12 and the external circuit, thereby realizing the encapsulation of the embedded multilayer chip packaging structure. This method not only improves the packaging density but also optimizes the circuit layout and ensures surface flatness.

[0060] In one embodiment, step 2 further includes: creating a connecting hole 3a on the laminate, masking the cutout portion 16, depositing a seed layer and electroplating on the hole wall of the connecting hole 3a and the surface of the laminate to form an electrical connection hole 3 in the connecting hole 3a, and forming a copper layer on the surface of the laminate.

[0061] The copper layer on the outer side of the outermost layer 1 is etched to obtain the first circuit pattern 5. The copper layer on the outer side of the other outermost layer 1 is etched to obtain the third circuit pattern 6.

[0062] After etching is complete, remove the mask from the cutout section 16.

[0063] In one embodiment, the mask may be made of polyacrylic acid, and the mask is removed by dissolving it in an alkaline solution.

[0064] In one embodiment, the connecting hole 3a is formed by laser drilling.

[0065] In one embodiment, a solder mask layer is provided on the first circuit pattern 5 and the third circuit pattern 6 to protect the first circuit pattern 5 and the third circuit pattern 6. At the same time, the solder mask layer is provided with a clearance to expose the electrical connection position, such as the electrical connection position between the first circuit pattern 5 and the second chip 7.

[0066] In one embodiment, step 4 includes:

[0067] The hollow part 16 is injection molded with epoxy resin to cover the second stepped surface 14 and the lead wire 122, resulting in an epoxy resin layer 41. Thermally conductive silver paste is further filled into the hollow part 16, and after curing, a thermally conductive layer 42 is obtained.

[0068] The first heat sink 8 is installed on the outer side of the outermost first chip 12, and the second heat sink 9 is installed on the outer side of the other outermost first chip 12.

[0069] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An embedded stacked chip packaging structure, characterized in that, The device comprises multiple stacked layers, each layer including a core board body and a first chip. The core board body has mounting holes into which the first chip is embedded. The multiple first chips are stacked in a staggered, stepped manner, with a first stepped surface formed on one side and a second stepped surface formed on the other side. The first stepped surface abuts against the inner wall of one side of the mounting hole, and a cutout is formed between the second stepped surface and the inner wall of the other side of the mounting hole. Each first chip has at least one first pad at the position of the second stepped surface, and adjacent first pads of two first chips are interconnected by leads. The outermost core board body has a first circuit pattern on its outer side, and one of the first chips in the outermost layer has a second pad on its outer side. The first circuit pattern extends to the surface of the first chip and is electrically connected to the second pad. The inner walls of one side of the plurality of mounting holes are staggered in a stepped manner to fit with the first stepped surface of the plurality of first chips. The inner walls of the other side of the plurality of mounting holes are flush with each other. The hollow portion is filled with an encapsulating adhesive layer, which includes an epoxy resin layer and a thermally conductive layer. The epoxy resin layer covers the second stepped surface and the lead wire, and the thermally conductive layer fills the area in the hollow portion where no epoxy resin layer is provided.

2. The embedded stacked chip packaging structure according to claim 1, characterized in that, A prepreg adhesive layer is provided between two adjacent layers, and the prepreg adhesive layer has clearance holes at the positions corresponding to the cutouts.

3. The embedded stacked chip packaging structure according to claim 1, characterized in that, The inner core board body has a second circuit pattern on its surface, and the outermost core board body has a third circuit pattern on its outer side. The embedded stacked chip packaging structure has multiple electrical connection holes that penetrate multiple core boards and electrically connect two or more of the first circuit pattern, multiple second circuit patterns, and the third circuit pattern.

4. The embedded stacked chip packaging structure according to claim 1, characterized in that, The embedded stacked chip packaging structure also includes a second chip, which is located on the outer side of the outermost core board body and is electrically connected to the first circuit pattern.

5. The embedded stacked chip packaging structure according to claim 4, characterized in that, The embedded stacked chip packaging structure further includes a first heat sink and a second heat sink. The first heat sink is located on the outer side of one of the outermost first chips, and the second heat sink is located on the outer side of another of the outermost first chips. The second heat sink extends to the cutout portion and abuts against the thermally conductive layer.

6. An integrated circuit board, characterized in that, Includes the embedded stacked chip packaging structure as described in any one of claims 1 to 5.

7. The packaging method for the embedded stacked chip packaging structure according to any one of claims 1 to 5, characterized in that, Includes the following operations: Step 1: Multiple layers and multiple prepreg adhesive layers are alternately stacked and pressed together to obtain a laminate. The inner walls of one side of the multiple mounting holes are staggered in a stepped manner to fit with the first stepped surface of the multiple first chips. The inner walls of the other side of the multiple mounting holes are flush with each other. A second stepped surface is formed on the other side of the multiple first chips. A hollow part is formed between the second stepped surface and the inner wall of the other side of the multiple mounting holes. The prepreg adhesive layer has a clearance hole corresponding to the position of the hollow part. Step 2: Create a first circuit pattern on the outer surface of the laminate, and electrically connect the first circuit pattern to the second pad. Step 3: Perform wire bonding operations between multiple first pads on the second step surface of the cutout section; Step 4: Seal the cut-out part to form a sealing adhesive layer.

8. The packaging method for the embedded stacked chip packaging structure according to claim 7, characterized in that, Step 2 further includes: creating connecting holes in the laminate, masking the cutouts, depositing and electroplating seed layers on the hole walls and the surface of the laminate to form electrical connection holes in the connecting holes, and forming a copper layer on the surface of the laminate. The copper layer on the outer side of the outermost layer is etched to obtain the first circuit pattern, and the copper layer on the outer side of the other outermost layer is etched to obtain the third circuit pattern. Remove the mask from the cutout area after etching is complete.

9. The packaging method for the embedded stacked chip packaging structure according to claim 8, characterized in that, Step 4 includes: The hollowed-out portion is injection molded with epoxy resin to cover the second stepped surface and the lead wire, thus obtaining an epoxy resin layer. The hollowed-out portion is further filled with thermally conductive silver paste, and after curing, a thermally conductive layer is obtained. The first heat sink is installed on the outer side of the outermost first chip, and the second heat sink is installed on the outer side of the other outermost first chip.

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