Semiconductor packaging structure and packaging method

Abstract

This application discloses a semiconductor packaging structure and packaging method, relating to the field of semiconductor technology. The structure includes a substrate with multiple wiring layers and a first chip, a second chip, a third chip, and a fourth chip stacked together. A groove is formed on the substrate. The first chip is mounted upright on the substrate and located within the groove. The second chip is flip-chip mounted on the substrate and the first chip, and its bumps are connected to the wiring layers and the pads of the first chip. A first through-hole is formed on the second chip. The third chip is mounted upright on the second chip. The fourth chip is flip-chip mounted on the second and third chips, and its conductive pillars pass through the first through-hole to connect to the pads of the first chip. The first bump of the fourth chip is connected to the pads of the third chip. This semiconductor packaging structure, by optimizing the chip stacking method and interconnection paths, reduces the use of TSV conductive pillars, effectively reducing leakage current risk and improving the stability and reliability of the HBM stacking system.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure and packaging method thereof. Background Technology

[0002] As the performance requirements of high-performance computing (HPC) chips such as CPUs, GPUs, and FPGAs continue to rise, a large number of chip units need to be integrated into their 2.5D packaging structures. To meet the demand for increased storage computing power, high-bandwidth memory (HBM) chip stacking technology has become a core solution.

[0003] In the traditional HBM chip manufacturing process, vias are typically formed first through etching, followed by the deposition of an insulating layer on the sidewalls of the vias, and finally electroplating to form through-silicon vias (TSVs). This structure allows stacked HBM chips to achieve efficient interconnection with high-density metal wiring through TSV vertical interconnects. However, in practical applications, TSVs are prone to leakage current, which can lead to electrical failure of transistors inside the chip, thereby affecting the stability and reliability of the entire HBM stacking system. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor packaging structure and packaging method thereof, which reduces the use of TSV conductive pillars by optimizing the chip stacking method and interconnection path, thereby effectively reducing the risk of leakage current and improving the stability and reliability of HBM stacking system.

[0005] The embodiments of this application are implemented as follows:

[0006] A first aspect of this application provides a semiconductor packaging structure, including a substrate having multiple wiring layers and a first chip, a second chip, a third chip, and a fourth chip stacked together. A groove is formed on the substrate. The first chip is mounted upright on the substrate and located within the groove. The second chip is flip-chip mounted on the substrate and the first chip, and a bump on the second chip is connected to the wiring layers and the pads of the first chip. A first through-hole is formed on the second chip. The third chip is mounted upright on the second chip. The fourth chip is flip-chip mounted on the second chip and the third chip, and a conductive post of the fourth chip passes through the first through-hole to connect to the pads of the first chip. A first bump on the fourth chip is connected to the pads of the third chip.

[0007] In one possible implementation, the diameter of the first through hole is larger than the diameter of the conductive post of the fourth chip, and the diameter of the first through hole is larger than the diameter of the pad of the first chip. A first adhesive layer is disposed between the first through hole and the conductive post of the fourth chip, and the first adhesive layer covers the conductive post of the fourth chip and the pad of the first chip.

[0008] In one possible implementation, the top surface of the first chip is provided with at least one first bonding wire, and the bottom surface of the fourth chip is provided with at least one second bonding wire, wherein the first bonding wire and the second bonding wire are close to each other and spaced apart.

[0009] As one possible implementation, it also includes a protective adhesive layer and a molding compound. The edge of the fourth chip has a second through hole. The protective adhesive layer covers the outside of the first chip, the second chip and the third chip, and covers the bottom of the fourth chip through the second through hole. The molding compound covers the outside of the protective adhesive layer and the top of the fourth chip.

[0010] In one possible implementation, a first through-silicon via (TSV) is provided on the second chip, and the second bump of the fourth chip is connected to the wiring layer through the first TSV.

[0011] In one possible implementation, there are multiple second chips, which are spaced apart. Each second chip has a first through hole. The fourth chip has multiple conductive pillars, which are correspondingly inserted into the first through holes of the multiple second chips.

[0012] In one possible implementation, the number of third chips is one, and one third chip is simultaneously disposed on multiple second chips; the number of first bumps of the fourth chip is multiple, and the multiple first bumps of the fourth chip are correspondingly connected to the pads of one third chip; or, the number of third chips is multiple, and multiple third chips are correspondingly disposed on multiple second chips; the number of first bumps of the fourth chip is multiple, and the multiple first bumps of the fourth chip are correspondingly connected to the pads of multiple third chips.

[0013] As one possible implementation, a fifth chip is also included, wherein the fourth chip has a second through-silicon via, the fifth chip is flip-chip mounted on the fourth chip, and the bumps of the fifth chip are connected to the pads of the third chip through the second through-silicon via.

[0014] As one possible implementation, the chip further includes a sixth chip and a seventh chip. The fourth chip has a third through-hole, a fourth through-hole, and a third through-silicon via (TSV). The sixth chip is flip-chip mounted on the fourth chip, and the conductive post of the sixth chip passes through the third through-hole to connect with the pads of the third chip. The sixth chip has a fourth TSV. The seventh chip is flip-chip mounted on the fourth chip and the sixth chip, and the conductive post of the seventh chip passes through the fourth through-hole to connect with the pads of the third chip. The first bump of the seventh chip is connected to the fourth chip through the third TSV, and the second bump of the seventh chip is connected to the sixth chip through the fourth TSV.

[0015] As one possible implementation, it also includes an eighth chip, wherein the fourth chip has a fifth through-hole and a fifth through-silicon via, the eighth chip is flip-chip mounted on the fourth chip, and the conductive post of the eighth chip passes through the fifth through-hole to be connected to the pad of one of the third chips, and the bump of the eighth chip is connected to the pad of another of the third chips through the fifth through-silicon via.

[0016] As one possible implementation, it also includes multiple HBM stacked structures, each of which includes a substrate die and multiple stacked core dies. The substrate dies of the multiple HBM stacked structures are mounted on the fourth chip. The eighth chip is provided with multiple sixth through-silicon vias. The core dies of the multiple HBM stacked structures near the substrate die are connected to the multiple substrate dies through the multiple sixth through-silicon vias.

[0017] In one possible implementation, the top surface of the fourth chip is provided with at least one third bonding wire, which extends toward the bottom surface of the eighth chip and is spaced apart from the bottom surface of the eighth chip.

[0018] In one possible implementation, the substrate, the first chip, the second chip, the third chip, and the fourth chip form a packaging module. There are multiple packaging modules. The eighth chip has a sixth through-hole. The multiple packaging modules are stacked, and two adjacent packaging modules are connected by solder balls disposed in the sixth through-hole.

[0019] In one possible implementation, the top surface of the eighth chip protrudes from the top surface of the plastic encapsulation body of the lower packaging module. A second adhesive layer with a cavity is provided between two adjacent packaging modules. The second adhesive layer fills the space between the sixth through-hole and the solder ball. The second adhesive layer covers the side surface of the eighth chip and the solder ball, and a portion of the top surface of the eighth chip is exposed in the cavity of the second adhesive layer.

[0020] A second aspect of this application provides a packaging method for a semiconductor packaging structure, used to prepare the aforementioned semiconductor packaging structure, the method comprising:

[0021] A substrate with multiple wiring layers is provided, and grooves are formed on the substrate by etching or laser grooving processes;

[0022] A first chip is provided, and the first chip is mounted and fixed in the groove using a positive mounting process;

[0023] A second chip is provided, which is fixed on the substrate and the first chip using a flip-chip process, and a first through-hole is formed on the second chip by a laser or etching process;

[0024] A third chip is provided, and the third chip is mounted and fixed on the second chip using a positive mounting process;

[0025] A fourth chip is provided, wherein the conductive post of the fourth chip is inserted into the first through hole and soldered to the pad of the first chip, and the first bump of the fourth chip is soldered to the pad of the third chip.

[0026] The beneficial effects of the embodiments of this application include:

[0027] This semiconductor packaging structure optimizes the chip stacking method by mounting the first chip upright in the substrate recess, the second chip flip-chip on the substrate and the first chip, the third chip upright on the second chip, and the fourth chip flip-chip on the second and third chips. The interconnect path, where the conductive pillars of the fourth chip pass through the first via of the second chip to connect to the pads of the first chip, significantly reduces the reliance on TSV conductive pillars for vertical interconnection in traditional HBM stacking. This fundamentally reduces the risk of leakage current caused by defects in the TSV conductive pillar insulation layer and metal diffusion. Effective control of leakage current risk not only prevents electrical failure of internal transistors due to leakage but also reduces additional power consumption and signal interference caused by leakage. Therefore, it significantly improves the overall performance of the HBM stacking system from multiple dimensions, including operational stability, data transmission reliability, and long-term durability. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1This is a schematic diagram of the semiconductor packaging structure provided in the first embodiment of this application;

[0030] Figure 2 This is a schematic diagram of the semiconductor packaging structure provided in the second embodiment of this application;

[0031] Figure 3 This is a schematic diagram of the semiconductor packaging structure provided in the third embodiment of this application;

[0032] Figure 4 This is a schematic diagram of the semiconductor packaging structure provided in the fourth embodiment of this application;

[0033] Figure 5 This is a schematic diagram of the semiconductor packaging structure provided in the fifth embodiment of this application;

[0034] Figure 6 This is a schematic diagram of the semiconductor packaging structure provided in the sixth embodiment of this application;

[0035] Figure 7 This is a schematic diagram of the semiconductor packaging structure provided in the seventh embodiment of this application.

[0036] Icons: 10-Substrate; 11-Wiring layer; 12-Groove; 20-First chip; 21-First wire bonding; 30-Second chip; 31-First via; 311-First adhesive layer; 32-First through-silicon via; 40-Third chip; 50-Fourth chip; 51-Second via; 52-Second through-silicon via; 53-Third via; 54-Fourth via; 55-Third through-silicon via; 56-Fifth via; 57-Fifth through-silicon via; 58-Placement groove; 5 91 - Second wire bonding; 592 - Third wire bonding; 60 - Fifth chip; 70 - Sixth chip; 71 - Fourth through-silicon via; 80 - Seventh chip; 90 - Eighth chip; 91 - Sixth through-silicon via; 92 - Sixth via; 921 - Solder ball; 100 - Protective adhesive layer; 110 - Molding package; 120 - Multiple HBM stacked structures; 121 - Base die; 122 - Core die; 130 - Packaging module; 140 - Second adhesive layer; 141 - Cavity. Detailed Implementation

[0037] The embodiments described below represent the information necessary for those skilled in the art to practice the embodiments and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will recognize the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0038] It should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending to another element," it may be directly on another element or directly extending to another element, or there may be an intermediate element. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending over another element," it may be directly on another element or directly extending to another element, or there may be an intermediate element.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that, when used herein, the term “comprising” indicates the presence of the stated feature, integer, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0040] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that the terms used herein should be interpreted as having the same meaning as they would in the context of this specification and the relevant field, and not in an idealized or overly formal sense, unless expressly defined herein.

[0041] In the traditional HBM chip manufacturing process, through-hole vias are first formed on the die through an etching process. Then, an insulating layer is prepared on the sidewalls of the vias using a deposition process to isolate the silicon substrate from the conductive layer. Finally, a metal (such as copper) is filled in using an electroplating process to form the conductive pillars of the through-holes. Based on this structure, the stacked HBM chips can build efficient interconnect links with TSV vertical interconnects and high-density metal wiring to meet high-bandwidth transmission requirements. However, in practical applications, the TSV conductive pillars are prone to leakage current due to problems such as insulating layer defects and metal diffusion. This can not only lead to electrical failure of the transistors inside the chip, but also directly affect the stability and long-term reliability of the entire HBM stacking system.

[0042] To solve the above problems, please refer to the following: Figures 1 to 7This application provides a semiconductor packaging structure and packaging method thereof. By optimizing the chip stacking method, a first chip 20 is mounted upright in the groove 12 of the substrate 10, a second chip 30 is flip-chip mounted on the substrate 10 and the first chip 20, a third chip 40 is mounted upright on the second chip 30, and a fourth chip 50 is flip-chip mounted on the second chip 30 and the third chip 40. The conductive pillars of the fourth chip 50 pass through the first through-hole 31 of the second chip 30 to connect to the pads of the first chip 20. This significantly reduces the scenario in traditional HBM stacking that relies on TSV conductive pillars to achieve vertical interconnection. It fundamentally reduces the risk of leakage current caused by defects in the insulation layer of TSV conductive pillars, metal diffusion, and other problems. The effective control of leakage current risk can not only avoid electrical failure of the transistors inside the chip due to leakage, but also reduce the additional power consumption and signal interference caused by leakage. Thus, it significantly improves the overall performance of the HBM stacking system from multiple dimensions such as operational stability, data transmission reliability, and long-term durability.

[0043] Specifically, the first aspect of the embodiments of this application, as follows: Figures 1 to 7 As shown, a semiconductor package structure is provided, including a substrate 10 having multiple wiring layers 11 and a first chip 20, a second chip 30, a third chip 40 and a fourth chip 50 stacked thereon. A groove 12 is formed on the substrate 10. The first chip 20 is mounted upright on the substrate 10 and located in the groove 12. The second chip 30 is flip-chip mounted on the substrate 10 and the first chip 20, and the bumps of the second chip 30 are connected to the wiring layers 11 and the pads of the first chip 20. A first through-hole 31 is formed on the second chip 30. The third chip 40 is mounted upright on the second chip 30. The fourth chip 50 is flip-chip mounted on the second chip 30 and the third chip 40, and the conductive post of the fourth chip 50 passes through the first through-hole 31 to connect with the pads of the first chip 20. The first bump of the fourth chip 50 is connected to the pads of the third chip 40.

[0044] It should be noted that the semiconductor package structure includes a substrate 10, a first chip 20, a second chip 30, a third chip 40, and a fourth chip 50. The substrate 10 has multiple wiring layers 11 (such as 3 to 6 layers) inside. The wiring layers 11 are interconnected by conductive vias to form a multi-layer three-dimensional wiring network. A groove 12 is formed on the surface of the substrate 10. The depth of the groove 12 is at least equal to the thickness of the first chip 20. The first chip 20 is fixedly mounted in the groove 12 of the substrate 10. The substrate 10 serves as the carrier for all chips. The multiple wiring layers 11 enable signal or power transmission between chips and between chips and external circuit boards. The groove 12 design provides a space for the first chip 20, reduces the overall package thickness, and avoids physical interference between the first chip 20 and other chips.

[0045] The first chip 20 uses a top-mount process, fixing its bottom surface to the groove 12 of the substrate 10 via an adhesive layer to reduce the impact of external vibrations. The top surface of the first chip 20 has multiple pads for connection with the second chip 30 and the fourth chip 50, meeting subsequent multilayer interconnect requirements. The second chip 30 uses a flip-chip process. Its bottom surface has an array of bumps; some bumps connect to the wiring layer 11 on the surface of the substrate 10 (excluding the groove 12 area), while others are soldered to the pads on the top surface of the first chip 20. A first via 31 is formed in the center of the second chip 30, penetrating both its top and bottom surfaces for the conductive pillars of the fourth chip 50. The second chip 30 interacts with both the substrate 10 and the first chip 20 simultaneously. The flip-chip bumps shorten the signal path, and the first via 31 is designed for the fourth chip 50. A direct interconnection channel is reserved between the fourth chip 40 and the first chip 20 to avoid signal detours. The third chip 40 adopts a forward mounting process, with its bottom surface fixed to the top surface of the second chip 30 (excluding the area of ​​the first via 31) through an adhesive layer. The top surface of the third chip 40 has multiple pads for connection with the fourth chip 50. The forward mounting method simplifies the assembly process and utilizes the top surface space of the second chip 30 to achieve stacking, further improving integration. The fourth chip 50 adopts a flip-chip process. The bottom surface of the fourth chip 50 has conductive pillars and a first bump. The conductive pillars pass through the first via 31 of the second chip 30, and their bottoms are soldered to the pads on the top surface of the first chip 20, realizing direct interconnection between the fourth chip 50 and the first chip 20. The first bump is connected to the pads on the top surface of the third chip 40. The design of the conductive pillars passing through the first via 31 avoids signal detours through the second chip 30, significantly reducing transmission delay.

[0046] The first chip 20 can be a GPU chip or a CPU chip, the second chip 30 can be a logic control chip or a SOC chip, the third chip 40 can be a storage chip, and the fourth chip 50 can also be a storage chip, so that the third chip 40 and the fourth chip 50 can be stacked for storage. The third chip 40 serves as a buffer storage area to improve computing power. Alternatively, the third chip 40 can also be a SOC chip or a logic control chip to improve the read and write speed of the fourth chip 50. Taking a first chip 20 as a GPU chip, a second chip 30 as a SOC chip, a third chip 40 as a memory chip, and a fourth chip 50 as a memory chip as an example, the workflow is as follows: External data (such as an image to be recognized) is transmitted to the second chip 30 via the wiring layer 11 of the substrate 10. After parsing, the second chip 30 sends a calculation instruction to the first chip 20 through bumps, and simultaneously sends a "buffer preparation" signal to the third chip 40. The third chip 40 activates a preset area as a temporary cache. After receiving the instruction, the first chip 20 reads the preprocessed model from the fourth chip 50 through the conductive pillar in the first through-hole 31 of the second chip 30. The intermediate data generated by the calculation is stored in the third chip 40 without occupying the internal cache of the first chip 20. When the buffer of the three-chip 40 is about to be full, the second chip 30 detects this and initiates "data migration". It transfers some intermediate data to the fourth chip 50 through the first bump of the fourth chip 50. The fourth chip 50 serves as the main storage area to store the model data and migration results. The second chip 30 implements hierarchical management of "hot data stored in the third chip 40 and cold data stored in the fourth chip 50". After the first chip 20 completes the calculation, it stores the recognition result in the fourth chip 50 through the conductive pillar and sends a "calculation completed" signal to the second chip 30. The second chip 30 reads the result from the fourth chip 50 and outputs it to the outside through the wiring layer 11 of the substrate 10. At the same time, it sends a "cache clearing" command to the third chip 40 and the fourth chip 50 to release space.

[0047] Traditional planar packaging, if integrating four layers of chips, requires the chips to be laid flat on the substrate 10, occupying a large area. This application, through "groove 12 accommodating + stepped stacking," allows the four layers of chips to be stacked vertically, occupying a smaller area and reducing the package volume compared to traditional solutions. This allows for direct application in scenarios with strict size requirements, such as smartphones, AR devices, or VR devices, while providing higher integration support for system-in-package. The fourth chip 50 is directly interconnected with the first chip 20 through conductive pillars, shortening the signal path length and improving the transmission rate. This meets the high-speed data transmission requirements of 5G, AI computing, etc. Furthermore, the shorter path reduces signal attenuation and crosstalk during transmission, ensuring the reliability of high-speed communication. The combination of chip 20 and third chip 40 with flip-chip (second chip 30 and fourth chip 50) technology allows for the selection of the optimal interconnection scheme based on chip type (e.g., memory chips are suitable for upright mounting, and computing chips are suitable for flip-chip). It also allows for flexible combination of chips with different functions (e.g., logic + memory + computing + power) to form a complete functional module without the need for external expansion modules, meeting the needs of different scenarios (e.g., signal processing modules for 5G base stations, computing power modules for AI terminals). The four-layer chip and substrate 10 are integrated into a single package, eliminating the need to separately solder each chip to external modules. Only the external pins of the package (e.g., solder balls set on the bottom surface of substrate 10) need to be soldered to the external circuit board, simplifying the assembly process and improving production line efficiency.

[0048] In one possible implementation, the top surface of the first chip 20 is recessed into the top surface of the substrate 10, or the top surface of the first chip 20 is flush with the top surface of the substrate 10.

[0049] It should be noted that in some embodiments, the depth of the groove 12 formed in the substrate 10 is greater than the thickness of the first chip 20. When the first chip 20 is mounted in the groove 12, the top surface of the first chip 20 is recessed into the top surface of the substrate 10. The recessed structure makes the first chip 20 "embedded" inside the substrate 10, rather than completely superimposed on the surface of the substrate 10. This can further reduce the thickness of the packaging structure in the vertical direction. When the packaging structure is scratched or impacted by external forces, the substrate 10 will bear the external force first, reducing the risk of the first chip 20 being directly subjected to force and improving its service life.

[0050] In other embodiments, such as Figures 1 to 7 As shown, the depth of the groove 12 in the substrate 10 is equal to the thickness of the first chip 20. When the first chip 20 is mounted upright in the groove 12, the top surface of the first chip 20 is flush with the top surface of the substrate 10. When the second chip 30 is flipped onto the substrate 10 and the first chip 20 with their surfaces flush, the bumps on the bottom surface of the second chip 30 can make uniform contact with the two carriers (i.e., the substrate 10 and the first chip 20), ensuring that the force is consistent during soldering and avoiding partial soldering failure due to height difference. This further improves the reliability of the connection between the second chip 30 and the substrate 10 and the first chip 20.

[0051] As one possible implementation method, such as Figures 1 to 7 As shown, the diameter of the first through-hole 31 is larger than the diameter of the conductive post of the fourth chip 50, and the diameter of the first through-hole 31 is larger than the diameter of the pad of the first chip 20. The gap can absorb the processing tolerance, avoid collision between the conductive post and the hole wall of the first through-hole 31 or misalignment with the pad of the first chip 20, which would lead to poor soldering. This improves the alignment rate between the conductive post and the pad, and ensures the stability of the direct interconnection between the fourth chip 50 and the first chip 20. Furthermore, after the conductive post is inserted into the first through-hole 31, a first adhesive layer 311 is provided between the inner wall of the first through-hole 31 and the outer wall of the conductive post of the fourth chip 50. The first adhesive layer 311 covers the conductive post of the fourth chip 50 and the pad of the first chip 20. The gap between the two can be filled with insulating thermally conductive adhesive (such as epoxy resin) to form the first adhesive layer 311, which not only fixes the position of the conductive post and prevents vibration displacement, but also further isolates impurities, and at the same time helps to conduct the working heat of the second chip 30 and the fourth chip 50.

[0052] As one possible implementation method, such as Figure 1 As shown, the top surface of the first chip 20 is provided with at least one first bonding wire 21, and the bottom surface of the fourth chip 50 is provided with at least one second bonding wire 591. The first bonding wire 21 and the second bonding wire 591 are close to each other and spaced apart.

[0053] It should be noted that the top surface of the first chip 20 is provided with at least one first bonding wire 21 (e.g., 1 to 4), and the bottom surface of the fourth chip 50 is provided with at least one second bonding wire 591 (e.g., 1 to 4). The first bonding wire 21 and the second bonding wire 591 can be made of highly conductive and thermally conductive gold or copper wire. One end of each wire is fixed to the pads on the top surface of the first chip 20 and the bottom surface of the fourth chip 50 respectively by a bonding process (e.g., ultrasonic bonding). The other ends extend towards each other to bring them closer together (e.g., vertically opposite each other). Furthermore, the other ends of the first bonding wire 21 and the second bonding wire 591 are spaced apart and do not contact each other. For example, when there are multiple first bonding wires 21 and multiple second bonding wires 591, they are arranged in a one-to-one correspondence.

[0054] The first chip 20 and the fourth chip 50 generate heat during operation. By setting a first bonding wire 21 on the top surface of the first chip 20 and a second bonding wire 591 on the bottom surface of the fourth chip 50, on the one hand, the first bonding wire 21 and the second bonding wire 591 can improve the heat dissipation of the first chip 20 and the fourth chip 50. The space between the two bonding wires can accelerate the airflow, carry away the heat between the two bonding wires, and prevent the heat from accumulating between the two bonding wires. On the other hand, if the potential of one chip is too high (such as the potential of the top surface of the first chip 20 being higher than the potential of the bottom surface of the fourth chip 50), the space between the two bonding wires can form an electric field coupling, causing the charge in the high potential area to slowly migrate to the low potential area, thereby achieving the same potential around the two chips (i.e., a small potential difference) and avoiding local static electricity accumulation.

[0055] As one possible implementation method, such as Figure 1 As shown, the semiconductor packaging structure also includes a protective adhesive layer 100 and a molding compound 110. A second through-hole 51 is provided on the edge of the fourth chip 50. The protective adhesive layer 100 covers the outer side of the first chip 20, the second chip 30 and the third chip 40, and covers the bottom of the fourth chip 50 through the second through-hole 51. The molding compound 110 covers the outer side of the protective adhesive layer 100 and the top of the fourth chip 50.

[0056] It should be noted that the semiconductor packaging structure also includes a protective adhesive layer 100 and a molding compound 110. The protective adhesive layer 100 can be made of highly insulating and highly adhesive epoxy resin or silicone gel. It is applied to the outside of the first chip 20, the second chip 30, and the third chip 40 by dispensing or potting. The edge of the fourth chip 50 has a second through-hole 51. The protective adhesive layer 100 penetrates to the bottom of the fourth chip 50 through the second through-hole 51, thus covering the area where the bottom of the fourth chip 50 connects with the top surface of the second chip 30. This forms a continuous coverage of "protective adhesive layer 100 - second through-hole 51 - bottom of the fourth chip 50". The protective adhesive layer 100 serves as an inner protective barrier to isolate moisture and dust from the core chip and interconnect structure, while also buffering local vibrations during chip operation.

[0057] The molding compound 110 can be made of high-temperature resistant and high-mechanical-strength epoxy resin composite material. It is completely wrapped around the outside of the protective adhesive layer 100 through mold injection molding process, covering the top of the fourth chip 50 and the edge area of ​​the substrate 10. Only the external pins of the bottom surface of the substrate 10 are exposed to facilitate connection with the circuit board. The molding compound 110 acts as an "outer protective barrier" to play a core role in shock resistance, scratch resistance, and high-temperature resistance. At the same time, it completely isolates each chip from the external environment, meets the IP65 dustproof and waterproof requirements, and is suitable for harsh working environments (such as industrial workshops and automotive electronic compartments).

[0058] As one possible implementation method, such as Figures 2 to 7 As shown, a first through-silicon via 32 is provided on the second chip 30, and the second bump of the fourth chip 50 is connected to the wiring layer 11 through the first through-silicon via 32.

[0059] It should be noted that the second chip 30 is provided with a first through-silicon via 32, and the bottom surface of the fourth chip 50 is provided with a second bump in addition to the conductive pillar and the first bump. When the fourth chip 50 is flipped, the second bump of the fourth chip 50 is precisely aligned with the top port of the first through-silicon via 32 on the top surface of the second chip 30. The two can be mechanically fixed and electrically connected by reflow soldering. The bottom port of the first through-silicon via 32 can be directly soldered to the wiring layer 11 on the surface of the substrate 10, thus forming a vertical interconnect link of "the second bump of the fourth chip 50 - the first through-silicon via 32 - the wiring layer 11 of the substrate 10". The vertical interconnect link constructed by the first through-silicon via 32 shortens the interconnection path between the fourth chip 50 and the wiring layer 11 of the substrate 10, reduces signal delay, and reduces signal attenuation during transmission inside the second chip 30. The first through-silicon via 32 adopts a vertical through-hole design, which does not occupy additional planar area of ​​the second chip 30. At the same time, the layout around the first through-hole 31 forms a compact spatial layout with the above-mentioned "conductive pillar through-hole" structure, which does not increase the overall area of ​​the package. It can also further enhance the advantages of high-density integration and adapt to the needs of miniaturized high-end electronic devices.

[0060] As one possible implementation method, such as Figures 1 to 7 As shown, there are multiple second chips 30, which are spaced apart. Each second chip 30 has a first through hole 31. There are multiple conductive posts of the fourth chip 50, which are respectively inserted into the first through holes 31 of the multiple second chips 30.

[0061] It should be noted that there are multiple second chips 30 (e.g., 2 to 4), which are spaced apart along the surface of the substrate 10 to avoid thermal interference and signal crosstalk between chips. Each second chip 30 has a first through-hole 31. The fourth chip 50 has multiple conductive pillars, which are aligned with the first through-holes 31 of the second chips 30. When the fourth chip 50 is flip-chip mounted, the multiple conductive pillars of the fourth chip 50 are simultaneously inserted into the first through-holes 31 of the corresponding second chips 30, and their bottoms are soldered to the pads of the first chip 20. The gaps between the inner walls of the multiple first through-holes 31 and the conductive pillars can be filled with insulating thermally conductive adhesive to form a first adhesive layer 311, which not only fixes the position of the conductive pillars but also helps to conduct the working heat of the second chips 30 and the fourth chip 50, avoiding local overheating.

[0062] As one possible implementation method, such as Figures 2 to 4As shown, there is one third chip 40, which is simultaneously disposed on multiple second chips 30. There are multiple first bumps on the fourth chip 50, and the multiple first bumps of the fourth chip 50 are connected to the pads of the third chip 40.

[0063] It should be noted that there is only one third chip 40. The bottom surface of the third chip 40 is simultaneously fixed to the top surface of multiple second chips 30 through an adhesive layer, covering the core interconnection area of ​​each second chip 30 without obstructing the first via 31 and the first silicon via 32, forming a centralized layout of "one third chip 40 bridging multiple second chips 30". If the third chip 40 is a memory chip, it serves as a "shared cache center" for multiple second chips 30, uniformly storing multi-channel data. If the third chip 40 is a control chip (such as a SOC), it serves as a "unified control hub", coordinating the working timing of multiple second chips 30 and avoiding synchronization deviations caused by decentralized control. The fourth chip 50 has multiple first bumps, matching the number of pads of the multiple third chips 40. When the fourth chip 50 is flip-chip mounted, the multiple first bumps of the fourth chip 50 are soldered to the pads of the third chip 40 to form a centralized interconnection link of "fourth chip 50 - multiple first bumps - third chip 40".

[0064] As one possible implementation method, such as Figure 3 As shown, the semiconductor package structure also includes a fifth chip 60, a second through-silicon via 52 is provided on the fourth chip 50, the fifth chip 60 is flip-chip mounted on the fourth chip 50, and the bumps of the fifth chip 60 are connected to the pads of the third chip 40 through the second through-silicon via 52.

[0065] It should be noted that this semiconductor packaging structure also includes a fifth chip 60. A second through-silicon via (TSV) 52 is provided on the fourth chip 50. The fifth chip 60 is connected to the top surface of the fourth chip 50 using a flip-chip process. The bumps of the fifth chip 60 are electrically connected to the pads of the third chip 40 through the second TSV 52, forming a vertical interconnect link of "fifth chip 60 - second TSV 52 - third chip 40". This shortens the interconnect path between the fifth chip 60 and the third chip 40, avoiding the traditional detour transmission of "fifth chip 60 - substrate 10 - third chip 40", and reducing transmission loss of high-frequency signals. The fifth chip 60 can be a dedicated function chip (such as an AI accelerator chip, image sensor, or RF chip), providing differentiated functions according to the application scenario. It forms a heterogeneous integration with the original chip, achieving integrated "acquisition-computation-storage" functions without external expansion, further improving system-level integration.

[0066] As one possible implementation method, such as Figure 4As shown, the semiconductor package structure also includes a sixth chip 70 and a seventh chip 80. The fourth chip 50 has a third through-hole 53, a fourth through-hole 54, and a third through-silicon via 55. The sixth chip 70 is flip-chip mounted on the fourth chip 50, and the conductive post of the sixth chip 70 passes through the third through-hole 53 to connect with the pads of the third chip 40. The sixth chip 70 has a fourth through-silicon via 71. The seventh chip 80 is flip-chip mounted on the fourth chip 50 and the sixth chip 70, and the conductive post of the seventh chip 80 passes through the fourth through-hole 54 to connect with the pads of the third chip 40. The first bump of the seventh chip 80 is connected to the fourth chip 50 through the third through-silicon via 55, and the second bump of the seventh chip 80 is connected to the sixth chip 70 through the fourth through-silicon via 71.

[0067] It should be noted that this semiconductor package structure also includes a sixth chip 70 and a seventh chip 80. The fourth chip 50 (main memory or bridge chip) serves as an intermediate interconnect hub, with a third through-hole 53, a fourth through-hole 54, and a third through-silicon via 55. The sixth chip 70 can be a dedicated acceleration chip (such as an AI inference chip or a signal processing chip). The sixth chip 70 is flip-chip mounted on the top surface of the fourth chip 50. The bottom surface of the sixth chip 70 has conductive pillars whose diameter matches the third through-hole 53. The conductive pillars of the sixth chip 70 pass through the third through-hole 53 and connect to the pads of the third chip 40, forming a direct data link between the sixth chip 70 and the third chip 40. The sixth chip 70 has a fourth through-silicon via 71 for interconnection with the seventh chip 80. The seventh chip 80 can be an auxiliary function chip (such as an interface control chip or a sensor signal processing chip). The seventh chip 80 is flip-chip mounted on the top surface of the fourth chip 50 and the sixth chip 70. The bottom surface of the seventh chip 80 has conductive pillars, a first bump, and a second bump. The conductive pillars of the seventh chip 80 pass through the fourth through-hole 54 and are connected to the pads of the third chip 40 at the bottom. The first bump of the seventh chip 80 is connected to the fourth chip 50 through the third through-silicon via 55, and the second bump of the seventh chip 80 is connected to the sixth chip 70 through the fourth through-silicon via 71, thereby achieving multi-dimensional interconnection. By extending AI inference, interface control, and other functions through the sixth chip 70 and the seventh chip 80, a complete "input-computation-output" link is formed with the original chips, eliminating the need for external modules and further improving system-level integration.

[0068] As one possible implementation method, such as Figures 5 to 7 As shown, there are multiple third chips 40, which are correspondingly disposed on multiple second chips 30. There are multiple first bumps on the fourth chip 50, and the multiple first bumps of the fourth chip 50 are correspondingly connected to the pads of the multiple third chips 40.

[0069] It should be noted that there are multiple third chips 40, matching the number of second chips 30. Each third chip 40 is independently mounted on the top surface of its corresponding second chip 30 and fixed by an adhesive layer, forming an independent functional unit of "second chip 30 - third chip 40". Each third chip 40 serves as a dedicated cache or control module for its corresponding second chip 30, independently undertaking the data temporary storage and processing tasks of its channel, avoiding delays caused by cross-channel data interaction. There are multiple first bumps on the fourth chip 50, and these bumps are connected to the pads of the third chips 40, forming an independent channel connection of "fourth chip 50 - third chip 40", avoiding signal crosstalk and ensuring independent and reliable data transmission in each channel.

[0070] As one possible implementation method, such as Figure 5 As shown, the semiconductor package structure also includes an eighth chip 90. The fourth chip 50 has a fifth through-hole 56 and a fifth through-silicon via 57. The eighth chip 90 is flip-chip mounted on the fourth chip 50, and the conductive pillars of the eighth chip 90 pass through the fifth through-hole 56 to be connected to the pads of a third chip 40. The bumps of the eighth chip 90 are connected to the pads of another third chip 40 through the fifth through-silicon via 57.

[0071] It should be noted that the semiconductor package structure also includes an eighth chip 90. The eighth chip 90 can be a data bridge chip or a dedicated coprocessor (such as a data exchange chip or an encryption acceleration chip) responsible for data transfer and collaborative processing between multiple independent third chips 40. The fourth chip 50 has a fifth through-hole 56 and a fifth through-silicon via 57. The eighth chip 90 is flip-chip mounted on the fourth chip 50, and the conductive pillars of the eighth chip 90 pass through the fifth through-hole 56 to connect with the pads of one third chip 40. The bumps of the eighth chip 90 are connected with the pads of another third chip 40 through the fifth through-silicon via 57, forming a direct cross-channel link of "one third chip 40 - eighth chip 90 - another third chip 40", which shortens the data interaction path between multiple third chips 40.

[0072] As one possible implementation method, such as Figure 6 As shown, the semiconductor packaging structure also includes multiple HBM stacked structures 120. Each HBM stacked structure includes a substrate die 121 and multiple stacked core dies 122. The substrate dies 121 of the multiple HBM stacked structures 120 are mounted on the fourth chip 50. The eighth chip 90 is provided with multiple sixth through-silicon vias 91. The core dies 122 of the multiple HBM stacked structures 120 on the side closest to the substrate die 121 are connected to the multiple substrate dies 121 through the multiple sixth through-silicon vias 91.

[0073] It should be noted that the semiconductor packaging structure also includes multiple HBM stacked structures 120. Each HBM stacked structure includes a substrate die 121 and multiple stacked core dies 122. The multiple stacked core dies 122 are interconnected through through-silicon vias and microbumps. For example, the fourth chip 50 has multiple placement slots 58. The number of placement slots 58 matches the number of HBM stacked structures. The depth of the placement slots 58 is at least equal to the thickness of the substrate die 121, ensuring that the top surface of the substrate die 121 does not protrude from the top surface of the fourth chip 50 (e.g., it is recessed or flush) after being properly mounted in the placement slots 58, thus improving stacking stability. In the HBM stacked structure, the core die 122, located near the substrate die 121, is connected to the substrate die 121 via the sixth through-silicon via 91 of the eighth chip 90, forming a vertical link of "core die 122 - sixth through-silicon via 91 - substrate die 121," enabling direct data transmission between layers. Multiple HBM stacked structures 120 are connected via the eighth chip 90 (bridge chip), ultimately connecting to the original chip to construct a full-link high-bandwidth network of "computation-cache-HBM." The parallel design of multiple HBM stacked structures 120 significantly increases the total bandwidth of the package. The placement slot 58 design allows the HBM stacked structure to be embedded within the fourth chip 50, resulting in a minimal increase in package thickness. This design saves more space than external HBM solutions and is suitable for high-density integration requirements.

[0074] As one possible implementation method, such as Figure 6 As shown, the top surface of the fourth chip 50 is provided with at least one third bonding wire 592, which extends toward the bottom surface of the eighth chip 90 and is spaced apart from the bottom surface of the eighth chip 90.

[0075] It should be noted that the top surface of the fourth chip 50 is provided with at least one third bonding wire 592 (e.g., 1 to 4). The third bonding wire 592 can be made of gold or copper wire with high conductivity and high thermal conductivity. One end of the wire is fixed to the pad on the top surface of the fourth chip 50 by a bonding process (e.g., ultrasonic bonding), and the other end extends toward the bottom surface of the eighth chip 90, so that the third bonding wire 592 is close to the bottom surface of the eighth chip 90 (e.g., the third bonding wire 592 extends vertically upward). Furthermore, the other end of the third bonding wire 592 is spaced apart from the bottom surface of the eighth chip 90 and will not come into contact with each other. For example, the top surface of the fourth chip 50 is provided with a fixing groove, and at least one third bonding wire 592 is disposed in the fixing groove.

[0076] The fourth chip 50 generates heat during operation. By setting a third bonding wire 592 on the top surface of the fourth chip 50, on the one hand, the third bonding wire 592 can improve the heat dissipation of the fourth chip 50. The space between the third bonding wire 592 and the bottom surface of the eighth chip 90 can accelerate airflow, carrying away the heat on the third bonding wire 592 and preventing heat from accumulating on the third bonding wire 592. On the other hand, if the potential of a chip is too high (such as the potential of the top surface of the fourth chip 50 being higher than the potential of the bottom surface of the eighth chip 90), the space between the third bonding wire 592 and the bottom surface of the eighth chip 90 can form an electric field coupling, causing the charge in the high potential area to slowly migrate to the low potential area, thereby achieving the same potential around the two chips (i.e., a small potential difference) and avoiding local static electricity accumulation.

[0077] As one possible implementation method, such as Figure 7 As shown, substrate 10, first chip 20, second chip 30, third chip 40 and fourth chip 50 form a packaging module 130. There are multiple packaging modules 130. A sixth through hole 92 is provided on the eighth chip 90. Multiple packaging modules 130 are stacked, and two adjacent packaging modules 130 are connected by solder balls 921 provided in the sixth through hole 92.

[0078] It should be noted that each package module 130 includes a substrate 10, a first chip 20 (computing core), a second chip 30 (control center), a third chip 40 (cache), and a fourth chip 50 (main storage), forming a complete "computing-storage-control" basic unit that can independently complete basic computing tasks. There are multiple package modules 130 (e.g., 2-4). A sixth via 92 is provided on the eighth chip 90. Multiple package modules 130 are stacked, and adjacent package modules 130 are connected by solder balls 921 located within the sixth via 92, forming a vertical interconnect link of "upper module - solder ball 921 - lower module." The system-level computing power increases linearly with the number of modules, saving more space than planar integration solutions and meeting high-density requirements.

[0079] As one possible implementation method, such as Figure 7 As shown, the top surface of the eighth chip 90 protrudes from the top surface of the plastic encapsulation body 110 of the lower packaging module 130. A second adhesive layer 140 with a cavity 141 is provided between two adjacent packaging modules 130. The second adhesive layer 140 fills the space between the sixth through hole 92 and the solder ball 921. The second adhesive layer 140 covers the side of the eighth chip 90 and the solder ball 921, and part of the top surface of the eighth chip 90 is exposed in the cavity 141 of the second adhesive layer 140.

[0080] It should be noted that the bottom surface of the eighth chip 90 is integrated inside the plastic package 110 of the lower packaging module 130, and the top surface of the eighth chip 90 protrudes from the top surface of the plastic package 110 of the lower packaging module 130. The specific height of the protrusion of the top surface of the eighth chip 90 needs to match the stacking gap between two adjacent packaging modules 130, so as to avoid excessive protrusion that would cause interference between the two adjacent packaging modules 130, and to ensure that the protruding part can fully contact the air, thereby improving the heat dissipation effect.

[0081] A second adhesive layer 140 with a cavity 141 is provided between two adjacent packaging modules 130. The second adhesive layer 140 fills the space between the sixth through-hole 92 and the solder ball 921 to improve the bonding force between the solder ball 921 and the eighth chip 90. The second adhesive layer 140 covers the sides of the eighth chip 90 and the solder ball 921. On the one hand, the second adhesive layer 140 covers and protects the connection between the sides of the eighth chip 90 and the molding compound 110 to prevent cracking at the connection point; on the other hand, it... The second adhesive layer 140 strengthens and supports the connection between the solder ball 921 and the eighth chip 90 and the upper packaging module 130, thereby effectively dispersing the stacking pressure on the solder ball 921 and preventing the solder ball 921 from breaking. In addition, part of the top surface of the eighth chip 90 is exposed in the cavity 141 inside the second adhesive layer 140, ensuring that part of the top surface of the eighth chip 90 is in full contact with the air in the cavity 141, preventing heat from accumulating at the connection between the solder ball 921 and the eighth chip 90 and the upper packaging module 130, thereby improving the heat dissipation effect.

[0082] In some embodiments, the gap between the sixth via 92 and the solder ball 921 can be filled separately by the second adhesive layer 140, which is simple to operate. In other embodiments, when the bottom surface of the eighth chip 90 is integrated into the molded body 110 of the lower packaging module 130, the gap between the sixth via 92 and the solder ball 921 near the bottom of the eighth chip 90 can be filled by the molded body 110. Then, when a second adhesive layer 140 with a cavity 141 is provided between two adjacent packaging modules 130, the gap between the sixth via 92 and the solder ball 921 near the top of the eighth chip 90 can be filled by the second adhesive layer 140. In the gap between the sixth via 92 and the solder ball 921, the lower molded body 110 and the upper second adhesive layer 140 form a connection. By complementing the characteristics of the molded body 110 and the second adhesive layer 140 (rigidity + flexibility), the reliability requirements of complex structures can be met. Both solutions can effectively fill the gap, prevent external moisture and contaminants from entering between the sixth through hole 92 and the solder ball 921, improve the bonding force between the solder ball 921 and the eighth chip 90, and prevent the solder ball 921 from breaking.

[0083] The second adhesive layer 140 can be made of a low thermal resistance, high adhesion epoxy thermally conductive adhesive to form a covering structure with different vertical projection shapes according to actual needs. It is only necessary that the second adhesive layer 140 has a cavity 141 inside to ensure that part of the top surface of the eighth chip 90 can be exposed in the cavity 141 inside the second adhesive layer 140. For example, when the number of solder balls 921 is four, the vertical projection shape of the second adhesive layer 140 can be a hollow ring; when the number of solder balls 921 is three, the vertical projection shape of the second adhesive layer 140 can be U-shaped; and when the number of solder balls 921 is two, the vertical projection shape of the second adhesive layer 140 can be bracket-shaped.

[0084] like Figures 1 to 4 As shown, in a second aspect of this application, a packaging method for a semiconductor packaging structure is provided for preparing the semiconductor packaging structure in the first embodiment described above. The method includes:

[0085] S1. Provide a substrate 10 having multiple wiring layers 11, and form a groove 12 on the substrate 10 by etching or laser grooving process;

[0086] S2. Provide a first chip 20, mount the first chip 20 into the groove 12 using a positive mounting process through an adhesive film layer, and bake to fix it;

[0087] S3. Provide a second chip 30, fix the second chip 30 onto the substrate 10 and the first chip 20 by flip-chip process through reflow soldering and baking, and form a first through hole 31 on the second chip 30 by laser or etching process.

[0088] S4. Provide a third chip 40, mount the third chip 40 onto the second chip 30 using a positive mounting process through an adhesive film layer, and bake to fix it;

[0089] S5. Provide a fourth chip 50, pass the conductive post of the fourth chip 50 through the first through hole 31 and solder it to the pad of the first chip 20, and solder the first bump of the fourth chip 50 to the pad of the third chip 40.

[0090] S6. A protective adhesive layer 100 is formed on the outer side of the first chip 20, the second chip 30 and the third chip 40 and on the bottom of the fourth chip 50 using a dispensing process.

[0091] S7. A molding compound 110 is formed on the outer side of the protective adhesive layer 100 and on the top of the fourth chip 50 using a molding process.

[0092] S8. Solder balls are formed at the bottom of substrate 10 using a ball-planting process;

[0093] S9. The product is cut into individual pieces using a cutting process.

[0094] It should be noted that the packaging method of the semiconductor package structure provided in this embodiment is the same as the specific structure of the semiconductor package structure described above. Those skilled in the art can deduce the packaging method of the semiconductor package structure based on the description of the specific structure of the semiconductor package structure described above, and this application will not repeat the description. Since the packaging method of the semiconductor package structure provided in this embodiment is used to prepare the above-described semiconductor package structure, the packaging method of this semiconductor package structure has the same beneficial effects as the above-described semiconductor package structure, and will not be described again here. Those skilled in the art should be able to reasonably deduce the preparation methods of the semiconductor package structures of other embodiments described above, and the packaging methods of the semiconductor package structures of other embodiments described above have the same beneficial effects as the semiconductor package structures of other embodiments described above, and will not be described again here.

[0095] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0096] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this application will not describe the various possible combinations separately.

Claims

1. A semiconductor package structure, comprising: The substrate with multiple wiring layers and the first chip, the second chip, the third chip and the fourth chip are stacked, a recess is formed on the substrate, the first chip is mounted on the substrate and located in the recess, the second chip is flip-chip mounted on the substrate and the first chip, the second chip bumps are connected with the wiring layer and the first chip pads, a first via hole is formed on the second chip, the third chip is mounted on the second chip, the fourth chip is flip-chip mounted on the second chip and the third chip, and the fourth chip conductive pillars are arranged in the first via hole to connect with the first chip pads, and the first bumps of the fourth chip are connected with the third chip pads.

2. The semiconductor package structure of claim 1, wherein, The diameter of the first via hole is greater than the diameter of the fourth chip conductive pillar, and the diameter of the first via hole is greater than the diameter of the first chip pad, a first adhesive layer is arranged between the first via hole and the fourth chip conductive pillar, and the first adhesive layer covers the fourth chip conductive pillar and the first chip pad.

3. The semiconductor package structure of claim 1, wherein, The top surface of the first chip is provided with at least one first wire, and the bottom surface of the fourth chip is provided with at least one second wire, the first wire and the second wire are arranged close to each other and spaced apart.

4. The semiconductor package structure of claim 1, wherein, Further comprising a protective adhesive layer and a plastic package, a second via hole is formed on the edge of the fourth chip, the protective adhesive layer covers the outer side of the first chip, the second chip and the third chip, and covers the bottom of the fourth chip through the second via hole, and the plastic package covers the outer side of the protective adhesive layer and the top of the fourth chip.

5. The semiconductor package structure of claim 1, wherein, The second chip is provided with a first through silicon via, and the second bumps of the fourth chip are connected with the wiring layer through the first through silicon via.

6. The semiconductor package structure of any one of claims 1 to 5, wherein, The number of the second chips is multiple, and the multiple second chips are arranged at intervals, the first via hole is formed on each of the second chips, and the number of the fourth chip conductive pillars is multiple, and the multiple fourth chip conductive pillars are arranged in the first via holes of the multiple second chips.

7. The semiconductor package structure of claim 6, wherein, The number of the third chips is one, and one third chip is arranged on the multiple second chips, the number of the first bumps of the fourth chip is multiple, and the multiple first bumps of the fourth chip are connected with the pads of one third chip. Or, the number of the third chips is multiple, and the multiple third chips are arranged on the multiple second chips, the number of the first bumps of the fourth chip is multiple, and the multiple first bumps of the fourth chip are connected with the pads of the multiple third chips.

8. The semiconductor package structure of claim 7, wherein, Further comprising a fifth chip, the fourth chip is provided with a second through silicon via, and the fifth chip is flip-chip mounted on the fourth chip, and the bumps of the fifth chip are connected with the third chip pads through the second through silicon via.

9. The semiconductor package structure of claim 7, wherein, The fourth chip is provided with a third through hole, a fourth through hole and a third through silicon hole, a sixth chip is flip-chip mounted on the fourth chip, and a conductive column of the sixth chip is arranged in the third through hole to be connected with a pad of the third chip, the sixth chip is provided with a fourth through silicon hole, and a seventh chip is flip-chip mounted on the fourth chip and the sixth chip, and a conductive column of the seventh chip is arranged in the fourth through hole to be connected with the pad of the third chip, a first bump of the seventh chip is connected with the fourth chip through the third through silicon hole, and a second bump of the seventh chip is connected with the sixth chip through the fourth through silicon hole.

10. The semiconductor package structure of claim 7, wherein, The fourth chip is provided with a fifth through hole and a fifth through silicon hole, an eighth chip is flip-chip mounted on the fourth chip, and a conductive column of the eighth chip is arranged in the fifth through hole to be connected with a pad of the third chip in correspondence, and a bump of the eighth chip is connected with a pad of another third chip in correspondence through the fifth through silicon hole.

11. The semiconductor package structure of claim 10, wherein, A plurality of HBM stack structures are further included, each of the HBM stack structures comprising a base die and a plurality of core dies stacked, the base dies of the plurality of HBM stack structures are surface mounted on the fourth chip, the eighth chip is provided with a plurality of sixth through silicon holes, and the core dies of the plurality of HBM stack structures on the side close to the base die are connected with the plurality of base dies through the plurality of sixth through silicon holes.

12. The semiconductor package structure of claim 11, wherein, The top surface of the fourth chip is provided with at least one third wire, the third wire extends towards the bottom surface of the eighth chip and is arranged in a spaced manner with the bottom surface of the eighth chip.

13. The semiconductor package structure of claim 10, wherein, The substrate, the first chip, the second chip, the third chip and the fourth chip form a packaging module, the number of the packaging modules is a plurality, the eighth chip is provided with a sixth through hole, the plurality of packaging modules are stacked, and two adjacent packaging modules are connected through a solder ball arranged in the sixth through hole.

14. The semiconductor package structure of claim 13, wherein, The top surface of the eighth chip protrudes from the top surface of the plastic package of the packaging module in the lower layer, a second glue layer with a cavity is arranged between two adjacent packaging modules, the second glue layer is filled between the sixth through hole and the solder ball, the second glue layer is wrapped on the side surface of the eighth chip and the outside of the solder ball, and part of the top surface of the eighth chip is exposed in the cavity of the second glue layer.

15. A packaging method of a semiconductor package structure, characterized by, A method for preparing the semiconductor packaging structure of any one of claims 1-14, the method comprising: providing a substrate with a plurality of wiring layers, and forming a groove on the substrate by etching or laser slotting process; providing a first chip, and surface mounting and fixing the first chip in the groove by surface mounting process; providing a second chip, and flip-chip mounting and fixing the second chip on the substrate and the first chip by flip-chip mounting process, and forming a first through hole on the second chip by laser or etching process; providing a third chip, and surface mounting and fixing the third chip on the second chip by surface mounting process; A fourth chip is provided, a conductive post of the fourth chip is passed through the first via and welded with the pad of the first chip, and a first bump of the fourth chip is welded with the pad of the third chip.

Images