Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate, a first dielectric layer, a first capacitor recess, a first electrode layer, a capacitor dielectric layer, a second dielectric layer and a second electrode layer. The substrate comprises a capacitor region. The first dielectric layer covers the capacitor region. The first capacitor recess is in the first dielectric layer of the capacitor region. The first electrode layer is filled in the first capacitor recess. The capacitor dielectric layer covers the first electrode layer. The second dielectric layer covers the capacitor dielectric layer. The second capacitor recess penetrates through the second dielectric layer, and the sidewall of the second capacitor recess is a first convex curved surface. The convex direction of the first convex curved surface is away from the inside of the second capacitor recess. The second electrode layer is filled in the second capacitor recess. The above scheme can reduce the risk of breakdown of the isolation capacitor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In high-voltage systems of integrated circuits, the most important thing is to protect the safety of maintenance personnel and end-users. The second most important thing is to achieve safe and reliable operation between high-voltage and low-voltage circuits. Electrical isolation solves these problems by isolating the high-voltage part from other low-voltage human-machine interface parts. At present, the most mature manufacturing process is to use isolation capacitors in the semiconductor structure for electrical isolation.

[0003] However, existing isolation capacitor designs suffer from the problem of isolation capacitor breakdown. Therefore, how to optimize the structure of isolation capacitors to reduce the risk of breakdown has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to optimize the structure of the isolation capacitor and reduce the risk of the isolation capacitor being broken down.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a capacitor region; a first dielectric layer covering the capacitor region; a first capacitor recess located within the first dielectric layer of the capacitor region; a first electrode layer filling the first capacitor recess; a capacitor dielectric layer covering the first electrode layer; a second dielectric layer covering the capacitor dielectric layer; a second capacitor recess penetrating the second dielectric layer, wherein the sidewall of the second capacitor recess has a first convex curved surface, the convex direction of the first convex curved surface being away from the interior of the second capacitor recess; and a second electrode layer filling the second capacitor recess.

[0006] Optionally, the projection of the second electrode layer onto the first dielectric layer is located within the projection of the first electrode layer onto the first dielectric layer.

[0007] Optionally, the semiconductor structure further includes: a protective layer covering the sidewall of the second recess of the capacitor; the protective layer material includes one or more of titanium nitride, tantalum nitride, samarium nitride, and zirconium nitride.

[0008] Optionally, the sidewall of the first groove of the capacitor is a second convex curved surface, and the convex direction of the second convex curved surface is away from the interior of the first groove of the capacitor.

[0009] Optionally, the semiconductor structure further includes: a redundant capacitor groove located in the capacitor dielectric layer at the bottom of the second capacitor groove, and the sidewall of the redundant capacitor groove presents a third convex curved surface, the convex direction of the third convex curved surface being away from the interior of the redundant capacitor groove; wherein, the bottom end face of the redundant capacitor groove is a plane and parallel to the substrate surface; the second electrode layer is further filled in the redundant capacitor groove.

[0010] Optionally, the projection of the redundant capacitor groove in the second dielectric layer is located within the projection of the second capacitor groove in the second dielectric layer.

[0011] Optionally, the semiconductor structure further includes: a redundant electrode layer located on the first electrode layer, wherein the two ends of the redundant electrode layer are connected by a fourth convex curved surface, the convex direction of the fourth convex curved surface is away from the surface of the substrate and away from the interior of the redundant electrode layer; the projection of the redundant electrode layer on the first dielectric layer is located within the projection of the first electrode layer on the first dielectric layer; wherein the top end face of the redundant electrode layer is a plane and parallel to the surface of the substrate; and the capacitor dielectric layer further covers the redundant electrode layer.

[0012] Optionally, the semiconductor structure further includes: a device region located on the substrate, wherein the first dielectric layer further covers the device region; a first device recess located in the first dielectric layer of the device region; a first metal layer filling the first device recess, wherein the capacitor dielectric layer further covers the first metal layer; a device connection recess located in the capacitor dielectric layer of the device region, wherein the bottom of the device connection recess exposes the first metal layer; and an interconnect metal layer filling the device connection recess.

[0013] Optionally, the semiconductor structure further includes: a second device recess located in the second dielectric layer of the device region, wherein the bottom of the second device recess exposes the interconnect metal layer; and a second metal layer filling the second device recess.

[0014] Optionally, the second groove sidewall of the device has a fifth convex curved surface, and the convex direction of the fifth convex curved surface is away from the interior of the second groove of the device.

[0015] Accordingly, this application also provides a method for forming a semiconductor structure, applied to any of the semiconductor structures described above, comprising: providing a substrate including a capacitor region; forming a first dielectric layer covering the capacitor region; forming a first capacitor groove in the first dielectric layer for the capacitor region; forming a first electrode layer filling the first capacitor groove; forming a capacitor dielectric layer covering the first electrode layer; forming a second dielectric layer covering the capacitor dielectric layer; forming a second capacitor groove penetrating the second dielectric layer, wherein the sidewall of the second capacitor groove presents a first convex curved surface, and the convex direction of the first convex curved surface is away from the interior of the second capacitor groove; and forming a second electrode layer filling the second capacitor groove.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0017] This invention provides a semiconductor structure, comprising: a substrate including a capacitor region; a first dielectric layer covering the capacitor region; a first capacitor recess located in the first dielectric layer of the capacitor region; a first electrode layer filling the first capacitor recess; a capacitor dielectric layer covering the first electrode layer; a second dielectric layer covering the capacitor dielectric layer; a second capacitor recess penetrating the second dielectric layer, wherein the sidewalls of the second capacitor recess have a first convex curved surface, and the convex direction of the first convex curved surface is away from the interior of the second capacitor recess; and a second electrode layer filling the second capacitor recess, wherein the shapes of the two ends of the second electrode layer also have a first convex curved surface, thereby reducing the risk of the isolation capacitor being broken down. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a semiconductor structure;

[0020] Figures 2 to 13 This is a cross-sectional structural schematic diagram of each step in the semiconductor structure formation method corresponding to the first embodiment of the semiconductor structure in this application;

[0021] Figures 14 to 16 This is a cross-sectional schematic diagram of each step in the semiconductor structure formation method corresponding to the second embodiment of the semiconductor structure in this application;

[0022] Figure 17 This is a schematic diagram of the semiconductor structure corresponding to the third embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] As is known from the background technology, isolation capacitors in semiconductor structures suffer from the problem of breakdown. The following section discusses this issue in conjunction with... Figure 1 The reasons for the breakdown of the isolation capacitor were analyzed.

[0025] refer to Figure 1 This is a schematic diagram of a semiconductor structure.

[0026] The semiconductor structure includes: a substrate 100, an isolation capacitor 101, and a semiconductor device 102; the isolation capacitor 101 includes a first capacitor electrode 103, a dielectric 104, and a second capacitor electrode 105.

[0027] The isolation capacitor 101 has the following problem:

[0028] First, the problem of isolation capacitor breakdown.

[0029] Because the isolation capacitor 101 has sharp corners at both ends, for example Figure 1 At the sharp corners between positions 106 and 109, charges can easily accumulate, such as static electricity, leading to the breakdown of the isolation capacitor.

[0030] Second, it affects the performance of semiconductor devices near the isolation capacitor.

[0031] Because the electric field intensity is relatively concentrated at the sharp corners of the first capacitor electrode 103 and the second capacitor electrode 105 of the isolation capacitor 101, it is easy to cause interference to the nearby semiconductor device 102, affecting the characteristics of the semiconductor device. Especially when the density of semiconductor devices on the substrate is getting higher and higher, the influence of the isolation capacitor 101 on the semiconductor device 102 becomes more and more prominent.

[0032] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure, comprising: a substrate including a capacitor region; a first dielectric layer covering the capacitor region; a first capacitor recess located within the first dielectric layer of the capacitor region; a first electrode layer filling the first capacitor recess; a capacitor dielectric layer covering the first electrode layer; a second dielectric layer covering the capacitor dielectric layer; a second capacitor recess penetrating the second dielectric layer, wherein the sidewall of the second capacitor recess has a first convex curved surface, the convex direction of the first convex curved surface being away from the interior of the second capacitor recess; and a second electrode layer filling the second capacitor recess.

[0033] By employing the above semiconductor structure, the shape of both ends of the second electrode layer of the isolation capacitor is designed as a first convex curved surface to reduce the probability of electric field and / or charge concentration at both ends of the second electrode layer of the isolation capacitor, thereby reducing the risk of the isolation capacitor being broken down.

[0034] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0035] First Embodiment

[0036] refer to Figure 13 This is a schematic diagram of the semiconductor structure corresponding to the first embodiment of this application.

[0037] The semiconductor structure includes: a substrate 200.

[0038] The substrate 200 is used to provide a process platform for the formation of semiconductor structures.

[0039] The substrate 200 includes a capacitor region 201 for forming an isolation capacitor for a semiconductor device.

[0040] In this embodiment, the substrate 200 is a silicon substrate 200, and the material of the substrate 200 is single-crystal silicon. In other embodiments, the material of the substrate 200 may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen nitride. The substrate 200 may also be other types of substrate 200, such as a silicon-on-insulator substrate 200 or a germanium-on-insulator substrate 200. In other embodiments, an epitaxial layer (not shown) with the same crystal structure as the substrate 200 may also be formed on the surface of the substrate 200 to improve the pattern transfer quality.

[0041] The semiconductor structure includes: a first dielectric layer 202 covering the capacitor region 201.

[0042] The first dielectric layer 202 has the following beneficial effects: First, it provides process space for the first electrode layer 206 of the isolation capacitor forming a semiconductor structure; Second, it provides a process basis for the shape of the end of the first electrode layer 206 of the isolation capacitor forming a semiconductor structure.

[0043] The material of the first dielectric layer 202 includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbide, silicon oxycarbonate, and silicon carbonitride. In this embodiment, the material of the first dielectric layer 202 is silicon nitride.

[0044] Continue to refer to Figure 13 , combined Figure 8 The semiconductor structure includes: a capacitor first groove 203 located in the first dielectric layer 202 of the capacitor region 201.

[0045] In this embodiment, the first groove 203 of the capacitor provides space for the first electrode layer 206 of the isolation capacitor forming a semiconductor structure.

[0046] In this embodiment, the sidewall of the first groove 203 of the capacitor presents a second convex curved surface 204. The convex direction of the second convex curved surface 204 is away from the interior of the first groove 203 of the capacitor, so that the shape of both ends of the first electrode layer 206 presents the second convex curved surface 204. This reduces the risk of electric field and / or charge accumulating at both ends of the first electrode layer 206, thereby reducing damage to semiconductor devices or interference with electrical performance and / or damage or destruction of isolation capacitors.

[0047] In this embodiment, the cross section of the second convex curved surface 204 along the direction perpendicular to the surface of the substrate 200 is a first sector, and the plane in which the first sector is located is parallel to the carrier movement direction of the semiconductor device. Furthermore, the line connecting the center of the arc length of the first sector and the center of the first sector is parallel to the surface of the substrate 200, which reduces the probability of sharp corners appearing at both ends of the first electrode, thereby reducing the risk of the isolation capacitor being damaged or destroyed, and / or the impact on the performance of the semiconductor device.

[0048] In this embodiment, the carrier movement direction of the semiconductor device is parallel to the surface of the substrate 200.

[0049] It should be noted that the central angle and arc length of the first sector are designed according to actual needs. In this embodiment, the central angle of the sector is 120 degrees, but this does not limit this application.

[0050] Continue to refer to Figure 13 , combined Figure 8 and Figure 9The semiconductor structure includes a protective layer (i.e., a first protective layer 205) covering the sidewall of the first recess 203 of the capacitor, which has the following beneficial effects:

[0051] First, the material used to reduce the diffusion of the first electrode layer 206 on the substrate 200 reduces the probability of the isolation capacitor affecting the performance of the semiconductor device. For example, the electric field at both ends of the isolation capacitor electrode interferes with the semiconductor device, or the coupling between the isolation capacitor electrode and the capacitance of the semiconductor device itself.

[0052] Second, to reduce the diffusion of the material of the first electrode layer 206 on the substrate 200, thereby reducing the probability of the external electric field affecting the capacitor isolation capacitor, in some embodiments, the protective layer also covers the bottom end face of the first groove 203 of the capacitor and is connected to the protective layer at the side wall of the first groove 203 of the capacitor. For example, a metal shielding layer is designed on the back of the substrate 200. The electric field of this metal shielding layer will affect the isolation effect of the capacitor isolation capacitor through the diffused first electrode layer 206.

[0053] Third, it is used to improve the contact characteristics between the first electrode layer 206 and the first dielectric layer 202.

[0054] Because when the first electrode layer 206 comes into contact with the first dielectric layer 202, there is a probability of poor adhesion, especially at the sidewall of the first groove 203 of the capacitor.

[0055] The protective layer material includes one or more of titanium nitride, tantalum nitride, samarium nitride, and zirconium nitride. In this embodiment, the protective layer material is titanium nitride.

[0056] Continue to refer to Figure 13 , combined Figure 8 and Figure 9 The semiconductor structure includes: a first electrode layer 206, which is filled in the first groove 203 of the capacitor.

[0057] The first electrode layer 206 is used to form the electrode of the isolation capacitor of the semiconductor device.

[0058] In this embodiment, the first electrode layer 206 fills the first groove 203 of the capacitor, and the upper surface of the first electrode layer 206 is flush with the upper surface of the first dielectric layer 202.

[0059] In this embodiment, the shapes of the two ends of the first electrode layer 206 present a second convex curved surface 204. For information about the second convex curved surface 204 presented at the two ends of the first electrode layer 206, please refer to the relevant description of the second convex curved surface 204 presented on the sidewall of the first groove 203 of the capacitor in the aforementioned semiconductor structure embodiment, which will not be repeated here.

[0060] The material of the first electrode layer 206 includes one or more of copper, tungsten, cobalt and ruthenium. In this embodiment, the material of the first electrode layer 206 is copper.

[0061] Continue to refer to Figure 13 The semiconductor structure includes a capacitor dielectric layer 207 covering the first electrode layer 206.

[0062] The capacitor dielectric layer 207 is used as the dielectric layer of the isolation capacitor.

[0063] The capacitor dielectric layer 207 is made of one or more of the following materials: silicon nitride, silicon oxide, silicon carbide, silicon carbide, silicon oxycarbonate, silicon oxynitride, and silicon carbonitride. In this embodiment, the capacitor dielectric layer 207 is made of silicon nitride.

[0064] Continue to refer to Figure 13 The semiconductor structure includes a second dielectric layer 208 covering the capacitor dielectric layer 207.

[0065] The second dielectric layer 208 has the following beneficial effects: first, it provides process space for forming the second electrode layer 211 of the isolation capacitor of the semiconductor device; second, it provides a process basis for the shape at the end of the second electrode layer 211 of the isolation capacitor of the semiconductor device.

[0066] The material of the second dielectric layer 208 includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbide, silicon oxycarbonate, silicon oxynitride, and silicon carbonitride. In this embodiment, the material of the second dielectric layer 208 is silicon nitride.

[0067] Continue to refer to Figure 13 , combined Figure 12 The semiconductor structure includes: a second recess 209 for capacitors, penetrating the second dielectric layer 208, and the sidewall of the second recess 209 for capacitors is a first convex surface 223, the convex direction of the first convex surface 223 being away from the interior of the second recess 209 for capacitors.

[0068] In this embodiment, the second groove 209 of the capacitor provides positional space for the second electrode layer 211 of the isolation capacitor of the semiconductor device.

[0069] In this embodiment, the second groove 209 of the capacitor penetrates the second dielectric layer 208, exposing the surface of the capacitor dielectric layer 207.

[0070] In this embodiment, the first convex curved surface 223 has a cross section perpendicular to the surface of the substrate 200 as a second sector, and the plane containing the second sector is parallel to the carrier movement direction of the semiconductor device. The line connecting the center of the arc length of the second sector and the center of the second sector is parallel to the surface of the substrate 200, which reduces the probability of sharp corners appearing at both ends of the second electrode, thereby reducing the risk of the isolation capacitor being damaged or destroyed, and / or the impact on the performance of the semiconductor device.

[0071] It should be noted that the central angle and arc length of the second sector are designed according to actual needs. In this embodiment, the central angle of the sector is 120 degrees, but this does not limit this application.

[0072] Continue to refer to Figure 13 The semiconductor structure includes a protective layer (i.e., a second protective layer 210) covering the sidewall of the second recess 209 of the capacitor, which has the following beneficial effects:

[0073] First, the material of the second electrode layer 211 is used to reduce diffusion on the substrate 200, thereby reducing the probability of the isolation capacitor affecting the formation of the semiconductor device, such as interference of the electric field of the isolation capacitor electrode on the semiconductor device, or capacitive coupling between the isolation capacitor and the semiconductor device.

[0074] Second, it is used to improve the contact characteristics between the second electrode layer 211 and the second dielectric layer 208.

[0075] Because there is a probability of poor adhesion when the second electrode layer 211 and the second dielectric layer 208 come into contact, especially at the sidewall of the second groove 209 of the capacitor.

[0076] The protective layer material includes one or more of titanium nitride, tantalum nitride, samarium nitride, and zirconium nitride. In this embodiment, the protective layer material is titanium nitride.

[0077] In this embodiment, the design parameters and manufacturing process parameters of the first protective layer 205 and the second protective layer 210 can be the same, such as thickness, material, and process parameters. In other embodiments, the design parameters and manufacturing process parameters of the first protective layer 205 and the second protective layer 210 can be selected as needed. For example, the protective layer may not be designed, and this does not limit this application.

[0078] Continue to refer to Figure 13 , combined Figure 12 The semiconductor structure includes a second electrode layer 211, which is filled in the second groove 209 of the capacitor.

[0079] The second electrode layer 211 is used to form the electrode of the isolation capacitor of the semiconductor device.

[0080] In this embodiment, the second electrode layer 211 fills the second groove 209 of the capacitor, and the upper surface of the second electrode layer 211 is flush with the upper surface of the second dielectric layer 208.

[0081] In this embodiment, the two ends of the second electrode layer 211 present a first convex curved surface 223.

[0082] For information regarding the shape of the first convex curved surface 223 at both ends of the second electrode layer 211, please refer to the description of the first convex curved surface 223 presented on the sidewall of the second groove 209 of the capacitor in the aforementioned semiconductor structure embodiment, which will not be repeated here.

[0083] The material of the second electrode layer 211 includes one or more of copper, tungsten, cobalt and ruthenium. In this embodiment, the material of the second electrode layer 211 is copper.

[0084] In this embodiment, the projection of the second electrode layer 211 onto the first dielectric layer 202 is located within the projection of the first electrode layer 206 onto the first dielectric layer 202, so that the area of ​​the first electrode layer 206 is greater than or equal to the area of ​​the second electrode layer 211, and the edge of the first electrode layer 206 is located outside the edge of the second electrode layer 211, which has the following beneficial effects:

[0085] First, the first electrode layer 206 can shield the semiconductor device from the influence of the second electrode layer 211.

[0086] Secondly, it can reduce the risk of changes in the size of the isolation capacitor caused by alignment deviations and / or etching deviations between the first electrode layer 206 and the second electrode layer 211.

[0087] Third, improve the uniformity of capacitance values ​​among the isolation capacitors on the substrate 200.

[0088] It should be noted that the distance between the edge of the first electrode layer 206 and the edge of the second electrode layer 211 can be set according to actual needs, and is not intended to limit this application.

[0089] In some embodiments, the thickness of the first electrode layer 206 is greater than the thickness of the second electrode layer 211, which has the following advantages:

[0090] First, it can improve the isolation capacitor's resistance to breakdown or damage;

[0091] Secondly, it can improve the mechanical strength of the isolation capacitor;

[0092] Third, it can enhance the shielding ability against external electromagnetic interference.

[0093] In some embodiments, the first electrode layer 206 and the second electrode layer 211 have equal thicknesses.

[0094] Continue to refer to Figure 13 The semiconductor structure includes a device region 212 located on the substrate 200.

[0095] The device region 212 is used to provide location space for the formation of semiconductor devices.

[0096] In this embodiment, the first dielectric layer 202 also covers the device region 212 to protect the channel layer, source and drain doped layers, etc. of the semiconductor device.

[0097] Continue to refer to Figure 13 , combined Figure 8 The semiconductor structure includes: a first device recess 213 located in the first dielectric layer 202 of the device region 212.

[0098] The first groove 213 of the device is used to provide positional space for the formation of the first metal layer 214.

[0099] Continue to refer to Figure 13 , combined Figure 9 The semiconductor structure includes a first metal layer 214, which is filled in the first groove 213 of the device.

[0100] The first metal layer 214 is used to connect the source and drain of the semiconductor device to an external circuit.

[0101] In this embodiment, the first metal layer 214 fills the first groove 213 of the device, and the upper surface of the first metal layer 214 is flush with the upper surface of the first dielectric layer 202.

[0102] The material of the first metal layer 214 includes one or more of copper, tungsten, cobalt and ruthenium. In this embodiment, the material of the first metal layer 214 is copper.

[0103] It should be noted that the shape of the sidewall of the first groove 213 of the device can be referred to the relevant description of the sidewall of the first groove 203 of the capacitor; the shape of the two ends of the first metal layer 214 can be referred to the relevant description of the shape of the two ends of the first electrode layer 206, and will not be repeated here.

[0104] Continue to refer to Figure 13 , combined Figure 10 In this embodiment, the capacitor dielectric layer 207 also covers the first metal layer 214.

[0105] Continue to refer to Figure 13 , combined Figure 9and Figure 10 The semiconductor structure includes: a device connection groove 215 located in the capacitor dielectric layer 207 of the device region 212, and the bottom of the device connection groove 215 exposes the first metal layer 214.

[0106] The device connection groove 215 is used to provide location space for forming the interconnect metal layer 216.

[0107] Continue to refer to Figure 13 , combined Figure 11 The semiconductor structure includes an interconnect metal layer 216, which fills the device connection groove 215.

[0108] The interconnect metal layer 216 is used to connect the source and drain of the semiconductor device to an external circuit.

[0109] The interconnect metal layer 216 is made of one or more of copper, tungsten, cobalt and ruthenium. In this embodiment, the interconnect metal layer 216 is made of copper.

[0110] Continue to refer to Figure 13 , combined Figure 11 and Figure 12 The semiconductor structure includes: a second device recess 217 located in the second dielectric layer 208 of the device region 212, wherein the bottom of the second device recess 217 exposes the interconnect metal layer 216.

[0111] In this embodiment, the second groove 217 of the device provides space for the formation of the second metal layer 218.

[0112] In this embodiment, the second groove 217 of the device penetrates the second dielectric layer 208 and exposes the surface of the interconnect metal layer 216.

[0113] In this embodiment, the sidewall of the second groove 217 of the device presents a fifth convex curved surface 224, and the convex direction of the fifth convex curved surface 224 is away from the interior of the second groove 217 of the device.

[0114] In this embodiment, the cross-section of the fifth convex curved surface 224 along the direction perpendicular to the surface of the substrate 200 is a sixth sector, and the plane in which the sixth sector is located is parallel to the carrier movement direction of the semiconductor device. Furthermore, the line connecting the center of the arc length of the sixth sector and the center of the sixth sector is parallel to the surface of the substrate 200, which reduces the probability of sharp corners appearing at both ends of the second metal layer, thereby reducing the risk of the isolation capacitor being damaged or destroyed, and / or the impact on the performance of the semiconductor device.

[0115] Continue to refer to Figure 13The semiconductor structure includes a second metal layer 218, which is filled in the second groove 217 of the device.

[0116] The second metal layer 218 is used to connect the source and drain of the semiconductor device to an external circuit via the first metal layer 214 and the interconnect metal layer 216.

[0117] The material of the second metal layer 218 includes one or more of copper, tungsten, cobalt and ruthenium. In this embodiment, the material of the second metal layer 218 is copper.

[0118] In this embodiment, the two ends of the second metal layer 218 present a fifth convex curved surface 224.

[0119] Regarding the shape of the second metal layer 218 at both ends forming a fifth convex curved surface 224, refer to the relevant description of the fifth convex curved surface 224 on the sidewall of the second groove 217 of the device.

[0120] Second Embodiment

[0121] refer to Figure 16 This is a schematic diagram of the structure corresponding to the second embodiment of the semiconductor structure in this application. Figure 16 Combination Figure 15 ,and Figure 13 A comparison reveals that the main difference between the second embodiment of the semiconductor structure and the first embodiment is that the second embodiment includes a redundant capacitor recess 219 and a redundant electrode layer 221. The redundant capacitor recess 219 and the redundant electrode layer 221 will be described in detail below.

[0122] refer to Figure 16 , combined Figure 15 In this embodiment, the semiconductor structure includes a redundant capacitor recess 219 located in the capacitor dielectric layer 207 at the bottom of the second capacitor recess 209.

[0123] In this embodiment, the sidewall of the redundant capacitor groove 219 presents a third convex curved surface 225. The protrusion direction of the third convex curved surface 225 is away from the interior of the redundant capacitor groove 219 and towards the surface of the substrate 200.

[0124] In this embodiment, the cross-section of the third convex curved surface 225 along the direction perpendicular to the surface of the substrate 200 is a third sector, and the plane in which the third sector is located is parallel to the carrier movement direction of the semiconductor device. The center of the third sector is located on the bottom surface of the second electrode layer 211 in the second groove 209 of the capacitor. This is beneficial for the two ends of the second electrode layer 211 in the redundant capacitor groove 219 to present the third convex curved surface 225, reducing the probability of sharp corners appearing at both ends of the second electrode layer 211 in the redundant capacitor groove 219, thereby reducing the risk of the isolation capacitor being damaged or destroyed, and / or the impact on the performance of the semiconductor device.

[0125] It should be noted that the central angle and arc length of the third sector are designed according to actual needs. In this embodiment, the central angle of the sector is 30 degrees, but this does not limit this application.

[0126] In this embodiment, the central angle of the third sector is smaller than that of the second sector, so that the edge 220 of the contact between the second electrode layer 211 in the redundant capacitor groove 219 and the second electrode layer 211 in the second capacitor groove 209 can be smoothly transitioned, thereby improving the film quality of the second electrode at the contact edge 220 and reducing the risk of the contact edge 220 breaking and producing a sharp corner.

[0127] In this embodiment, the second electrode layer 211 is also filled within the redundant capacitor groove 219, which has the following beneficial effects:

[0128] First, it is used to compensate for the losses of the isolation capacitor, for the following reasons:

[0129] When the shapes at both ends of the first electrode layer 206 form a second convex curved surface 204, and the shapes at both ends of the second electrode layer 211 form a first convex curved surface 223, the isolation capacitor becomes smaller, reducing the isolation capacitor's ability to resist damage or destruction, especially when the semiconductor device density on the substrate 200 increases.

[0130] Secondly, the second electrode layer 211 located within the redundant capacitor recess 219 increases the overall thickness of the second electrode layer 211 of the isolation capacitor, which has the following beneficial effects:

[0131] (I) It can improve the ability of isolation capacitors to resist breakdown or damage;

[0132] (II) It can improve the mechanical strength of the isolation capacitor;

[0133] (III) It can enhance the shielding ability against external electromagnetic interference.

[0134] In this embodiment, the bottom end face of the redundant capacitor groove 219 is a plane and parallel to the surface of the substrate 200, which is used to reduce the probability of a sharp point appearing at the bottom of the second electrode layer 211 located in the redundant capacitor groove 219, thereby reducing the probability of the isolation capacitor being broken down or damaged.

[0135] In this embodiment, the shape of the two ends of the second electrode layer 211 in the redundant capacitor groove 219 presents a third convex curved surface 225. For information about the third convex curved surface 225 presented at both ends of the second electrode layer 211 in the redundant capacitor groove 219, please refer to the relevant description of the third convex curved surface 225 presented on the sidewall of the redundant capacitor groove 219 in the aforementioned semiconductor structure embodiment, which will not be repeated here.

[0136] In this embodiment, the projection of the redundant capacitor groove 219 onto the second dielectric layer 208 is located within the projection of the second capacitor groove 209 onto the second dielectric layer 208. That is, the projection of the top end face of the redundant capacitor groove 219 onto the second dielectric layer 208 is located within the projection of the bottom end face of the second electrode layer 211 within the second capacitor groove 209. This makes the two ends of the second electrode layer 211 within the redundant capacitor groove 219 far away from the two ends of the second electrode layer 211 within the second capacitor groove 209, reducing the probability that the edge of the second electrode layer 211 within the redundant capacitor groove 219 extends beyond the edge of the second electrode layer 211 within the second capacitor groove 209, and improving the uniformity of the capacitance size of the isolation capacitor on the substrate 200.

[0137] It should be noted that the distance between the edge of the second electrode layer 211 in the redundant capacitor groove 219 and the edge of the second electrode layer 211 in the capacitor second groove 209 is set according to actual needs (such as not generating sharp corners, isolation capacitor compensation, etc.).

[0138] In this embodiment, the semiconductor structure includes a redundant electrode layer 221 located on the first electrode layer 206.

[0139] The beneficial effects of the redundant electrode layer 221 can be seen in the beneficial effects of the second electrode layer 211 in the redundant capacitor groove 219, which will not be elaborated here.

[0140] It should be noted that, when the isolation capacitor is destroyed, the redundant electrode layer 221 and the second electrode layer 211 in the redundant capacitor groove 219 are also used to short-circuit the first electrode layer 206 and the second electrode layer 211 to the same potential, thereby reducing the probability of the first electrode layer 206 and / or the second electrode layer 211 being suspended, and thus reducing the impact of the suspended first electrode layer 206 and / or the second electrode layer 211 on the semiconductor device.

[0141] In this embodiment, the redundant electrode layer 221 has a fourth convex curved surface 226 at both ends. The convex direction of the fourth convex curved surface 226 is away from the surface of the substrate 200 and away from the interior of the redundant electrode layer 221.

[0142] In this embodiment, the cross-section of the fourth convex curved surface 226 along the direction perpendicular to the surface of the substrate 200 is a fourth sector, and the plane in which the fourth sector is located is parallel to the carrier movement direction of the semiconductor device. The center of the fourth sector is located on the surface of the first electrode layer 206. This is beneficial for the redundant electrode layer 221 to present the fourth convex curved surface 226 at both ends, reducing the probability of sharp corners appearing at both ends of the redundant electrode layer 221, thereby reducing the risk of the isolation capacitor being damaged or destroyed, and / or the impact on the performance of the semiconductor device.

[0143] The redundant electrode layer 221 is made of one or more of copper, tungsten, cobalt and ruthenium. In this embodiment, the redundant electrode layer 221 is made of copper.

[0144] In this embodiment, the projection of the redundant electrode layer 221 onto the first dielectric layer 202 is located within the projection of the first electrode layer 206 onto the first dielectric layer 202. That is, the projection of the redundant electrode layer 221 onto the first dielectric layer 202 is located within the projection of the top end face of the first electrode layer 206 onto the first dielectric layer 202. This arrangement, where the two ends of the redundant electrode layer 221 are far from the two ends of the first electrode layer 206, has the following beneficial effects: First, it reduces the risk of the isolation capacitor being damaged or destroyed, and / or the impact on the performance of the semiconductor device. Second, it blocks the diffusion of the material of the redundant electrode layer 221 at its two ends, thereby reducing the risk of the isolation capacitor being damaged or destroyed, and / or the impact on the performance of the semiconductor device.

[0145] In this embodiment, the top end face of the redundant electrode layer 221 is a plane and parallel to the surface of the substrate 200; the top end face of the first electrode layer 206 is parallel to the surface of the substrate 200.

[0146] In this embodiment, the capacitor dielectric layer 207 also covers the redundant electrode layer 221.

[0147] It should be noted that, in some embodiments, the protective layer covers the fourth convex curved surface 226 at both ends of the redundant electrode layer 221 and the top end face of the redundant electrode layer 221, which can reduce the breakdown and destruction of the isolation capacitor.

[0148] Third Embodiment

[0149] refer to Figure 17This is a schematic diagram of the structure corresponding to the third embodiment of the semiconductor structure in this application. Figure 17 and Figure 13 A comparison reveals that the main difference between the third embodiment of the semiconductor structure in this application and the first embodiment is that the third embodiment includes a filling layer 222. The filling layer 222 will be described in detail below.

[0150] The semiconductor structure further includes a filling layer 222 covering the sidewall of the first groove 203 of the capacitor.

[0151] The filling layer 222 has the following beneficial effects: it reduces the probability of sharp points appearing in the first protective layer 205 and / or the first electrode layer 206 at the sidewall of the first groove 203 of the capacitor, for the following reasons:

[0152] When etching to form the sidewall of the first groove 203 of the capacitor, there is a probability that holes or protrusions will form on the sidewall of the first groove 203 of the capacitor, which may cause the first protective layer 205 and / or the first electrode layer 206 to form sharp points on the sidewall of the first groove 203 of the capacitor, increasing the risk that the isolation capacitor will be damaged or destroyed.

[0153] In this embodiment, the filling layer 222 covers the sidewall of the first groove 203 of the capacitor, and the first protective layer 205 covers the filling layer 222.

[0154] In this embodiment, the filling layer 222 also covers the sidewall of the second groove 209 of the capacitor.

[0155] The filling layer 222 has the following beneficial effects: it reduces the probability of sharp points appearing in the second protective layer 210 and / or the second electrode layer 211 at the sidewall of the second groove 209 of the capacitor, for the following reasons:

[0156] When etching to form the sidewall of the second groove 209 of the capacitor, there is a probability that holes or protrusions will form on the sidewall of the second groove 209 of the capacitor, which may cause the second protective layer 210 and / or the second electrode layer 211 to form sharp points on the sidewall of the second groove 209 of the capacitor, thereby increasing the risk of the isolation capacitor being damaged or destroyed.

[0157] In this embodiment, the filling layer 222 covers the sidewall of the second groove 209 of the capacitor, and the second protective layer 210 covers the filling layer 222.

[0158] It should be noted that, according to actual needs, the redundant capacitor recess 219, the first device recess 213, the first via 309, and the second via 312 (e.g.) Figure 6 As shown), the third via 315 (as shown) Figure 7(As shown) and the filling layer 222 is covered by the sidewall of the second groove 217 of the device.

[0159] Accordingly, this application also provides an electronic device comprising the above-described semiconductor structure.

[0160] Accordingly, this application also provides a method for forming the corresponding semi-structure.

[0161] refer to Figures 2 to 13 This is a cross-sectional schematic diagram of each step in the semiconductor structure formation method corresponding to the first embodiment of the semiconductor structure in this application.

[0162] refer to Figure 2 Provides a base of 200.

[0163] The substrate 200 is used to provide a process platform for the formation of semiconductor structures.

[0164] The substrate 200 includes a capacitor region 201 for forming an isolation capacitor for a semiconductor device.

[0165] In this embodiment, the substrate 200 is a silicon substrate 200, and the material of the substrate 200 is single-crystal silicon. In other embodiments, the material of the substrate 200 may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen nitride. The substrate 200 may also be other types of substrate 200, such as a silicon-on-insulator substrate 200 or a germanium-on-insulator substrate 200. In other embodiments, an epitaxial layer (not shown) with the same crystal structure as the substrate 200 may also be formed on the surface of the substrate 200 to improve the pattern transfer quality.

[0166] refer to Figure 3 This forms an isolation trench 300 located on the substrate 200.

[0167] The isolation trench 300 is used for electrical isolation between semiconductor devices.

[0168] In this embodiment, an isolation trench 300 is formed on the substrate 200 by an etching process;

[0169] An isolation medium layer 301 is formed within the isolation trench 300;

[0170] The material of the isolation dielectric layer 301 includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbide, silicon oxynitride, and silicon carbonitride. In this embodiment, the material of the isolation dielectric layer 301 is silicon nitride.

[0171] In this embodiment, an isolation medium layer 301 is formed in the isolation trench 300 by chemical vapor deposition and chemical mechanical polishing processes.

[0172] N-type wells 302 and / or P-type wells 303 are formed between the isolation trenches 300. In this embodiment, the N-type wells 302 and P-type wells 303 are formed between the isolation trenches 300 by ion implantation or doping processes.

[0173] refer to Figure 4 A gate oxide layer 304 is formed on or inside the N-type well 302 and the P-type well 303.

[0174] The gate oxide layer 304 is used to form the gate oxide layer of a semiconductor device.

[0175] The gate oxide layer 304 is made of silicon oxide and a high-k dielectric material. In this embodiment, the gate oxide layer 304 is made of silicon oxide.

[0176] In this embodiment, a gate oxide layer 304 is formed on the N-type well 302 and the P-type well 303 by a thermal oxidation process.

[0177] A gate layer 305 is formed on the gate oxide layer 304. In this embodiment, the material of the gate layer 305 includes polysilicon.

[0178] In this embodiment, the gate layer 305 is formed on the substrate 200 by chemical vapor deposition.

[0179] A sidewall layer 306 is formed on the sidewalls of the gate oxide layer 304 and the gate layer 305.

[0180] The material of the sidewall layer 306 includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbide, silicon oxycarbonate, and silicon carbonitride. In this embodiment, the material of the sidewall layer 306 is silicon oxide.

[0181] In this embodiment, a sidewall layer 306 is formed on the sidewalls of the gate oxide layer 304 and the gate layer 305 by chemical vapor deposition.

[0182] The source / drain doped layer 307 is formed.

[0183] In this embodiment, the source / drain doped layer 307 is formed through a doping process.

[0184] refer to Figure 5 , forming an interlayer dielectric layer 308.

[0185] The interlayer dielectric layer 308 serves to provide electrical isolation, mechanical support (e.g., stress buffering, planarization), and thermal management (e.g., heat dissipation, thermal expansion matching).

[0186] The material of the interlayer dielectric layer 308 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 308 is silicon oxide.

[0187] In this embodiment, an interlayer dielectric layer 308 is formed on the substrate 200 by chemical vapor deposition.

[0188] A first via 309 is formed on the interlayer dielectric layer 308 by an etching process. The first via 309 exposes the source / drain doped layer 307 and the gate layer 305.

[0189] It should be noted that, for the sake of brevity, the accompanying diagrams are provided. Figure 5 The first via 309, which does not fully expose all the source / drain doped layers 307 and gate layer 305, can be configured according to actual needs by those skilled in the art.

[0190] A first connecting layer 310 is formed within the first via 309 using a damascus process.

[0191] The materials of the first connecting layer 310 include copper, tungsten, cobalt and ruthenium. In this embodiment, the material of the first connecting layer 310 is copper.

[0192] The first connection layer 310 is used to connect the source / drain doped layer 307 to an external circuit.

[0193] refer to Figure 6 A first insulating layer 311 is formed on the substrate 200.

[0194] The material of the first insulating layer 311 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, and silicon carbonitride. In this embodiment, the material of the first insulating layer 311 is silicon oxide.

[0195] In this embodiment, a first insulating layer 311 is formed on the substrate 200 by chemical vapor deposition.

[0196] A second via 312 is formed on the first insulating layer 311 by an etching process, and the second via 312 exposes the first interconnect layer 310.

[0197] The second connecting layer 313 is filled into the second via 312 using the damascus process.

[0198] The materials of the second connecting layer 313 include copper, tungsten, cobalt and ruthenium. In this embodiment, the material of the second connecting layer 313 is copper.

[0199] The second connection layer 313 is connected to the first connection layer 310 and is used to connect the source / drain doping layer to an external circuit.

[0200] refer to Figure 7 A second insulating layer 314 is formed on the substrate 200.

[0201] The material of the second insulating layer 314 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, and silicon carbonitride. In this embodiment, the material of the second insulating layer 314 is silicon oxide.

[0202] In this embodiment, a second insulating layer 314 is formed on the substrate 200 by chemical vapor deposition.

[0203] A third via 315 is formed on the second insulating layer 314 by an etching process, and the third via 315 exposes the second interconnecting layer 313.

[0204] Continue to refer to Figure 7 The third connecting layer 316 is filled in the third through hole 315.

[0205] The third connection layer 316 is connected to the second connection layer 313 and is used to connect the source / drain doping layer to an external circuit.

[0206] The materials of the third connecting layer 316 include copper, tungsten, cobalt and ruthenium. In this embodiment, the material of the third connecting layer 316 is copper.

[0207] A third connecting layer 316 is formed by filling the third through-hole 315 using the damascus process.

[0208] It should be noted that in other embodiments, the process can be repeated as needed. Figure 7 The corresponding process steps.

[0209] refer to Figure 8 A first dielectric layer 202 is formed covering the capacitor region 201.

[0210] The first dielectric layer 202 has the following beneficial effects: first, it provides process space for the first electrode layer 206 of the isolation capacitor of the semiconductor device; second, it provides a process basis for the sidewall shape of the first electrode layer 206 of the isolation capacitor of the semiconductor device.

[0211] The material of the first dielectric layer 202 includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbide, silicon oxycarbonate, and silicon carbonitride. In this embodiment, the material of the first dielectric layer 202 is silicon nitride.

[0212] In this embodiment, a first dielectric layer 202 covering the capacitor region 201 is formed on the substrate 200 by a chemical vapor deposition process.

[0213] Continue to refer to Figure 8 A capacitor first groove 203 of the capacitor region 201 is formed in the first dielectric layer 202.

[0214] In this embodiment, the first dielectric layer 202 is formed by an exposure, development and etching process to form the first capacitor groove 203 of the capacitor region 201.

[0215] For a description of the first groove 203 of the capacitor, please refer to the description of the first groove 203 of the capacitor in the aforementioned semiconductor structure embodiment, which will not be repeated here.

[0216] In this embodiment, during the step of forming the capacitor first groove 203, a device first groove 213 located in the device region 212 is also formed, and the sidewall of the device first groove 213 presents a second convex curved surface 204.

[0217] For a description of the second convex curved surface 204 on the sidewall of the first groove 213 of the device, please refer to the description of the second convex curved surface 204 on the sidewall of the first groove 203 of the capacitor in the aforementioned semiconductor structure embodiment, which will not be repeated here.

[0218] The etching process includes dry etching and wet etching, or a combination of dry etching and wet etching. In this embodiment, the etching process is a dry etching process.

[0219] refer to Figure 9 This forms a first electrode layer 206 that fills the first groove 203 of the capacitor.

[0220] The first electrode layer 206 is used to form the electrode of the isolation capacitor of the semiconductor device.

[0221] The material of the first electrode layer 206 includes one or more of copper, tungsten, cobalt and ruthenium. In this embodiment, the material of the first electrode layer 206 is copper.

[0222] In this embodiment, the step of forming the first electrode layer 206 that fills the first groove 203 of the capacitor includes:

[0223] A first electrode layer 206 is formed by using the damascus process to fill the first groove 203 of the capacitor. The first electrode layer 206 is also filled in the first groove 213 of the device, that is, a first metal layer 214 is formed in the first groove 213 of the device.

[0224] The first electrode layer 206 (i.e., the first metal layer 214) filled in the first groove 213 of the device is connected to the third connection layer 316 and is used to connect the source and drain doping layer to the external circuit.

[0225] For information regarding the first electrode layer 206, please refer to the description of the first electrode layer 206 in the aforementioned semiconductor structure embodiments, which will not be repeated here.

[0226] Continue to refer to Figure 9 , combined Figure 8 After forming the first groove 203 of the capacitor and before forming the first electrode layer 206, the forming method further includes: forming a protective layer (i.e., a first protective layer 205) covering the sidewall of the first groove 203 of the capacitor.

[0227] The protective layer material includes one or more of titanium nitride, tantalum nitride, samarium nitride, and zirconium nitride. In this embodiment, the protective layer material is titanium nitride.

[0228] In this embodiment, the process of forming a protective layer (i.e., the first protective layer 205) covering the sidewall of the first recess 203 of the capacitor includes:

[0229] The first protective material layer is formed on the substrate 200 using an atomic layer deposition process. This first protective material layer covers the surface of the first dielectric layer 202, as well as the sidewalls and bottom of the first recess 203 of the capacitor. In other embodiments, chemical vapor deposition or physical vapor deposition processes can be used to form the first protective material layer on the substrate 200.

[0230] The first protective material layer is formed by using processes such as exposure, development, and etching to form a protective layer (i.e., the first protective layer 205) covering the sidewall of the first groove 203 of the capacitor. In other embodiments, the first protective layer 205 also covers the bottom end face of the first groove 203 of the capacitor.

[0231] For information regarding the first protective layer 205, please refer to the description of the first protective layer 205 in the aforementioned semiconductor structure embodiments, which will not be repeated here.

[0232] It should be noted that, in some embodiments, during the step of forming a protective layer covering the sidewall of the first recess 203 of the capacitor, the protective layer may also cover the sidewall of the first recess 213 of the device.

[0233] refer to Figure 10 A capacitor dielectric layer 207 is formed covering the first electrode layer 206.

[0234] The capacitor dielectric layer 207 is used as the dielectric layer of the isolation capacitor.

[0235] The capacitor dielectric layer 207 is made of one or more of the following materials: silicon nitride, silicon oxide, silicon carbide, silicon carbide, silicon oxycarbonate, silicon oxynitride, and silicon carbonitride. In this embodiment, the capacitor dielectric layer 207 is made of silicon nitride.

[0236] In this embodiment, a capacitor dielectric layer 207 covering the capacitor region 201 is formed on the substrate 200 by a chemical vapor deposition process.

[0237] In this embodiment, the capacitor dielectric layer 207 also covers the device region 212.

[0238] Continue to refer to Figure 10 A device connection groove 215 is formed that penetrates the capacitor dielectric layer 207 of the device region 212.

[0239] In this embodiment, a device connection groove 215 is formed through the capacitor dielectric layer 207 of the device region 212 by processes such as exposure, development and etching. The device connection groove 215 exposes the first metal layer 214 in the first device groove 213 of the device region 212.

[0240] refer to Figure 11 An interconnect metal layer 216 is formed to fill the device connection groove 215.

[0241] The interconnect metal layer 216 is connected to the first metal layer 214 and is used to connect the source / drain doping layer to an external circuit.

[0242] The interconnect metal layer 216 is made of one or more of copper, tungsten, cobalt and ruthenium. In this embodiment, the interconnect metal layer 216 is made of copper.

[0243] An interconnecting metal layer 216 is filled into the device connection groove 215 using a damascus process.

[0244] refer to Figure 12 A second dielectric layer 208 is formed covering the capacitor dielectric layer 207.

[0245] The second dielectric layer 208 has the following advantages: First, it provides process space for forming the second electrode layer 211 of the isolation capacitor in the semiconductor device. Second, it provides a process basis for the sidewall shape of the second electrode layer 211 of the isolation capacitor in the semiconductor device.

[0246] The material of the second dielectric layer 208 includes one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbide, silicon oxynitride, and silicon carbonitride. In this embodiment, the material of the second dielectric layer 208 is silicon nitride. In this embodiment, the second dielectric layer 208 covering the capacitor dielectric layer 207 is formed on the substrate 200 by a chemical vapor deposition process.

[0247] For information regarding the second dielectric layer 208, please refer to the description of the second dielectric layer 208 in the aforementioned semiconductor structure embodiments, which will not be repeated here.

[0248] Continue to refer to Figure 12 This forms a second recess 209 for the capacitor that penetrates the second dielectric layer 208.

[0249] In this embodiment, the second dielectric layer 208 is formed by an exposure, development and etching process to create the second capacitor groove 209 in the capacitor region 201.

[0250] In this example, the sidewall of the second groove 209 of the capacitor presents a first convex curved surface 223, and the convex direction of the first convex curved surface 223 is away from the interior of the second groove 209 of the capacitor.

[0251] For information regarding the second groove 209 of the capacitor, please refer to the description of the second groove 209 of the capacitor in the aforementioned semiconductor structure embodiment, which will not be repeated here.

[0252] In this embodiment, during the step of forming the capacitor second groove 209 that penetrates the second dielectric layer 208, a device second groove 217 located in the device region 212 is also formed, and the device second groove 217 exposes the interconnect metal layer 216.

[0253] In this embodiment, the sidewall of the second groove 217 of the device presents a first convex curved surface 223.

[0254] For information regarding the first convex curved surface 223 on the sidewall of the second groove 217 of the device, please refer to the description of the first convex curved surface 223 on the sidewall of the second groove 209 of the capacitor in the aforementioned semiconductor structure embodiment, which will not be repeated here.

[0255] The etching process includes dry etching and wet etching, or a combination of dry etching and wet etching. In this embodiment, the etching process is a dry etching process.

[0256] refer to Figure 13 This forms a second electrode layer 211 that fills the second groove 209 of the capacitor.

[0257] The second electrode layer 211 is used to form the electrode of the isolation capacitor of the semiconductor device.

[0258] The material of the second electrode layer 211 includes one or more of copper, tungsten, cobalt and ruthenium. In this embodiment, the material of the second electrode layer 211 is copper.

[0259] In this embodiment, the step of forming the second electrode layer 211 that fills the second groove 209 of the capacitor includes:

[0260] A second electrode layer 211 is formed by using a damascus process to fill the second groove 209 of the capacitor.

[0261] In this embodiment, during the step of forming the second electrode layer 211 that fills the second groove 209 of the capacitor, the second electrode layer 211 is also formed to fill the second groove 217 of the device, that is, the second metal layer 218 is filled in the second groove 217 of the device.

[0262] For information regarding the second metal layer 218, please refer to the description of the second metal layer 218 in the aforementioned semiconductor structure embodiments, which will not be repeated here.

[0263] For information regarding the second electrode layer 211, please refer to the description of the second electrode layer 211 in the aforementioned semiconductor structure embodiments, which will not be repeated here.

[0264] Continue to refer to Figure 13 After forming the second groove 209 of the capacitor and before forming the second electrode layer 211, the forming method further includes: forming a protective layer (i.e., a second protective layer 210) covering the sidewall of the second groove 209 of the capacitor.

[0265] The protective layer material includes one or more of titanium nitride, tantalum nitride, samarium nitride, and zirconium nitride. In this embodiment, the protective layer material is titanium nitride.

[0266] In this embodiment, the process of forming a protective layer (i.e., the second protective layer 210) covering the sidewall of the second recess 209 of the capacitor includes:

[0267] The second protective material layer is formed on the substrate 200 using an atomic layer deposition process. This second protective material layer covers the surface of the second dielectric layer 208, as well as the sidewalls and bottom of the second recess 209 of the capacitor. In other embodiments, chemical vapor deposition or physical vapor deposition processes can be used to form the second protective material layer on the substrate 200.

[0268] The second protective material layer is formed by using processes such as exposure, development, and etching to form a protective layer (i.e., the second protective layer 210) covering the sidewalls and bottom of the second groove 209 of the capacitor.

[0269] In this embodiment, in the step of forming a protective layer (i.e., the second protective layer 210) covering the sidewall of the second recess 209 of the capacitor, the protective layer (i.e., the second protective layer 210) also covers the sidewall of the second recess 217 of the device.

[0270] For information regarding the second protective layer 210, please refer to the description of the second protective layer 210 in the aforementioned semiconductor structure embodiments, which will not be repeated here.

[0271] It should be noted that, according to actual needs, a protective layer is covered on the sidewalls and / or bottom of the capacitor first groove 203, capacitor second groove 209, redundant capacitor groove 219, device first groove 213, first via 309, second via 312, third via 315 and device second groove 217.

[0272] refer to Figures 14 to 16 This is a cross-sectional structural schematic diagram of each step in the semiconductor structure formation method corresponding to the second embodiment of the semiconductor structure in this application.

[0273] Will Figure 16 Combination Figure 15 ,and Figure 13 A comparison reveals that the main difference between the second embodiment of the semiconductor structure and the first embodiment is that the second embodiment includes a redundant capacitor recess 219 and a redundant electrode layer 221. The following describes in detail the methods for forming the redundant capacitor recess 219 and the redundant electrode layer 221.

[0274] refer to Figure 14 A redundant electrode layer 221 is formed on the first electrode layer 206.

[0275] In this embodiment, a redundant electrode material layer is formed on the substrate 200 by physical vapor deposition.

[0276] The redundant electrode material layer is formed by using processes such as exposure, development, and etching to form a redundant electrode layer 221 located on the first electrode layer 206.

[0277] For information regarding the redundant electrode layer 221, please refer to the description of the redundant electrode layer 221 in the foregoing embodiments, which will not be repeated here.

[0278] refer to Figure 15 This forms redundant capacitor recesses 219 located in the capacitor dielectric layer 207.

[0279] In this embodiment, after forming the second capacitor groove 209 and before forming the second electrode layer 211, a redundant capacitor groove 219 is formed in the capacitor dielectric layer 207 located at the bottom of the second capacitor groove 209 by processes such as exposure, development and etching. The redundant capacitor groove 219 and the second capacitor groove 209 are connected through each other in a direction perpendicular to the surface of the substrate 200.

[0280] For information regarding the redundant capacitor recess 219, please refer to the description of the redundant capacitor recess 219 in the foregoing embodiments, which will not be repeated here.

[0281] refer to Figure 16 This forms a second electrode layer 211 that fills the redundant capacitor groove 219.

[0282] In this embodiment, a second electrode layer 211 is formed by using a damascus process to fill the second groove 209 of the capacitor and the groove 219 of the redundant capacitor.

[0283] For information regarding the second electrode layer 211 in the redundant capacitor recess 219 and the second electrode layer 211 in the capacitor second recess 209, please refer to the relevant description of the second electrode layer 211 in the aforementioned semiconductor structure embodiments, which will not be repeated here.

[0284] It should be noted that the methods for forming other film layers corresponding to the second embodiment of the semiconductor structure of this application can be derived by those skilled in the art based on the methods for forming film layers corresponding to the first embodiment of the semiconductor structure of this application, and will not be elaborated here.

[0285] It should be noted that the method for forming the semiconductor structure corresponding to the third embodiment of this application can be derived by those skilled in the art based on the method for forming the semiconductor structure corresponding to the first embodiment of this application, and will not be elaborated here.

[0286] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes, modifications and combinations of the technical solutions of the present invention by using the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: The substrate, including the capacitor region; A first dielectric layer covers the capacitor region; The first groove of the capacitor is located in the first dielectric layer of the capacitor region; The first electrode layer fills the first groove of the capacitor; A capacitor dielectric layer covers the first electrode layer; A second dielectric layer covers the capacitor dielectric layer; The capacitor has a second groove that penetrates the second dielectric layer, and the sidewall of the capacitor has a first convex curved surface, the convex direction of which is away from the interior of the capacitor's second groove. The second electrode layer fills the second groove of the capacitor; The semiconductor structure further includes: a redundant capacitor groove located in the capacitor dielectric layer at the bottom of the second capacitor groove, wherein the sidewall of the redundant capacitor groove presents a third convex curved surface, and the convex direction of the third convex curved surface is away from the interior of the redundant capacitor groove; wherein the bottom end face of the redundant capacitor groove is a plane and parallel to the substrate surface; and a second electrode layer is further filled in the redundant capacitor groove. A redundant electrode layer is located on the first electrode layer; the top end face of the redundant electrode layer is planar and parallel to the substrate surface; the capacitor dielectric layer also covers the redundant electrode layer; The cross-section of the third convex curved surface is a third sector, and the center of the circle is located on the bottom surface of the second electrode layer; The cross-section of the first convex curved surface is a second sector, and the line connecting the center of the arc length of the second sector and the center of the circle is parallel to the surface of the base.

2. The semiconductor structure as described in claim 1, characterized in that, The projection of the second electrode layer onto the first dielectric layer is located within the projection of the first electrode layer onto the first dielectric layer.

3. The semiconductor structure as described in claim 1, characterized in that, Also includes: A protective layer covers the sidewall of the second recess of the capacitor; The protective layer material includes one or more of titanium nitride, tantalum nitride, samarium nitride, and zirconium nitride.

4. The semiconductor structure as described in claim 1, characterized in that, The sidewall of the first groove of the capacitor is a second convex curved surface, and the convex direction of the second convex curved surface is away from the interior of the first groove of the capacitor.

5. The semiconductor structure as described in claim 1, characterized in that, The projection of the redundant capacitor groove in the second dielectric layer is located within the projection of the second capacitor groove in the second dielectric layer.

6. The semiconductor structure as described in claim 1, characterized in that, Also includes: The redundant electrode layer is connected at both ends by a fourth convex curved surface, and the convex direction of the fourth convex curved surface is away from the surface of the substrate and away from the interior of the redundant electrode layer. The projection of the redundant electrode layer onto the first dielectric layer is located within the projection of the first electrode layer onto the first dielectric layer. The top end face of the redundant electrode layer is planar and parallel to the substrate surface; The capacitor dielectric layer also covers the redundant electrode layer.

7. The semiconductor structure as described in claim 1, characterized in that, Also includes: The device region is located on the substrate, and the first dielectric layer also covers the device region; The first recess of the device is located in the first dielectric layer of the device region; A first metal layer is filled in the first groove of the device, and the capacitor dielectric layer also covers the first metal layer; A device connection groove is located in the capacitor dielectric layer of the device region, and the bottom of the device connection groove exposes the first metal layer; An interconnecting metal layer is filled within the device connection groove.

8. The semiconductor structure as described in claim 7, characterized in that, Also includes: The second device recess is located in the second dielectric layer of the device region, and the bottom of the second device recess exposes the interconnect metal layer. A second metal layer is filled in the second groove of the device.

9. The semiconductor structure as described in claim 8, characterized in that, The second groove sidewall of the device presents a fifth convex curved surface, and the convex direction of the fifth convex curved surface is away from the interior of the second groove of the device.

10. A method for forming a semiconductor structure, characterized in that, include: Provide a substrate, including the capacitance region; A first dielectric layer is formed to cover the capacitor region; A first capacitor groove of the capacitor region is formed in the first dielectric layer; A first electrode layer is formed to fill the first groove of the capacitor; A capacitor dielectric layer covering the first electrode layer is formed; A second dielectric layer is formed to cover the capacitor dielectric layer; A second recess for a capacitor is formed that penetrates the second dielectric layer, and the sidewall of the second recess for a capacitor presents a first convex curved surface, the protrusion direction of the first convex curved surface being away from the interior of the second recess for a capacitor; A second electrode layer is formed to fill the second groove of the capacitor; The forming method further includes: forming a redundant capacitor groove located in the capacitor dielectric layer at the bottom of the second capacitor groove, wherein the sidewall of the redundant capacitor groove presents a third convex curved surface, and the convex direction of the third convex curved surface is away from the interior of the redundant capacitor groove; wherein the bottom end face of the redundant capacitor groove is a plane and parallel to the substrate surface; the second electrode layer is also filled in the redundant capacitor groove. A redundant electrode layer is formed on the first electrode layer; the top end face of the redundant electrode layer is planar and parallel to the substrate surface; the capacitor dielectric layer also covers the redundant electrode layer. The cross-section of the third convex curved surface is a third sector, and the center of the circle is located on the bottom surface of the second electrode layer; The cross-section of the first convex curved surface is a second sector, and the line connecting the center of the arc length of the second sector and the center of the circle is parallel to the surface of the base.

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