A high-reliability superjunction trench gate silicon carbide VDMOS with voltages above 3kV and its fabrication method

Abstract

This invention provides a high-reliability superjunction trench gate silicon carbide VDMOS with voltages above 3kV and its fabrication method. The method includes depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer, and epitaxially growing on the upper side of the silicon carbide substrate to form a buffer zone; epitaxially growing on the buffer zone to obtain a first drift region; ion implantation to form a P-type region; removing the barrier layer, epitaxially growing on the first drift region to obtain a second drift region; forming the barrier layer, etching, and ion implantation to form a P-type well region, a P+ region, and an N-type source region; etching the P-type well region and the N-type source region to form a first trench; etching the N-type source region, and then depositing metal to form a source metal layer; oxidizing to form an insulating dielectric layer, the insulating dielectric layer having trenches within it; depositing metal to form a gate metal layer; removing the barrier layer to complete the fabrication. By constructing a device gate and source region comprehensively encapsulated by the P-type well region and the P-type region, the breakdown voltage and reliability of the device are improved.

Description

Technical Field

[0001] This invention relates to a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher and its fabrication method. Background Technology

[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices naturally have high voltage withstand capability compared to silicon VDMOS devices. As the voltage withstand capability of the devices continues to increase, under voltage withstand conditions above 3kV, the quality problems of the insulating dielectric of the device gate are amplified due to the continuously increasing voltage, and the probability of breakdown increases significantly. The drain-source reliability of the device is also seriously threatened by the high voltage at the drain. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a high-reliability superjunction trench gate silicon carbide VDMOS above 3kV and its fabrication method, which improves the voltage withstand capability and reliability of the device by constructing a P-type well region and a device gate and source that are comprehensively wrapped by the P-type region.

[0004] In a first aspect, the present invention provides a method for fabricating a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher, characterized by comprising the following steps:

[0005] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially grow metal on the upper side of the silicon carbide substrate to form a buffer zone;

[0006] Step 2: Epitaxial growth is performed on the buffer zone to obtain the first drift region;

[0007] Step 3: Form a barrier layer above the first drift region, etch the barrier layer to form a via, and implant ions to form a P-type region;

[0008] Step 4: Remove the blocking layer from Step 3, and epitaxially grow on the first drift region to obtain the second drift region. The drift layer includes the first drift region and the second drift region.

[0009] Step 5: Form a barrier layer above the drift layer, etch the barrier layer to form a via, and implant ions to form a P-type trap region;

[0010] Step 6: Ion implantation to form P+ regions;

[0011] Step 7: Ion implantation to form an N-type source region;

[0012] Step 8: Etch the P-type well region and the N-type source region to form the first trench;

[0013] Step 9: Etch the N-type source region, and then deposit metal to form the first source metal region;

[0014] Step 10: Deposit metal to form a second source metal region. The source metal layer includes a first source metal region and a second source metal region.

[0015] Step 11: Oxidation to form an insulating dielectric layer, wherein the insulating dielectric layer has grooves;

[0016] Step 12: Deposit metal to form a gate metal layer, remove the barrier layer, and complete the fabrication;

[0017] Steps 6 through 12 all require removing the barrier layer from the previous step and reforming the barrier layer, then etching the barrier layer to form a through-hole.

[0018] Secondly, the present invention provides a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher, wherein the silicon carbide VDMOS is prepared by the preparation method of the high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher described in the first aspect.

[0019] The advantages of this invention are:

[0020] I. This invention constructs an N-type source region enclosed by a P-type well region, and constructs a P-type well region and a P+ region between the drain, source, and gate. This can effectively ensure the withstand voltage characteristics of the device when the drain is subjected to a large voltage, thereby improving the reliability of the device.

[0021] 2. The source metal layer of the present invention is distributed in the middle of the gate, and the source metal layer forms a low-resistance ohmic contact with the N-type source region and the P+ region, which can effectively reduce the on-resistance of the device and the on-resistance of the parasitic body diode.

[0022] Third, the present invention has a P-type well region directly below the gate metal layer, which forms a gate-drain capacitance shield for the gate and drain, thereby reducing the Miller capacitance of the device, reducing the switching charge of the device, and improving the switching speed of the device.

[0023] Fourth, the source metal layer, P+ region, and P-type region of the present invention form a large pn junction contact surface, which can increase the freewheeling capability of the body diode. At the same time, the P-type region and drift layer located directly below the source metal layer of the device form a superjunction structure of the device, which improves the device's withstand voltage and reduces the device's on-resistance. Attached Figure Description

[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0025] Figure 1 This is a schematic diagram of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention.

[0026] Figure 2 This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 1.

[0027] Figure 3 This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 2 .

[0028] Figure 4 This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 3 .

[0029] Figure 5 This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 4 .

[0030] Figure 6 This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 5 .

[0031] Figure 7 This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 6 .

[0032] Figure 8 This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 7 .

[0033] Figure 9 This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 8 .

[0034] Figure 10 This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 9 .

[0035] Figure 11 This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 10 .

[0036] Figure 12 This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 10 one.

[0037] Figure 13 This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 10 two.

[0038] Figure 14This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 10 three.

[0039] Figure 15 This is a cross-sectional view of the process of a high-reliability superjunction trench gate silicon carbide VDMOS with a voltage of 3kV or higher according to the present invention. Figure 10 Four. Detailed Implementation

[0040] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0044] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0045] like Figures 1 to 15 As shown, this application embodiment provides a method for fabricating a high-reliability superjunction trench-gate silicon carbide VDMOS with a voltage of 3kV or higher, comprising the following steps:

[0046] Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 7, and epitaxially grow on the upper side of silicon carbide substrate 1 to form buffer zone 2;

[0047] Step 2: Epitaxial growth is performed on buffer zone 2 to obtain the first drift region 35;

[0048] Step 3: Form a barrier layer 8 above the first drift region 35, etch the barrier layer 8 to form a via, and implant ions to form a P-type region 31;

[0049] Step 4: Remove the blocking layer 8 from step 3, and epitaxially grow on the first drift region 35 to obtain the second drift region 36. The drift layer 3 includes the first drift region 35 and the second drift region 36.

[0050] Step 5: Form a barrier layer 8 above the drift layer 3, etch the barrier layer 8 to form a via, and implant ions to form a P-type trap region 33;

[0051] Step 6: Ion implantation to form P+ region 32;

[0052] Step 7: Ion implantation to form N-type source region 34;

[0053] Step 8: Etch the P-type well region 33 and the N-type source region 34 to form the first trench 9;

[0054] Step 9: Etch the N-type source region 34, and then deposit metal to form the first source metal region 61;

[0055] Step 10: Deposit metal to form a second source metal region 62. The source metal layer includes a first source metal region 61 and a second source metal region 62.

[0056] Step 11: Oxidation to form an insulating dielectric layer 4, wherein the insulating dielectric layer 4 is provided with grooves 41;

[0057] Step 12: Deposit metal to form gate metal layer 5, remove barrier layer 8, and complete the fabrication;

[0058] Steps 6 to 12 all require removing the barrier layer 8 from the previous step and reforming the barrier layer 8, and etching the barrier layer 8 to form a through hole.

[0059] In this embodiment, preferably, the doping concentration of the buffer layer 2 is greater than the doping concentration of the drift layer 3.

[0060] In this embodiment, preferably, the doping concentration of the P-type region 31 is greater than or equal to the doping concentration of the drift layer 3.

[0061] In this embodiment, preferably, the width of the P-type region 31 is greater than the width of the P+ region 32.

[0062] In this embodiment, preferably, the doping concentration of the P+ region 32 is greater than the doping concentration of the P-type region 31.

[0063] In this embodiment, preferably, the width of the P-type well region 33 is greater than the width of the N-type source region 34.

[0064] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0065] Silicon carbide substrate 1,

[0066] Buffer zone 2, the lower side of which is connected to the upper side of silicon carbide substrate 1;

[0067] A drift layer 3 is provided, with its lower side connected to the upper side of the buffer zone 2. The drift layer 3 contains a P-type region 31, a P+ region 32, a P-type well region 33, an N-type source region 34, and a groove (not shown in the figure). The lower side of the P+ region 32 is connected to the P-type region 31, the P-type well region 33 is connected to the outer side of the P+ region 32, and the N-type source region 34 is connected to the P-type well region 33. The groove is inverted convex.

[0068] An insulating dielectric layer 4 is disposed within the groove, and the outer surface of the insulating dielectric layer 4 is respectively connected to the drift layer 3, the P-type well region 33, and the N-type source region 34; a trench 41 is provided inside the insulating dielectric layer 4;

[0069] Gate metal layer 5, the gate metal layer 5 being disposed within the trench 41;

[0070] Source metal layer 6, which is disposed in the groove, and is connected to the inner side of insulating dielectric layer 4, N-type source region 34 and upper side of P+ region 32 respectively.

[0071] And a drain metal layer 7, which is connected to the lower side of the silicon carbide substrate 1.

[0072] In another embodiment of the present invention, the silicon carbide substrate 1, the buffer zone 2, and the drift layer 3 are all N-type; the doping concentration of the silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of buffer 2 is 6-10e17cm. -3 The doping concentration of drift layer 3 is 6-10e16cm. -3 The doping concentration of P-type region 31 is 1-5e17cm. -3 The doping concentration of P+ region 32 is 1-5e18cm. -3 The doping concentration of the P-type well region 33 is 1-5e16cm. -3 The insulating dielectric layer 4 can be made of silicon dioxide, and the doping concentration of the N-type source region 34 is 2-8e18cm. -3 The doping concentration of silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with drain metal layer 7, reducing the overall on-resistance of the device. Buffer layer 2 is to form a buffer structure with gradually varying doping concentration between silicon carbide substrate 1 and drift layer 3, thereby improving the quality at the device interface and suppressing reliability issues caused by interface defects during high-voltage applications. The doping concentration of drift layer 3 and P-type region 31 is a trade-off between reverse breakdown voltage and on-resistance. Their concentration relationship can ensure the lateral and longitudinal diffusion relationship of the space charge region of the pn junction, realizing the superjunction structure of the device, thus ensuring both breakdown voltage and low on-resistance. The doping concentration design of P+ region 32 can form a low-resistance contact with P-type region 31, thereby reducing the body diode freewheeling loss of the device.

[0073] The concentration of the P-type well region 33 serves two purposes: First, the P-type well region 33 distributed on the upper part of the N-type source region 34 can effectively form the gate control structure of the device, realizing trench gate control of the device; Second, the P-type well region 33 distributed at the bottom of the N-type source region 34 can effectively protect the gate of the device from being broken down by the drain voltage, improve the device's withstand voltage and resistance to drain voltage surges, shield the gate-drain capacitance, reduce the device's Miller capacitance, and improve the device's switching speed.

[0074] The silicon carbide substrate 1 has a thickness of 1.2~1.5μm. Since trench gate silicon carbide VDMOS devices above 3kV require thick epitaxy, this ensures support during device fabrication. The buffer layer 2 has a thickness of 500nm, and the drift layer 3 has a thickness of 60~100μm. This is a trade-off between the device's on-resistance and epitaxial thickness. The 100μm thickness is the maximum thickness that can guarantee the quality of the thick epitaxy under current process conditions. The P-type region 31 has a width of 1μm and a thickness of 45-85μm. This is to form the device's superjunction structure. The thicker the superjunction structure, the stronger the device's breakdown voltage, while ensuring the other structures of the device are maintained. The P-type region 31 of the above size can increase the contact area of ​​the parasitic body diode pn junction without affecting the device's on-resistance, thereby improving the body diode's freewheeling capability.

[0075] The P+ region 32 has a width of 500nm and a thickness of 800nm. Together with the P-type well region 33, it forms a protective barrier for the device gate and source, improving the device's reliability.

[0076] The thickness of the P-type well region 33 at the bottom of the N-type source region 34 is 800nm. This is to ensure the vertical pn junction structure of the device, improve the device's ability to withstand drain voltage surges, and improve the device's reliability. The maximum width of the P-type well region 33 is 1.6μm and the maximum thickness is 1.7μm. This is to form a complete wrap around the N-type source region 34 to form the device's voltage withstand structure and gate control structure.

[0077] The source metal layer 6 has a maximum thickness of 1.2 μm, a minimum thickness of 900 nm, a maximum width of 1 μm, and a minimum width of 500 nm. This is to form an inverted convex structure to ensure low on-resistance and low body diode freewheeling loss of the device.

[0078] The insulating dielectric layer 4 has a width of 500 nm, a maximum thickness of 900 nm, a bottom thickness of 100 nm, and widths of 50 nm on the left and right sides. This is to ensure the gate control capability on the left and right sides of the device and the thickness relationship between the bottom and the left and right sides under the process conditions.

[0079] The maximum width of the N-type source region 34 is 1.2 μm, the bottom width of the insulating dielectric layer 4 is 500 nm, the bottom width of the source metal layer is 250 nm, the bottom width of the P-type well region 33 is 250 nm, the thickness at the bottom of the source metal layer 6 and the insulating dielectric layer 4 is 300 nm, and the maximum thickness of the N-type source region 34 is 600 nm. This is a compromise to ensure the low on-resistance gate control capability of the device.

[0080] The gate metal layer 5 has a thickness of 800nm ​​and a width of 400nm, which is to ensure high density of device cells within the limits of process capability.

[0081] The width of the device cell is 5.7 μm. This is to ensure that the width of the N-type drift layer on both sides of the P-type well region of the device is 1 μm, so as to achieve low-resistance conduction of the device.

[0082] In this embodiment, an N-type source region 34 is constructed within a P-type well region 33. A P-type well region 33 and a P+ region 32 are constructed between the drain, source, and gate of the device. This effectively ensures the withstand voltage characteristics of the device and improves the reliability of the device when the drain is subjected to a large voltage.

[0083] The source metal layer 6 of the device is distributed in the middle of the gate metal layer 5 of the device. The source metal layer 6 forms a low-resistance ohmic contact with the N-type source region 34 and the P+ region 32, which can effectively reduce the on-resistance of the device and the on-resistance of the parasitic body diode.

[0084] There is a P-type well region 33 directly below the gate metal layer 5 of the device, which forms a gate-drain capacitance shield for the gate and drain, thereby reducing the Miller capacitance of the device, reducing the switching charge of the device, and improving the switching speed of the device.

[0085] The source metal layer 6, P+ region 32, and P-type region 31 of the device form a large pn junction contact surface, which can increase the freewheeling capability of the body diode. At the same time, the P-type region 31 and drift layer 3 located directly below the source of the device form a superjunction structure of the device, which improves the device's withstand voltage and reduces the device's on-resistance.

[0086] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a high-reliability superjunction trench-gate silicon carbide VDMOS with voltages above 3kV, characterized in that: The method comprises the following steps: Step 1, depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the upper side of the silicon carbide substrate to form a buffer region; Step 2, epitaxially growing on the buffer region to obtain a first drift region; Step 3, forming a barrier layer above the first drift region, etching the barrier layer to form a through hole, and ion implantation to form a P-type region; Step 4, removing the barrier layer of step 3, epitaxially growing on the first drift region to obtain a second drift region, and the drift layer comprising the first drift region and the second drift region; Step 5, forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and ion implantation to form a P-type well region; Step 6, ion implantation to form a P+ region; Step 7, ion implantation to form an N-type source region; Step 8, etching the P-type well region and the N-type source region to form a first groove; Step 9, etching the N-type source region, and then depositing metal to form a first source metal region; Step 10, depositing metal to form a second source metal region, and the source metal layer comprising the first source metal region and the second source metal region; Step 11, oxidizing to form an insulating medium layer, and the insulating medium layer being provided with a groove; Step 12, depositing metal to form a gate metal layer, removing the barrier layer, and completing the preparation; The steps 6 to 12 all need to remove the barrier layer of the previous step and re-form the barrier layer, and etch the barrier layer to form a through hole.

2. The preparation method of the high-reliability super-junction trench gate silicon carbide VDMOS above 3kV of claim 1, characterized in that: The doping concentration of the buffer region is greater than the doping concentration of the drift layer.

3. The preparation method of the high-reliability super-junction trench gate silicon carbide VDMOS above 3kV of claim 1, characterized in that: The doping concentration of the P-type region is greater than or equal to the doping concentration of the drift layer.

4. The preparation method of the high-reliability super-junction trench gate silicon carbide VDMOS above 3kV of claim 1, characterized in that: The width of the P-type region is greater than the width of the P+ region.

5. The preparation method of the high-reliability super-junction trench gate silicon carbide VDMOS above 3kV of claim 1, characterized in that: The doping concentration of the P+ region is greater than the doping concentration of the P-type region.

6. The preparation method of a high-reliability super-junction trench gate silicon carbide VDMOS above 3kV of claim 1, characterized in that: The width of the P-type well region is greater than the width of the N-type source region.

7. A 3kV and above high-reliability super-junction trench-gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method of any one of claims 1 to 6.

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