A 3kV high-reliability trench-gate silicon carbide VDMOS and its fabrication method

Abstract

This invention provides a 3kV high-reliability trench-gate silicon carbide VDMOS and its fabrication method. The method involves depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a buffer zone; epitaxially growing to form a drift layer; forming a barrier layer above the drift layer; etching the barrier layer to form vias; and ion implantation to form a P-type region; epitaxially growing to form an epitaxial layer; etching and ion implantation to form a P+ region; a P-type well region and an N-type source region; etching the epitaxial layer and the P+ region; depositing metal to form a first source metal region; etching the epitaxial layer to form protrusions and grooves; and oxidizing to form an insulating dielectric layer, the insulating dielectric layer containing trenches; depositing metal to form a gate metal layer; etching the epitaxial layer; and depositing metal to form a second source metal region, the source metal layer including the first and second source metal regions, thus constructing a source metal layer structure to improve device reliability.

Description

Technical Field

[0001] This invention relates to a 3kV high-reliability trench-gate silicon carbide VDMOS and its fabrication method. Background Technology

[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices naturally possess higher voltage withstand capability compared to Si VDMOS devices. However, in fields such as high-voltage power transmission, the voltage withstand capability of the device comes at the cost of increasing the thickness of the epitaxial layer. Under high voltage conditions, the reliability problems of the N-type drift layer, N-type silicon carbide substrate, and gate of the device become increasingly serious, severely affecting the reliability of the device. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a 3kV high-reliability trench gate silicon carbide VDMOS and its fabrication method. By constructing a buffer in the device structure, the concentration difference between the silicon carbide substrate and the drift layer is reduced, the interface quality between the drift layer and the silicon carbide substrate is improved, and a source metal layer structure is constructed to improve the reliability of the device.

[0004] In a first aspect, the present invention provides a method for fabricating a 3kV high-reliability trench-gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; grow metal epitaxially on the upper side of the silicon carbide substrate to form a buffer zone;

[0006] Step 2: Epitaxial growth is performed on the side of the buffer zone to form a drift layer;

[0007] Step 3: Form a barrier layer above the drift layer, etch the barrier layer to form vias, and implant ions to form P-type regions;

[0008] Step 4: Remove the blocking layer from Step 3, and perform epitaxial growth on the drift layer to form an epitaxial layer;

[0009] Step 5: Form a barrier layer above the epitaxial layer, etch the barrier layer to form a via, and implant ions to form a P+ region;

[0010] Step 6: Ion implantation to form a P-type trap region;

[0011] Step 7: Ion implantation to form an N-type source region;

[0012] Step 8: Etch the epitaxial layer and P+ region, deposit metal to form the first source metal region;

[0013] Step 9: Etch the epitaxial layer to form protrusions and grooves, and oxidize to form an insulating dielectric layer, wherein the insulating dielectric layer has grooves.

[0014] Step 10: Deposit metal to form a gate metal layer;

[0015] Step 11: Etch the epitaxial layer and deposit metal to form the second source metal region. The source metal layer includes the first source metal region and the second source metal region.

[0016] Steps 6, 8 to 11 all require removing the barrier layer from the previous step, reforming the barrier layer, and etching the barrier layer to form a through-hole.

[0017] Secondly, the present invention provides a 3kV high-reliability trench gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the preparation method of the 3kV high-reliability trench gate silicon carbide VDMOS described in the first aspect.

[0018] The advantages of this invention are:

[0019] I. This invention constructs a buffer zone, creating a structural buffer zone between the silicon carbide substrate and the drift layer, thereby improving the interface quality between the silicon carbide substrate and the drift layer and enhancing the reliability of the device.

[0020] 2. In this invention, source metal layers are constructed on both sides of the gate metal layer. The space charge region formed by the P+ region and the drift region can form protection at the corner of the insulating dielectric layer, thereby improving the gate reliability of the device.

[0021] Third, the source metal layer and P+ region of the present invention form a structure that penetrates deep into the device, thereby reducing the resistance from the source metal layer to the drift layer and thus reducing the freewheeling loss of the device body diode.

[0022] Fourth, the drift layer and P-type region of the present invention form a superjunction structure, which can reduce the large on-resistance of the device while ensuring the device's voltage withstand capability. Attached Figure Description

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] Figure 1 This is a schematic diagram of a 3kV high-reliability trench gate silicon carbide VDMOS according to the present invention.

[0025] Figure 2 This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 1 .

[0026] Figure 3 This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 2 .

[0027] Figure 4This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 3 .

[0028] Figure 5 This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 4 .

[0029] Figure 6 This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 5 .

[0030] Figure 7 This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 6 .

[0031] Figure 8 This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 7 .

[0032] Figure 9 This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 8 .

[0033] Figure 10 This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 9 .

[0034] Figure 11 This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 10 .

[0035] Figure 12 This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 10 one.

[0036] Figure 13 This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 10 two.

[0037] Figure 14 This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 10 three.

[0038] Figure 15 This is a cross-sectional view of the process of a 3kV high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 10 Four. Detailed Implementation

[0039] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0043] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0044] like Figures 1 to 15 As shown in the figure, this application provides a method for fabricating a 3kV high-reliability trench-gate silicon carbide VDMOS, including the following steps:

[0045] Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 110; grow epitaxially on the upper side of silicon carbide substrate 101 to form buffer zone 102;

[0046] Step 2: Epitaxial growth is performed on the side of buffer zone 102 to form drift layer 103;

[0047] Step 3: Form a barrier layer 111 above the drift layer 103, etch the barrier layer to form a via, and implant ions to form a P-type region 1031;

[0048] Step 4: Remove the blocking layer 111 from step 3, and epitaxially grow on the drift layer 103 to form the epitaxial layer 112;

[0049] Step 5: Form a barrier layer 111 above the epitaxial layer 112, etch the barrier layer 111 to form a via, and implant ions to form a P+ region 104.

[0050] Step 6: Ion implantation to form a P-type well region 105;

[0051] Step 7: Ion implantation to form an N-type source region 106;

[0052] Step 8: Etch epitaxial layer 112 and P+ region 104, deposit metal to form first source metal region 1091;

[0053] Step 9: Etch the epitaxial layer 112 to form protrusions 1032 and grooves 10321, and oxidize to form an insulating dielectric layer 107, wherein the insulating dielectric layer 107 has grooves 1071.

[0054] Step 10: Deposit metal to form gate metal layer 108;

[0055] Step 11: Etch epitaxial layer 112, deposit metal to form second source metal region 1092, source metal layer 109 includes first source metal region 1091 and second source metal region 1092;

[0056] Steps 6, 8 to 11 all require removing the barrier layer 111 from the previous step, reforming the barrier layer 111, and etching the barrier layer 111 to form a through hole.

[0057] In this embodiment, preferably, the doping concentration of the P-type region 1031 is greater than or equal to the doping concentration of the drift layer 103, and the doping concentration of the P+ region 104 is greater than the doping concentration of the P-type region 1031.

[0058] In this embodiment, preferably, the doping concentration of the P-type well region 105 is less than the doping concentration of the P+ region 104.

[0059] In this embodiment, preferably, the P-shaped region 1031 is not located directly below the protrusion 1032.

[0060] In this embodiment, preferably, the thickness of the P+ region 104 is equal to the thickness of the protrusion 1032, and the depth of the groove 10321 is less than the thickness of the protrusion 1032.

[0061] In this embodiment, preferably, the width of the P-type region is equal to the width of the P+ region.

[0062] like Figure 1 , Figure 11 and Figure 12 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0063] Silicon carbide substrate 101,

[0064] Buffer 102, the lower side of which is connected to the upper side of the silicon carbide substrate 101;

[0065] A drift layer 103 is provided, the lower side of which is connected to the upper side of the buffer zone 102; the drift layer 103 is provided with a P-shaped area 1031 and a protrusion 1032, the P-shaped area 1031 is located on both sides of the drift layer 103, and the protrusion 1032 is provided with a groove 10321.

[0066] P+ area 104, the lower side of P+ area 104 is connected to P-shaped area 1031; the inner side of P+ area 104 is connected to the outer side of protrusion 1032, and P+ area 104 is L-shaped.

[0067] P-type well region 105, the lower side of which is connected to P+ region 104 and protrusion 1032 respectively;

[0068] N-type source region 106, the lower side of which is connected to P-type well region 105;

[0069] An insulating dielectric layer 107 is provided at its lower part within the groove 10321. The insulating dielectric layer 107 is connected to the P-type well region 105 and the N-type source region 106 respectively. A trench 1071 is provided within the insulating dielectric layer 107.

[0070] A gate metal layer 108 is disposed within the trench 1071;

[0071] Source metal layer 109, which is connected to the P+ region 104, the P-type well region 105 and the N-type source region 106 respectively;

[0072] And a drain metal layer 110, which is connected to the lower side of the silicon carbide substrate 101.

[0073] Another embodiment of the present invention:

[0074] The silicon carbide substrate, buffer zone, and drift layer are all N-type; the doping concentration of the silicon carbide substrate 101 is 2-8e18cm. -3 The doping concentration of buffer 102 is 6-10e17cm. -3 The doping concentration of drift layer 103 is 6-10e16cm. -3 The doping concentration of the P-type region 1031 is 1-5e17cm. -3 The doping concentration of P+ region 104 is 1-5e18cm. -3 The doping concentration of the P-type well region 105 is 1-5e16cm. -3 The insulating dielectric layer 107 can be made of silicon dioxide, and the doping concentration of the N-type source region 106 is 2-8e18cm. -3 ;

[0075] The doping concentration of the silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer, thereby reducing the overall on-resistance of the device. The buffer zone 102 is to form a buffer structure with a gradually changing doping concentration between the silicon carbide substrate 101 and the drift layer 103, thereby improving the quality at the device interface and suppressing reliability issues caused by interface defects in high-voltage applications. The doping concentration of the drift layer 103 and the P-type region 1031 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. Their concentration relationship can ensure the lateral and longitudinal diffusion relationship of the space charge region of the pn junction, realizing the superjunction structure of the device, thereby ensuring both the breakdown voltage and low on-resistance of the device.

[0076] The doping concentration of the P+ region 104 is considered for two reasons. The first is to form a low-resistance ohmic contact with the source metal layer 109, thereby reducing the on-resistance of the device's body diode and reducing the freewheeling loss of the device's body diode. The second is to form a space charge region with the drift layer 103 to surround the gate corner of the device, thereby suppressing the electric field concentration problem at the gate corner and improving the gate reliability of the device.

[0077] The P-type well region 105 is used to form the gate control structure of the device and realize the trench gate control of the device. The source metal layer 109 of the device includes a first source metal region 1091 and a second source metal region 1092. The second source metal region 1092 is used to form a vertical conductive channel of the device to prevent electrons from changing the channel direction inside the silicon carbide material and improve the switching speed of the device. The first source metal region 1091 is used to reduce the body diode loss of the device and transfer the source potential of the device to the P+ region 104 of the device, thereby ensuring the protection effect of the space charge region formed by the P+ region 104 and the drift layer 103 on the gate corner of the device.

[0078] The silicon carbide substrate 101 has a thickness of 1.2 μm. Since the 3kV trench-gate silicon carbide VDMOS device requires a thick epitaxial layer, the silicon carbide substrate 101 is designed with a thickness of 1.2 μm to ensure support during device fabrication. The buffer layer 102 has a thickness of 500 nm, and the drift layer 103 has a thickness of 60 μm. This represents a trade-off between the device and doping concentration on on-resistance and epitaxial thickness. The P-type region 1031 has a width of 800 nm and a thickness of 45 μm. This is to... The superjunction structure of the device is formed. The thicker the superjunction structure, the stronger the device's breakdown voltage, while ensuring the stability of the rest of the device structure. The P+ region 104 has a width of 800 nm and a maximum thickness of 700 nm. The P+ region 104 at the bottom of the first source metal region 1091 has a thickness of 300 nm. This is to ensure the wrapping of the device's source metal layer 109. The width of the protrusions 1032 on both sides of the groove 10321 is sufficient to protect the gate corner of the device during reverse breakdown voltage. The second source metal region 1092 has a thickness of 200 nm. The source metal layer 109 has a maximum thickness and a width of 1 μm and a minimum width of 500 nm. This is to ensure the withstand voltage characteristics of the device during reverse breakdown. The N-type source region 106 has a width of 500 nm and a thickness of 200 nm. This is to reduce the resistance of the conductive channel of the device. The P-type well region 105 has a thickness of 200 nm and a width of 500 nm. This is to improve the gate control capability of the device. The insulating dielectric layer 107 has a maximum thickness of 800 nm. This is to ensure the reliability of the bottom gate of the device and the gate control capability on the left and right sides of the device. The gate metal layer 108 has a width of 600 nm and a thickness of 700 nm. This is to ensure the gate control capability of the device and improve the structural density of the device, thereby reducing the cell size. The bottom of the source metal layer of the device should be lower than the bottom of the insulating dielectric layer of the device to ensure that the space charge region of the P+ region 104 and the drift layer 103 protect the gate corner of the device.

[0079] A structural buffer 102 is constructed between the silicon carbide substrate 101 and the drift layer 103, thereby improving the interface quality between the N-type silicon carbide substrate 101 and the N-type drift layer 103 and improving the reliability of the device.

[0080] The first source metal region 1091 and the P+ region 104 form a structure that extends deep into the device, thereby reducing the resistance from the source metal layer 109 to the drift layer 103 and thus reducing the freewheeling loss of the device's body diode.

[0081] The drift layer 103 and the P-type region 1031 form a superjunction structure, which can reduce the on-resistance of the device while ensuring the device's voltage withstand capability.

[0082] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing a 3kV high-reliability trench-gate silicon carbide VDMOS, characterized in that: The method comprises the following steps: Step 1, depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a buffer region; Step 2, epitaxially growing on the upper side of the buffer region to form a drift layer; Step 3, forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and ion implantation to form a P-type region; Step 4, removing the barrier layer of step 3, epitaxially growing on the drift layer to form an epitaxial layer; Step 5, forming a barrier layer above the epitaxial layer, etching the barrier layer to form a through hole, and ion implantation to form a P+ region; Step 6, ion implantation to form a P-type well region; Step 7, ion implantation to form an N-type source region; Step 8, etching the epitaxial layer and the P+ region, depositing metal to form a first source metal region; Step 9, etching the epitaxial layer to form a protrusion and a groove, and oxidizing to form an insulating medium layer, wherein a groove is arranged in the insulating medium layer; Step 10, depositing metal to form a gate metal layer; Step 11, etching the epitaxial layer, depositing metal to form a second source metal region, and the source metal layer comprises the first source metal region and the second source metal region; The steps 6, 8 to 11 all need to remove the barrier layer of the previous step, re-form the barrier layer, and etch the barrier layer to form a through hole; the drift layer has a doping concentration of 6-10e16 cm -3 the P-type region has a doping concentration of 1-5e17 cm -3 the P-type region has a doping concentration greater than the doping concentration of the drift layer The lower side of the drift layer is connected to the upper side of the buffer region; the P-type region is located on both sides of the drift layer, the protrusion is provided with a groove; The lower side of the P+ region is connected to the P-type region; the inner side of the P+ region is connected to the outer side of the protrusion; The lower side of the P-type well region is connected to the P+ region and the protrusion respectively; The lower side of the N-type source region is connected to the P-type well region; The gate metal layer is arranged in the groove; The source metal layer is connected to the P+ region, the P-type well region and the N-type source region respectively The doping concentration of the P-type region is greater than or equal to the doping concentration of the drift layer, and the doping concentration of the P+ region is greater than the doping concentration of the P-type region. 。 2. The preparation method of a 3kV high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type well region is less than the doping concentration of the P+ region.

3. The method of claim 1, wherein the 3kV high-reliability trench-gate silicon carbide VDMOS is prepared by the steps of: The P-type region is not located directly below the protrusion. ​ 4. The method of claim 1, wherein the 3kV high-reliability trench gate silicon carbide VDMOS is prepared by the steps of: The thickness of the P+ region is equal to the thickness of the protrusion, and the depth of the groove is less than the thickness of the protrusion. ​ 5. The method of claim 1, wherein the 3kV high-reliability trench gate silicon carbide VDMOS is prepared by the steps of: The width of the P-type region is equal to the width of the P+ region. ​ 6. The method of claim 1, wherein the 3kV high-reliability trench gate silicon carbide VDMOS is prepared by the steps of: The silicon carbide VDMOS is prepared by the method of any one of claims 1 to 6. ​ 7. A 3kV high-reliability trench-gate silicon carbide VDMOS, characterized in that, ​

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