Semiconductor structure and manufacturing method thereof
By forming a bowl-shaped depression and setting a protrusion in front of the gate oxide layer, the "bird's beak effect" caused by partial oxidation of the active region during the gate oxide growth process is solved, resulting in better device performance and yield.
Patent Information
- Application Number
- CN202410564576.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-08
- Publication Date
- 2025-11-14
AI Technical Summary
In existing technologies, the "bird's beak effect" caused by partial oxidation of the active region during gate oxide growth affects device performance and yield.
Before the gate oxide layer is formed, a bowl-shaped recess is formed on the substrate and protrusions are set at both ends. The bowl-shaped structure is formed by ion implantation and wet etching. Then, the growth rate of the second gate oxide layer is accelerated in the middle region of the bowl-shaped recess to prevent oxygen from entering the sidewall and contacting silicon.
It effectively suppressed the oxidation of Si in the source region, reduced the "bird's beak effect," and improved device performance and yield.
Smart Images
Figure CN120957474A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology and relates to a semiconductor structure and its fabrication method. Background Technology
[0002] A common problem in Local Oxidation of Silicon (LOCOS) technology is the "bird's beak" that grows at the edge of the silicon nitride during the channel isolation process (the length of the bird's beak increases with the depth of the pre-etching of the channel). The "bird's beak" grown in the source region increases the circuit volume and also causes stress damage in the silicon, which is detrimental to the product yield and device performance.
[0003] One method for eliminating the bird beak effect uses silicon nitride as a sidewall isolation, which can effectively block oxygen from reacting with the silicon on the sidewall. However, the disadvantage of this method is that an extra layer of silicon nitride is deposited for sidewall isolation. If sidewall silicon nitride particles fall in when etching the trench opening of the gate oxide (GOX) region, it will greatly affect the threshold voltage of the device.
[0004] Another method for eliminating the bird's beak effect involves the following steps: A pad oxide layer and a dielectric layer are sequentially prepared from bottom to top on the upper surface of the substrate; the dielectric layer and pad oxide layer are then partially etched into the substrate to form trenches; a tilted ion implantation process is performed to generate a barrier layer at the bottom and sidewalls of the trench; the barrier layer at the bottom of the trench is removed, while the barrier layer covering the sidewalls is retained; after a first oxide layer fills the trench, the remaining dielectric layer and the remaining pad oxide layer are sequentially removed; a second oxide layer is then prepared on the exposed substrate surface. However, a drawback of this method is that due to N ion doping, Si and N can form silicon nitride at high temperatures, and the stress generated between silicon nitride and Si can easily cause unnecessary damage to the substrate.
[0005] Therefore, how to solve the "bird's beak effect" caused by the partial oxidation of the active region during the gate oxide growth process has become an important technical problem that needs to be solved by those skilled in the art.
[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention
[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor structure and its fabrication method to solve the problem of the "bird's beak effect" caused by partial oxidation of the active region during the gate oxide growth process in the prior art.
[0008] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor structure, comprising the following steps:
[0009] A substrate is provided, and a hard mask layer is formed on the substrate;
[0010] An opening is formed in the hard mask layer, and the bottom of the opening exposes the surface of the substrate;
[0011] A first gate oxide layer is formed on the surface of the substrate exposed by the opening;
[0012] A bowl-shaped recess is formed in the first gate oxide layer, and the bowl-shaped recess has protrusions at both ends, with the top surface of the protrusions being higher than the bottom surface of the hard mask layer;
[0013] Remove the hard mask layer;
[0014] A second gate oxide layer continues to form in the region where the first gate oxide layer is located, and the growth rate of the second gate oxide layer in the middle region of the bowl-shaped depression is faster than the growth rate in the edge region of the bowl-shaped depression.
[0015] Optionally, forming a bowl-shaped recess in the first gate oxide layer includes the following steps:
[0016] Ion implantation is performed to break some of the Si-O bonds in the first gate oxide layer. The ions used for ion implantation include one or more of Ar ions, Xe ions, and Kr ions. Under the scattering effect of the hard mask layer on both sides of the opening, the bottom of the region of the first gate oxide layer to which ions are implanted is bowl-shaped.
[0017] The first gate oxide layer is etched by wet etching with a solution containing hydrofluoric acid to obtain the bowl-shaped recess.
[0018] Optionally, forming a bowl-shaped recess in the first gate oxide layer includes the following steps:
[0019] A sacrificial layer is formed, which covers the hardening mask layer and the first gate oxide layer;
[0020] The sacrificial layer is subjected to dry anisotropic etching until the upper surface of the hard mask layer and most of the upper surface of the first gate oxide layer are exposed. The hard mask layer and the first gate oxide layer are both over-etched to a certain thickness. A portion of the sacrificial layer remains on the sidewall of the opening. The portion of the first gate oxide layer covered by the remaining sacrificial layer is not over-etched, forming a protrusion.
[0021] The sacrificial layer remaining on the sidewall of the opening is removed by wet etching, and the bowl-shaped recess located in the first gate oxide layer is obtained.
[0022] Optionally, the sacrificial layer may be made of TEOS, and the etching solution used to remove the sacrificial layer remaining on the sidewall of the opening by wet etching may be a hydrofluoric acid solution.
[0023] Optionally, the upper surface of the substrate has a surface oxide layer, and the hard mask layer covers the surface oxide layer.
[0024] Optionally, before forming the bowl-shaped recess, the top surface of the first gate oxide layer is higher than the top surface of the surface oxide layer.
[0025] Optionally, after the bowl-shaped recess is formed, the top surface of the protrusion is higher than the top surface of the surface oxide layer, and the center of the bottom surface of the bowl-shaped recess is lower than the top surface of the surface oxide layer.
[0026] Optionally, the hard mask layer includes a silicon nitride layer, and the method for removing the hard mask layer includes wet etching with a phosphoric acid solution containing hydrofluoric acid, wherein the protrusions are reduced during the removal of the hard mask layer.
[0027] Optionally, it may also include at least one of the following:
[0028] (1) The method for forming the first gate oxide layer includes thermal oxidation, and the method for forming the second gate oxide layer includes in-situ water vapor generation, or...
[0029] (2) The temperature range used to form the first gate oxide layer is 900℃-950℃, and the temperature range used to form the second gate oxide layer is 950℃-1050℃, or
[0030] (3) Before the bowl-shaped recess is formed, the thickness of the first gate oxide layer is 300 angstroms to 800 angstroms. After the second gate oxide layer is formed, the total thickness of the gate oxide layer composed of the first gate oxide layer and the second gate oxide layer is 1300 angstroms to 1800 angstroms.
[0031] The present invention also provides a semiconductor structure, comprising:
[0032] Substrate;
[0033] The gate oxide layer is located in a predetermined area on the front side of the substrate;
[0034] The semiconductor structure is formed using any of the semiconductor structure fabrication methods described above.
[0035] As described above, in the semiconductor structure and fabrication method of the present invention, the gate oxide layer is formed by stacking a first gate oxide layer and a second gate oxide layer. Before growing the second gate oxide layer in the region where the first gate oxide layer is located, a bowl-shaped recess is first formed in the first gate oxide layer. The bowl-shaped recess has protrusions at both ends, and the top surface of the protrusions is higher than the bottom surface of the hard mask layer. When the second gate oxide layer is subsequently grown, the growth rate of the second gate oxide layer in the middle region of the bowl-shaped recess is faster than the growth rate in the edge region of the bowl-shaped recess. The top surface of the final gate oxide layer is horizontal or nearly horizontal. At the same time, since the bowl-shaped recess and the protrusions at both ends are equivalent to providing sidewall isolation for the substrate on both sides of the gate oxide region, oxygen can be prevented from entering the sidewall and contacting Si, thereby suppressing the oxidation of Si in the source region and improving the "bird's beak effect" caused by partial oxidation of the source region during the gate oxide growth process. Attached Figure Description
[0036] Figure 1 The diagram shows a process flow chart of the method for fabricating the semiconductor structure of the present invention.
[0037] Figure 2 The diagram shows a schematic of the structure obtained after forming a hard mask layer on a substrate, as described in the method for fabricating the semiconductor structure of the present invention.
[0038] Figure 3 The diagram shows a schematic of the structure obtained after forming an opening in a hard mask layer, as described in the method for fabricating the semiconductor structure of the present invention.
[0039] Figure 4 The diagram shows a schematic of the structure obtained after forming a first gate oxide layer on the surface of a substrate exposed by an opening, as described in the method for fabricating the semiconductor structure of the present invention.
[0040] Figure 5 The diagram shows an Ar ion implantation process for fabricating the semiconductor structure of the present invention.
[0041] Figure 6 The diagram shows a schematic of the structure obtained after wet etching of the first gate oxide layer to obtain a bowl-shaped recess, which is a method for fabricating the semiconductor structure of the present invention.
[0042] Figure 7 The diagram shown is a schematic diagram of the structure obtained after forming the sacrificial layer in the semiconductor structure fabrication method of the present invention.
[0043] Figure 8The diagram shown illustrates the semiconductor structure fabrication method of the present invention, which involves removing the sacrificial layer using dry etching and wet etching to obtain a bowl-shaped recess.
[0044] Figure 9 The diagram shown is a schematic of the structure obtained after removing the hard mask layer in the semiconductor structure fabrication method of the present invention.
[0045] Figure 10 The diagram shown is a schematic of the structure obtained after growing the second gate oxide layer according to the semiconductor structure fabrication method of the present invention.
[0046] Explanation of reference numerals in the attached figures
[0047] Steps S1 to S6
[0048] 1 Substrate
[0049] 2 Hard mask layer
[0050] 3. Tunnel
[0051] 4. Isolation Structure
[0052] 5 Surface oxide layer
[0053] 6 Openings
[0054] 7 First gate oxide layer
[0055] 8, 8' Bowl-shaped depression
[0056] 9. Sacrificial Layer
[0057] 10. Protrusions
[0058] 11 Second gate oxide layer Detailed Implementation
[0059] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0060] Please see Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0061] This invention provides a method for fabricating a semiconductor structure; please refer to [link / reference]. Figure 1 The diagram shows the process flow of this method, which includes the following steps:
[0062] S1: Provide a substrate and form a hard mask layer on the substrate;
[0063] S2: An opening is formed in the hard mask layer, the bottom of which exposes the surface of the substrate;
[0064] S3: Form a first gate oxide layer on the surface of the substrate exposed by the opening;
[0065] S4: A bowl-shaped recess is formed in the first gate oxide layer, the bowl-shaped recess having protrusions at both ends, and the top surface of the protrusions being higher than the bottom surface of the hard mask layer;
[0066] S5: Remove the hard mask layer;
[0067] S6: A second gate oxide layer continues to be formed in the region where the first gate oxide layer is located, and the growth rate of the second gate oxide layer in the middle region of the bowl-shaped depression is faster than the growth rate in the edge region of the bowl-shaped depression.
[0068] The following section details each of the above steps in conjunction with the structural diagram.
[0069] Please refer to the following first. Figure 2 Perform step S1: Provide a substrate 1 and form a hard mask layer 2 on the substrate 1.
[0070] As an example, the substrate 1 may be a silicon substrate, a silicon-on-insulator substrate, or other suitable semiconductor substrate.
[0071] In some embodiments, the substrate 1 is a P-type silicon substrate, wherein a well region 3 of a certain thickness is pre-fabricated.
[0072] In some embodiments, an isolation structure 4 is pre-fabricated in the substrate 1 to define the desired active region. The isolation structure 4 may be, for example, a shallow trench isolation structure (STI) or other suitable isolation structure.
[0073] In some embodiments, a surface oxide layer 5 may be pre-grown on the upper surface of the substrate 1 using furnace tube deposition or other suitable methods, and the surface oxide layer 5 may be used as a transition layer between the substrate 1 and the subsequently formed hard mask layer 2 to relieve stress.
[0074] In some embodiments, the hard mask layer 2 includes a silicon nitride layer, which can be obtained by furnace tube deposition.
[0075] In some embodiments, to improve channel performance, the silicon nitride layer includes stressed silicon nitride, the specific stress of which can be adjusted according to actual needs.
[0076] Please see again Figure 3 Step S2 is performed: an opening 6 is formed in the hard mask layer 2 using patterning processes such as photolithography and etching, and the bottom of the opening 6 exposes the surface of the substrate 1.
[0077] Specifically, the opening 6 is used to define the gate oxide (GOX) region of a specific device, such as the gate oxide region of a high-voltage device. In order to withstand a sufficiently high voltage, the gate oxide region of a high-voltage device usually needs to be thicker than that of medium- and low-voltage devices. Therefore, it requires a longer oxidation process during formation. The longer the oxidation process, the more severe the oxygen penetration into the substrate of the device. Therefore, it is easier to form a larger beak in places where oxides do not need to be formed.
[0078] It should be noted that the term "high voltage" in this invention is a relative concept, relative to "low voltage" and "medium voltage." The power supply voltage of a low-voltage device is lower than that of a high-voltage device, and the specific voltage value is not particularly limited. For example, in one embodiment, the power supply voltage of the low-voltage device is 1.1V, the power supply voltage of the high-voltage device is 5V, and the power supply voltage of the medium-voltage device is between that of the low-voltage and high-voltage devices. In another embodiment, the power supply voltage of the low-voltage device is 1.1V, the power supply voltage of the high-voltage device is 32V, and devices with a power supply voltage of 5V or 8V are considered medium-voltage devices.
[0079] Please see again Figure 4 Step S3 is performed: a first gate oxide layer 7 is formed on the surface of the substrate 1 exposed by the opening 6.
[0080] As an example, the method for forming the first gate oxide layer 7 includes thermal oxidation, and the temperature range used when forming the first gate oxide layer 7 is 900°C-950°C.
[0081] Specifically, the top surface of the first gate oxide layer 7 needs to be lower than the top surface of the hard mask layer 2, and the specific reasons will be explained in detail later.
[0082] As an example, the thickness of the first gate oxide layer 7 is in the range of 300 angstroms to 800 angstroms, as long as the density is sufficient. For example, in one embodiment, the thickness of the first gate oxide layer 7 is 500 angstroms.
[0083] In some embodiments, the top surface of the first gate oxide layer 7 is higher than the top surface of the surface oxide layer 5.
[0084] The next step is step S4: forming a bowl-shaped recess in the first gate oxide layer 7, wherein the bowl-shaped recess has protrusions at both ends, and the top surface of the protrusions is higher than the bottom surface of the hard mask layer. In this invention, different methods can be used to form the bowl-shaped recess in the first gate oxide layer 7.
[0085] Please see Figure 5 and Figure 6 In one embodiment, forming a bowl-shaped recess in the first gate oxide layer includes the following steps:
[0086] S4-1: As Figure 5 As shown, ion implantation is performed to break some of the Si-O bonds in the first gate oxide layer 7. The ions used for ion implantation are inert ions with a large atomic mass, including but not limited to one or more of Ar ions, Xe ions and Kr ions. The bottom of the region of the first gate oxide layer to which the ions are implanted is bowl-shaped.
[0087] S4-2: As Figure 6 As shown, the first gate oxide layer 7 is wet-etched using a solution containing hydrofluoric acid to obtain a bowl-shaped recess 8, which has protrusions 10 at both ends.
[0088] Specifically, since the top surface of the first gate oxide layer 7 is lower than the top surface of the hard mask layer 2, in step S4-1, during ion implantation, the ion implantation depth and concentration in the first gate oxide layer 7 are affected by the scattering effect of the hard mask layer 2 on both sides of the opening 6. Ultimately, the bottom edge region of the area where the first gate oxide layer is implanted with ions resembles a bowl shape. Furthermore, because the Si-O bonds in the region where ions are implanted in the first gate oxide layer 7 are broken, and the closer to the center of this region, the deeper the Si-O bond breakage, the more efficient the process becomes in step S4-2. Therefore, adding hydrofluoric acid in step S4-2 can accelerate the "bond breaking" of Si and F. - SiF production through coordination between ions x The process ultimately forms the bowl-shaped depression 8.
[0089] Specifically, the top surface of the protrusion 10 is higher than the top surface of the surface oxide layer 5 (i.e., higher than the bottom surface of the hard mask layer 2). This is so that during the subsequent gate oxide formation process, it can provide as much obstruction as possible to the silicon substrate near the edge of the opening 6, reduce oxygen penetration, and thus reduce the bird beak effect.
[0090] Specifically, after ion bombardment and wet etching, the first gate oxide layer 7 in the opening 6 forms a structure with a higher outer edge and a lower inner edge on the inner sidewall. In some embodiments, it is necessary to ensure that the center of the bottom surface of the bowl-shaped recess 8 is lower than the top surface of the surface oxide layer 5. This ensures that during the subsequent formation of the gate oxide layer, more oxygen above the recess can penetrate into the silicon substrate. That is, the oxygen in the silicon substrate at the opening 6 gradually decreases from the center of the opening 6 to both sides. This is beneficial for the re-formed gate oxide layer to have a structure that gradually decreases from the center to both sides in the opening 6, which complements the structure of the wet-etched first gate oxide layer 7, thereby forming a flatter final gate oxide layer. Furthermore, due to the blocking effect of the protrusion 10, the bird's beak effect near the substrate surface on both sides of the opening 6 can be effectively reduced.
[0091] It should be noted that HF wet etching is isotropic etching, but the etching rate will vary greatly for gate oxide layers grown by different processes. For gate oxide layers grown in situ with dry oxygen, directly using HF wet etching will result in a slow etching rate and poor reproducibility of the "bowl-shaped" morphology. In the above embodiments of the present invention, the ion implantation depth can be determined by experimental simulation and transmission electron microscopy (TEM) + energy dispersive spectroscopy (EDS), and correlated with the parameters of the equipment. A fault defect classification (FDC) is set to control the morphology of the bowl-shaped recess 8, which is ultimately controllable.
[0092] Specifically, the above embodiment utilizes ion implantation of inert gas to disrupt the integrity of the first gate oxide layer 7, and after wet etching, forms a SiO2 sidewall structure (composed of the edge region of the bowl-shaped recess 8 and the protrusion 10), which can effectively prevent O2 from continuously oxidizing the source region during the subsequent growth of the second gate oxide layer.
[0093] In addition, the injection of inert gas will not affect the device performance, because the inert gas itself does not react with Si. It only relies on the high energy during ion implantation to break the Si-O-Si bond. Furthermore, the area defined by ion implantation will be more easily "eaten up" by the wet etching in step S4-2.
[0094] Please see Figure 7 and Figure 8 In another embodiment, forming a bowl-shaped recess in the first gate oxide layer 7 includes the following steps:
[0095] S4-1': As Figure 7 As shown, a sacrificial layer 9 is formed, which covers the hardened mask layer 2 and the first gate oxide layer 7;
[0096] S4-2': As Figure 8 As shown, the sacrificial layer 9 is subjected to dry anisotropic etching until the upper surface of the hard mask layer 2 and most of the upper surface of the first gate oxide layer 7 are exposed, wherein both the hard mask layer 2 and the first gate oxide layer 7 are over-etched to a certain thickness. Figure 8 The dashed line represents the original top surface of the hard mask layer 2. A portion of the sacrificial layer 9 remains on the sidewall of the opening 6 (intermediate process not shown). The portion of the first gate oxide layer 7 covered by the remaining sacrificial layer 9 is not over-etched, forming a protrusion 10. Then, wet etching is used to remove the remaining sacrificial layer 9 on the sidewall of the opening 6, resulting in a bowl-shaped recess 8' located in the first gate oxide layer 7.
[0097] Specifically, in the aforementioned dry anisotropic etching, while the sacrificial layer 9 on the hard mask layer 2 is consumed, the sacrificial layer 9 on the first gate oxide layer 7 is also consumed in equal amounts. There are more sacrificial layers 9 at the edge of the first gate oxide layer 7. After dry etching, the sacrificial layers 9 at the edge will remain, forming a sidewall structure to protect the first gate oxide layer 7 at the bottom contact portion. Meanwhile, the sacrificial layers 9 on the surface of the first gate oxide layer 7 at other positions in the opening 6 and the sacrificial layers 9 on the surface of the hard mask layer 2 are simultaneously removed by dry etching, exposing the first gate oxide layer 7 in the middle portion. After a certain over-etching process, the portion of the first gate oxide layer 7 covered by the remaining sacrificial layer 9 is not etched and forms the protrusion 10. After subsequent wet etching to remove the remaining sacrificial layer 9, the bowl-shaped recess 8' located in the first gate oxide layer 7 is obtained.
[0098] Specifically, the material selection of the sacrificial layer 9 needs to meet certain requirements, namely, during the aforementioned dry anisotropic etching and wet etching, it has a different selection ratio than that of the hard mask layer 2 and the first gate oxide layer 7. During the dry anisotropic etching process, a certain amount of over-etching must be ensured. At this time, the hard mask layer 2 will have some loss, but this is necessary because this over-etching is used to perform a certain amount of surface ion bombardment on the exposed first gate oxide layer 7, providing an initial surface depression morphology. Furthermore, due to the ion bombardment and the scattering effect of the ions on the sides of the opening 6, the area of the bombarded region in the middle of the first gate oxide layer 7 is larger than the area of the bombarded region at the edges. Therefore, a more ideal central depression morphology can be obtained during subsequent wet etching.
[0099] In some embodiments, the sacrificial layer 9 is made of tetraethoxysilane (TEOS), which is silicon dioxide grown by chemical vapor deposition (CVD) and has a softer texture than the first gate oxide layer 7.
[0100] In some embodiments, the etching gas used for dry anisotropic etching of the sacrificial layer 9 includes CF4 and O. x (e.g., O2), the etching solution used when removing the sacrificial layer 9 remaining on the sidewall of the opening 6 by wet etching includes hydrofluoric acid solution.
[0101] Specifically, because the sacrificial layer 9 of TEOS material is softer and has a higher etching rate, the silicon oxide loss of the first gate oxide layer 7 can be reduced during wet removal of TEOS.
[0102] Specifically, the morphology of the bowl-shaped recess 8' is mainly determined by the dry etching gas ratio and time, and the amount and time of HF. Compared with the bowl-shaped recess 8 obtained by Ar ion implantation + wet etching in the previous embodiment, the morphology of the bowl-shaped recess 8' obtained by sacrificial layer + dry etching + wet etching is more consistent.
[0103] Please see again Figure 9 Then, perform step S5: remove the hard mask layer 2.
[0104] As an example, the method for removing the hard mask layer 2 includes wet etching with a phosphoric acid solution containing HF, and the protrusion 10 is reduced during the removal of the hard mask layer 2.
[0105] Specifically, the phosphoric acid solution is usually hot phosphoric acid, and the specific temperature can be adjusted according to actual needs, without specific limitations here.
[0106] Please see again Figure 10 Step S6 is performed: a second gate oxide layer 11 is formed in the region where the first gate oxide layer 7 is located. The growth rate of the second gate oxide layer 11 in the middle region of the bowl-shaped recess 8 is faster than the growth rate in the edge region of the bowl-shaped recess 8.
[0107] As an example, the method for forming the second gate oxide layer 11 includes an in-situ water vapor generation method, and the temperature range used when forming the second gate oxide layer 11 is 950℃-1050℃.
[0108] As an example, after the second gate oxide layer 11 is formed, the total thickness of the gate oxide layer composed of the first gate oxide layer 7 and the second gate oxide layer 11 ranges from 1300 angstroms to 1800 angstroms.
[0109] In one embodiment, the second gate oxide layer 11 is grown in situ at 1000°C, resulting in a gate oxide layer with a total thickness of 1500 angstroms.
[0110] As an example, during the growth of the second gate oxide layer 11, the area of the surface oxide layer 5 that is not covered also thickens to some extent.
[0111] It should be noted that before the second gate oxide layer 11 is grown, the first gate oxide layer 7 has the bowl-shaped recess 8, and the bowl-shaped recess 8 has the protrusions 10 at both ends. At this time, since there is a height difference between the edge region and the center region of the first gate oxide layer 7, when the second gate oxide layer 11 is grown, the center region is linear oxide growth (for example, before the oxide layer thickness reaches 1100-1200 angstroms at the center, the oxide layer thickness increases linearly), while the edge region is first linear oxide growth and then oxide polishing growth (the oxide layer thickness increases parabolically). The difference in the growth rates of the two will gradually smooth out the height difference between the edge region and the center region, and the top surface of the gate oxide layer obtained is horizontal or nearly horizontal.
[0112] Specifically, to ensure that the top surface of the final grid oxide layer is horizontal or nearly horizontal, parameters such as the gas supply, time, and temperature of the furnace tube can be adjusted.
[0113] Specifically, the bowl-shaped recess 8 and the protrusions 10 at both ends of the first gate oxide layer 7 are equivalent to providing sidewall isolation for the substrate on both sides of the gate oxide region. This can prevent oxygen from entering the sidewall and contacting Si, thereby inhibiting the oxidation of Si in the source region and improving the "bird's beak effect" caused by partial oxidation of the source region during the gate oxide growth process.
[0114] Specifically, in the two different methods of forming a bowl-shaped recess in the first gate oxide layer, the latter method retains more of the protrusion 10 in subsequent processes and has a denser mass because the sacrificial layer 9 initially protects the area where the protrusion 10 is to be formed. This results in a better blocking effect during the formation of the beak effect, and the resulting beak is smaller or almost negligible.
[0115] Thus, a semiconductor structure comprising a substrate and a gate oxide layer is fabricated, the gate oxide layer being located in a predetermined region on the front side of the substrate. This semiconductor structure can be applied to high-voltage devices or other suitable semiconductor devices.
[0116] In summary, in the semiconductor structure and fabrication method of the present invention, the gate oxide layer is formed by stacking a first gate oxide layer and a second gate oxide layer. Before growing the second gate oxide layer in the region where the first gate oxide layer is located, a bowl-shaped recess is first formed in the first gate oxide layer. The bowl-shaped recess has protrusions at both ends, and the top surface of the protrusions is higher than the bottom surface of the hard mask layer. During the subsequent growth of the second gate oxide layer, the growth rate of the second gate oxide layer in the middle region of the bowl-shaped recess is faster than the growth rate in the edge region of the bowl-shaped recess. The final top surface of the gate oxide layer is horizontal or nearly horizontal. Simultaneously, since the bowl-shaped recess and the protrusions at both ends act as sidewalls to isolate the substrate on both sides of the gate oxide region, oxygen can be prevented from entering the sidewalls and contacting Si, thereby suppressing the oxidation of Si in the source region and improving the "bird's beak effect" caused by partial oxidation of the source region during gate oxide growth. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0117] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, and a hard mask layer is formed on the substrate; An opening is formed in the hard mask layer, and the bottom of the opening exposes the surface of the substrate; A first gate oxide layer is formed on the surface of the substrate exposed by the opening; A bowl-shaped recess is formed in the first gate oxide layer, and the bowl-shaped recess has protrusions at both ends, with the top surface of the protrusions being higher than the bottom surface of the hard mask layer; Remove the hard mask layer; A second gate oxide layer continues to form in the region where the first gate oxide layer is located, and the growth rate of the second gate oxide layer in the middle region of the bowl-shaped depression is faster than the growth rate in the edge region of the bowl-shaped depression.
2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Forming a bowl-shaped recess in the first gate oxide layer includes the following steps: Ion implantation is performed to break some of the Si-O bonds in the first gate oxide layer. The ions used for ion implantation include one or more of Ar ions, Xe ions, and Kr ions. Under the scattering effect of the hard mask layer on both sides of the opening, the bottom of the region of the first gate oxide layer to which ions are implanted is bowl-shaped. The first gate oxide layer is etched by wet etching with a solution containing hydrofluoric acid to obtain the bowl-shaped recess.
3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Forming a bowl-shaped recess in the first gate oxide layer includes the following steps: A sacrificial layer is formed, which covers the hardening mask layer and the first gate oxide layer; The sacrificial layer is subjected to dry anisotropic etching until the upper surface of the hard mask layer and most of the upper surface of the first gate oxide layer are exposed. The hard mask layer and the first gate oxide layer are both over-etched to a certain thickness. A portion of the sacrificial layer remains on the sidewall of the opening. The portion of the first gate oxide layer covered by the remaining sacrificial layer is not over-etched, forming a protrusion. The sacrificial layer remaining on the sidewall of the opening is removed by wet etching, and the bowl-shaped recess located in the first gate oxide layer is obtained.
4. The method for fabricating a semiconductor structure according to claim 1, characterized in that: The sacrificial layer is made of TEOS, and the etching solution used to remove the sacrificial layer remaining on the sidewall of the opening by wet etching includes hydrofluoric acid solution.
5. The method for fabricating a semiconductor structure according to claim 1, characterized in that: The substrate has a surface oxide layer on its upper surface, and the hard mask layer covers the surface oxide layer.
6. The method for fabricating a semiconductor structure according to claim 5, characterized in that: Before the bowl-shaped recess is formed, the top surface of the first gate oxide layer is higher than the top surface of the surface oxide layer.
7. The method for fabricating a semiconductor structure according to claim 6, characterized in that: After the bowl-shaped recess is formed, the top surface of the protrusion is higher than the top surface of the surface oxide layer, and the center of the bottom surface of the bowl-shaped recess is lower than the top surface of the surface oxide layer.
8. The method for fabricating a semiconductor structure according to claim 1, characterized in that: The hard mask layer includes a silicon nitride layer, and the method for removing the hard mask layer includes wet etching with a phosphoric acid solution containing hydrofluoric acid, wherein the protrusions are reduced during the removal of the hard mask layer.
9. The method for fabricating a semiconductor structure according to claim 1, characterized in that, It also includes at least one of the following: (1) The method for forming the first gate oxide layer includes thermal oxidation, and the method for forming the second gate oxide layer includes in-situ water vapor generation, or... (2) The temperature range used to form the first gate oxide layer is 900℃-950℃, and the temperature range used to form the second gate oxide layer is 950℃-1050℃, or... (3) Before the bowl-shaped recess is formed, the thickness of the first gate oxide layer is 300 angstroms to 800 angstroms. After the second gate oxide layer is formed, the total thickness of the gate oxide layer composed of the first gate oxide layer and the second gate oxide layer is 1300 angstroms to 1800 angstroms.
10. A semiconductor structure, characterized in that, include: Substrate; The gate oxide layer is located in a predetermined area on the front side of the substrate; The semiconductor structure is formed using the semiconductor structure fabrication method as described in any one of claims 1-9.