Diamond-gallium nitride phase inverter based on multilayer wiring process and preparation method thereof

Abstract

The invention discloses a diamond-gallium nitride phase inverter based on a multilayer wiring process and a preparation method thereof. The phase inverter comprises a diamond-gallium nitride composite substrate, a gallium nitride HEMT device formed on the front side of the composite substrate, a diamond MOSFET device formed on the back side of the composite substrate and a multilayer interconnection wiring structure. The multi-layer interconnection wiring structure comprises a plurality of through holes formed in a composite substrate; a plurality of through holes respectively penetrate through the whole composite substrate from the lower parts of the electrodes of the gallium nitride HEMT device to the upper parts of the electrodes of the diamond MOSFET device; and the plurality of through holes are filled with metal electroplating liquid so as to realize interconnection between the front and back devices. According to the structural design, the area utilization rate of a chip is improved, the problems of large parasitic parameters, poor reliability, poor high-frequency performance, limited integration level, high cost and the like caused by existing lead bonding and single-face interconnection wiring devices on a composite substrate are solved, and the performance of a circuit system with a higher level is facilitated.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a diamond-gallium nitride inverter based on multilayer wiring technology and its fabrication method. Background Technology

[0002] Diamond and gallium nitride (GaN), as representatives of wide-bandgap semiconductor materials, possess excellent properties such as wide bandgap, high breakdown electric field, and high electron saturation drift velocity, showing great potential in high-power, high-frequency electronic devices. Furthermore, diamond, with the highest known thermal conductivity, is considered an ideal material for solving the heat dissipation problem of GaN devices. Simultaneously, diamond-gaN integrated devices based on wide-bandgap platforms can fully leverage the advantages of wide-bandgap materials, effectively solving the failure problem of traditional silicon-based circuits under extreme environments such as high temperatures when used as peripheral circuits in wide-bandgap semiconductor power electronic systems. The fabrication of inverters, as the smallest unit of power electronic systems, is particularly important.

[0003] Currently, there is limited research on the integration of gallium nitride (GaN) and diamond (GaN) devices both domestically and internationally. Integration is typically achieved using wire bonding technology on discrete devices on different substrates. Wire bonding in discrete devices is a core bonding technology in traditional packaging and is one of the commonly used methods for integrating GaN and diamond devices. It mainly involves connecting the electrodes of the GaN device to the electrodes of the diamond device using bonding wires (such as gold or copper wires) to complete the integration. Furthermore, for monolithically integrated diamond-gaN inverters, single-sided interconnect wiring on a diamond-gaN composite substrate can be used for integration.

[0004] However, the drawbacks of the aforementioned wire bonding technology are becoming increasingly apparent under the demands of high frequency, high power, miniaturization, and high reliability. These drawbacks mainly manifest in larger parasitic parameters, susceptibility to additional heat generation, poor stability, poor mechanical reliability, and limitations in high-frequency applications. Furthermore, single-sided interconnect devices on composite substrates exhibit complex interconnect wiring, high device fabrication difficulty and cost, and limited integration density. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a diamond-gallium nitride inverter based on a multilayer wiring process and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention proposes a diamond-gallium nitride inverter based on a multilayer wiring process, comprising: The diamond-gallium nitride composite substrate comprises, from bottom to top, an intrinsic diamond layer, a buffer layer, a gallium nitride layer, and an aluminum gallium nitride layer; A gallium nitride (GaN) HEMT device, formed on the front side of a composite substrate, includes a first source electrode, a first drain electrode, a first gate electrode, and a first gate dielectric layer. The first gate dielectric layer is located within a gate trench on an aluminum gallium nitride (AGaN) layer and extends to a portion of the AGaN layer surface on both sides of the gate trench. The first gate electrode is located on the first gate dielectric layer within the gate trench. The first source electrode and the first drain electrode are located on the AGaN layers on both sides of the first gate electrode. The entire surface of the GaN HEMT device is also covered with an anti-contamination layer. A diamond MOSFET device is formed on the back side of a composite substrate and includes a second source electrode, a second drain electrode, a second gate electrode, and a second gate dielectric layer. The second gate dielectric layer is located on the lower surface of the intrinsic diamond layer, and the second gate electrode is located on the second gate dielectric layer. The second source electrode and the second drain electrode are respectively located on the lower surface of the intrinsic diamond layer on both sides of the second gate electrode. The second source electrode, the second drain electrode, and the second gate electrode are respectively disposed in a direction perpendicular to the first source electrode, the first drain electrode, and the first gate electrode along the vertical direction of the composite substrate. The multilayer interconnect wiring structure includes multiple vias disposed on a composite substrate; the multiple vias extend from below each electrode of the gallium nitride HEMT device through the entire composite substrate to above each electrode of the diamond MOSFET device; and the multiple vias are filled with metal plating solution to achieve interconnection between the gallium nitride HEMT device and the diamond MOSFET device.

[0006] Secondly, this invention proposes a method for fabricating a diamond-gallium nitride inverter based on a multilayer wiring process, comprising: S1. Obtain a diamond-gallium nitride composite substrate and perform pretreatment; wherein, from bottom to top, the composite substrate includes an intrinsic diamond layer, a buffer layer, a gallium nitride layer and an aluminum gallium nitride layer; S2. Fabricate gallium nitride HEMT devices on the front side of the pretreated composite substrate; S3. Deposit an anti-contamination layer on the surface of the gallium nitride HEMT device; S4. Etch multiple vias on the composite substrate and fill each via with a metal plating solution to form a multilayer interconnect wiring structure; wherein, the multiple vias are located below each electrode of the gallium nitride HEMT device and penetrate the entire composite substrate. S5. The intrinsic diamond layer on the back side of the composite substrate is treated with a hydrogen plasma atmosphere to form a hydrogen-terminated surface. S6. Using multiple via locations as references for each electrode of the diamond MOSFET device, and combining alignment photolithography, a diamond MOSFET device is fabricated on the hydrogen-terminated surface on the back side of the composite substrate, thereby realizing a diamond-gallium nitride inverter based on a multilayer wiring process.

[0007] The beneficial effects of this invention are: This invention provides a diamond-gallium nitride (GaN) inverter based on a multilayer wiring process and its fabrication method. The inverter includes a diamond-gallium nitride composite substrate, a GaN HEMT device formed on the front side of the composite substrate, a diamond MOSFET device formed on the back side of the composite substrate, and a multilayer interconnect wiring structure. The multilayer interconnect wiring structure includes multiple vias disposed on the composite substrate. These vias extend from below each electrode of the GaN HEMT device through the entire composite substrate to above each electrode of the diamond MOSFET device. The vias are filled with a metal plating solution to achieve interconnection between the GaN HEMT device and the diamond MOSFET device. This structural design fully utilizes the area of ​​the composite substrate and combines the processes of classic planar diamond and gallium nitride devices. It employs a through-hole metal filling process to achieve interconnection between the front and back devices. This not only enables low-cost device development but also achieves a comprehensive breakthrough in the device's thermo-electro-mechanical performance, specifically manifested in: 1. Reducing parasitic parameters, improving heat dissipation, and supporting ultra-high power density; 2. Combining high-frequency and high-voltage performance, broadening application scenarios; 3. Significantly enhanced reliability, enabling adaptation to extreme environments; 4. Three-dimensional integration potential, promoting system miniaturization.

[0008] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0009] Figure 1 A schematic diagram of a diamond-gallium nitride inverter based on multilayer wiring technology provided in an embodiment of the present invention; Figure 2 A schematic flowchart illustrating the fabrication method of a diamond-gallium nitride inverter based on multilayer wiring technology provided in an embodiment of the present invention; Figure 3A-3M A process diagram illustrating the fabrication of a diamond-gallium nitride inverter based on a multilayer wiring process is provided for an embodiment of the present invention. Explanation of reference numerals in the attached figures: 1-Intrinsic diamond layer; 2-Gallium nitride layer; 3-Aluminum gallium nitride layer; 4-Buffer layer; 5a-First drain electrode; 5b-First source electrode; 6-First gate dielectric layer; 7-First gate electrode; 8-Anti-contamination layer; 9-Etching mask layer; 10a-Second drain electrode; 10b-Second source electrode; 11-Second gate dielectric layer; 12-Second gate electrode. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] A first aspect of this invention provides a diamond-gallium nitride inverter based on a multilayer wiring process. See also... Figure 1 , Figure 1 This is a schematic diagram of a diamond-gallium nitride inverter based on multilayer wiring technology provided in an embodiment of the present invention. The inverter includes: The diamond-gallium nitride composite substrate comprises, from bottom to top, an intrinsic diamond layer 1, a buffer layer 4, a gallium nitride layer 2, and an aluminum gallium nitride layer 3; A gallium nitride (GaN) HEMT device is formed on the front side of a composite substrate and includes a first source electrode 5b, a first drain electrode 5a, a first gate electrode 7, and a first gate dielectric layer 6. The first gate dielectric layer 6 is located in a gate trench on an aluminum gallium nitride (AGaN) layer 3 and extends to a portion of the AGaN layer 3 surface on both sides of the gate trench. The first gate electrode 7 is located on the first gate dielectric layer 6 within the gate trench. The first source electrode 5b and the first drain electrode 5a are located on the AGaN layer 3 on both sides of the first gate electrode 7, respectively. The entire surface of the GaN HEMT device is also covered with an anti-contamination layer 8. A diamond MOSFET device is formed on the back side of a composite substrate and includes a second source electrode 10b, a second drain electrode 10a, a second gate electrode 12, and a second gate dielectric layer 11. The second gate dielectric layer 11 is located on the lower surface of the intrinsic diamond layer 1, and the second gate electrode 12 is located on the second gate dielectric layer 11. The second source electrode 10b and the second drain electrode 10a are respectively located on the lower surface of the intrinsic diamond layer 1 on both sides of the second gate electrode 12. The second source electrode 10b, the second drain electrode 10a, and the second gate electrode 12 are respectively disposed in a direction perpendicular to the first source electrode 5b, the first drain electrode 5a, and the first gate electrode 7 along the vertical direction of the composite substrate. The multilayer interconnect wiring structure includes multiple vias disposed on a composite substrate; the multiple vias extend from below each electrode of the gallium nitride HEMT device through the entire composite substrate to above each electrode of the diamond MOSFET device; and the multiple vias are filled with metal plating solution to achieve interconnection between the gallium nitride HEMT device and the diamond MOSFET device.

[0012] Specifically, the thickness of the composite substrate is generally selected to be 48-52 μm, preferably 50 μm.

[0013] It is understood that in this embodiment, isolation structures are provided outside the active regions of both the gallium nitride HEMT device on the front side of the composite substrate and the diamond MOSFET device on the back side of the composite substrate; wherein, the gallium nitride HEMT device uses trench isolation, and the diamond MOSFET device uses ICP-RIE oxygen isolation, such as... Figure 1 As shown.

[0014] Optionally, as one implementation, the first source electrode 5b and the first drain electrode 5a, i.e., the source and drain electrodes of the gallium nitride HEMT device, can be made of a combination of metals Ti / Al / Ni / Au, with a reference thickness of 20 / 100 / 40 / 50 nm. The first gate dielectric layer 6, i.e., the gate dielectric layer of the gallium nitride HEMT device, can be made of Al2O3 material with a thickness of 10-25 nm. The first gate electrode 7, i.e., the gate electrode of the gallium nitride HEMT device, can be made of a Ni / Au alloy with a reference thickness of 20 / 100 nm.

[0015] In addition, the anti-contamination layer 8 of the gallium nitride HEMT device, also called the passivation layer or process protection layer in this embodiment, can be an Al2O3 layer of 10-20nm.

[0016] Furthermore, for the second source electrode 10b and the second drain electrode 10a, i.e., the source and drain electrodes of the diamond MOSFET device, an 80-100 nm gold thin film layer can be used. For the second gate dielectric layer 11, i.e., the gate dielectric layer of the diamond MOSFET device, Al2O3 material with a thickness of 10-25 nm can be used. For the second gate electrode 12, i.e., the gate electrode of the diamond MOSFET device, an aluminum thin film with a thickness of 100 nm can be used.

[0017] In addition, it should be noted that in the multilayer interconnect wiring structure, the diameter of multiple vias is 50-70μm; the metal plating solution is one of copper plating solution, nickel plating solution, tin plating solution, and gold plating solution, with copper plating solution being preferred. This ensures connection reliability and provides multi-dimensional heat dissipation pathways.

[0018] This embodiment provides a diamond-gallium nitride (GaN) inverter based on multilayer wiring technology, comprising a GaN composite substrate, a GaN HEMT device formed on the front side of the composite substrate, a diamond MOSFET device formed on the back side of the composite substrate, and a multilayer interconnect wiring structure. The multilayer interconnect wiring structure includes multiple vias disposed on the composite substrate. These vias extend from below each electrode of the GaN HEMT device through the entire composite substrate to above each electrode of the diamond MOSFET device. The vias are filled with a metal plating solution to achieve interconnection between the GaN HEMT device and the diamond MOSFET device. This structural design utilizes a multilayer metal wiring structure to achieve interconnection between the front and back devices, improving chip area utilization and avoiding the problems of large parasitic parameters, poor reliability, poor high-frequency performance, limited integration, and high cost associated with existing wire bonding and single-sided interconnect wiring devices on composite substrates. It also increases the multi-dimensional heat dissipation pathways of metal wires such as copper, contributing to higher-level circuit system performance.

[0019] Based on the same inventive concept, a second aspect of this invention also provides a method for fabricating a diamond-gallium nitride inverter based on a multilayer wiring process. Please refer to the following: Figure 2 and Figure 3A-3M , Figure 2 A schematic flowchart illustrating the fabrication method of a diamond-gallium nitride inverter based on multilayer wiring technology provided in an embodiment of the present invention; Figure 3A-3M This is a process diagram illustrating the fabrication of a diamond-gallium nitride inverter based on a multilayer wiring process, provided for an embodiment of the present invention.

[0020] The method for fabricating a diamond-gallium nitride inverter based on multilayer wiring technology provided in this embodiment mainly includes the following steps: S1. Obtain the diamond-gallium nitride composite substrate and perform pretreatment.

[0021] Optionally, in this embodiment, the diamond-gallium nitride composite substrate comprises, from bottom to top, an intrinsic diamond layer 1, a buffer layer 4, a gallium nitride layer 2, and an aluminum gallium nitride layer 3. Pretreatment of the composite substrate mainly includes thinning, inorganic surface cleaning, and organic surface cleaning.

[0022] Specifically, the composite substrate is first thinned and flattened by chemical mechanical polishing or back-side grinding to control the thickness of the composite substrate to 48-52 μm, preferably 50 μm. Then, the composite substrate is immersed in BOE solution for 30 seconds, and finally ultrasonically cleaned in acetone, anhydrous ethanol and deionized water for 15 minutes in sequence.

[0023] S2. Gallium nitride HEMT devices are fabricated on the front side of the pretreated composite substrate.

[0024] Alternatively, as one implementation method, S2 can be implemented according to the following steps S21-S25.

[0025] S21. The aluminum gallium nitride layer 3 and gallium nitride layer 2 on the front side of the pretreated composite substrate are etched to form electrical isolation outside the active region of the device and leave groove photolithographic alignment marks.

[0026] Specifically, firstly, AZ6130 photoresist was uniformly coated as a photoresist mask on the aluminum gallium nitride (AGaN) layer 3 of the composite substrate. The pre-baking temperature was 90℃ for 90 seconds, the exposure time was 2.2 seconds, and the development time was 45 seconds. Next, dry etching (ICP-RIE) with chlorine-based gas (Cl2 / BCl3) plasma was used to etch down to the gallium nitride layer 2. Then, the photoresist was washed away with acetone. The etching depth and the depth of the groove photolithographic markings were 1-5 μm to ensure that the optical detection system could recognize them. Figure 3A As shown.

[0027] S22. Ohmic metal electrodes are deposited in the source and drain regions of the gallium nitride HEMT device to form a first source electrode 5b and a first drain electrode 5a.

[0028] Specifically, firstly, AZ5214 is uniformly coated onto the sample surface obtained in S21 as a photoresist mask, and dried at 100℃ for 150s. Using a UV lithography machine, the source and drain regions are exposed through the pattern of the mask for 3.3s. Subsequently, the area is developed in a positive developer for 45s, exposing the exposed region. Ohmic metal is deposited using an electron beam evaporation device, with the alloy layer being a Ti / Al / Ni / Au stack with a reference thickness of 20 / 100 / 40 / 50nm. Excess metal is removed using acetone solution. Next, annealing is performed in a rapid thermal annealing device to optimize the ohmic contacts. The annealing temperature is 800-900℃ under a nitrogen atmosphere for 3-5 minutes, obtaining the source and drain metals of the gallium nitride HEMT device, namely the first source electrode 5b and the first drain electrode 5a, as shown below. Figure 3B As shown.

[0029] S23. The aluminum gallium nitride layer 3 below the gate region of the gallium nitride HEMT device is etched to form a gate trench.

[0030] Specifically, a layer of photoresist AZ6130 is uniformly coated in the region below the gate and dried at 90°C for 90 seconds. A pattern is then left in the predetermined etching location region under the gate using a UV lithography machine through a mask gate pattern. Next, etching is performed using ICP-RIE plasma chlorine gas, with a chlorine flow rate of 50-70 sccm, process parameters of ICP power 100-200W, RF bias power 20-50W, temperature 10-20°C, and etching time 6 minutes, to form a gate trench on the aluminum gallium nitride layer 3 between the source and drain electrodes. Figure 3CAs shown.

[0031] S24. Deposit the first gate dielectric layer 6 above the gate trench.

[0032] Specifically, on the material obtained in S23, an Al2O3 layer with a thickness of 10nm to 25nm is deposited above the gate trench using an atomic layer deposition process at a temperature of 150℃ to 300℃ to form the first gate dielectric layer 6, as shown below. Figure 3D As shown.

[0033] S25. Deposit gate metal above the first gate dielectric layer 6 to form the first gate electrode 7, thereby completing the fabrication of the front-side gallium nitride HEMT device on the composite substrate.

[0034] Specifically, a layer of photoresist AZ5214 is uniformly coated onto the front substrate surface of the material obtained in S24, dried at 100°C for 150 seconds, and exposed to the gate location region using a UV lithography machine through a mask pattern for 3.3 seconds. Subsequently, it is developed in a positive developer for 45 seconds to expose the exposed area. A Ni / Au alloy layer with a thickness of 20 / 100 nm is deposited by electron beam evaporation as the gate metal, obtaining the gate metal of the gallium nitride HEMT device, i.e., the first gate electrode 7. Figure 3E As shown.

[0035] This completes the fabrication of the front-side gallium nitride HEMT device on the composite substrate.

[0036] S3. Deposit an anti-contamination layer 8 on the surface of the gallium nitride HEMT device.

[0037] Specifically, an Al2O3 layer is deposited on the surface of a gallium nitride HEMT device using atomic layer deposition equipment, serving as both a passivation layer and an anti-contamination layer. Figure 3F As shown in the figure. The thickness of the Al2O3 layer is 10-20 nm, and the deposition temperature is 300-400℃.

[0038] S4. Etch multiple vias on the composite substrate and fill each via with a metal plating solution to form a multilayer interconnect wiring structure; wherein, the multiple vias are located below each electrode of the gallium nitride HEMT device and penetrate the entire composite substrate.

[0039] Alternatively, as one implementation method, S4 can be implemented according to the following steps S41-S44.

[0040] S41. A SiO2 dielectric layer is deposited on the intrinsic diamond layer on the back side of the composite substrate as a diamond surface etching mask layer 9.

[0041] Specifically, firstly, a dense SiO2 dielectric layer with a thickness of 2 μm is deposited using a PECVD equipment as an etching mask layer 9; then, via patterns are created on the surface of the dielectric layer using 6130 photoresist; next, vias are formed using CF4 / O2 (50 / 20 sccm) plasma gas ICP-RIE etching. The ICP power is 150-300 W, the RF bias power is 30-50 W, and the temperature is 10-20 °C.

[0042] S42. The composite substrate is etched using photolithography and dry etching processes to form multiple vias; wherein the multiple vias are located below each electrode of the gallium nitride HEMT device and penetrate the entire composite substrate.

[0043] Specifically, RIE plasma etching is employed, with process conditions of 100-200W ICP power, 50-100W RF power, 5-10℃ temperature, and 2-5mTorr pressure. The gallium nitride substrate region uses Cl2 / BCl3 (20 / 10 sccm) gas, and the diamond substrate region uses O2 (30-40 sccm) gas. Subsequently, annealing is performed in a nitrogen atmosphere at 600-800℃ to form multiple vias.

[0044] Among them, the diameter of multiple through holes is 50-70μm.

[0045] It should be noted that, in order to save time and cost, femtosecond laser can be used to prepare the through-hole in step S42, as follows: The preset through-hole positions are processed using an ultra-short pulse (pulse width < 1ps) ultraviolet laser with an energy density of 1-10J / cm2 and a repetition frequency of 10kHz-1MHz. Oxygen-assisted processing is used to remove residual graphite.

[0046] S43. Fill multiple through holes and grooves with metal plating solution, such as Figure 3G As shown.

[0047] The metal plating solution can be one of copper plating solution, nickel plating solution, tin plating solution, or gold plating solution.

[0048] Specifically, taking copper electroplating solution as an example, the sample is placed in the copper electroplating solution and pulse electroplating is performed to reduce tip deposition. The components of the electroplating solution are copper sulfate (Cu2+ source), sulfuric acid (to improve conductivity), and Cl- (to promote anodic dissolution). The current density is optimized to 0.5-2A / dm2, and the temperature is controlled at 20-50℃.

[0049] S44. Remove the etched mask layer and perform chemical mechanical polishing to smooth the surface, thereby forming a multilayer interconnect wiring structure.

[0050] Specifically, the sample is placed in BOE solution for 1-2 minutes to completely remove the SiO2 mask layer, and excess copper on the surface is removed by chemical mechanical polishing (CMP) to ensure flatness. Figure 3H As shown.

[0051] S5. The intrinsic diamond layer on the back side of the composite substrate is treated with a hydrogen plasma atmosphere to form a hydrogen-terminated surface.

[0052] Specifically, the intrinsic diamond layer on the back side of the composite substrate is treated with a hydrogen plasma atmosphere under the preset MPCVD chamber conditions to form a hydrogen-terminated surface; wherein the preset MPCVD chamber conditions are: hydrogen flow rate of 100 sccm-200 sccm, methane flow rate of 5 sccm-10 sccm, temperature of 600℃-800℃, chamber pressure of 140 mbar-160 mbar, and time of 10 min-30 min.

[0053] S6. Using multiple via locations as references for each electrode of the diamond MOSFET device, and combining alignment photolithography, a diamond MOSFET device is fabricated on the hydrogen-terminated surface on the back side of the composite substrate, thereby realizing a diamond-gallium nitride inverter based on a multilayer wiring process.

[0054] Alternatively, as one implementation method, S6 can be implemented according to the following steps S61-S64.

[0055] S61. Using multiple via locations as references for each electrode of the diamond MOSFET device, ohmic metal electrodes are deposited on the source and drain regions of the diamond MOSFET device on the hydrogen terminal surface to form a second source electrode 10b and a second drain electrode 10a.

[0056] Specifically, an 80-100 nm gold thin film is first deposited on the diamond surface with a hydrogen-terminated conductive layer using a thermal evaporation process. Then, photoresist AZ6112 is uniformly coated and dried at 90°C for 100 seconds. The non-source / drain electrode patterns on the mask are exposed using ultraviolet lithography. Afterward, the mask is immersed in a KI / I2 solution for 3-6 seconds to remove the gold thin film at the non-source / drain locations, leaving the source / drain electrode metals to form the source and drain electrodes of the diamond MOSFET device, namely the second source electrode 10b and the second drain electrode 10a. Figure 3I As shown.

[0057] S62. Apply oxygen plasma treatment to the active region outside the hydrogen terminal surface to form device isolation.

[0058] Specifically, a layer of photoresist AZ6130 is uniformly coated on the active region of the intrinsic diamond layer 1 surface and dried at 90°C for 90 seconds. A photoresist mask is then applied to the predetermined location area using a UV lithography machine through a MESA mask pattern. Finally, device isolation is formed using ICP-RIE oxygen isolation. Figure 3J As shown. The process conditions are: ICP power 100W-150W, RF power 20-30W, time 10-15s.

[0059] S63. A second gate dielectric layer 11 is deposited on the intrinsic diamond layer 1 on the back side of the composite substrate.

[0060] Specifically, the channel surface is treated with ozone, and then an Al2O3 layer with a thickness of 10nm~25nm is deposited using atomic layer deposition at a temperature of 150℃-400℃ as the second gate dielectric layer 11. Figure 3K As shown.

[0061] S64. Use low-power Cl-based gases (Cl2 and BCl3) from ICP to etch the second gate dielectric layer 11 to form a multilayer interconnect structure with reserved vias.

[0062] Specifically, firstly, a layer of photoresist AZ6130 is uniformly coated on the surface of the intrinsic diamond layer 1 having the second gate dielectric layer 11, and dried at 90°C for 90 seconds. Using an ultraviolet lithography machine, a photoresist mask is left in a predetermined location area through a MESA pattern mask. Then, ICP etching is performed to form the etched area, which serves as the reserved via location for multilayer interconnects, such as... Figure 3L As shown. The through-hole size is consistent with that obtained in step S4. The process conditions are: ICP power 50-60W, RF power 0, and time 2min.

[0063] S65. Deposit gate metal on the second gate dielectric layer 11 to form the second gate electrode 12, fill the reserved via formed in S64, and connect the multilayer interconnect structure formed in step S4 with the second gate electrode 12, thereby completing the fabrication of the composite substrate back-side diamond MOSFET device.

[0064] Specifically, firstly, a layer of photoresist AZ5214 is uniformly coated on the surface of the intrinsic diamond layer 1 having the second gate dielectric layer 11, and then dried at 110°C for 130 seconds; then, a pattern is left in the preset gate position area through the gate pattern of the mask using an ultraviolet lithography machine, and then aluminum is deposited by electron beam evaporation with a thickness of 100 nm to obtain the gate metal of the diamond MOSFET device, that is, the second gate electrode 12, as shown below. Figure 3M As shown, this completes the fabrication of a diamond MOSFET device on the back side of a composite substrate.

[0065] Through the above steps, the fabrication of a diamond-gallium nitride inverter based on multilayer wiring technology was completed. This method replaces wire bonding with a through-hole filling metal process to achieve interconnection between diamond and gallium nitride devices. Furthermore, the classic planar device process was used to fabricate devices on both the front and back sides of the composite substrate, which greatly improved the device integration.

[0066] The method for fabricating diamond-gallium nitride inverters based on multilayer wiring technology provided by this invention makes full use of the area of ​​the composite substrate. Combining the classic planar diamond and gallium nitride device processes, the interconnection between the front and back devices is achieved using a through-hole metal filling process. This not only enables low-cost device development but also achieves a comprehensive breakthrough in the device's thermo-electro-mechanical performance, specifically manifested in: 1. Reducing parasitic parameters, improving heat dissipation capacity, and supporting ultra-high power density; 2. Combining high-frequency and high-voltage performance, broadening application scenarios; 3. Significantly enhanced reliability, adapting to extreme environments; 4. Three-dimensional integration potential, promoting system miniaturization.

[0067] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0068] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0069] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0070] In the description of this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0071] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A diamond-gallium nitride inverter based on multilayer wiring technology, characterized in that, include: The diamond-gallium nitride composite substrate comprises, from bottom to top, an intrinsic diamond layer, a buffer layer, a gallium nitride layer, and an aluminum gallium nitride layer; A gallium nitride (GaN) HEMT device, formed on the front side of the composite substrate, includes a first source electrode, a first drain electrode, a first gate electrode, and a first gate dielectric layer; the first gate dielectric layer is located within a gate trench on the aluminum gallium nitride layer and extends to a portion of the aluminum gallium nitride layer surface on both sides of the gate trench; the first gate electrode is located on the first gate dielectric layer within the gate trench; the first source electrode and the first drain electrode are respectively located on the aluminum gallium nitride layer on both sides of the first gate electrode; the entire surface of the GaN HEMT device is also covered with an anti-fouling layer; A diamond MOSFET device is formed on the back side of the composite substrate and includes a second source electrode, a second drain electrode, a second gate electrode, and a second gate dielectric layer. The second gate dielectric layer is located on the lower surface of the intrinsic diamond layer, and the second gate electrode is located on the second gate dielectric layer. The second source electrode and the second drain electrode are respectively located on the lower surface of the intrinsic diamond layer on both sides of the second gate electrode. The second source electrode, the second drain electrode, and the second gate electrode are respectively disposed corresponding to the first source electrode, the first drain electrode, and the first gate electrode along the vertical direction of the composite substrate. A multilayer interconnect wiring structure includes a plurality of vias disposed on the composite substrate; the plurality of vias extend from below each electrode of the gallium nitride HEMT device through the entire composite substrate to above each electrode of the diamond MOSFET device; and the plurality of vias are filled with a metal plating solution to achieve interconnection between the gallium nitride HEMT device and the diamond MOSFET device.

2. The diamond-gallium nitride inverter based on multilayer wiring technology according to claim 1, characterized in that, The diameter of the plurality of through holes is 50-70 μm; the metal plating solution is one of copper plating solution, nickel plating solution, tin plating solution, and gold plating solution.

3. A method for fabricating a diamond-gallium nitride inverter based on a multilayer wiring process, characterized in that, include: S1. Obtain a diamond-gallium nitride composite substrate and perform pretreatment; wherein, the composite substrate comprises, from bottom to top, an intrinsic diamond layer, a buffer layer, a gallium nitride layer and an aluminum gallium nitride layer; S2. Fabricate gallium nitride HEMT devices on the front side of the pretreated composite substrate; S3. Deposit an anti-contamination layer on the surface of the gallium nitride HEMT device; S4. A plurality of vias are etched on the composite substrate, and a metal plating solution is filled into each via to form a multilayer interconnect wiring structure; wherein the plurality of vias are located below each electrode of the gallium nitride HEMT device and penetrate the entire composite substrate. S5. The intrinsic diamond layer on the back side of the composite substrate is subjected to hydrogen plasma atmosphere treatment to form a hydrogen-terminated surface. S6. Using the locations of the multiple vias as references for each electrode of the diamond MOSFET device, and combining alignment photolithography, a diamond MOSFET device is fabricated on the hydrogen-terminated surface on the back side of the composite substrate, thereby realizing a diamond-gallium nitride inverter based on a multilayer wiring process.

4. The method for fabricating a diamond-gallium nitride inverter based on multilayer wiring technology according to claim 3, characterized in that, S1 includes: The composite substrate is thinned and flattened by chemical mechanical polishing or back-side grinding to control the thickness of the composite substrate to 48-52 μm; then the composite substrate is immersed in BOE solution for 30s, and then ultrasonically cleaned in acetone, anhydrous ethanol and deionized water for 15min in sequence.

5. The method for fabricating a diamond-gallium nitride inverter based on multilayer wiring technology according to claim 3, characterized in that, S2 include: S21. Etch the aluminum gallium nitride layer and gallium nitride layer on the front side of the pretreated composite substrate to form electrical isolation outside the active region of the device and leave groove photolithographic alignment marks. S22. Ohmic metal electrodes are deposited in the source and drain regions of the gallium nitride HEMT device to form the first source electrode and the first drain electrode, respectively. S23. Etch the aluminum gallium nitride layer below the gate region of the gallium nitride HEMT device to form a gate trench; S24. Deposit a first gate dielectric layer above the gate trench; S25. Deposit gate metal above the first gate dielectric layer to form the first gate electrode, thereby completing the fabrication of the front-side gallium nitride HEMT device on the composite substrate.

6. The method for fabricating a diamond-gallium nitride inverter based on multilayer wiring technology according to claim 3, characterized in that, S3 include: An Al2O3 layer is deposited on the surface of the gallium nitride HEMT device using an atomic layer deposition apparatus as a passivation layer and anti-contamination layer for the device.

7. The method for fabricating a diamond-gallium nitride inverter based on multilayer wiring technology according to claim 3, characterized in that, S4 include: S41. A SiO2 dielectric layer is deposited on the intrinsic diamond layer on the back side of the composite substrate as a diamond surface etching mask layer. S42. The composite substrate is etched using photolithography and dry etching processes to form multiple vias; wherein the multiple vias are located below each electrode of the gallium nitride HEMT device and penetrate the entire composite substrate; S43. Fill the plurality of through holes and grooves with metal electroplating solution; S44. Remove the etched mask layer and perform chemical mechanical polishing to flatten the surface, thereby forming a multilayer interconnect wiring structure.

8. The method for fabricating a diamond-gallium nitride inverter based on multilayer wiring technology according to claim 7, characterized in that, In S42, the diameter of the plurality of through holes is 50-70 μm; in S43, the metal plating solution is one of copper plating solution, nickel plating solution, tin plating solution, and gold plating solution.

9. The method for fabricating a diamond-gallium nitride inverter based on multilayer wiring technology according to claim 3, characterized in that, S5 include: The intrinsic diamond layer on the back side of the composite substrate was subjected to hydrogen plasma atmosphere treatment under MPCVD preset chamber conditions; wherein the MPCVD preset chamber conditions were: hydrogen flow rate 100 sccm-200 sccm, methane flow rate 5 sccm-10 sccm, temperature 600℃-800℃, chamber pressure 140 mbar-160 mbar, and time 10 min-30 min.

10. The method for fabricating a diamond-gallium nitride inverter based on multilayer wiring technology according to claim 3, characterized in that, S6 include: S61. Using the locations of the multiple vias as references for each electrode of the diamond MOSFET device, an ohmic metal electrode is deposited in the source and drain regions of the diamond MOSFET device on the surface of the hydrogen terminal to form a second source electrode and a second drain electrode. S62. Perform oxygen plasma treatment on the active region outside the surface of the hydrogen terminal to form device isolation; S63. Deposit a second gate dielectric layer on the intrinsic diamond layer on the back side of the composite substrate; S64. Use ICP low-power Cl-based gas to etch the second gate dielectric layer to form a multilayer interconnect structure with reserved vias; S65. Deposit gate metal on the second gate dielectric layer to form the second gate electrode, fill the reserved via formed in S64, and connect the multilayer interconnect structure formed in S4 with the second gate electrode to complete the fabrication of the composite substrate back-side diamond MOSFET device.

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