Semiconductor structure, preparation method of semiconductor structure, device and electronic equipment

Abstract

The invention provides a semiconductor structure, a preparation method of the semiconductor structure, a device and electronic equipment. The semiconductor structure includes: a first transistor; a second transistor; the first transistor and the second transistor are vertical field effect transistors; a gate lead-out structure; the grid leading-out structure is connected with the grid of the semiconductor structure and the front back-end interconnection layer of the semiconductor structure, or the grid leading-out structure is connected with the grid of the semiconductor structure and the back back-end interconnection layer of the semiconductor structure; wherein in the first direction, the projection of the gate lead-out structure does not coincide with the projection of the first source drain of the first transistor and the projection of the second source drain of the second transistor, and the projection of the gate lead-out structure does not coincide with the projection of the first region; the first region is located between the first source drain and the second source drain, and the first direction is the direction from the front back-end interconnection layer to the back back-end interconnection layer. According to the semiconductor structure provided by the invention, the size miniaturization of the semiconductor structure can be realized.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a semiconductor structure, a method for preparing the semiconductor structure, a device, and an electronic device. Background Technology

[0002] Vertical field-effect transistors (VFETs) effectively improve transistor integration density and performance by conducting current in the vertical direction of the semiconductor material. However, further miniaturizing the semiconductor structure formed by VFETs remains a pressing issue. Summary of the Invention

[0003] This application provides a semiconductor structure, a method for fabricating the semiconductor structure, a device, and an electronic device, which can achieve miniaturization of the semiconductor structure.

[0004] In a first aspect, this application provides a semiconductor structure, including: a first transistor; a second transistor; the first transistor and the second transistor are vertical field-effect transistors; the first transistor and the second transistor are disposed adjacent to each other; a gate lead-out structure; the gate lead-out structure connects the gate of the semiconductor structure and the front-side back-channel interconnect layer of the semiconductor structure, or the gate lead-out structure connects the gate of the semiconductor structure and the back-side back-channel interconnect layer of the semiconductor structure; wherein, in a first direction, the projection of the gate lead-out structure does not coincide with the projection of the first source / drain of the first transistor and the projection of the second source / drain of the second transistor, and the projection of the gate lead-out structure does not coincide with the projection of a first region; the first region is located between the first source / drain and the second source / drain, and the first direction is the direction from the front-side back-channel interconnect layer to the back-side back-channel interconnect layer.

[0005] In some possible implementations, the gate includes a first gate in a first transistor, a second gate in a second transistor, and a gate interconnect structure; wherein the gate interconnect structure is located between the first gate and the second gate, and the two ends of the gate interconnect structure are respectively connected to the first gate and the second gate.

[0006] In some possible implementations, the front-side back-end interconnect layer includes: a first front-side metal layer and a second front-side metal layer; the first front-side metal layer includes a first front-side power rail, a plurality of first front-side signal lines, and a second front-side power rail; the first front-side power rail and the second front-side power rail are symmetrically arranged on both sides of the plurality of first front-side signal lines; the second front-side metal layer includes a plurality of second front-side signal lines.

[0007] In some possible implementations, the first source drain includes a first front source drain, and the second source drain includes a second front source drain; at least two of the plurality of first front signal lines are connected to the first front source drain and the second front source drain via a first front back interconnect; the first front signal line connecting the first front source drain and the second front source drain is connected to the second front signal line via a second front back interconnect.

[0008] In some possible implementations, the back-side interconnect layer includes: a first back-side metal layer and a second back-side metal layer; the first back-side metal layer includes a first back-side power rail, a plurality of first back-side signal lines, and a second back-side power rail; the first back-side power rail and the second back-side power rail are symmetrically arranged on both sides of the plurality of first back-side signal lines; the second back-side metal layer includes a plurality of second back-side signal lines.

[0009] In some possible implementations, the first source drain further includes a first back-side source drain, and the second source drain further includes a second back-side source drain; the first back-side source drain is connected to the first back-side power rail via a first back-side back-end interconnect; and the second back-side source drain is connected to the second back-side power rail via the first back-side back-end interconnect.

[0010] In some possible implementations, the gate lead structure is connected to one of a plurality of first front signal lines; or, the gate lead structure is connected to one of a plurality of first back signal lines.

[0011] In a second aspect, this application provides a method for fabricating a semiconductor structure, used to fabricate the semiconductor structure as described in the first aspect. The method includes: forming a fin structure on a substrate; the fin structure including a front fin structure and a back fin structure stacked together; forming a gate of a semiconductor structure based on the fin structure; forming a first front source drain of a first transistor and a second front source drain of a second transistor based on the front fin structure; performing back-end processes on the first and second front source drains to form a front-end back-end interconnect layer; wafer flipping and thinning the substrate; forming a first back-end source drain of the first transistor and a second back-end source drain of the second transistor based on the back fin structure; and performing back-end processes on the first and second back-end source drains to form a front-end back-end interconnect layer; wafer flipping and thinning the substrate; and forming a first back-end source drain of the first transistor and a second back-end source drain of the second transistor based on the back fin structure; and performing back-end processes on the first and second back-end source drains. The method further includes performing back-end processes on the source and drain to form a back-end back-end interconnect layer; the method also includes forming a gate lead structure during the formation of the front-end back-end interconnect layer; the two ends of the gate lead structure are respectively connected to the gate and the front-end back-end interconnect layer; or, during the formation of the back-end back-end interconnect layer, forming a gate lead structure, the two ends of the gate lead structure are respectively connected to the gate and the back-end back-end interconnect layer; wherein, in a first direction, the projection of the gate lead structure does not coincide with the projection of the front-end source and drain, and the projection of the gate lead structure does not coincide with the projection of the first region; the first region is located between the first front-end source and drain and the second front-end source and drain, and the first direction is the direction from the front-end back-end interconnect layer to the back-end back-end interconnect layer.

[0012] Thirdly, this application provides a semiconductor device, which includes a semiconductor structure as described in the above embodiments.

[0013] Fourthly, this application provides an electronic device comprising: a circuit board and a semiconductor device as described in the above embodiments, the semiconductor device being disposed on the circuit board.

[0014] In this application, by placing the gate lead-out structure on the side of the channel and avoiding the first source drain, the second source drain, and the position between the first source drain and the second source drain, the distance between the first transistor and the second transistor can be shortened, thereby achieving miniaturization of the semiconductor structure and improving integration.

[0015] Furthermore, the gate lead-out structure can be positioned on the front or back of the semiconductor structure; or, depending on the actual situation, the gate lead-out structure can be positioned near the first gate or the second gate; the various positions of the gate lead-out structure inside the semiconductor make the wiring inside the semiconductor more flexible.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] Figure 1 This is a schematic diagram of a standard unit structure in an embodiment of this application;

[0019] Figure 2 This is a first design layout of the semiconductor structure in the embodiments of this application;

[0020] Figure 3 This is a first schematic diagram of a semiconductor structure in an embodiment of this application;

[0021] Figure 4 This is a second design layout of the semiconductor structure in the embodiments of this application;

[0022] Figure 5 This is a second schematic diagram of the semiconductor structure in the embodiments of this application;

[0023] Figure 6 This is a third design layout of the semiconductor structure in the embodiments of this application;

[0024] Figure 7 This is a third schematic diagram of the semiconductor structure in the embodiments of this application;

[0025] Figure 8 This is a fourth design layout of the semiconductor structure in the embodiments of this application;

[0026] Figure 9 This is a fourth schematic diagram of the semiconductor structure in the embodiments of this application;

[0027] Figure 10 This is a schematic diagram illustrating one implementation process of the semiconductor structure fabrication method in this application.

[0028] The above images:

[0029] 10. Semiconductor structure; 11. First transistor; 111. First gate; 1121. First front-side source / drain epitaxial layer; 1122. First back-side source / drain epitaxial layer; 1131. First front-side source / drain metal; 1132. First back-side source / drain metal; 114. First gate dielectric layer; 1151. First front-side fin structure; 1152. First back-side fin structure; 12. Second transistor; 121. Second gate; 1221. Second front-side source / drain epitaxial layer; 1222. Second back-side source / drain epitaxial layer; 1231. Second front-side source / drain metal; 1232. Second back-side source / drain metal; 124. Second gate dielectric layer Layer; 1251, Second front fin structure; 1252, Second back fin structure; 13, Front back interconnect layer; 1311, First front signal line; 1312, First front power rail; 1313, Second front power rail; 1321, Second front signal line; 133, First front back interconnect line; 134, Second front back interconnect line; 14, Back back interconnect layer; 1411, First back signal line; 1412, First back power rail; 1413, Second back power rail; 142, First back back interconnect line; 15, Gate interconnect structure; 16, Gate lead-out structure. Detailed Implementation

[0030] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0031] As integrated circuit (IC) dimensions continue to shrink and functions to improve, the layout and interconnect design of semiconductor devices face increasing challenges. Vertical field-effect transistors (VFETs) effectively improve transistor integration density and performance by conducting current along the vertical direction of the semiconductor material. However, existing VFET device electrode designs still suffer from problems such as complex signal routing, high interconnect losses, and low power transfer efficiency.

[0032] In some embodiments, Figure 1 This is a schematic diagram of a standard unit structure in an embodiment of this application. See also... Figure 1 As shown, the distance between the two dashed lines represents the cell height of a standard cell. Continuously reducing the cell height of standard cells has always been one of the directions of semiconductor optimization, and the internal metal interconnects of the standard cells after reducing the cell height also need to be further optimized accordingly.

[0033] In some embodiments, Figure 2 This is a first design layout of the semiconductor structure in an embodiment of this application, wherein, Figure 2 (a) in the image is the front-side layout of the semiconductor structure. Figure 2 (b) in the diagram is the back side layout of the semiconductor structure. Figure 3 This is a first schematic diagram of a semiconductor structure in an embodiment of this application, wherein, Figure 3 For along Figure 2 A cross-sectional view taken along the AA' direction in the layout shown. See also... Figure 2 and Figure 3 As shown, the gate lead-out structure used to bring out the gate signal is placed between two transistors. This requires that space be left between the two transistors for the gate lead-out structure during layout design, which increases the spacing between M0 and the height of the standard cell, which is not conducive to the design of integrated circuit devices.

[0034] And see also Figure 3 The semiconductor structure shown has a large parasitic capacitance between the gate and the source / drain, which affects the performance of the semiconductor structure.

[0035] To address the aforementioned technical problems, embodiments of this application provide a semiconductor structure that enables miniaturization of the semiconductor structure's dimensions.

[0036] In some possible implementations, Figure 4 This is a second design layout of the semiconductor structure in an embodiment of this application, wherein, Figure 4 (a) in the image is the front-side layout of the semiconductor structure. Figure 4 (b) in the diagram is the back side layout of the semiconductor structure. Figure 5 This is a second schematic diagram of a semiconductor structure in an embodiment of this application, wherein, Figure 5 (a) in the middle is along Figure 4 The cross-sectional view taken along the AA' direction in the layout shown. Figure 5 (b) in the middle is along Figure 4 A cross-sectional view taken along the BB' direction in the layout shown. See also... Figure 5As shown, the semiconductor structure 10 includes two transistors, namely a first transistor 11 and a second transistor 12. Both the first transistor 11 and the second transistor 12 are vertical field-effect transistors. The first transistor 11 and the second transistor 12 are arranged adjacent to each other.

[0037] See also some possible implementations. Figure 5 As shown, the first transistor 11 includes a first gate 111, a first front-side source-drain epitaxial layer 1121, a first back-side source-drain epitaxial layer 1122, a first front-side source-drain metal 1131, a first back-side source-drain metal 1132, a first gate dielectric layer 114, a first front-side fin structure 1151, and a first back-side fin structure 1152.

[0038] See also some possible implementations. Figure 5 As shown, the second transistor 12 includes a second gate 121, a second front-side source-drain epitaxial layer 1221, a second back-side source-drain epitaxial layer 1222, a second front-side source-drain metal 1231, a second back-side source-drain metal 1232, a second gate dielectric layer 124, a second front-side fin structure 1251, and a second back-side fin structure 1252.

[0039] It should be noted that in the embodiments of this application, "source and drain" is an abbreviation for "source and / or drain". For example, the first source and drain can represent the first source and the first drain. In the same vertical field-effect transistor, the source and drain on the front and back sides are different. For example, when the first front source and drain is the first front drain, the corresponding first back source and drain is the first back source.

[0040] In some embodiments, see Figure 5 As shown, the semiconductor structure 10 also includes a front-side back-end interconnect layer 13 and a back-side back-end interconnect layer 14. The front-side back-end interconnect layer 13 is used to implement internal interconnects of the semiconductor structure 10 on the front side. The back-side back-end interconnect layer 14 is used to implement internal interconnects of the semiconductor structure 10 on the back side. The front-side back-end interconnect layer 13 and the back-side back-end interconnect layer 14 together constitute the metal interconnect network inside the semiconductor structure 10.

[0041] In some embodiments, see Figure 5 As shown, the front-side back-end interconnect layer 13 includes a first front-side metal layer and a second front-side metal layer. The first front-side metal layer includes a plurality of first front-side signal lines 1311, a first front-side power rail 1312, and a second front-side power rail 1313. The first front-side power rails 1312 and 1313 are distributed on both sides of the plurality of first front-side signal lines 1311. The second front-side metal layer includes a plurality of second front-side signal lines 1321.

[0042] Among them, the first front signal line is M0 (metal 0), and the second front signal line is M1 (metal 1).

[0043] In some embodiments, see Figure 5 As shown, the back-side interconnect layer 14 includes a first back-side metal layer and a second back-side metal layer (not shown in the figure). The first back-side metal layer includes a plurality of first back-side signal lines 1411, a first back-side power rail 1412, and a second back-side power rail 1413. The first back-side power rails 1412 and the second back-side power rails 1413 are distributed on both sides of the plurality of first back-side signal lines 1411. The second back-side metal layer includes a plurality of second back-side signal lines (not shown in the figure).

[0044] Among them, the first back signal line is M0 (metal 0), and the second back signal line is M1 (metal 1).

[0045] In the embodiments of this application, the first front power rail and the first rear power rail are power rails of the same type, such as VDD (voltage drain drain); the second front power rail and the second rear power rail are power rails of the same type, such as VSS (voltage source and sink).

[0046] In some embodiments, see Figure 5 As shown, the semiconductor structure 10 includes a gate interconnect structure 15; the gate interconnect structure 15 is located between the first gate 111 and the second gate 121. The gate interconnect structure 15 is connected to the first gate 111 and the second gate 121 respectively, for realizing the interconnection of the first gate 111 and the second gate 121.

[0047] In some embodiments, see Figure 5 As shown, the semiconductor structure 10 includes a gate lead-out structure 16, with its two ends connected to a second gate 121 and a first front-side signal line 1311, respectively. (See also...) Figure 4 As shown, in the first direction, the projection of the gate lead-out structure 16 does not coincide with the projection of the first front source / drain metal 1131 and the projection of the second front source / drain metal 1231; and the projection of the gate lead-out structure 16 is not located at the position between the first front source / drain metal 1131 and the second front source / drain metal 1231 (i.e., the first region).

[0048] In this embodiment, the position of the gate lead-out structure does not coincide with the positions of the first source drain, the second source drain, and the channel. Instead, the gate signal is led out on the side of the channel. This gate lead-out method can improve the flexibility of wiring in the transistor and reduce the spacing between the first transistor and the second transistor, thereby achieving miniaturization of the semiconductor structure.

[0049] It should be noted that the first front source drain epitaxial layer and the first front source drain metal form the first front source drain, the first back source drain epitaxial layer and the first back source drain metal form the first back source drain, and the first front source drain and the first back source drain form the first source drain; the second source drain is similar, and this application embodiment will not elaborate on this.

[0050] In some embodiments, the connection between the gate lead-out structure and the second gate is only one example. The gate lead-out structure can also be flexibly set in other positions according to actual wiring requirements.

[0051] In some embodiments, Figure 6 This is a third design layout of the semiconductor structure in the embodiments of this application, wherein, Figure 6 (a) in the image is the front-side layout of the semiconductor structure. Figure 6 (b) in the diagram is the back side layout of the semiconductor structure. Figure 7 This is a third schematic diagram of a semiconductor structure in an embodiment of this application, wherein, Figure 7 (a) in the middle is along Figure 6 The cross-sectional view taken along the AA' direction in the layout shown. Figure 7 (b) in the middle is along Figure 6 A cross-sectional view taken along the BB' direction in the layout shown. See also... Figure 6 and Figure 7 As shown, the gate lead-out structure 16 is connected to the first gate 111 and the first front signal line 1311.

[0052] In some embodiments, Figure 8 This is a fourth design layout of the semiconductor structure in the embodiments of this application, wherein, Figure 8 (a) in the image is the front-side layout of the semiconductor structure. Figure 8 (b) in the diagram is the back side layout of the semiconductor structure. Figure 9 This is a fourth schematic diagram of a semiconductor structure in an embodiment of this application, wherein, Figure 9 (a) in the middle is along Figure 8 The cross-sectional view taken along the AA' direction in the layout shown. Figure 9 (b) in the middle is along Figure 8 A cross-sectional view taken along the BB' direction in the layout shown. See also... Figure 8 and Figure 9 As shown, the gate lead-out structure 16 corresponds to the region between the first source drain and the second source drain (i.e., the first region), and the gate lead-out structure 16 is connected to the gate interconnect structure 15 and the first front signal line 1311.

[0053] In some embodiments, the gate lead-out structure can be disposed on the front or back side of the semiconductor structure, depending on actual needs. Figure 5 , Figure 7 and Figure 9 The gate lead-out structure shown is only an example of leading out the gate signal on the front side of the semiconductor structure. When the gate lead-out structure leads out the gate signal on the back side, the gate lead-out structure is connected to the back side gate (i.e., the back side of the second gate behind the first gate) and the first back side signal line.

[0054] In some embodiments, see Figure 5 As shown, two first front-side signal lines 1311 in the first front-side metal layer are connected to the first front-side source / drain metal 1131 and the second front-side source / drain metal 1231 respectively via two first front-side back-end interconnects 133. The two first front-side signal lines 1311 connecting the first front-side source / drain metal 1131 and the second front-side source / drain metal 1231 are connected to the second front-side signal line 1321 via a second front-side back-end interconnect 134.

[0055] In this embodiment, the first front-side source / drain and the second front-side source / drain are interconnected between the first transistor and the second transistor via a first front-side signal line, a first front-side back-channel interconnect line, a second front-side back-channel interconnect line, and a second front-side signal line. It should be noted that... Figure 5 , Figure 7 and Figure 9 The first and second transistors shown are only examples of source-drain interconnection on the front side. Depending on actual needs, the source-drain interconnection between the first and second transistors can be implemented on the back side of the semiconductor structure. When the first and second transistors are interconnected on the back side, the first and second back-side source-drain metals are electrically connected through a first back-side signal line, a first back-side rear-channel interconnect, a second back-side rear-channel interconnect, and a second back-side signal line.

[0056] In some embodiments, see Figure 5 As shown, in the AA' direction, the widths of the first back-side source / drain metal and the second back-side source / drain metal are greater than the widths of the first front-side source / drain metal and the second front-side source / drain metal. When the first transistor and the second transistor are interconnected on the front side, the widths of the first front-side source / drain metal and the second front-side source / drain metal can be set to be greater than the widths of the first back-side source / drain metal and the second back-side source / drain metal.

[0057] In some embodiments, see Figure 5 As shown, the first rear power rail 1412 is connected to the first rear source / drain metal 1132 via the first rear back interconnect 142, and the second rear power rail 1413 is connected to the second rear source / drain metal 1232 via the first rear back interconnect 142.

[0058] In some embodiments, the first transistor and the second transistor are transistors of different polarities. For example, when the first transistor is a P-channel metal oxide semiconductor (PMOS), the second transistor is an N-channel metal oxide semiconductor (NMOS); or when the first transistor is an NMOS, the second transistor is a PMOS.

[0059] The following is combined with Figure 5 , Figure 7 and Figure 9 The semiconductor structure shown illustrates the fabrication method of the semiconductor structure provided in the embodiments of this application.

[0060] Figure 10 This is a schematic diagram illustrating one implementation process of the semiconductor structure fabrication method in this application. See also... Figure 10 As shown, the method for fabricating a semiconductor structure may include:

[0061] Step S1001: Form a fin structure on the substrate; the fin structure includes a front fin structure and a back fin structure stacked together.

[0062] In some embodiments, a substrate is provided; then, the fin structure is patterned and the substrate is etched using standard process steps to form a front fin structure and a back fin structure. The front fin structure and the back fin structure are formed in the same process.

[0063] In one example, the substrate can be a silicon substrate.

[0064] In some embodiments, after forming the fin structure, a dielectric material can be deposited on the substrate and the fin structure to form a shallow trench isolation (STI) layer. The shallow trench isolation layer encapsulates the fin structure and covers the substrate.

[0065] Step S1002: Based on the fin structure, a gate of the semiconductor structure is formed.

[0066] In some embodiments, a shallow trench isolation layer of a predetermined height is etched, with the etching stopping below the gate region. As the gate region is exposed, an insulating material is first deposited in the gate region to form a gate dielectric layer, which includes a first gate dielectric layer in the first transistor and a second gate dielectric layer in the second transistor. Next, a metal material is deposited in the gate region. The metal material located outside the gate region is removed by processes such as photolithography and etching. The unetched metal material located in the gate region forms the gate. The gate includes a first gate in the first transistor, a second gate in the second transistor, and a gate interconnect structure.

[0067] In some embodiments, before forming the gate, the gate region is first opened by photolithography and etching. The gate region includes a first gate region in a first transistor, a second gate region in a second transistor, and a gate interconnect trench located between the first gate region and the second gate region. Metal material is filled into the first gate region, the second gate region, and the gate interconnect trench, and then excess metal material is removed by processes such as photolithography and etching to form the first gate, the second gate, and the gate interconnect structure.

[0068] In some embodiments, the unetched shallow trench isolation layer is located between the gate and the substrate. After the semiconductor structure is fabricated, this portion of the shallow trench isolation layer can be used to isolate the gate and the source / drain on the back side.

[0069] Step S1003: Based on the front fin structure, form the first front source drain of the first transistor and the second front source drain of the second transistor.

[0070] In some embodiments, after the gate is formed, a dielectric material can be deposited on the gate, and then a portion of the dielectric material can be removed by etching, leaving a predetermined height of dielectric material to expose a portion of the front-side fin structure and form a first shallow trench isolation layer. After the semiconductor structure is fabricated, the first shallow trench isolation layer is used to isolate the gate and the front-side source / drain.

[0071] In some embodiments, source / drain epitaxial growth is performed based on the front fin structure to form a first front source / drain epitaxial layer and a second front source / drain epitaxial layer. Metallic material is deposited over the first and second front source / drain epitaxial layers to form a first front source / drain metal and a second front source / drain metal.

[0072] Step S1004: Perform back-end processes on the first and second front-side source drains to form a front-side back-end interconnect layer.

[0073] In some embodiments, back-end processing is performed on the first and second front-side source drains to form a front-side back-end interconnect layer.

[0074] In some embodiments, when the gate lead-out structure is disposed on the front side, during the formation of the front-side back interconnect layer, a gate lead-out groove can be etched in the first shallow trench isolation layer, and a metal material can be filled in the gate lead-out groove to form the gate lead-out structure. After the gate lead-out structure is fabricated, during the formation of the first front-side metal layer, one of the first front-side signal lines is disposed above the gate lead-out structure and connected to the gate lead-out structure to lead the gate signal to the front-side back interconnect layer.

[0075] Step S1005: Pour the wafer and thin the substrate.

[0076] In some embodiments, prior to step S1005, the method for fabricating the semiconductor structure may further include: depositing an insulating material on the surface of the front-side back-end interconnect layer to form an insulating layer; and bonding the insulating layer to a carrier wafer.

[0077] In this embodiment, the bonded carrier wafer can provide physical support for the flipped semiconductor structure after the wafer is flipped, effectively preventing the semiconductor structure on the front side from being broken by external force during the fabrication of the back side of the semiconductor structure.

[0078] In some embodiments, the substrate can be thinned using a chemical-mechanical planarization (CMP) process.

[0079] Step S1006: Based on the back fin structure, form the first back-side source drain of the first transistor and the second back-side source drain of the second transistor.

[0080] In some embodiments, source / drain epitaxial growth is performed based on the back fin structure to form a first back source / drain epitaxial layer and a second back source / drain epitaxial layer. Metallic material is deposited over the first and second back source / drain epitaxial layers to form a first back source / drain metal and a second back source / drain metal.

[0081] Step S1007: Perform back-end processing on the first back-side source drain and the second back-side source drain to form a back-side back-end interconnect layer.

[0082] In some embodiments, when the gate lead-out structure is disposed on the back side, during the formation of the back-side interconnect layer, a gate lead-out groove can first be etched in the shallow trench isolation layer, and then a metal material can be filled into the gate lead-out groove to form the gate lead-out structure. After the gate lead-out structure is fabricated, during the formation of the first back-side metal layer, one of the first back-side signal lines is disposed above the gate lead-out structure and connected to the gate lead-out structure to lead the gate signal to the back-side interconnect layer.

[0083] In this embodiment, by setting the gate lead-out structure on the side of the channel and avoiding the first source drain, the second source drain, and the position between the first source drain and the second source drain, the distance between the first transistor and the second transistor can be shortened, thereby achieving miniaturization of the semiconductor structure and improving integration.

[0084] Furthermore, the gate lead-out structure can be positioned on the front or back of the semiconductor structure; or, depending on the actual situation, the gate lead-out structure can be positioned near the first gate or the second gate; the various positions of the gate lead-out structure inside the semiconductor make the wiring inside the semiconductor more flexible.

[0085] Furthermore, the semiconductor structure provided in this application embodiment can be detected using detection and analysis instruments, such as scanning electron microscope (SEM), transmission electron microscope (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, the semiconductor structure provided in this application embodiment can be detected by TEM slicing. For example, the gate lead structure, the first front signal line, and the first back signal line can be observed in the TEM slice.

[0086] This application provides a semiconductor device, including the semiconductor structure as described in the above embodiments. Specific limitations of the semiconductor structure can be found above. Figure 5 , Figure 7 and Figure 9 The structure shown will not be elaborated upon here.

[0087] This application provides an electronic device, including a circuit board and a semiconductor device as described in the above embodiments, wherein the semiconductor device is disposed on the circuit board. The semiconductor device includes the semiconductor structure described above. Specific limitations of the semiconductor structure can be found above. Figure 5 , Figure 7 and Figure 9 This will not be elaborated upon here.

[0088] In the description of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine different embodiments or examples described in this application, as well as features of different embodiments or examples.

[0089] The above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor structure, characterized in that, include: First transistor; Second transistor; The first transistor and the second transistor are vertical field-effect transistors; the first transistor and the second transistor are arranged adjacent to each other; A gate lead-out structure; the gate lead-out structure connects the gate of the semiconductor structure to the front-side back-end interconnect layer of the semiconductor structure, or the gate lead-out structure connects the gate of the semiconductor structure to the back-side back-end interconnect layer of the semiconductor structure; In the first direction, the projection of the gate lead-out structure does not coincide with the projection of the first source drain of the first transistor and the projection of the second source drain of the second transistor, and the projection of the gate lead-out structure does not coincide with the projection of the first region; the first region is located between the first source drain and the second source drain, and the first direction is the direction from the front back-end interconnect layer to the back-end interconnect layer.

2. The semiconductor structure according to claim 1, characterized in that, The gate includes a first gate in the first transistor, a second gate in the second transistor, and a gate interconnect structure; The gate interconnect structure is located between the first gate and the second gate, and its two ends are respectively connected to the first gate and the second gate.

3. The semiconductor structure according to claim 1, characterized in that, The front-side back-end interconnect layer includes: a first front-side metal layer and a second front-side metal layer; The first front metal layer includes a first front power rail, a plurality of first front signal lines, and a second front power rail; the first front power rail and the second front power rail are symmetrically arranged on both sides of the plurality of first front signal lines; The second front metal layer includes a plurality of second front signal lines.

4. The semiconductor structure according to claim 3, characterized in that, The first source drain includes a first positive source drain, and the second source drain includes a second positive source drain; At least two of the plurality of first front signal lines are connected to the first front source drain and the second front source drain via a first front back-end interconnect. The first front-side signal line connecting the first front-side source / drain and the second front-side source / drain is connected to the second front-side signal line via the second front-side back-end interconnect.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The back-side interconnect layer includes: a first back-side metal layer and a second back-side metal layer; The first back metal layer includes a first back power rail, a plurality of first back signal lines, and a second back power rail; the first back power rail and the second back power rail are symmetrically arranged on both sides of the plurality of first back signal lines; The second back metal layer includes a plurality of second back signal lines.

6. The semiconductor structure according to claim 5, characterized in that, The first source drain further includes a first back-side source drain, and the second source drain further includes a second back-side source drain; The first back-side source drain is connected to the first back-side power rail via a first back-side rear interconnect; The second back-side source drain is connected to the second back-side power rail via the first back-side back-side interconnect.

7. The semiconductor structure according to claim 6, characterized in that, The gate lead-out structure is connected to one of the plurality of first front signal lines; or, The gate lead-out structure is connected to one of the plurality of first backside signal lines.

8. A method for fabricating a semiconductor structure, characterized in that, The method for preparing the semiconductor structure according to any one of claims 1 to 7 comprises: A fin-like structure is formed on a substrate; the fin-like structure includes a front fin-like structure and a back fin-like structure stacked together. The gate of the semiconductor structure is formed based on the fin-like structure; Based on the aforementioned front fin structure, a first front source / drain of the first transistor and a second front source / drain of the second transistor are formed. Back-end processes are performed on the first and second front-end source drains to form a front-end back-end interconnect layer. The substrate is then poured and thinned. Based on the aforementioned back fin structure, a first back-side source / drain of the first transistor and a second back-side source / drain of the second transistor are formed. Back-end processes are performed on the first back-end source drain and the second back-end source drain to form a back-end back-end interconnect layer; The method further includes: forming a gate lead-out structure during the formation of the front-side back-end interconnect layer; the two ends of the gate lead-out structure are respectively connected to the gate and the front-side back-end interconnect layer; or, forming a gate lead-out structure during the formation of the back-side back-end interconnect layer, the two ends of the gate lead-out structure are respectively connected to the gate and the back-side back-end interconnect layer. In the first direction, the projection of the gate lead-out structure does not coincide with the projection of the front source / drain, and the projection of the gate lead-out structure does not coincide with the projection of the first region; the first region is located between the first front source / drain and the second front source / drain, and the first direction is the direction from the front back-end interconnect layer to the back-end interconnect layer.

9. A semiconductor device, characterized in that, include: The semiconductor structure as described in claim 8.

10. An electronic device, characterized in that, include: The circuit board and the semiconductor device as described in claim 9, wherein the semiconductor device is disposed on the circuit board.

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