Method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method, comprising the following steps: providing a substrate, a plurality of functional structures are formed on a first surface of the substrate; forming a dielectric layer on the first surface of the substrate and the functional structures, a top surface of the dielectric layer has a plurality of protrusions and a plurality of recesses arranged at intervals; forming an amorphous silicon layer in the recesses, the amorphous silicon layer covers the inner wall of the recesses; oxidizing the amorphous silicon layer to form a silicon oxide layer, the silicon oxide layer fills the recesses; and grinding the top surface of the silicon oxide layer and the dielectric layer to planarize the top surface of the silicon oxide layer and the dielectric layer. The amorphous silicon layer is formed in the recesses, and the amorphous silicon layer is oxidized, the volume of the amorphous silicon layer increases during the oxidation, so that the formed silicon oxide layer can fill the recesses, the film layer covering the top corner of the functional structure is thickened, and the problem that the functional structure is exposed during the subsequent grinding of the top surface of the silicon oxide layer and the dielectric layer is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a preparation method of a semiconductor device. BACKGROUND

[0002] Complementary Metal-Oxide-Semiconductor (CMOS) image sensors, as a kind of widely used image sensors, include front side illumination (FSI) image sensors and back side illumination (BSI) image sensors. The back side illumination image sensor sets the elements (such as microlenses and photodiodes) of the photosensitive layer on the back surface of the substrate, and allows light energy to directly enter from the back surface of the substrate, avoiding the influence of the metal layer between the microlenses and the photodiodes in the front side illumination image sensor structure, thereby significantly improving the light efficiency and greatly improving the photosensitive effect of the image sensor under low light conditions.

[0003] The backside metal grid (BMG) process is one of the core processes of the back side illumination image sensor. By arranging a metal layer and an interconnection structure on the back surface of the substrate, the interference with the front surface structure of the substrate is reduced, more efficient power delivery and signal transmission are achieved, and the overall performance of the device is improved. The backside metal grid process usually forms a metal material layer on the back surface of the substrate, then etches the metal material layer to form a metal grid, then forms a dielectric layer on the metal grid, and then performs a planarization process on the dielectric layer.

[0004] Because there is a height difference between the top surface of the metal grid and the top surface of the substrate, after the dielectric layer is deposited on the metal grid, the top surface of the dielectric layer also has a step, showing a topography with ups and downs. When the planarization process is performed on the dielectric layer, the metal grid is easily exposed. SUMMARY

[0005] Therefore, the embodiments of the present application aim to provide a preparation method of a semiconductor device to solve the problem that the metal grid is easily exposed after the planarization process is performed on the dielectric layer in the prior art.

[0006] In one aspect, the present application provides a preparation method of a semiconductor device, comprising:

[0007] providing a substrate, a plurality of functional structures are formed on a first surface of the substrate in a spaced arrangement;

[0008] forming a dielectric layer on the first surface of the substrate and the functional structures, the top surface of the dielectric layer having a plurality of protrusions and recesses arranged in a spaced arrangement;

[0009] forming an amorphous silicon layer in the recess, the amorphous silicon layer conformally covering inner walls of the recess;

[0010] oxidizing the amorphous silicon layer to form a silicon oxide layer, the silicon oxide layer filling the recess; and,

[0011] polishing top surfaces of the silicon oxide layer and the dielectric layer to planarize the top surfaces of the silicon oxide layer and the dielectric layer.

[0012] In some embodiments, the step of forming the amorphous silicon layer in the recess comprises:

[0013] forming the amorphous silicon layer on the dielectric layer, the amorphous silicon layer conformally covering a top surface of the dielectric layer; and,

[0014] polishing a top surface of the amorphous silicon layer until the amorphous silicon layer on the top surface of the protrusion is removed.

[0015] In some embodiments, after forming the amorphous silicon layer on the dielectric layer, a top surface of the amorphous silicon layer is etched using a wet etching process to form a microporous structure on the top surface of the amorphous silicon layer; or, after forming the amorphous silicon layer on the dielectric layer, a top surface of the amorphous silicon layer is bombarded by plasma to generate nanoscale pits on the top surface of the amorphous silicon layer.

[0016] In some embodiments, when polishing the top surface of the amorphous silicon layer, a polishing liquid has a polishing speed on the amorphous silicon layer that is greater than a polishing speed on the dielectric layer.

[0017] In some embodiments, a lateral width of the recess is 3-5 times a thickness of the amorphous silicon layer.

[0018] In some embodiments, a bottom surface of the recess is higher than a top surface of the functional structure; and / or, after polishing top surfaces of the silicon oxide layer and the dielectric layer, the top surfaces of the silicon oxide layer and the dielectric layer are higher than the top surface of the functional structure.

[0019] In some embodiments, the amorphous silicon layer is oxidized using a thermal oxidation process or a water vapor oxidation process.

[0020] In some embodiments, the amorphous silicon layer is oxidized at 400-450°C; and / or, a time for oxidizing the amorphous silicon layer is 8-10h.

[0021] In some embodiments, the semiconductor device is a backside illuminated image sensor, the substrate is a substrate of a pixel wafer, the first surface of the substrate is a back surface thereof, a logic wafer is also bonded on the second surface of the substrate, and the functional structures are metal layers formed in a backside metal grid on the second surface of the substrate.

[0022] In some embodiments, the substrate has source regions and drain regions arranged in an array, the functional structures are gate structures, and the gate structures are located between the source regions and the drain regions.

[0023] After polishing the top surface of the silicon oxide layer and the dielectric layer, an electrical connection structure is formed in the dielectric layer and electrically connected to the source region, the drain region, and the gate structure, respectively.

[0024] The present application provides a method for manufacturing a semiconductor device, including providing a substrate, a first surface of the substrate has a plurality of functional structures arranged in an array; forming a dielectric layer on the first surface of the substrate and the functional structures, a top surface of the dielectric layer has protrusions and recesses arranged in an array; forming an amorphous silicon layer in the recesses, the amorphous silicon layer covers the inner wall of the recesses; oxidizing the amorphous silicon layer to form a silicon oxide layer, the silicon oxide layer fills the recesses; and polishing the top surface of the silicon oxide layer and the dielectric layer to planarize the top surface of the silicon oxide layer and the dielectric layer. The unexpected effect of the present application is that by forming an amorphous silicon layer in the recesses and oxidizing the amorphous silicon layer, the volume of the amorphous silicon layer increases during oxidation, so that the formed silicon oxide layer can fill the recesses, the film layer covering the top corner of the functional structure is thickened, and the problem of exposing the functional structure during subsequent polishing of the top surface of the silicon oxide layer and the dielectric layer is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A structure diagram for forming a plurality of metal layers on a substrate is provided for an embodiment of the present application.

[0026] Figure 2 A structure diagram for forming a dielectric layer on the back surface of the substrate and the metal layers is provided for an embodiment of the present application.

[0027] Figure 3 A structure diagram for polishing the top surface of the dielectric layer to planarize the top surface of the dielectric layer is provided for an embodiment of the present application.

[0028] Figure 4 A flowchart of a method for manufacturing a semiconductor device is provided for an embodiment of the present application.

[0029] Figure 5A structural diagram of forming a functional structure on a substrate is provided for an embodiment of the present application.

[0030] Figure 6 A structural diagram of forming a dielectric layer on a first surface of a substrate and a functional structure is provided for an embodiment of the present application.

[0031] Figure 7 A structural diagram of forming an amorphous silicon layer on the dielectric layer is provided for an embodiment of the present application.

[0032] Figure 8 A structural diagram of grinding a top surface of the amorphous silicon layer until the amorphous silicon layer on the top surface of the protruding portion is removed is provided for an embodiment of the present application.

[0033] Figure 9 A structural diagram of oxidizing the amorphous silicon layer to form a silicon oxide layer is provided for an embodiment of the present application.

[0034] Figure 10 A structural diagram of grinding a top surface of the silicon oxide layer and the dielectric layer is provided for an embodiment of the present application.

[0035] In the drawings:

[0036] 100 - substrate; 200 - functional structure; 300 - dielectric layer; 400 - amorphous silicon layer; 500 - silicon oxide layer; w - lateral width of the recessed portion; d - thickness of the amorphous silicon layer. DETAILED DESCRIPTION

[0037] A method for manufacturing a backplane metal grid of a back-illuminated image sensor can refer to Figures 1-3 as shown.

[0038] As Figure 1 shown, a plurality of metal layers are formed on the back surface of the base of the pixel wafer, the metal layers are arranged at intervals on the back surface of the base, the metal layers protrude from the back surface of the base, and there is a certain gap between adjacent two metal layers.

[0039] As Figure 2 shown, an insulating layer is formed on the back surface of the base and the metal layers. Since there is a height difference between the top surface of the metal layer and the back surface of the base, after the insulating layer is formed, the top surface of the insulating layer is also not flat, but has a certain undulation. As Figure 2 can be seen, the insulating layer at the two top corners (the dotted circles in Figure 2 ) of the metal layer is thin, and the insulating layer in other areas of the metal layer is thick.

[0040] As Figure 3As shown, the top surface of the insulating layer is polished to flatten the top surface of the insulating layer. It can be understood that, due to the uneven top surface of the insulating layer, the uniformity and accuracy of polishing are affected, and the insulating layer at the two top corners of the metal layer is relatively thin. After polishing the top surface of the insulating layer, the two top corners of the metal layer are easily exposed, thereby causing problems of the device.

[0041] Based on this, the application provides a preparation method of a semiconductor device, comprising the following steps: providing a substrate, a plurality of functional structures being arranged at intervals on a first surface of the substrate; forming a dielectric layer on the first surface of the substrate and the functional structures, a top surface of the dielectric layer having a plurality of protruding parts and a plurality of recessed parts arranged at intervals; forming an amorphous silicon layer in the recessed parts, the amorphous silicon layer conformally covering inner walls of the recessed parts; oxidizing the amorphous silicon layer to form a silicon oxide layer, the silicon oxide layer filling the recessed parts; and polishing the silicon oxide layer and the top surface of the dielectric layer to flatten the silicon oxide layer and the top surface of the dielectric layer. In the application, the amorphous silicon layer is formed in the recessed parts, and the amorphous silicon layer is oxidized. Due to the increase in volume of the amorphous silicon layer during oxidation, the formed silicon oxide layer can fill the recessed parts, the film layer covering the top corners of the functional structures is thickened, and the problem of exposure of the functional structures during subsequent polishing of the top surface of the silicon oxide layer and the dielectric layer is avoided.

[0042] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person of ordinary skill in the art without creative effort fall within the protection scope of the application.

[0043] An embodiment of the application provides a preparation method of a semiconductor device, Figure 4 A flowchart of the preparation method of the semiconductor device provided by an embodiment of the application is shown in FIG. 1. Figure 4 As shown, the preparation method of the semiconductor device comprises the following steps.

[0044] Step S100: providing a substrate, a plurality of functional structures being arranged at intervals on a first surface of the substrate.

[0045] Step S200: forming a dielectric layer on the first surface of the substrate and the functional structures, a top surface of the dielectric layer having a plurality of protruding parts and a plurality of recessed parts arranged at intervals.

[0046] Step S300: forming an amorphous silicon layer in the recessed parts, the amorphous silicon layer conformally covering inner walls of the recessed parts.

[0047] Step S400: oxidizing the amorphous silicon layer to form a silicon oxide layer, the silicon oxide layer filling the recessed parts; and

[0048] Step S500: grinding the top surface of the silicon oxide layer and the dielectric layer to planarize the top surface of the silicon oxide layer and the dielectric layer.

[0049] Figures 5-10 The corresponding structure diagram corresponding to the respective steps of the preparation method of the semiconductor device provided by an embodiment of the present application is shown. Next, the preparation method of the semiconductor device in the present application will be described in detail. Figures 5-10 The preparation method of the semiconductor device in the present application will be described in detail.

[0050] As shown in Figure 5 , step S100 is performed to provide a substrate 100, which can be a silicon substrate, but is not limited thereto, and can be a germanium substrate, a silicon germanium substrate, a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate, a gallium arsenide substrate, etc. A certain doping ion can also be implanted in the substrate 100 according to design requirements to change the electrical parameters. The substrate 100 has opposite first and second surfaces.

[0051] Please continue to refer to Figure 5 , a plurality of functional structures 200 are formed on the first surface of the substrate 100, the functional structures 200 are arranged on the first surface of the substrate 100 with a certain interval, the functional structures 200 protrude from the first surface of the substrate 100, and there is a certain gap between the adjacent two functional structures 200. In some embodiments, the semiconductor device can be a back-illuminated image sensor, at this time, the substrate 100 is a substrate of a pixel wafer, the first surface of the substrate 100 is its back surface, the second surface of the substrate 100 is its front surface, and a logic wafer is also bonded on the second surface of the substrate 100, and the functional structure 200 is a metal layer in the back surface metal grid of the back-illuminated image sensor. In other embodiments, the semiconductor device is not limited to be a back-illuminated image sensor, but can also be other possible devices, such as a memory device or a MOS tube, etc., at this time, the first surface of the substrate 100 can also be its front surface, and the functional structure 200 can also be other device structures, for example, the substrate 100 has source and drain regions arranged with a certain interval, at this time, the functional structure can be a gate structure, and the gate structure is located between the adjacent source and drain regions.

[0052] Further, the functional structure 200 can be a single-layer structure or a multi-layer laminated structure, and the material thereof can be selected from one or more of aluminum, copper, nickel, tungsten, etc.

[0053] As shown in Figure 6As shown in FIG. 2, step S200 is performed to form a dielectric layer 300 on the first surface of the substrate 100 and the functional structure 200. Since there is a height difference between the top surface of the functional structure 200 and the first surface of the substrate 100, after the dielectric layer 300 is formed, the top surface of the dielectric layer 300 is not flat but has a certain fluctuation. Specifically, the top surface of the dielectric layer 300 has protruding portions and recessed portions arranged at intervals, the protruding portions are located above the functional structure 200, and the recessed portions are located above the gaps between the functional structure 200.

[0054] In some embodiments, the dielectric layer 300 can be appropriately thick, so that the bottom surface of the recessed portion can be higher than the top surface of the functional structure 200, thereby avoiding that the width w and the aspect ratio of the recessed portion are too large and increasing the difficulty of subsequently forming the amorphous silicon layer.

[0055] In some embodiments, the material of the dielectric layer 300 can be a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, tetraethyl orthosilicate (TEOS), etc. The dielectric layer 300 can be a single-layer structure or a multi-layer structure.

[0056] As shown in FIG. 4, step S300 is performed to form an amorphous silicon layer 400 in the recessed portion, and the amorphous silicon layer 400 conformally covers the inner wall of the recessed portion. Figures 7-8 First, referring to FIG. 3,

[0057] The amorphous silicon layer 400 is formed on the dielectric layer 300, and the amorphous silicon layer 400 conformally covers the top surface of the dielectric layer 300. Of course, at this time, the amorphous silicon layer 400 also covers the inner wall of the recessed portion and the outer wall of the protruding portion. Figure 7 The process of forming the amorphous silicon layer 400 can be plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), etc. Specifically, a mixed gas of silane and hydrogen can be used for deposition at a temperature lower than 350°C, the silane is decomposed by high-frequency plasma to form a disordered silicon atom network, and then the discharge power is adjusted to 50W-100W to control the defect density in the amorphous silicon layer 400. The defect sites can be used as active starting points for subsequent oxidation reactions to promote the oxidation reaction. In some embodiments, the deposition rate can be adjusted (controlled at 2nm / s-5nm / s) to form a porous amorphous silicon layer 400, so that the surface area of the amorphous silicon layer 400 is increased by 3-5 times, which is beneficial to the subsequent oxidation reaction.

[0058]

[0059] ​In some embodiments, after forming an amorphous silicon layer 400 on the dielectric layer 300, a microporous structure can be formed on the top surface of the amorphous silicon layer 400 using a wet etching process (such as alkaline etching), or plasma bombardment can be used to generate nanoscale pits on the top surface of the amorphous silicon layer 400, thereby increasing the roughness by 3-5 times and reducing the oxidation difficulty of the amorphous silicon layer 400.

[0060] Then as Figure 8 As shown, the top surface of the amorphous silicon layer 400 is polished until the amorphous silicon layer 400 on the top surface of the protrusion is removed, leaving only the amorphous silicon layer 400 in the recess. When polishing the top surface of the amorphous silicon layer 400, the polishing speed of the polishing fluid on the amorphous silicon layer 400 needs to be greater than the polishing speed on the dielectric layer 300, so that the polishing can stop on the dielectric layer 300, thereby preventing damage to the dielectric layer 300 when removing the amorphous silicon layer 400 on the top surface of the protrusion.

[0061] It should be noted that when grinding the top surface of the amorphous silicon layer 400, a circulating cooling system can be used to keep the temperature of the grinding interface below 80°C to prevent the amorphous phase of the amorphous silicon layer 400 from transforming into the crystalline phase. Heat dissipation can be paused after a certain grinding time to prevent thermal stress from causing microcracks to propagate.

[0062] In some embodiments, after grinding the top surface of the amorphous silicon layer 400, a low-temperature oxygen plasma treatment process (power 300W~500W, time 5min~10min) can be used to treat the surface of the amorphous silicon layer 400 to remove organic contaminants on the surface of the amorphous silicon layer 400 and generate Si-OH active sites, thereby reducing the difficulty of oxidation.

[0063] In some embodiments, the amorphous silicon layer 400 can be pretreated with ultraviolet light and ozone. The wavelength of the ultraviolet light can be 254 nm, and the concentration of ozone can be 20 ppm to 50 ppm, so that Si-O-Si dangling bonds are generated on the surface of the amorphous silicon layer 400, and the starting temperature of subsequent oxidation can be reduced by about 150 °C.

[0064] like Figure 9 As shown, in step S400, the amorphous silicon layer 400 is oxidized to form a silicon oxide layer 500, which fills the recess. Specifically, when the amorphous silicon layer 400 is oxidized to form the silicon oxide layer 500, the volume increases, meaning the volume of the silicon oxide layer 500 is larger than that of the amorphous silicon layer 400, allowing the silicon oxide layer 500 to fill the recess. Furthermore, since the atomic arrangement of the amorphous silicon layer 400 is disordered (amorphous), it is easy to prepare and oxidize. Therefore, the process of forming and oxidizing the amorphous silicon layer 400 does not significantly increase the complexity and cost of the process.

[0065] It should be noted that the density of amorphous silicon ρ1 is 2.32 g / cm 3 ~2.34 g / cm 3 The density of silicon oxide ρ2 is 2.2 g / cm 3 ~2.66 g / cm 3 The molar mass of silicon m1 is 28.0855 g / mol, and the molar mass of silicon oxide m2 is 60.084 g / mol. According to the density formula (m2 / ρ2) / (m1 / ρ1)≈2, that is, 1 mol of amorphous silicon is oxidized to form silicon oxide, the volume increases by about 1 times.

[0066] Based on this, the transverse width w of the recess can be 3-5 times the thickness of the amorphous silicon layer 400, so that most of the depth of the recess can be filled with the silicon oxide layer 500. Preferably, the transverse width w of the recess can be 4 times the thickness of the amorphous silicon layer 400, so that the silicon oxide layer 500 can just fill the recess, avoiding the top surface of the silicon oxide layer 500 and the top surface of the dielectric layer 300 having a height difference and affecting the subsequent grinding process.

[0067] In some embodiments, the amorphous silicon layer 400 can be oxidized by a thermal oxidation process or a water vapor oxidation process. The principle of oxidizing the amorphous silicon layer 400 by the thermal oxidation process can refer to the chemical formula Si+O2=SiO2, and the principle of oxidizing the amorphous silicon layer 400 by the water vapor oxidation process can refer to the chemical formula Si+H2O=SiO2+2H2. The oxidation rate of the water vapor oxidation process can be 5-10 times higher than that of the thermal oxidation process.

[0068] In some embodiments, the amorphous silicon layer 400 can also be oxidized by a normal pressure plasma-assisted oxidation process. The normal pressure plasma-assisted oxidation process can use O2 / Ar mixed gas as process gas, and the oxidation temperature is about 600°C. Of course, the amorphous silicon layer 400 can also be oxidized by a supercritical water oxidation process. The temperature of the supercritical water oxidation process is greater than 374°C, and the pressure is greater than 22.1 MPa, which can greatly shorten the oxidation time.

[0069] In some embodiments, the amorphous silicon layer 400 can be oxidized in a low-temperature environment to avoid the influence of high temperature on the device. For example, the amorphous silicon layer 400 can be oxidized at 400°C-450°C. Further, when oxidizing the amorphous silicon layer 400, the oxidation temperature can be controlled by gradient temperature control. In the initial stage, the temperature is slowly raised to about 300°C to induce lattice defects, and then gradually raised to 400°C-450°C to realize rapid oxidation of the amorphous silicon layer 400.

[0070] In some embodiments, the oxidation time of the amorphous silicon layer 400 can be 8h to 10h, but should not be limited thereto.

[0071] like Figure 10 As shown, step S500 is performed to grind the top surfaces of the silicon oxide layer 500 and the dielectric layer 300 to flatten them. It is conceivable that because the silicon oxide layer 500 fills the recesses, the film layer at the corner of the functional structure 200 becomes thicker (from only the dielectric layer 300 to dielectric layer 300 + silicon oxide layer 500). Grinding the top surfaces of the silicon oxide layer 500 and the dielectric layer 300 avoids exposing the functional structure 200. Simultaneously, after the silicon oxide layer 500 fills the recesses, it also reduces the surface unevenness of the dielectric layer 300, which is beneficial for the grinding process and reduces its difficulty.

[0072] It should be noted that after grinding the top surfaces of the silicon oxide layer 500 and the dielectric layer 300, the top surfaces of the silicon oxide layer 500 and the dielectric layer 300 need to be higher than the top surface of the functional structure 200. That is, after grinding the top surfaces of the silicon oxide layer 500 and the dielectric layer 300, the functional structure 200 is not exposed from the dielectric layer 300. In some embodiments, grinding the top surfaces of the silicon oxide layer 500 and the dielectric layer 300 removes part of the thickness of the silicon oxide layer 500 and the dielectric layer 300, but a portion of the thickness of the silicon oxide layer 500 and the dielectric layer 300 is still retained.

[0073] It should be noted that when the functional structure is a gate structure, after grinding the top surfaces of the silicon oxide layer 500 and the dielectric layer 300, the dielectric layer 300 and the silicon oxide layer 500 can be etched to form contact holes that expose the top surfaces of the source region, drain region and gate structure. Then, conductive material is filled into the contact holes to form an electrical connection structure (plug) that electrically connects the source region, drain region and gate structure respectively within the dielectric layer 300.

[0074] To sum up, the embodiment provides a preparation method of a semiconductor device, including providing a substrate 100, a plurality of functional structures 200 are formed on a first surface of the substrate 100; forming a dielectric layer 300 on the first surface of the substrate 100 and the functional structures 200, a top surface of the dielectric layer 300 has a plurality of protruding parts and recessed parts arranged at intervals; forming an amorphous silicon layer 400 in the recessed parts, the amorphous silicon layer 400 covers the inner walls of the recessed parts; oxidizing the amorphous silicon layer to form a silicon oxide layer 500, the silicon oxide layer 500 fills the recessed parts; and grinding the top surface of the silicon oxide layer 500 and the dielectric layer 300 to planarize the top surface of the silicon oxide layer 500 and the dielectric layer 300. The unexpected effect of the application is that: by forming the amorphous silicon layer 400 in the recessed parts and oxidizing the amorphous silicon layer 400, the volume of the amorphous silicon layer 400 increases when it is oxidized, so that the formed silicon oxide layer 500 can fill the recessed parts, so that the film layer at the top corner of the functional structure 200 is thickened, and the problem that the functional structure 200 is exposed when the top surface of the silicon oxide layer 500 and the dielectric layer 300 is ground subsequently is avoided.

[0075] It should be noted that the embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0076] It should also be noted that, although the above embodiments have been disclosed as the preferred embodiments, the above embodiments are not intended to limit the present application. For any skilled person in the art, many possible changes, modifications and modifications of the technical solutions disclosed in the present application can be made without departing from the scope of the technical solutions of the present application, or modified as equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification of the above embodiments made according to the technical essence of the present application without departing from the technical solutions of the present application, all still belong to the scope of protection of the technical solutions of the present application.

[0077] It should also be understood that, unless specifically described or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish the components, elements, steps and the like in the specification, and not to indicate the logical relationship or sequence relationship between the components, elements, steps and the like.

[0078] It is also important to note that the term "comprising" or "comprises" or "including" or "includes" or "containing" or "contains" or "has" or "having" or "composed of" or "comprise" or "comprised of" or "comprising of" or "comprise of" or "comprised" or "comprise" or "comprises" or "comprised of" or "comprise of" or "comprising of" or "comprise of" or "comprises" or "comprised of" or "comprise of" or "comprising of" or "comprise of" or "comprises" or "comprised of" or "comprise of" or "comprising of" or "comprise of" or "comprises" or "comprised of" or "comprise of" or "comprising of" or "comprise of" or "comprises" or "comprised of" or "comprise of" or "comprising of" or "comprise of" or "comprises" or "comprised of" or "comprise of" or "comprising of" or "comprise of" or "comprises" or "comprised of" or "comprise of" or "comprising of" or "comprise of" or "comprises" or "comprised of" or "comprise of" or "comprising of" or "comprise of" or "comprises" or "comprised of" or "comprise of" or "comprising of" or "comprise of" or "comprises" or "comprised of" or "comprise of" or "comprising of" or "comprise of" or "comprises" or "comprised of" or "comprise of" or "comprising of" or "

Claims

1. A method of manufacturing a semiconductor device, characterized by, The application relates to a semiconductor device and a manufacturing method thereof. The application provides a substrate, a first surface of the substrate is provided with a plurality of spaced functional structures; A dielectric layer is formed on the first surface of the substrate and the functional structures, a top surface of the dielectric layer is provided with spaced convex parts and concave parts; An amorphous silicon layer is formed in the concave parts, the amorphous silicon layer conformally covers inner walls of the concave parts; The amorphous silicon layer is oxidized to form a silicon oxide layer, the silicon oxide layer fills the concave parts; and The top surface of the silicon oxide layer and the top surface of the dielectric layer are polished to planarize the top surface of the silicon oxide layer and the top surface of the dielectric layer; The step of forming the amorphous silicon layer in the dielectric layer comprises: The amorphous silicon layer is formed on the dielectric layer, and the amorphous silicon layer conformally covers the top surface of the dielectric layer; and The top surface of the amorphous silicon layer is polished until the amorphous silicon layer on the top surface of the convex parts is removed. After the amorphous silicon layer is formed on the dielectric layer, the top surface of the amorphous silicon layer is etched by using a wet etching process to form a microporous structure on the top surface of the amorphous silicon layer; or after the amorphous silicon layer is formed on the dielectric layer, the top surface of the amorphous silicon layer is bombarded by using a plasma to form nanoscale pits on the top surface of the amorphous silicon layer.

2. The method of producing a semiconductor device according to claim 1, wherein When the top surface of the amorphous silicon layer is polished, the polishing liquid has a polishing speed on the amorphous silicon layer greater than that on the dielectric layer.

3. The method of manufacturing a semiconductor device according to claim 1, wherein The transverse width of the concave part is 3-5 times the thickness of the amorphous silicon layer.

4. The method of producing a semiconductor device according to Claim 1, wherein The bottom surface of the concave part is higher than the top surface of the functional structure; and / or after the top surface of the silicon oxide layer and the top surface of the dielectric layer are polished, the top surface of the silicon oxide layer and the top surface of the dielectric layer are higher than the top surface of the functional structure.

5. The method of producing a semiconductor device according to claim 1, wherein The amorphous silicon layer is oxidized by using a thermal oxidation process or a water vapor oxidation process.

6. The method of producing a semiconductor device according to claim 1, wherein The amorphous silicon layer is oxidized at 400-450 DEG C; and / or the amorphous silicon layer is oxidized for 8-10 hours.

7. The method of producing a semiconductor device according to claim 1 or 6, wherein The semiconductor device is a back-illuminated image sensor, the substrate is a substrate of a pixel wafer, the first surface of the substrate is a back surface, a logic wafer is further bonded to a second surface of the substrate, and the functional structure is a metal layer in a back surface metal grid formed on the second surface of the substrate.

8. The method of producing a semiconductor device according to Claim 1, wherein The substrate is provided with spaced source regions and drain regions, the functional structure is a gate structure, and the gate structure is located between the source regions and the drain regions; and 9. The method of producing a semiconductor device according to Claim 1, wherein After the top surface of the silicon oxide layer and the top surface of the dielectric layer are polished, an electric connection structure electrically connected to the source regions, the drain regions and the gate structure respectively is formed in the dielectric layer. ​

Images