Anti-thermal decay red light micro LED epitaxial structure and preparation method

Abstract

The application discloses an anti-thermal-degradation red light Micro LED epitaxial structure and a preparation method thereof. The epitaxial structure comprises, from bottom to top, a substrate layer, an n-type buffer layer, an n-type etching stop layer, an n-type ohmic contact layer, an n-type confinement layer, a quantum well structure, a p-type spacer layer, a p-type electron blocking layer and a p-type ohmic contact layer. The quantum well structure is alternatively composed of 1-5 pairs of InGaP well layers and three-section p-type AlGaInP barrier layers. The three-section barrier layers are designed with gradient energy levels and are all p-type doped. The application blocks the overflow of electrons by the gradient energy level barrier and supplements the hole concentration by p-type doping, solves the problems of high-temperature carrier loss and low recombination efficiency in the prior art, makes the 85 DEG C external quantum efficiency decay rate less than or equal to 10%, prolongs the service life to more than 50,000 hours, is compatible with mass production, and is suitable for the fields of display, illumination and the like.

Description

Technical Field

[0001] This invention relates to the field of Micro-LED chip technology, specifically to a heat-resistant red-light Micro LED epitaxial structure and its fabrication method. It can be widely used in micro-display panels (such as AR / VR near-eye displays, Mini LED backlight modules), high-precision red light illumination devices, short-range optical communication emitting devices, and sensors for biological fluorescence detection, providing core technical support for the commercialization breakthrough of AlGaInP-based red-light Micro LEDs. Background Technology

[0002] As a core direction of next-generation display and optoelectronic technology, the key bottleneck for achieving full-color Micro LED lies in the performance of red light devices—existing red Micro LED technologies all have insurmountable defects that cannot meet commercial demands for brightness stability, efficiency, and lifespan.

[0003] 1. Inherent limitations of GaN-based red light routes:

[0004] GaN-based material systems achieve emission wavelength coverage by adjusting the In composition in the InGaN quantum well, but to reach the red light band (620–650 nm), the In composition needs to exceed 35%. High In composition leads to a lattice mismatch between the InGaN quantum well and the GaN substrate exceeding 5%, resulting in high-density dislocation defects (dislocation density can reach...). The combination of radiation and non-radiative recombination centers ultimately results in an internal quantum efficiency (IQE) that is only 1 / 5 to 1 / 3 of that of blue-green GaN-based LEDs. Furthermore, when the temperature exceeds 60°C, the efficiency decay rate rapidly exceeds 40%, making it completely unsuitable for the long-term stable operation requirements of display devices.

[0005] 2. The thermal decay challenges of the AlGaInP-based red light pathway:

[0006] To circumvent the defects of GaN-based red light, the industry generally uses the AlGaInP quaternary material system to fabricate native red Micro LEDs. This system has direct bandgap characteristics and good lattice matching with GaAs substrates (mismatch <0.1%), which can effectively reduce dislocation defects. However, the epitaxial design of existing AlGaInP red Micro LEDs suffers from carrier transport failure caused by thermal accumulation. The root cause lies in two core limitations: Firstly, the pixel size of Micro LEDs is usually less than 10 μm (as small as 1 μm), and the specific surface area is much larger than that of traditional LEDs (size ≥4 μm). The quantum well active region is only 1.5–4.5 nm thick, with an extremely short heat conduction path. The heat generated during operation is difficult to dissipate quickly, causing the quantum well junction temperature to rise rapidly to 80–120 °C. On the other hand, under high temperature conditions, the quantum well bandgap tilts, the carrier recombination position shifts to the n-type side, and the electrons, due to the increased energy of thermal motion, easily break through the limitation of the traditional single-segment barrier layer and overflow the active region. Meanwhile, the hole mobility decreases due to the high temperature (the decrease can be as much as 30%), resulting in insufficient hole concentration in the quantum well. Ultimately, the carrier radiative recombination efficiency decreases by more than 30%, and the device lifetime is shortened to less than 10,000 hours, which cannot meet the basic lifetime requirements of commercial products (usually more than 50,000 hours).

[0007] 3. Shortcomings of existing solutions:

[0008] To address the aforementioned thermal decay problem, existing technologies mostly focus on single-dimensional optimization and have not formed a systematic solution. Specific limitations are as follows: First, some solutions enhance electron confinement by thickening the barrier layer (thickness > 5 nm), but this exacerbates the lattice mismatch between the AlGaInP barrier layer and the InGaP well layer, increasing the mismatch from 0.8% to 2.5%, which in turn induces new dislocation defects, leading to increased nonradiative recombination. Second, some solutions introduce high-concentration p-type doping (doping concentration > 5 nm) into the n-type confinement layer. To fill holes, high-concentration doping can lead to reverse diffusion of charge carriers, disrupting the balance of charge carrier distribution within the quantum well and further reducing radiative recombination efficiency; thirdly, some schemes focus on surface passivation or heat dissipation structure optimization, such as deposition via plasma-enhanced chemical vapor deposition (PECVD). Passivation layers reduce surface recombination, or diamond substrates improve heat dissipation, but these solutions only work on the device surface or external structure and do not address the root cause of carrier transport failure inside the quantum well. The core contradiction of electron overflow and hole insufficiency at high temperatures remains unresolved.

[0009] In summary, existing technologies have not yet achieved a combination of "precise control of barrier layer energy levels and synergistic optimization of carrier concentration," and cannot fundamentally solve the thermal decay problem of AlGaInP red Micro LEDs. A novel epitaxial structure and fabrication method are urgently needed to overcome the technical bottleneck. Summary of the Invention

[0010] The purpose of this invention is to provide an epitaxial structure and fabrication method for heat-resistant red-light Micro LEDs, overcoming the three major problems caused by thermal accumulation in existing AlGaInP red-light Micro LED chips—electron overflow, insufficient hole concentration, and low radiative recombination efficiency. Ultimately, this invention provides an epitaxial structure and its fabrication method that can stably maintain high luminous efficiency under high-temperature conditions and is compatible with mass production processes, laying the foundation for the commercialization of AlGaInP-based red-light Micro LEDs.

[0011] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0012] An epitaxial structure for a heat-resistant red LED comprises, from bottom to top, a substrate layer, an n-type buffer layer, an n-type etch barrier layer, an n-type ohmic contact layer, an n-type confinement layer, a quantum well structure, a p-type spacer layer, a p-type electron blocking layer, and a p-type ohmic contact layer. The quantum well structure is composed of 1-5 pairs of InGaP well layers and three-segment p-type AlGaInP barrier layers alternatingly. The three-segment p-type AlGaInP barrier layers are, from bottom to top, a first barrier layer, a second barrier layer, and a third barrier layer, and the Al composition of the three-segment p-type AlGaInP barrier layers satisfies the following order: Al composition of the first barrier layer > Al composition of the third barrier layer > Al composition of the second barrier layer, forming a gradient energy level structure. All three p-type AlGaInP barrier layers are p-type doped with a doping concentration of [missing information]. .

[0013] In a preferred embodiment, the substrate is a GaAs substrate, which is selected from semi-insulating GaAs substrates or n-type doped GaAs substrates, with a wafer size of 2-12 inches, a thickness of 350-650 μm, and a bevel angle of 2-15°.

[0014] In a preferred embodiment, the InGaP well layer is composed of: In components =0.3–0.7, thickness 1.5–4.5 nm; the n-type confinement layer is an n-type AlGaInP confinement layer, with the following composition: Al component =0.7–1.0, =0.5, doping concentration Thickness 150–500nm.

[0015] In a preferred embodiment, the three-segment p-type AlGaInP barrier layer comprises: the first segment barrier layer consisting of... , =0.7–1.0, =0.5, thickness 2–5 nm; the composition of the second barrier layer is , =0.5–0.7, =0.5, thickness 1–3 nm; the composition of the third barrier layer is , satisfy < < , =0.5, thickness 1–3 nm.

[0016] In a preferred embodiment, the p-type spacer layer is a p-type AlGaInP spacer layer, and its composition is as follows: , =0.8–0.9, =0.5, doping concentration The thickness is 30–100 nm; the p-type electron blocking layer is a p-type AlInP electron blocking layer, with the following composition: , =0.5, doping concentration Thickness 200–900nm.

[0017] This application also provides a method for fabricating a heat-resistant red light Micro LED epitaxial structure, comprising the following steps:

[0018] S1, Epitaxial layer growth: Using MOCVD technology with hydrogen as the carrier gas, an n-type buffer layer, an n-type etch barrier layer, an n-type ohmic contact layer, and an n-type confinement layer are sequentially grown on the substrate. Then, an InGaP well layer and a three-segment p-type AlGaInP barrier layer are alternately grown 1–5 times to form a quantum well structure. Finally, a p-type spacer layer, a p-type electron blocking layer, and a p-type ohmic contact layer are grown.

[0019] S2, Post-chip processes: including p-type transparent conductive layer evaporation and annealing, epitaxial wafer and driver circuit bonding, substrate removal, Micro LED mesa fabrication, sidewall passivation and device isolation, n-type interconnect and electrode fabrication.

[0020] In a preferred embodiment, during step S1, when growing the three-segment p-type AlGaInP barrier layer, a p-type dopant source and a growth source are introduced, the growth temperature is 700–780℃, and the growth rate is 0.1–0.2 nm / s; the p-type dopant source is selected from at least one of dimethylzinc and dimagnesium thiocene; the growth source includes Al group source, Ga group source, In group source, and P group source; the Al group source is selected from trimethylaluminum or triethylaluminum, the Ga group source is selected from trimethylgallium or triethylgallium, the In group source is selected from trimethylindium or triethylindium, and the P group source is selected from phosphine or phosphine.

[0021] In a preferred embodiment, in step S2, the p-type transparent conductive layer is ITO, deposited using an electron beam evaporation process, with a thickness of 100–200 nm, an annealing temperature of 380–420 °C, and an annealing time of 150–210 s.

[0022] The parameters for the bonding process between the epitaxial wafer and the driving circuit are: bonding temperature 400–700℃, bonding pressure 3000–9000kg, and bonding time 10–60 minutes.

[0023] The substrate removal is performed using a wet solution of 10% ammonia and 10% hydrogen peroxide in a volume ratio of 4:1, with a treatment time of 35–45 minutes.

[0024] In a preferred embodiment, in step S2, the Micro LED mesa is fabricated using inductively coupled plasma etching, and the etching gas is... + ;

[0025] The sidewall passivation was performed using PECVD deposition. Passivation layer, reactant gas flow rate 1000–1400 sccm With a flow rate of 250–350 sccm Deposition temperature 230–270℃, thickness 10–100nm;

[0026] The device isolation is achieved by ion beam etching with an etching power of 280–320W and an etching time of 550–650s.

[0027] In a preferred embodiment, the driving circuit is selected from one of Si-based CMOS driving circuits, glass-based driving circuits, and flexible-based driving circuits; the prepared AlGaInP red Micro LED chip has a pixel size of 1–50 μm and a pixel pitch of 2–75 μm.

[0028] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are as follows:

[0029] This invention achieves a comprehensive breakthrough in the performance of AlGaInP red Micro LED chips through a core design of "gradient energy level barrier + p-type doping synergy" combined with a mass-production compatible fabrication process. Specific advantages are as follows:

[0030] 1. Address the root cause of electron overflow and significantly reduce thermally induced carrier loss.

[0031] To address the deficiency in existing technologies where "a single barrier layer cannot prevent electron overflow at high temperatures," this invention employs a three-stage gradient energy level design: "direct blocking by a first high-energy barrier + secondary blocking by a third relatively high-energy barrier." This reduces the probability of electron overflow at 85°C from over 30% in existing technologies to below 10%, thereby reducing thermally induced losses at the source of carrier transport and laying the foundation for improved radiative recombination efficiency.

[0032] 2. Precisely replenish hole concentration and balance carrier distribution.

[0033] To address the problem of insufficient concentration due to decreased hole mobility at high temperatures in existing technologies, this invention introduces [a specific technology / method] in all three stages of the barrier layer. The p-type doping (doping source is dimethyl zinc, doping efficiency > 80%) increases the hole concentration in the active region of the quantum well by 40%, and optimizes the carrier concentration ratio from 1:0.3 in the prior art to 1:0.8, which greatly reduces nonradiative recombination caused by carrier imbalance and reduces nonradiative recombination efficiency by 50%.

[0034] 3. Significantly improves thermal stability and extends device lifespan.

[0035] By combining the synergistic effect of electron confinement and hole replenishment, this invention effectively solves the core thermal decay problem of "sharp drop in radiative recombination efficiency at high temperatures" in existing technologies: at 85°C, the external quantum efficiency (EQE) decay rate is reduced from more than 30% in existing technologies to less than 10%; after 1000 hours of high-temperature aging at 85°C, the EQE retention rate is increased from less than 60% in existing technologies to more than 80%, and the device lifespan is extended to more than 50,000 hours, meeting the basic requirements of commercial products for stability and lifespan.

[0036] 4. Fully optimize luminous performance to adapt to various scenario requirements.

[0037] Addressing the shortcomings of existing technologies such as "low brightness, unstable wavelength, and poor current adaptability": ① Room temperature EQE has been increased from 28% to 30-32%, and the maximum luminous intensity at 85℃ has increased from 800 ppm. Increase to 1200–1300 ① To meet the brightness requirements of different scenarios such as micro-displays and lighting; ② The wavelength offset in the red light band (620–650nm) is <2 nm to avoid color deviation; ③ In the 10–100 Within the current density range, EQE fluctuation is <5% (compared to >15% in existing technologies), adapting to the flexible adjustment needs of low-brightness near-eye displays and high-brightness outdoor lighting.

[0038] 5. Compatible with mass production processes, reducing commercialization costs.

[0039] Addressing the issues of high equipment investment and low yield due to special process requirements in existing technologies: ① Epitaxial growth is based on mature MOCVD equipment, and post-chip processes use conventional equipment such as electron beam evaporation, ICP etching, and PECVD, eliminating the need for additional dedicated equipment; ② Parameters such as layer thickness, doping concentration, and growth temperature are all set within reasonable ranges (e.g., growth temperature 700–780℃, bonding time 10–60 minutes), providing a wide process window, high fault tolerance, and device yield exceeding 90%; ③ Pixel sizes can cover 1–50μm, and the driving circuit is compatible with Si-based CMOS, glass-based, and flexible substrates, offering strong application scalability and providing flexible solutions for commercialization in different fields. Attached Figure Description

[0040] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of a heat-resistant red light Micro LED epitaxial structure according to the present invention;

[0042] Figure 2 This is a flowchart illustrating a method for fabricating a heat-resistant red-light Micro LED epitaxial structure according to the present invention.

[0043] Figure 3 This is a schematic diagram of the chip structure of a heat-resistant red light Micro LED according to the present invention;

[0044] The components are as follows: 1. Substrate layer; 2. n-type buffer layer; 3. n-type etch barrier layer; 4. n-type ohmic contact layer; 5. n-type confinement layer; 6. Quantum well structure; 7. First barrier layer; 8. Second barrier layer; 9. Third barrier layer; 10. p-type spacer layer; 11. p-type electron blocking layer; 12. p-type ohmic contact layer; 13. Epitaxial wafer; 14. p-type ITO transparent conductive layer; 15. Bonding metal layer; 16. Si-based CMOS driving circuit; 17. Passivation layer; 18. n-type ITO transparent conductive layer; 19. n-type electrode. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0046] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0048] Furthermore, some of the aforementioned terms, besides indicating direction or positional relationships, may also have other meanings. For example, the term "above" may, in certain circumstances, indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0049] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0050] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0051] Example 1

[0052] Please see Figure 1 This application provides a heat-resistant red-light Micro LED epitaxial structure, which, from bottom to top, consists of a substrate layer 1, an n-type buffer layer 2, an n-type etch barrier layer 3, an n-type ohmic contact layer 4, an n-type confinement layer 5, a quantum well structure 6, a p-type spacer layer 10, a p-type electron blocking layer 11, and a p-type ohmic contact layer 12. The material selection, parameter settings, and design principles of each layer are as follows:

[0053] Substrate 1: A GaAs substrate is used, which can be a semi-insulating GaAs substrate or an n-type doped GaAs substrate. The wafer size covers 2–12 inches, the thickness is 350–650 μm, and the bevel angle is 2–15°. The reason for choosing the GaAs substrate is that its lattice constant matches the AlGaInP material very well (mismatch <0.1%), which can reduce epitaxial layer dislocation defects. The bevel angle design can effectively suppress the generation of twin defects, while the thickness and size range are suitable for the wafer mounting requirements of mainstream metal-organic chemical vapor deposition (MOCVD) equipment, avoiding substrate warping during growth.

[0054] n-type buffer layer 2: This is an n-type GaAs buffer layer, using silane as the dopant source, with the doping concentration controlled at [value missing]. The thickness is 100–300 nm; the core function of this layer is to provide a flat, low-defect epitaxial growth surface, so that the dislocation density of subsequent epitaxial layers is reduced from that on the substrate surface. Down to The following provides a fundamental guarantee for device performance.

[0055] n-type etch stop layer 3: This is an n-type AlGaInP etch stop layer, and its composition is as follows: (Where the Al component x = 0.1–0.4, y = 0.5), also using silane as the doping source, the doping concentration is consistent with that of the n-type buffer layer 2. The thickness of this layer is 100–300 nm. The purpose of this layer is to achieve selective etching stop in subsequent chip etching processes by utilizing the fact that the etching rate of AlGaInP is much lower than that of GaAs substrate, thus avoiding the penetration of etching solution into the epitaxial layer when GaAa substrate is removed, and protecting the structural integrity of the epitaxial layer.

[0056] n-type ohmic contact layer 4: This is an n-type GaAs ohmic contact layer, with the doping concentration increased to [missing value]. The thickness is controlled between 10 and 50 nm; a high doping concentration can significantly reduce the contact resistance between this layer and the subsequent n-type electrode 19 (making the contact resistance < 10 nm). The thinner design reduces the absorption loss of red light, ensuring the light output efficiency of the device.

[0057] n-type confinement layer 5: This is an n-type AlGaInP confinement layer, with the following composition: (Among them, Al component) =0.7–1.0, =0.5), doping concentration is The thickness is 150–500 nm; the high Al composition design enables the layer to form a high barrier of more than 300 meV, which can effectively limit the diffusion of charge carriers to the n-type side; the setting of the thickness range ensures the barrier height while taking into account the lattice matching, and avoids stress accumulation due to excessive layer thickness.

[0058] Quantum well structure 6: As the core innovation of this invention, this structure consists of 1–5 pairs of alternating "InGaP well layers + three-segment p-type AlGaInP barrier layers", which is the core region for carrier radiative recombination.

[0059] InGaP well layer: composition is (In component) =0.3–0.7), with a thickness of 1.5–4.5 nm; the choice of In composition corresponds to the red light band of 620–650 nm, and the thickness needs to balance the luminescence intensity and carrier confinement - too thin will easily lead to carrier quantum tunneling overflow, while too thick will aggravate the lattice mismatch with the barrier layer.

[0060] The three-segment p-type AlGaInP barrier layer consists of three layers from bottom to top: the first barrier layer (7), the second barrier layer (8), and the third barrier layer (9). The Al composition of these three barrier layers satisfies the formula: Al composition of the first barrier layer (7) > Al composition of the third barrier layer (9) > Al composition of the second barrier layer (8), forming a gradient energy level structure of "high energy level - slightly lower energy level - relatively higher energy level." All three barrier layers are p-type doped with a doping concentration of [missing information]. The doping source is dimethyl zinc (dimethyl zinc has a doping efficiency of over 80% in AlGaInP and does not introduce deep-level defects); the first barrier layer consists of 7 components. ( =0.7–1.0, =0.5), with a thickness of 2–5 nm, the high-energy barrier can directly block electrons from overflowing upwards from the InGaP well layer; the second barrier layer is composed of 8 components. ( =0.5–0.7, =0.5), with a thickness of 1–3 nm. The slightly lower energy level design reduces the lattice mismatch with the InGaP well layer (reducing the mismatch from 2.5% to 0.8%), while guiding holes to migrate to the well layer; the third barrier layer is composed of 9 components. ( satisfy < < , =0.5), with a thickness of 1–3 nm. The higher energy level design forms a "secondary barrier" to prevent electrons from overflowing from the second barrier layer 8, further enhancing the electron confinement capability;

[0061] The introduction of p-type doping can directly supplement the hole concentration in the quantum well, solve the problem of insufficient concentration caused by the decrease in hole mobility at high temperature, optimize the carrier concentration ratio from 1:0.3 in the existing technology to 1:0.8, and significantly reduce nonradiative recombination.

[0062] p-type spacer layer 10: is a p-type AlGaInP spacer layer, with the following composition: ( =0.8–0.9, =0.5), using magnesia-dicenocene as the doping source, the doping concentration is The thickness is 30–100 nm. The function of this layer is to isolate the quantum well structure 6 from the upper p-type electron blocking layer 11, so as to avoid the two layers from directly contacting each other and generating nonradiative recombination centers at the interface. At the same time, the choice of Al composition is adapted to the p-type electron blocking layer 11 to avoid the abrupt change of the barrier that would hinder carrier transport.

[0063] p-type electron blocking layer 11: is a p-type AlInP electron blocking layer, with the following composition: ( =0.5), doping concentration is The thickness is 200–900 nm; AlInP material has an extremely high barrier height (over 400 meV), which can further prevent electrons from overflowing to the p-type ohmic contact layer 12, ensuring that electrons are confined in the quantum well to participate in recombination; the thickness range needs to ensure the blocking effect, while avoiding excessive layer thickness leading to stress accumulation.

[0064] p-type ohmic contact layer 12: This is a p-type GaP ohmic contact layer, using magnesia-diocene and carbon tetrabromide as common doping sources (carbon tetrabromide can help improve the uniformity of p-type doping), with a doping concentration of [missing information]. The thickness is 50–300 nm; the band gap of GaP material is 2.26 eV, and it does not absorb red light in the 620–650 nm range, thus avoiding light loss; at the same time, its contact resistance with the ITO transparent conductive layer is low (< This can reduce the series resistance of the device.

[0065] Example 2

[0066] Please see Figure 2-3 This application provides a method for fabricating a heat-resistant red-light Micro LED epitaxial structure, based on mature MOCVD technology and post-chip processing. The method is divided into two parts: "epitaxy layer growth" and "post-chip processing." The process parameters, control logic, and operational objectives for each step are as follows:

[0067] S1, Epitaxial layer growth (based on MOCVD system, with hydrogen as the carrier gas).

[0068] Substrate pretreatment: The GaAs substrate was placed in the MOCVD reaction chamber, and arsine was introduced at 50 sccm at 600°C. Annealing for 10 minutes is intended to remove the natural oxide layer on the substrate surface, ensuring good adhesion between the subsequent epitaxial layer and the substrate, and avoiding the formation of interface defects.

[0069] n-type GaAs buffer layer growth: Trimethylgallium (TMGa, flow rate 50–100 sccm) and arsenide are introduced into the reaction chamber. (flow rate 100–200 sccm) and silane ( The growth rate is 1–5 sccm, and the growth is carried out at a temperature of 620–700℃ for 100–300 nm. The growth rate is controlled at 0.2–0.7 nm / s. The growth rate needs to be strictly controlled—too fast will easily lead to an increase in defects in the layer, while too slow will reduce production efficiency. The core of this step is to form a uniform buffer layer to provide a flat substrate for the subsequent growth of AlGaInP layers.

[0070] n-type AlGaInP etching barrier layer growth: Adjust the gas source in the reaction chamber, introducing trimethylaluminum (TMAl, flow rate 30–80 sccm), TMGa (flow rate 20–50 sccm), trimethylindium (TMIn, flow rate 10–30 sccm), and phosphine (…). The layer was grown at 700–780 °C for 100–300 nm using 150–300 sccm flow rate and 1–5 sccm flow rate of silane at a growth rate of 0.2–0.7 nm / s. The Al composition was adjusted to 0.1–0.4 by controlling the TMAl flow rate to ensure that the layer had etching resistance.

[0071] n-type GaAs ohmic contact layer growth: recovery of TMGa and The flow rate of silane was increased to 5–100 sccm and 100–200 sccm, respectively, while the flow rate of silane was increased to 5–10 sccm. The growth was carried out at 620–700 °C for 10–50 nm, and the growth rate was reduced to 0.1–0.3 nm / s. The high flow rate of silane was used to achieve a high doping concentration, while the low growth rate ensured doping uniformity and avoided contact resistance fluctuations caused by uneven doping.

[0072] n-type AlGaInP confinement layer growth: TMAl (flow rate 80–150 sccm), TMGa (flow rate 10–30 sccm), and TMIn (flow rate 10–30 sccm) are introduced again. (Flow rate 150–300 sccm) and silane (flow rate 1–5 sccm) were used to grow 150–500 nm at 700–780 °C at a growth rate of 0.2–0.5 nm / s; by increasing the TMAl flow rate, the Al composition was made to reach 0.7–1.0, forming a high barrier confinement layer.

[0073] Quantum well structure growth 6: This is the core step of epitaxial growth, which requires alternating growth of InGaP well layers and three-segment p-type AlGaInP barrier layers 1–5 times (the number of pairs is adjusted according to the brightness requirements of the device; 5 pairs result in the highest brightness, but the total thickness must be controlled to avoid stress).

[0074] InGaP well layer growth: TMGa (flow rate 30–60 sccm) and TMIn (flow rate 20–40 sccm) are introduced. (Flow rate 150–300 sccm), grow 1.5–4.5 nm at 700–780 °C, with the growth rate controlled at 0.1–0.2 nm / s. The slow growth rate ensures uniform well layer thickness and avoids wavelength shift due to thickness fluctuations.

[0075] The first stage of p-type AlGaInP barrier layer growth: Based on the above gas source, dimethyl zinc (DMZn, flow rate 0.5–2 sccm) is added as a p-type dopant source, and 2–5 nm is grown at 700–780℃ at a growth rate of 0.1–0.2 nm / s. The Al composition is adjusted to 0.7–1.0 by adjusting the TMAl flow rate.

[0076] Second stage p-type AlGaInP barrier layer growth: Reduce TMAl flow rate to reduce Al composition to 0.5–0.7, other gas sources and process parameters are the same as the first stage barrier layer 7, grow 1–3 nm.

[0077] Third-stage p-type AlGaInP barrier layer growth: Adjusting the TMAl flow rate to meet Al composition requirements < < Under otherwise unchanged conditions, growth was achieved at 1–3 nm.

[0078] p-type AlGaInP spacer layer growth: TMAl (flow rate 90–120 sccm), TMGa (flow rate 15–30 sccm), TMIn (flow rate 10–30 sccm) are introduced. (Flow rate 150–300 sccm) and magnesium thiophene ( At a flow rate of 1–5 sccm, the material was grown at 700–780 °C for 30–100 nm at a growth rate of 0.2–0.5 nm / s, with the Al composition controlled to 0.8–0.9 by the TMAl flow rate.

[0079] Growth of p-type AlInP electron blocking layer: TMAl (flow rate 100–180 sccm) and TMIn (flow rate 100–180 sccm) are introduced. (Flow rate 150–300 sccm) and magnesia-dicerocene (flow rate 1–5 sccm) were used to grow 200–900 nm at 700–780 °C at a growth rate of 0.2–0.5 nm / s. The flow rate ratio of TMAl to TMIn was controlled at 1:1 to ensure the Al composition was optimal. =0.5.

[0080] p-type GaP ohmic contact layer growth: TMGa is introduced (flow rate 50–100 sccm). (Flow rate 150–300 sccm), magnesia (flow rate 5–10 sccm) and carbon tetrabromide ( The flow rate is 0.1–1 sccm, and the growth temperature is 700–780℃ for 50–300 nm. The growth rate is 0.2–0.5 nm / s. The addition of carbon tetrabromide can improve the uniformity of p-type doping and avoid the increase in contact resistance caused by excessively low local doping concentration.

[0081] S2, Post-chip process (compatible with existing Micro LED mass production line equipment)

[0082] p-type ITO transparent conductive layer 14 vapor deposition and annealing:

[0083] A p-type ITO transparent conductive layer 14 (indium tin molar ratio 9:1) was deposited on the surface of a p-type GaP ohmic contact layer using electron beam evaporation (EB) process, with the thickness controlled at 100–200 nm (too thin a layer would result in excessive resistance, while too thick a layer would affect the red light transmittance), and the deposition rate was 0.5–1.5 nm / s.

[0084] After vapor deposition, rapid thermal annealing (RTA) is performed at 380–420°C for 150–210 seconds. The purpose is to activate the charge carriers in ITO and reduce the contact resistance between ITO and the p-type GaP layer, thus reducing the contact resistance from the level before annealing. Down to the following;

[0085] Epitaxial wafer 13 is bonded to the drive circuit:

[0086] Preparation of bonding metal layer 15: A multilayer metal structure of “300nm Cr / 300nm Pt / 200nm Au” was deposited on the surface of the ITO layer by electron beam evaporation. The Cr layer is used to enhance the adhesion between the metal and ITO, the Pt layer is used to prevent Au from diffusing into the epitaxial layer, and the Au layer ensures excellent conductivity. The deposition rate is 0.5–1.5 nm / s.

[0087] Driving circuit preprocessing: A “Cr / Pt / Au” bonding metal layer 15, consistent with the epitaxial wafer 13, is deposited on the front side of the driving circuit. The driving circuit can be selected according to the application scenario, such as Si-based CMOS driving circuit 16 (suitable for high integration display), glass-based driving circuit (suitable for flexible display), or flexible-based driving circuit (suitable for wearable devices).

[0088] Bonding process: Use a high-pressure bonding machine to bond for 10–60 minutes at 400–700℃ and 3000–9000 kg pressure. Too low a temperature will cause insufficient inter-metal melting and weak bonding; too high a temperature will cause metal to diffuse into the epitaxial layer and damage the device performance. The pressure setting must ensure that the metal layers are in close contact to form a stable electromechanical connection.

[0089] GaAs substrate removal:

[0090] Wet etching process is adopted, and the etching solution is a mixed solution of "10% ammonia water + 10% hydrogen peroxide" (volume ratio 4:1). The bonded structure is immersed in the etching solution for 35–45 minutes.

[0091] The corrosion mechanism is: hydrogen peroxide oxidizes GaAs to form... Ammonia water can dissolve This allows for selective removal of GaAs substrates. The etching solution exhibits an extremely low etching rate (<0.1 nm / min) on the upper AlGaInP layer, effectively protecting the epitaxial layer structure.

[0092] Micro LED mesa fabrication:

[0093] Photolithography patterning: A 500–3000 nm thick positive photoresist (such as model 5214) is spin-coated onto the exposed n-type AlGaInP etch barrier layer. After UV exposure, it is developed with a tetramethylammonium hydroxide (TMAH) aqueous solution for 100–140 s to form a mesa pattern with a diameter of 1–50 μm and a pixel pitch of 2–75 μm (the pixel size and pitch are adjusted according to the display resolution requirements, such as AR / VR displays requiring a small size of less than 5 μm, and outdoor displays requiring a large size of 50 μm).

[0094] Inductively Coupled Plasma Etching (ICP): + The etching gas is 1:1 (volume ratio), the etching power is 300–500W, and the etching depth is up to the p-type ITO transparent conductive layer 14. The mesa verticality (sidewall verticality > 85°) and the sidewall roughness < 5nm are ensured to avoid leakage due to sidewall roughness. After etching, the residual photoresist is removed with a mixed solution of acetone and isopropanol.

[0095] Sidewall passivation and device isolation:

[0096] Passivation layer 17 deposition: PECVD process was used. (Flow rate 1000–1400 sccm) and (Flow rate 250–350 sccm) as reactant gas, depositing a 10–100 nm thick layer at 230–270 °C and 90–110 W power. Passivation layer 17, deposition rate 0.8–1.2 nm / s; low-temperature deposition avoids device damage due to high temperature, resulting in a dense layer. Passivation layer 17 can effectively cover the sidewalls of the countertop, reducing the recombination of sidewall leakage current and surface non-radiative current.

[0097] Device isolation: Ion beam etching (IBE) is used to etch through the p-type ITO transparent conductive layer 14 and the bonding metal layer 15 at a power of 280–320W for 550–650s to achieve electrical isolation between adjacent Micro LED pixels. The etching selectivity must be >20:1 to avoid damage to the underlying epitaxial structure.

[0098] n-type interconnects and electrode fabrication:

[0099] Mask layer deposition and patterning: A 300nm thick mask layer was deposited using PECVD technology. A mask layer (process parameters are the same as passivation layer 17) is then spin-coated with photoresist and patterned to expose the area where n-type electrodes 19 need to be fabricated.

[0100] Window etching: ICP etching process is used to... Etching gas (flow rate 25 sccm) was used for 350–450 s to remove the mask layer and expose the n-type GaAs ohmic contact layer; an n-type ITO transparent conductive layer 18 was deposited to realize the n-type interconnect.

[0101] Electrode deposition: "300nm Cr / 300nm Pt / 200nm Au" is deposited as n-type electrode 19 by electron beam evaporation. Then, excess photoresist and metal are removed by "lift-off" to form the n-type electrode 19 pattern, ensuring that the electrode and the n-type ohmic contact layer 4 form a good ohmic connection.

[0102] Example 3

[0103] This application provides a method for fabricating a heat-resistant red-light Micro LED epitaxial structure, featuring a 6-pair quantum well structure suitable for AR / VR near-eye displays, with a pixel size of 5μm, specifically including:

[0104] Substrate selection: 4-inch n-type GaAs substrate, 500μm thick, with a 6° bevel angle;

[0105] Key parameters for epitaxial layer growth:

[0106] n-type GaAs buffer layer: silane doping concentration Thickness 200nm, growth temperature 650℃, growth rate 0.5nm / s;

[0107] n-type AlGaInP etch barrier layer: Al composition x=0.2, silane doping concentration Thickness 200nm, growth temperature 750℃, growth rate 0.5nm / s;

[0108] n-type GaAs ohmic contact layer: silane doping concentration Thickness 30nm, growth temperature 650℃, growth rate 0.2nm / s;

[0109] n-type AlGaInP confinement layer: Al component =0.8, silane doping concentration Thickness 300nm, growth temperature 750℃, growth rate 0.4nm / s;

[0110] Quantum well structure 6 (3 pairs):

[0111] InGaP well layer: In composition =0.5, thickness 3nm, growth temperature 750℃, growth rate 0.15nm / s;

[0112] First barrier layer: Al component =0.9, dimethylzinc doping concentration Thickness 3nm, growth rate 0.15 nm / s;

[0113] Second barrier layer: Al component =0.6, dimethyl zinc doping concentration Thickness 2nm, growth rate 0.15nm / s;

[0114] Third barrier layer: Al component =0.8, dimethylzinc doping concentration Thickness 2nm, growth rate 0.15nm / s;

[0115] p-type AlGaInP spacer layer: Al composition =0.85, magnesium pyrocene doping concentration Thickness 50nm, growth temperature 750℃, growth rate 0.4nm / s;

[0116] p-type AlInP electron blocking layer: Al composition =0.5, magnesium pyrocene doping concentration Thickness 500nm, growth temperature 750℃, growth rate 0.4nm / s;

[0117] p-type GaP ohmic contact layer: Magnesium diacene and carbon tetrabromide doping concentration Thickness 150nm, growth temperature 750℃, growth rate 0.4nm / s;

[0118] Key parameters of post-chip manufacturing process:

[0119] ITO transparent conductive layer: thickness 150 nm, electron beam evaporation rate 1 nm / s, annealing temperature 400℃, annealing time 180s;

[0120] Bonding process: Si-based CMOS driving circuit is selected, bonding temperature is 500℃, bonding pressure is 4500kg, and bonding time is 30 minutes.

[0121] Substrate removal: Immersion time in etching solution for 40 minutes;

[0122] Mesa fabrication: mesa diameter 5μm, pixel pitch 10μm, ICP etching power 400W;

[0123] Passivation and isolation: The passivation layer thickness is 50nm, the IBE etching power is 300W, and the etching time is 600s.

[0124] Example 4

[0125] This application provides a method for fabricating a heat-resistant red-light Micro LED epitaxial structure, featuring a quantum well structure with 5 pairs of 6 quantum wells, suitable for outdoor displays, and a pixel size of 50μm. Specifically, it includes:

[0126] The difference from Example 3 is as follows:

[0127] Quantum well structure 6: It adopts 5 pairs of "InGaP well layers + three-segment barrier layers", wherein the thickness of the InGaP well layer is 2 nm, the thickness of the first barrier layer is 2.5 nm, and the thickness of the second and third barrier layers is 1.5 nm each. The remaining parameters are the same as those in Example 3.

[0128] Post-chip manufacturing process:

[0129] The driving circuit uses a glass-based driving circuit, with a bonding temperature of 600℃, a bonding pressure of 6000kg, and a bonding time of 40 minutes.

[0130] The table surface has a diameter of 50μm and a pixel pitch of 75μm.

[0131] The remaining epitaxial growth and post-processing parameters are completely consistent with those in Example 3.

[0132] Performance comparison tests were conducted on the chips of Examples 3 and 4 and existing technology chips:

[0133]

[0134] Note: 1. The existing technology chip used in the test has the same basic structure as the chip of this invention (except for the quantum well barrier layer design) to ensure the comparability of the test results; 2. The wavelength offset test range is 620–650nm red light band; 3. The device lifetime estimation is based on the high temperature accelerated aging model and refers to the industry's general lifetime assessment standards.

[0135] Test results show that the high-temperature stability and luminous brightness of the chip of the present invention are significantly better than those of the prior art. Furthermore, the brightness of the 5-pair quantum well chip is slightly higher than that of the 3-pair quantum well chip due to the larger volume of the active region, which verifies the effectiveness and flexibility of the technical solution of the present invention.

[0136] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A heat-resistant red Micro LED epitaxial structure, characterized in that, From bottom to top, the structure comprises a substrate layer, an n-type buffer layer, an n-type etching stop layer, an n-type ohmic contact layer, an n-type confinement layer, a quantum well structure, a p-type spacer layer, a p-type electron blocking layer and a p-type ohmic contact layer; the quantum well structure is composed of 1-5 pairs of InGaP well layers and three-section p-type AlGaInP barrier layers alternately; the three-section p-type AlGaInP barrier layers are sequentially a first section barrier layer, a second section barrier layer and a third section barrier layer from bottom to top, and the Al component of the three-section p-type AlGaInP barrier layers satisfies the condition of first section barrier layer Al component > third section barrier layer Al component > second section barrier layer Al component, forming a gradient energy level structure; the three-section p-type AlGaInP barrier layers are all p-type doped, and the doping concentration is .

2. The heat-resistant red light Micro LED epitaxial structure of claim 1, wherein, The substrate layer is a GaAs substrate selected from a semi-insulating GaAs substrate or an n-type doped GaAs substrate, with a wafer size of 2-12 inches and a thickness of 350-650 μm and an offcut angle of 2-15°.

3. The heat-resistant red Micro LED epitaxial structure of claim 1, wherein, The composition of the InGaP well layer is , the In composition = 0.3-0.7, and the thickness is 1.5-4.5 nm; the n-type confinement layer is an n-type AlGaInP confinement layer, the composition of which is , the Al composition = 0.7-1.0, = 0.5, the doping concentration , and the thickness is 150-500 nm.

4. The heat-resistant red Micro LED epitaxial structure of claim 1, wherein, The three-section p-type AlGaInP barrier layer has: a first section barrier layer with a composition of , = 0.7 - 1.0, = 0.5, a thickness of 2 - 5 nm; a second section barrier layer with a composition of , = 0.5 - 0.7, = 0.5, a thickness of 1 - 3 nm; and a third section barrier layer with a composition of , satisfying < < , = 0.5, a thickness of 1 - 3 nm.

5. The heat-resistant red Micro LED epitaxial structure of claim 1, wherein, The p-type spacer layer is a p-type AlGaInP spacer layer, the composition is , = 0.8-0.9, = 0.5, the doping concentration , the thickness is 30-100 nm; the p-type electron blocking layer is a p-type AlInP electron blocking layer, the composition is , = 0.5, the doping concentration , the thickness is 200-900 nm.

6. A method for preparing the heat-resistant red light Micro LED epitaxial structure according to any one of claims 1-5, characterized in that, The method comprises the following steps: S1, epitaxial layer growth: using MOCVD technology, an n-type buffer layer, an n-type etching stop layer, an n-type ohmic contact layer and an n-type confinement layer are sequentially grown on the substrate layer by using hydrogen as a carrier gas; then, an InGaP well layer and a three-segment p-type AlGaInP barrier layer are alternately grown 1-5 times to form a quantum well structure; finally, a p-type spacer layer, a p-type electron blocking layer and a p-type ohmic contact layer are grown; S2, chip post-process: including p-type transparent conductive layer evaporation and annealing, epitaxial wafer and driving circuit bonding, substrate removal, Micro LED mesa preparation, sidewall passivation and device isolation, n-type interconnection and electrode preparation.

7. The method of claim 6, wherein the method further comprises: In step S1, when the three-segment p-type AlGaInP barrier layer is grown, a p-type doping source and a growth source are introduced, the growth temperature is 700-780°C, and the growth rate is 0.1-0.2 nm / s; the p-type doping source is selected from at least one of dimethyl zinc and methylmagnesium; the growth source includes an Al group source, a Ga group source, an In group source and a P group source; the Al group source is selected from trimethylaluminum or triethylaluminum, the Ga group source is selected from trimethylgallium or triethylgallium, the In group source is selected from trimethylindium or triethylindium, and the P group source is selected from phosphine or phosphine.

8. The preparation method of the heat-resistant red light Micro LED epitaxial structure according to claim 6, characterized in that, In step S2, the p-type transparent conductive layer is ITO, which is deposited by an electron beam evaporation process, with a thickness of 100-200 nm, an annealing temperature of 380-420°C and an annealing time of 150-210 s; The parameters of the epitaxial wafer and driving circuit bonding process are as follows: bonding temperature 400-700°C, bonding pressure 3000-9000 kg, and bonding time 10-60 minutes; The substrate removal is performed by using a wet solution of 10% ammonia water and 10% hydrogen peroxide with a volume ratio of 4:1, and the processing time is 35-45 minutes.

9. The method of claim 6, wherein the method further comprises: In step S2, the Micro LED mesa preparation adopts inductively coupled plasma etching, and the etching gas is + ; The sidewall passivation is by PECVD deposition The passivation layer is by a reaction gas with a flow rate of 1000-1400 seem with a flow rate of 250-350 seem at a deposition temperature of 230-270 °C and a thickness of 10-100 nm; The device isolation is performed by ion beam etching, with an etching power of 280-320 W and an etching time of 550-650 s.

10. The method of claim 6, wherein the method further comprises: The driving circuit is selected from one of a Si-based CMOS driving circuit, a glass-based driving circuit and a flexible-based driving circuit; the prepared AlGaInP red light Micro LED chip has a pixel size of 1-50 μm and a pixel pitch of 2-75 μm.

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