Optoelectronic device with improved charge carrier injection and method for manufacture thereof

Abstract

The invention concerns an optoelectronic device comprising a hole injection channel with inclined sidewalls extending through the active layer and an underlying first n-doped layer, such that charge carriers from a second p-doped layer arranged above the active layer are injected both vertically and laterally into the underlying active layer. Improved mobility of holes and a resultant higher rate of recombination results in improved quantum efficiency. The dimensions and location of the hole injection channel are controllable, allowing greater uniformity of performance. A method of manufacturing such an optoelectronic device based on an epitaxial lateral overgrowth process and an optoelectronic arrangement comprising such optoelectronic devices are also disclosed.

Description

[0001] 2024PF00205

[0002] OPTOELECTRONIC DEVICE WITH IMPROVED CHARGE CARRIER INJECTION AND METHOD FOR MANUFACTURE THEREOF

[0003] The current application claims priority of the German patent application DE 10 2024 123 929 . 8 dated August 21 , 2024 , the disclosure of which is incorporated herein in its entirety by reference . The present invention concerns an optoelectronic device , particularly a micro light emitting diode ( pLED) , configured to achieve improved internal quantum efficiency and more uniform, reliable performance parameters .

[0004] BACKGROUND

[0005] Optoelectronic devices , in particular , pLEDs , are used in a variety of applications such as video displays for consumer electronics , wearable devices and cars , augmented and virtual reality devices , and highspeed short distance datalinks . Typically pLEDs are defined by lateral dimensions in the micrometer range , in particular , between 1 pm and 100 pm .

[0006] Conventional pLEDs are typically based on a common epitaxial structure where the active region is sandwiched between a p-doped layer and an n-doped layer to form a p-n j unction . Charge carriers , that is , holes from the p-doped layer and electrons from the n-doped layer diffuse into the active region, which typically comprises a multi quantum well structure , formed by alternating quantum well and quantum barrier layers . The charge carriers diffuse from one quantum well to the next sequentially . In nitride-based semiconductors , the wider bandgap of the barrier layers obstructs diffusion, particularly for holes , due to their lower mobility . As a result , most of the holes recombine in quantum wells closest to the p-doped layer before they have a chance of diffusing any further . This results in reduced internal quantum efficiency .

[0007] Carrier inj ection via v-pits has been proposed, for example , in DE102016103346A1 and US8698163B2 , where v-pits randomly formed at the surface of semiconductor material through propagation of threading dislocations in the epitaxial structures are used as sites of carrier 2024PF00205 inj ection, allowing access to more quantum well layers via the v-pit sidewalls . Due to the statistically random distribution of the size , density and location of v-pits , implementation of v-pit-based carrier inj ection in small-area pLEDs is challenging due significant variation in the number and size of v-pits per device , thus contributing to nonuniformity and unreliability of achievable resultant output performance . Large density and / or dimensions of v-pits in the ]1LED reduces the available active illumination area , whereas low density and / or dimensions of v-pits , or absence of v-pits in a ]1LED results in lower rates of hole inj ection . As the dimension of the optoelectronic device is reduced, in particular , for devices with lateral dimensions below 10 pm, the resultant variation in output performance has significant implications on the achievable output quality .

[0008] It is an obj ect of the present application to address the above mentioned challenges , thereby enabling production of efficient pLEDs with a narrow distribution of performance parameters .

[0009] SUMMARY OF THE INVENTION

[0010] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0011] The inventors propose a novel optoelectronic device with reduced defect density and lateral hole inj ection via one controllably positioned hole inj ection channel featuring inclined sidewalls . In particular , the proposed optoelectronic device features epitaxial layers deposited using an epitaxial lateral overgrowth ( ELO ) process that is controlled to result in a hole inj ection channel with inclined sidewalls located at the center of the device , resulting in uniform current inj ection in the active region .

[0012] The proposed approach is in particular concerned with pLED devices having lateral dimensions between 0 . 5 pm and 50 pm, in particular , between 1 pm and 20 pm, and in particular, between 1 pm and 10 pm. 2024PF00205

[0013] Epitaxial lateral overgrowth ( ELO ) relies on selective epitaxy, m particular as exhibited in processes such as metalorganic vapour phase epitaxy (MOVPE ) , hydride vapour phase epitaxy ( HVPE ) and sublimation growth . Selective epitaxy describes spatially controlled growth of an epitaxial layer through openings in a patterned mas k . The mas k material , usually a dielectric , is selected such that nucleation and direct growth of the semiconductor material on the surface of the mas k is effectively suppressed . As a result of the selectivity of the mask, growth starts from a seed layer deposited underneath and / or within the openings in the mask and expands laterally . The choice of mask will therefore depend on the semiconductor material system used, with common dielectric mas k materials for nitride-based epitaxy including silicon oxide ( SiO2) , silicon nitrides ( SiNx) , among others .

[0014] During an ELO process , the patterned mas k leads to a filtering of defects , in particular , crystal defects for example threading dislocations and the like , with the microstructure of the deposited epitaxial layers above the mas k reproducing the underlying template formed by the seed layer and the openings in the mask . In essence , the propagation of crystal defects arising from the seed layer is substantially prevented by the mask, thereby constraining dislocations to regions corresponding to the mas k openings . A filtering of defects above the mas k thereby results , allowing the growth of regions of significantly reduced density of crystal defects , with a comparative reduction in threading dislocation density in the laterally overgrown region in the order of 102to 104cm-2. In this regard the term crystal defects shall encompass several different types of defects and dislocations , including for example threading dislocations or screw dislocation .

[0015] Conventionally ELO is implemented using mas k patterns comprising stripe-shaped openings . The resultant elongated profile is particularly suitable for long and narrow devices such as laser diodes , but is unsuitable for pLEDs due to geometrical restrictions . Furthermore , the location of naturally formed v-pits in conventional stripe-based ELO follows the underlying mas k pattern . However, the dimensions and density of v-pits within the elongated strips corresponding to the 2024PF00205 openings m the patterned mas k are randomly distributed, making it challenging to design separation planes within the deposited semiconductor material that would ensure uniform distribution of v- pits in optoelectronic devices formed therefrom. The variation in v- pit dimensions additionally results in a variation in achievable quantum efficiency in the resultant optoelectronic devices due to a variation in the achievable rate of charge inj ection via the v-pits .

[0016] An alternative to striped patterning of the dielectric mas k has been the use of circular, hexagonal or triangular dot-like openings . However, the formation of slow-growth facets limits the size of the overgrown area , thereby limiting the applications of the resultant semiconductor structures . In GaN, for example , implementation of ELO on a mask with circular or hexagonal dot-like openings results in hexagonal or truncated hexagonal pyramids bounded by side facets along { 1101 } planes , which are slow growing . The lateral expansion is slowed down by the formation of the slow-growth facets , thereby making it challenging to produce wide overgrown regions with low dislocation density . Furthermore , the density and dimensions of v-pits arising from threading dislocations propagating from the openings in the mask is randomly distributed, thereby making it challenging to achieve uniform performance from optoelectronic devices fabricated from the resulting semiconductor materials .

[0017] A modified approach involving use of regularly distributed circular discs to form a patterned mask on a patterned sapphire substrate is described in C-T Kuo , et al . , 2017 . "Si te-controlled crystalline InN growth from the V-pi ts of a GaN substra te . '' , Applied Surface Science 405 , 449-454 ( doi : 10 . 1016 / . apsusc . 2017 . 02 . 042 ) . The resultant pattern of regularly positioned v-pits is however characterized by a random distribution of dimensions , with reported sizes ranging from less than 1 pm to 6 pm. Such a variation of v-pit dimensions , particularly in pLEDs with lateral dimensions lower than 10 pm would result in significant performance variation . Additionally, the size of v-pits , particularly at the upper range of achieved dimensions , is too large for implementation of lateral hole inj ection, and the mas ked area 2024PF00205 covers only a small fraction of the total area, resulting m a high dislocation density in the semiconductor material .

[0018] To address the abovementioned challenges inherent in current ELO implementation approaches , the inventors propose a new approach to the design of the patterned mas k layer and the lateral overgrowth process to achieve the desired uniformity of performance in the resultant optoelectronic devices .

[0019] The proposed approach results in a reduced dislocation density over laterally overgrown semiconductor layers typical of ELO processes , making processing of devices with a very narrow distribution of pLED parameters possible . The overgrown epitaxial film is partially or fully relaxed, as thermal and lattice mismatch-based strains which characterize heteroepitaxial films directly grown on foreign substrates are avoided by growing the epitaxial film laterally from homogeneous semiconductor material . A reduction in the piezoelectric field and associated quantum confined Stark effect (QCSE ) in the quantum well active region leads to improved efficiency of pLED devices .

[0020] Additionally, inverted pyramid-shaped cavities are formed during coalescence at a geometric center of the device . These cavities have controllable dimensions and positioning , and are formed without a reliance on propagation of threading dislocations within the epitaxially grown layers . The cavities function as a hole inj ection channel . As a result , the efficiency and yield of the semiconductor fabrication process is improved, and greater uniformity in the semiconductor material is achieved . Additionally, ELO processes result in a compliance layer between the starting substrate and the epitaxial structure , said compliance layer arising either from an integrated dielectric mas k layer or a void . The compliance layer serves to substantially eliminate or greatly reduce cracking, improving wafer yield during manufacture of optoelectronic devices .

[0021] Inverted pyramid-shaped cavities in the active region are formed by coalescence during the ELO process , allowing for controllable formation of a hole inj ection channel with inclined sidewalls exactly or 2024PF00205 substantially at the center of the ]1LED chip . This enables uniform current distribution in the ]1LED and minimizes variation among pLEDs . The dimensions of the cavities can be controlled by adj ustment of process parameters and growth time . Areas with higher density of threading dislocations corresponding to mas k openings are positioned adj acent to the designated chip area , and may be used as separation planes , so that randomly distributed dislocation-related v-pits formed in the semiconductor material are subj ected to removal during further processing steps .

[0022] The design of the patterned mas k is configured to result in a concave epitaxial growth process , wherein inward growth results in expansion of fast-growing ELO facets , thereby preventing growth of fast-growing facets to extinction and the resultant sharp corners characteristic of convex epitaxial growth processes involving growth to extinction of fast-growing facets .

[0023] The proposed epitaxial structure comprises a starting substrate upon which a semiconductor seed layer, a patterned mask layer , a laterally overgrown epitaxial layer and a semiconductor stack are deposited . The deposited semiconductor stack is further processed to form optoelectronic devices .

[0024] Common starting substrates used in manufacture of ]1LED devices typically comprise silicon and sapphire . Substrates comprising bulk GaN or a GaN template deposited on a silicon or sapphire substrate may also be used . Potential formation of defects due to thermal and lattice mismatch is avoided through the ELO process , thereby allowing great flexibility in the choice of semiconductor material for subsequent semiconductor layers .

[0025] The semiconductor layers forming both the seed layer and the laterally overgrown epitaxial layer may comprise any suitable II I / V material , depending on intended application . Common material systems are based on nitrides , phosphides and arsenides , with various combinations of IT I-group elements resulting in binary, ternary or quaternary compounds . The nitride material system is of particular interest in 2024PF00205 manufacture of pLED devices due to the encompassed spectral range , with wavelengths covering the entire visible spectrum, and extending into the infrared and deep ultraviolet ranges . Implementation of ternary and / or quaternary compounds allows achievement of a tunable bandgap , with the achievable wavelengths dependent on the proportion of specific II I-group elements within the semiconductor material composition .

[0026] While the following description primarily refers to nitride-based semiconductor materials , in particular, Il l-nitrides exhibiting wurtzite crystal structures , the proposed approach is not limited thereto , and may be applied to any other semiconductor materials and / or material systems , either singly or in combination .

[0027] A method of processing an optoelectronic device according to the proposed principle involves a first step of providing a growth substrate . The growth substrate may comprise any suitable material , with commonly available options including but not limited to silicon and sapphire . The growth substrate may be subj ected to a variety of processes to improve surface characteristics conducive to epitaxial growth . Preparatory processes employed to growth substrates include but are not limited to annealing , chemical cleaning, polishing and / or structuring of the growth surface . Additional preparation may include low temperature deposition of a buffer layer of semiconductor material , typically comprising a compound from the same material system as the semiconductor layers to be grown on the growth substrate . For I II- nitride materials , the buffer layer may comprise low-temperature and optionally high temperature binary, ternary or quaternary Il l-nitrides .

[0028] A first layer of semiconductor material , hereafter also referred to as a semiconductor seed layer, is deposited on an upper surface of the prepared growth substrate . The semiconductor seed layer preferably comprises a binary semiconductor material , as the control of lateral to vertical growth is achievable through suitable variation of growth parameters , in particular growth temperature and pressure . In some aspects , the semiconductor seed layer and the subsequent laterally grown layers may comprise a ternary or quaternary semiconductor material . Where ternary semiconductor materials are used, the control 2024PF00205 of lateral to vertical growth requires additional adj ustment of process parameters based on material composition, increasing the complexity of the process , in particular where the composition of the ternary semiconductor material is not uniform within the epitaxially grown layers .

[0029] A patterned dielectric mask layer is arranged on a surface of the semiconductor seed layer facing away from the growth substrate . The dielectric mas k is selected to prevent nucleation and direct growth of semiconductor material on its surface , restricting epitaxial growth to openings in the mask . The dielectric mas k layer may comprise any suitably selective material , with dielectric materials comprising silicon oxide ( SiO2) , silicon nitrides ( SiNx) commonly employed for ELO processes involving GaN . Suitable processes for the deposition of the dielectric mas k layer include but are not limited to plasma-enhanced chemical vapour deposition ( PECVD) , metal organic chemical vapour deposition (MOCVD) or RF sputtering .

[0030] The dielectric mask layer is designed to comprise substantially rectangular elements arranged to form a pattern of lattices of substantially equilateral polygons bounded by the mas k openings , each opening arranged at an angle substantially equal to 60 ° or 120 ° with respect to adj acent openings , forming, in particular substantially equilateral triangles , rhombuses and / or hexagons . Some aspects feature parallelograms with 120 ° / 60 ° and / or elongated hexagons . In some aspects , each of the faces of the polygons is aligned along a direction substantially parallel to the <1100> crystal direction of the semiconductor lattice .

[0031] The orientation of the dielectric mask openings determines the growth rate of the facets comprising the epitaxial layer . In particular , for wurtzite I ll-nitrides , it is particularly advantageous to align the openings along <1100> crystal directions of the semiconductor seed layer . This allows achievement of fast lateral growth rate cross sections with top facets aligned on the { 0001 } crystal plane , and sidewall topology dependent on growth conditions , in particular , growth pressure and temperature . 2024PF00205

[0032] In some aspects , the substantially rectangular elements are incorporated into the mas k design in the form of rectangular openings in the mask layer . The length of the openings corresponding to the edges of each polygon is in some aspects restricted to a range between 1 ]im and 200 m, in particular between 5 ]im and 150 ]im, and in particular between 5 pm and 100 pm. Restriction of the opening length to micrometre dimensions serves to limit bowing of the wafer during growth and after cooling down, and additionally prevents formation and propagation of cracks . The openings are designed with a width between 0 . 1 pm and 20 pm, in particular between 0 . 1 pm and 10pm, with the width of the opening corresponding directly to the extent of the regions of the epitaxial structure exhibiting an elevated density of crystal defects .

[0033] Epitaxial growth of the semiconductor layers is achieved using suitable processes characterized by selective epitaxy and growth anisotropy . In particular , MOVPE and HVPE processes allow suppression of growth on the dielectric mask through suitable choice of growth parameters , temperature , pressure , and mole fraction of the active elements . Achievement of different growth rates on different crystallographic planes as a result of growth anisotropy allows control of the topography of lateral overgrowth . Sublimation growth may also be used to implement the ELO process .

[0034] Considering a single rectangular opening with a length L and a width W, initial growth occurs within the opening in the dielectric mas k until the top surface of the patterned mas k is reached, forming a first region of semiconductor material with a density of crystal defects , in particular , threading dislocations , corresponding to the underlying semiconductor seed layer underneath the dielectric mas k, as the opening provides uninterrupted vertical growth planes . Existing crystal defects therefore propagate through the openings in the patterned mas k layer into the first region of the epitaxial layer , extending to the surface of the deposited semiconductor material in the region vertically above the openings in the patterned mask . In some aspects , in particular , where the crystal defects comprise threading dislocations , propagation of the defects through the epitaxial layers results in formation of v- pits at the upper surface of the semiconductor layers . 2024PF00205

[0035] Subsequent deposition of semiconductor results m vertical growth extending the region above the mask opening upwards , extending the first region of the epitaxial layer , and additional lateral growth, expanding the epitaxial layer laterally over the masked area, and forming a second region of semiconductor material . This second region of semiconductor material is characterized by a second density of crystal defects that is lower than the first density of crystal defects . The reduction in threading dislocation density between the first region and the second region is of an order of magnitude in the range between 102and 105cm-2and arises from the interruption of propagation planes of crystal defects from the semiconductor seed layer by the dielectric mask layer .

[0036] Crystal facets with faster growth rates tend to disappear, leaving only the slower-growing facets , which limits the size of the overgrown region . This issue can be resolved by arranging multiple fast-growing facets to form a concave growth front . Connection of the rectangular elements to form a lattice of polygon-shaped mas k material results in inward lateral growth of the epitaxial layer from boundaries formed by the plurality of mas k openings . The ELO layer is grown laterally until growth facets originating from the openings in the dielectric mas k layer partially coalesce to form a central cavity above each polygonshaped area of mask material . The lateral and vertical dimensions of the cavity are dependent on the extent of coalescence of growth fronts , which can be controlled by adj usting process parameters , in particular , growth time .

[0037] The epitaxial layer comprises regions of high threading dislocation density in regions vertically above the openings in the dielectric mask, with at least some of the threading dislocations propagating through the epitaxial layer and terminating in v-pits at the surface . The epitaxial layer further comprises hole inj ection channels with inclined sidewalls at locations substantially corresponding to the geometric centroids of the respective polygonal shapes . The hole inj ection channels are formed as a result of coalescence of inwardgrowing facets , thus the dimensions of the hole inj ection channels are governed by the extent of coalescence of the laterally overgrown layers 2024PF00205 over the patterned mas k . The resultant epitaxial structures are therefore characterized by lattices comprising polygons of ELO material formed above mask material , bounded by regions of high threading dislocation density, corresponding to the mask openings , and additionally comprising hole inj ection channels with inclined sidewalls , each located substantially at a geometric centroid of a polygon corresponding to an area of mask material .

[0038] Because the central cavities are formed by coalescence of lateral growth fronts rather than termination of threading dislocations , a cross section of the semiconductor material through the central cavities reveals an absence of threading dislocations originating in the buffer underneath the mas k, thus differentiating the cavities from naturally occurring v-pits .

[0039] While the description addresses conventional ELO, and therefore refers to openings in the dielectric mask layer, the proposed invention may be implemented in pendeo-epitaxy through suitable design of dielectric mask elements arranged on the surface of the semiconductor seed layer prior to etching to form substantially rectangular semiconductor seed columns , which are connected to form lattices of substantially equilateral polygons . The subsequent epitaxial growth steps are correspondingly adapted to pendeo-epitaxy, with formation of central cavities achieved through partial coalescence of ELO facets originating from the seed columns .

[0040] The ELO semiconductor layer forms a first doped layer on which an active layer and a second doped semiconductor layer may be deposited to form optoelectronic devices . In some aspects of the proposed invention, the first doped layer comprises an n-dopant material .

[0041] The active layer is deposited on an upper surface of the first doped semiconductor layer following the surface topography, such that an upper surface of the active layer comprises cavities with inclined sidewalls corresponding to the cavities in the first doped layer . The active layer comprises a multi quantum well structure including a plurality of barrier and quantum well layers . The lateral dimensions 2024PF00205 of the cavities measured at an upper surface of the active layer facing away from the first doped layer is between 50 nm and 2 ]im, in particular , between 100 nm and 1 ]im, in particular, between 200 nm and 400 nm, in particular , between 250 nm and 300 nm . The depth of the hole inj ection channel is in some aspects of the same order as the lateral dimensions . Additionally, a lateral distance measured from an edge of the hole inj ection channel at the upper surface of the active layer to a plane corresponding to an opening in the underlying patterned mask is between 0 . 3 ]im and 10 m, in particular, between 0 . 6 ]im and 5 ]im, in particular , between 0 . 6 ]im and 3 pm. Optimization of the lateral dimensions of the hole inj ection channel in relation to active layer surface area available for photoluminescence leads to improved output performance .

[0042] The active layer may be undoped but can also comprise a small doping concentration in some aspects . In some further aspects , the active layer may comprise at least two cladding layers , which are undoped . The cladding layers reduce or prevent a diffusion of dopants into the active layer , thus reducing aging effects . The thickness of the quantum wells and quantum barriers along the inclined sidewalls is lower than the thickness of the quantum wells and barriers along substantially horizontal planes . The reduced barrier thickness along the inclined sidewalls facilitates improved carrier mobility within the multiquantum well structure , allowing lateral inj ection of carriers into the quantum well structure . As a result , an improved carrier recombination rate is achieved throughout the active layer , in particular , in quantum well layers situated farther away from doped semiconductor layers .

[0043] A second doped semiconductor layer, in particular, a p-doped layer, is thereafter deposited on an upper surface of the active region facing away from the growth substrate , at least filling the cavities thereon . The second doped layer is in some aspects deposited such that a substantially planar upper surface is achieved .

[0044] In some aspects , the first and / or second doped semiconductor layers comprise multiple sublayers . In particular , the first doped layer may 2024PF00205 comprise additional sublayers deposited on the ELO semiconductor layer following the surface topography of the underlying template , such that the upper surface of the additional sublayers of the first doped layer comprise central cavities corresponding to the cavities formed during the ELO process . The sublayers may comprise different material composition based on the selected system, different doping concentration, doping gradients and may even be undoped in some instances . The sublayers provide a dedicated functionality such as current spreading, current inj ection, to mention a few .

[0045] In some aspects , the proposed method may comprise further processing steps including but not limited to planarizing an upper surface of the second doped semiconductor layer and / or depositing protective layers , outcoupling elements , color conversion layers , etc .

[0046] The proposed method comprises in some aspects a subsequent step involving etching through the second doped layer , the active layer and at least partially into the first doped layer such that material deposited vertically above the openings in the patterned mas k is removed . In aspects involving partial etching through the first doped layer, an optoelectronic arrangement comprising a plurality of isolated optoelectronic devices with a common first doped layer is formed . Such aspects are further processed by depositing at least one first contact surface on an exposed surface of the first doped layer , and depositing a plurality of second contact surfaces such that each isolated optoelectronic device comprises one second contact surface . The second contact surface is in some aspects positioned centrally on the upper surface of the optoelectronic device .

[0047] In other aspects , the etching process involves removal of the first doped layer at least to a depth corresponding to an upper surface of the patterned mask . A lateral etch is then conducted to separate individual optoelectronic devices from the growth substrate , the seed layer and the patterned mask . The resultant optoelectronic device is provided with a first and a second contact surface corresponding to the first and second doped semiconductor layers . 2024PF00205

[0048] The proposed invention additionally concerns an optoelectronic device , in particular, a pLED chip . The proposed optoelectronic device comprises a semiconductor stack comprising a first doped layer , an active layer with a multi quantum well structure arranged on a surface of the first doped layer , and a second doped layer arranged on a surface of the active layer . At least the first doped layer and the active layer comprise one hole inj ection channel characterized by inclined sidewalls . The hole inj ection channel is located substantially at a geometric centroid of the first doped layer and the active layer . In some aspects , the active layer , the second doped layer and at least part of the first doped layer consist of material that is substantially free of threading dislocations . The quantum well and quantum barrier layers of the active layer along the inclined sidewalls of the hole inj ection channel comprise a smaller thickness than corresponding layers aligned perpendicular to the direction of epitaxial growth .

[0049] In some aspects the optoelectronic device is characterized by a polygonal shape when viewed from the top . In particular, the device may comprise a hexagon, a triangle or a quadrilateral , in particular , a rhombus . In some aspects , at least one sidewall forming at least one of the peripheral boundaries of the optoelectronic device is oriented along the <1100> crystal direction of the semiconductor stack material . Some aspects of the optoelectronic device comprise a top surface of a semiconductor layer , in particular , a top surface of the first doped layer that is oriented substantially parallel to the { 1010 } crystal plane , i . e . the m-plane . Certain aspects of optoelectronic devices according to the proposed principle comprise at least two sidewalls inclined substantially parallel to a { 1011 } crystal facet of the material in the first doped layer .

[0050] Further aspects of the proposed invention relate to an optical arrangement comprising a plurality of optoelectronic devices according to the proposed principle . The optoelectronic arrangement further comprises at least one first contact surface connected electrically to the first doped layer , and a plurality of second contact surfaces connected electrically to the second doped layer , with each of the 2024PF00205 plurality of optoelectronic devices comprising a second contact surface .

[0051] In some aspects , the at least one first contact is formed on a common first doped layer connecting the plurality of optoelectronic devices . This configuration is achieved through an etching process that simultaneously serves as a singulation process for optoelectronic devices grown on a common substrate , wherein the etching is configured to attain an etch depth corresponding to the second doped layer, the active layer and part of the first doped layer, said part of the first doped layer being smaller than the thickness of the first doped layer . Each optoelectronic device is separated from adj acent optoelectronic devices by a trench whose upper surface comprises material of the first doped layer . In other aspects the plurality of optoelectronic devices remain as a monolithic arrangement , that is , the singulation process is omitted during processing of the optoelectronic arrangement . In other aspects , the common substrate on which the optoelectronic devices are epitaxially grown and a patterned mas k layer used during the ELO process are retained as part of the structure of the optoelectronic arrangement . In other aspects , the common substrate and the mas k layer are removed, such that a bottom surface of the optoelectronic arrangement comprises the first doped layer . In some such aspects , at least one first contact is positioned on the bottom surface of the optoelectronic arrangement to provide electrical connection to the first doped layer .

[0052] In other aspects , the optoelectronic arrangement further comprises a carrier substrate to which the plurality of optoelectronic devices is bonded, in particular , such that the geometrical relation between individual optoelectronic devices as produced on the growth substrate is maintained during transfer of the optoelectronic devices and subsequent bonding onto the carrier substrate . Such a carrier substrate comprises , in some aspects , additional circuitry required for operation of the optoelectronic arrangement , including but not limited to driver circuitry . 2024PF00205 16

[0053] In some aspects , the optoelectronic arrangement comprises connected at least some connected optoelectronic devices which are commonly controlled such that the at least some connected optoelectronic devices operate as a single device . In some such aspects , the at least some connected optoelectronic devices may comprise at least one connected or common epitaxial layer . Some aspects are configured such that at least one first group of connected optoelectronic devices is operated as an emitter while at least one other second group is operated as a detector .

[0054] SHORT DESCRIPTION OF THE DRAWINGS

[0055] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

[0056] Figure 1 shows an exemplary optoelectronic device in accordance with some aspects of the proposed principle ;

[0057] Figures 2 illustrates a top view of optoelectronic devices during a processing step in accordance with some aspects of the proposed principle ;

[0058] Figure 3 shows a cross sectional view representing a step during processing of an optoelectronic device in accordance with some aspects of the proposed principle ;

[0059] Figures 4A and 4B illustrate further aspects of the proposed optoelectronic device during a processing step in accordance with some aspects of the proposed principle ;

[0060] Figures 5A and 5B illustrate two more exemplary optoelectronic arrangements in accordance with some aspects of the proposed principle ;

[0061] Figures 6A to 6C show some process steps in manufacturing of an optoelectronic device in accordance with some aspects of the proposed principle . 2024PF00205

[0062] DETAILED DESCRIPTION

[0063] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle. The embodiments and examples are not always to scale. Likewise, different elements can be displayed enlarged or reduced in size to emphasize individual aspects. It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado, without this contradicting the principle according to the invention. Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without, however, contradicting the inventive idea.

[0064] In addition, the individual figures and aspects are not necessarily shown in the correct size, nor do the proportions between individual elements have to be essentially correct. Some aspects are highlighted by showing them enlarged. However, terms such as "above", "over", "below", "under" "larger", "smaller" and the like are correctly represented with regard to the elements in the figures. So it is possible to deduce such relations between the elements based on the figures .

[0065] Figure 1 shows an exemplary optoelectronic device (1) in accordance with some aspects of the proposed principle. The optoelectronic device (1) comprises a semiconductor stack (10) with a first doped layer (11) , an active layer (12) arranged on an upper surface of the first doped layer, and a second doped layer (13) arranged on an upper surface of the active layer. The optoelectronic device further comprises a first contact surface (16) connected to the first doped layer, and a second contact surface (17) connected to the second doped layer (13) . The first and second doped layer in the illustrated aspect comprise n- doped and p-doped semiconductor material respectively, in particular, n-doped and p-doped nitride-based semiconductor material. The first doped layer (11) and the active layer (12) are characterized by a hole injection channel (15) with inclined sidewalls, said hole injection channel being positioned substantially at a geometric centroid of the optoelectronic device. Material of the second doped layer (13) is 2024PF00205 arranged to frll in the hole injection channel (15) within the active layer (12) and extend vertically away from the active layer. In the illustrated aspect of the proposed device, an upper surface (19) of the second doped layer is planarized.

[0066] The active layer (12) is configured as a multi-quantum layer structure, comprising alternating quantum well and quantum barrier layers . The quantum well and quantum barrier layers comprise a smaller thickness along the inclined sidewalls of the hole injection channel (15) , and a greater thickness along planes substantially parallel to an upper surface (14) of the underlying first doped layer, said upper surface (14) being substantially perpendicular to the direction of epitaxial growth. The reduced thickness, in particular, of the quantum barrier layers along the sidewalls of the hole injection channel (15) allows carrier injection from the second doped layer (13) laterally into the active layer (12) . This results in a higher recombination rate, as diffusion of the holes from the second doped layer (13) into quantum well layers farther away from the second doped layer is improved. The optoelectronic device thus exhibits increased internal quantum efficiency .

[0067] The material forming the semiconductor stack (10) is in some aspects characterized by material that is substantially free of threading dislocations, particularly, threading dislocations terminating in v- pits at upper surfaces (14) of the first doped layer (11) and / or the active layer (12) and / or the second doped layer (13) . In particular, the material below the hole injection channel (15) is substantially free of threading dislocations, in particular, threading dislocations originating from below the hole injection channel and terminating at a vertex of the hole injection channel located within the first doped layer (11) . In some aspects, the substantially vertical sidewalls (18) of the device are characterized by etching-induced defects. In other aspects, the sidewalls (18) comprise surfaces subjected to regrowth or other surface treatments to mitigate etching-induced defects .

[0068] Figure 2 illustrates a top view of an exemplary optoelectronic arrangement according to some aspects of the proposed invention, said 2024PF00205 19 optoelectronic arrangement comprising a plurality of optoelectronic devices, each comprising a semiconductor stack (10) . The optoelectronic devices comprise hexagonally shaped semiconductor stacks (10) enclosed within connected substantially rectangular regions of semiconductor material corresponding to underlying openings (20) in a patterned mask arranged below the first doped layer of the semiconductor stack during an epitaxial lateral overgrowth (ELO) process. The lateral growth of the semiconductor stack occurs inwards, as shown by the inwardly advancing growth facets (22) . A partial coalescence of the growth facets originating from the surrounding openings results in formation of a hole injection channel (15) substantially at the center of the semiconductor stack. The upper surface (14) of the semiconductor stack surrounding the hole injection channel (15) is shaped like an inverted pyramid with a hexagonal base, and its lateral and vertical dimensions can be controlled through suitable selection of growth parameters such as chamber pressure and temperature, and growth time. Longer growth times corresponding to greater coalescence of lateral growth facets results in shallower cavities with smaller cross-sections. Conversely, shorter growth time corresponds to reduced coalescence of lateral growth facets, resulting in an increase in the depth and cross section of the hole injection channel. In some aspects, lateral overgrowth is terminated immediately coalescence begins, resulting in a hole injection channel terminating substantially at an upper surface of the patterned mask underlying the first doped layer of the semiconductor stack. Parts of the surface of the optoelectronic arrangement positioned vertically above openings (20) in the patterned mask are characterized by v-pits (21) , which form as a result of propagation of crystal defects, in particular, threading dislocations, through openings in the patterned mask. The threading dislocations terminate in v-pits (21) whose dimensions, density and positioning follows a random distribution. In some aspects, the semiconductor material positioned vertically above openings in the patterned mask (20) is removed by an etching process, either for singulation of the growth substrate to produce individual optoelectronic devices, or for providing access to the first doped layer, such that a contact surface can be arranged on the exposed first doped layer vertically above openings in the patterned mask. In some aspects, the semiconductor 2024PF00205 20 material positioned vertically above openings m the patterned mask (20) can be electrically inactivated by an insulating layer or by making the material insulating.

[0069] Figure 3 shows a cross-sectional view representing an exemplary optoelectronic device during an intermediate manufacturing step. A seed layer (30) comprising a binary, ternary or quaternary nitride, in particular, GaN, is provided. In the illustrated aspect, the seed layer comprises a homogeneous growth substrate for the ELO process. A patterned mask (32) comprising a plurality of substantially rectangular openings (20) connected to form polygonal patterns is arranged on an upper surface of the seed layer.

[0070] A semiconductor stack (10) comprising a first doped layer, an active layer and a second doped layer is deposited above the patterned mask (32) . The deposited semiconductor material initially grows vertically from an upper surface of the seed layer (30) via the openings (20) in the mask, subsequently extending laterally over the patterned mask (32) until growth facets originating from adjacent openings in the mask partially coalesce, resulting in a hole injection channel (15) with inclined sidewalls centered about a plane of coalescence, which substantially corresponds to a geometrical centroid of the underlying polygon-shaped mask material (32) . The active layer follows the template provided by the first doped layer, thereby comprising a corresponding hole injection channel. The second doped layer is deposited within and around the hole injection channel, extending vertically away from the active layer to form a substantially planar surface. The substantially planar surface may be achieved by a planarization process during or following deposition of the second doped layer.

[0071] Within the seed layer, crystal defects (31a, 31b) arising during the epitaxial growth process are present, with the location and density of such defects exhibiting a random distribution. The mask material (32) obstructs propagation of crystal defects (31a) situated under it. Defects located at openings (20) in the patterned mask (32) extend vertically upwards into subsequently deposited layers, terminating in 2024PF00205 21 v-pits ( 21 ) . The laterally overgrown semrconductor material is substantially free of threading dislocations , as propagation of threading dislocations ( 31a ) is hindered by the patterned mas k ( 32 ) . The central hole inj ection channel ( 15 ) formed by coalescence of growth fronts is distinguishable from the v-pits ( 21 ) formed at terminal points of threading dislocations by the substantially defect-free material at a vertex at the bottom of the hole inj ection channel . Further, the dimensions and location of the central hole inj ection channel are controllable , whereas the dimensions and location of the v-pits arising from propagation of threading dislocations are randomly distributed .

[0072] Figures 4A and 4B illustrate further aspects of the proposed invention, wherein the patterned mask is configured to comprise triangular patterns surrounded by substantially rectangular openings which are connected to form the resultant triangular lattice shown in Figure 4A . Deposition of semiconductor material through an ELO process results in triangular regions of substantially defect-free semiconductor material ( 14 ) surrounded by material deposited above openings ( 20 ) in a patterned mask, said material comprising randomly distributed threading dislocations . The growth facets ( 22 ) advance inwards during the ELO process , forming a hole inj ection channel ( 15 ) with inclined sidewalls at the center of the substantially defect-free semiconductor surface ( 14 ) .

[0073] Figures 5A and 5B show a section of an optical arrangement according to some aspects of the proposed principle . The optical arrangement comprises a plurality of optoelectronic devices ( 1 ) . For simplicity, one such optoelectronic device is shown, with adj acent optoelectronic devices only partially illustrated . In the illustration shown in Figure 5A, the plurality of optoelectronic devices is deposited on a common substrate , which, in some aspects , comprises a seed layer ( 30 ) . A patterned mask ( 32 ) is arranged on the seed layer , and a semiconductor stack is deposited selectively within the openings ( 20 ) then laterally grown over the mas k in an ELO process . Separation of the individual optoelectronic devices is achieved by etching along areas of semiconductor material corresponding to openings ( 20 ) in the underlying 2024PF00205 patterned mask. An etched trench (25) laterally surrounding each optoelectronic device (1) extends through the second doped layer (13) , the active layer (12) and partially through the first doped layer (11) such that an upper surface of the trench (25) is located within the first doped layer.

[0074] At least one first contact surface (16) is arranged on the upper surface of the trench (25) , such that an electrical connection to the plurality of optoelectronic devices (1) is achieved. Each optoelectronic device (1) is provided with a second contact surface (17) in contact with the second doped layer, with the second contact surface optionally positioned at the center of the upper surface of the optoelectronic device. Injection of electrons (23b) into the active layer (12) occurs vertically from the first doped layer (11) , while hole injection (23a) is achieved both vertically and laterally from the second doped layer (13) , with lateral hole injection facilitated by the inclined sidewalls of the hole injection channel in the first doped layer (11) and the active layer (12) .

[0075] In some aspects, as illustrated in Figure 5B the seed layer (30) and the patterned mask (32) , and optionally, part of the first doped layer (11) facing away from the second doped layer (13) is removed, such that a bottom surface of the optoelectronic arrangement comprises material of the first doped layer (11) . In some such aspects, at least one first contact surface (16) is arranged on the bottom surface of the first doped layer. The first contact surface (16) in such an arrangement may be aligned to correspond to the trenches (25) on the opposite surface of the first doped layer (11) .

[0076] In Figures 6A to 6C, steps in a method for processing an optoelectronic device according to the proposed principle are shown. In an initial step, a growth substrate (40) is provided. The growth substrate may comprise any material suitable for epitaxial growth of semiconductor material, in particular, suitable for growth of nitride-based semiconductor material. Such substrate materials include but are not limited to sapphire, silicon and bulk GaN. A seed layer (30) is deposited on the growth substrate. A patterned mask (32) is thereafter 2024PF00205 deposited on the seed layer (32) , said patterned mask comprising a plurality of substantially rectangular-shaped openings (20) connected to form patterns of polygons, in particular, hexagons, triangles and / or rhombuses. Thereafter, a first doped layer (11) , in particular, an n- doped layer, is deposited above the patterned mask, with epitaxial growth initially occurring as vertical growth on surfaces of the seed layer exposed through the openings (20) in the patterned mask (32) , and thereafter involving both vertical and lateral growth, such that the material of the first doped layer spreads laterally from the openings in the patterned mask to cover the surface of the patterned mask .

[0077] Partial coalescence of laterally advancing growth facets results in a hole injection channel (15) with inclined sidewalls. The vertical and lateral dimensions of the hole injection channel are dependent on the extent of coalescence, and can therefore be controlled by suitably adjusting process parameters, in particular, growth time. Propagation of threading dislocations from the seed layer (30) is obstructed by the patterned mask (32) . However, some threading dislocations originating from material aligned to the openings (20) in the patterned mask may propagate through the deposited semiconductor material, terminating in v-pits (21) at the upper surface of the deposited material. The dimensions, location and density of such v-pits (21) follows a random distribution.

[0078] Subsequently, an active layer (12) is deposited on a surface of the first doped layer facing away from the growth substrate. The active layer is characterized by a multi-quantum layer structure, comprising alternating quantum well and quantum barrier layers. The surface topography of the active layer follows a template provided by the underlying first doped layer (11) , such that the active layer comprises corresponding cavities (15) with inclined sidewalls. The inclination of the sidewalls of the hole injection channel (15) results in deposition of thinner quantum well and quantum barrier layers along the incline in comparison to active layer material deposited substantially perpendicular to the direction of epitaxial growth, thereby allowing lateral injection of charge carriers via the inclined 2024PF00205 24 sidewalls of the hole injection channel, and facilitating greater mobility of charge carriers, in particular, holes, between quantum wells. In some aspects, the active layer further comprises v-pits (21) extending from the first doped layer, such v-pits formed by termination of threading dislocations propagating from the seed layer (30) through openings (20) in the patterned mask.

[0079] Thereafter, a second doped layer (13) , in particular, a p-doped layer, is deposited on the active layer such that the hole injection channel (15) in the active layer is filled with material of the second doped layer (13) . The upper surface of the second doped layer (13) may be planarized. The first doped layer (11) , the active layer (12) and the second doped layer (13) form a semiconductor stack (10) .

[0080] In a further processing step illustrated in Figure 6B, an etching process is conducted, wherein semiconductor material corresponding to openings (20) in the underlying patterned mask is removed, resulting in isolated semiconductor stacks (10) , each stack corresponding to an individual optoelectronic device. The depth of an etched trench (25) laterally surrounding each semiconductor stack (10) is such that material of the patterned mask (32) and the seed layer (30) is removed so that a bottom surface of the etched trench (25) corresponds to a surface of the growth substrate (40) . Subsequent to the vertical etch, a lateral etch is performed to separate the semiconductor stack from the patterned mask, as shown in Figure 6C. Contact surfaces (16, 17) are arranged on surfaces of the first doped layer and the second doped layer respectively.

[0081] 2024PF00205

[0082] LIST OF REFERENCES

[0083] 1 optoelectronic device

[0084] 10 semiconductor stack

[0085] 11 first doped layer

[0086] 12 active layer

[0087] 13 second doped layer

[0088] 14 upper surface of first doped layer

[0089] 15 hole inj ection channel

[0090] 16 first contact surface

[0091] 17 second contact surface

[0092] 18 device sidewall

[0093] 19 upper surface of second doped layer

[0094] 20 mas k openings

[0095] 21 v-pit

[0096] 22 advancing growth facet

[0097] 23a, 23b charge carrier inj ection

[0098] 25 etched trench

[0099] 30 seed layer

[0100] 31a, 31b threading dislocations

[0101] 32 patterned mas k

[0102] 40 growth substrate

Claims

2024PF00205 26CLAIMS1. Optoelectronic device comprising:A first doped layer (11) ;An active layer (12) arranged on a surface of the first doped layer ( 11 ) ;A second doped layer (13) arranged on a surface of the active layer (12) facing away from the first doped layer; wherein the first doped layer (11) and at least the active layer (12) comprise a hole injection channel (15) with inclined sidewalls positioned substantially at a geometric centroid of the optoelectronic device when viewed from above, and wherein a bottom point of the hole injection channel (15) is located in semiconductor material that is substantially free of threading dislocations propagating from below the cavity.

2. Device according to claim 1, comprising one of the following shapes:A regular hexagon,An equilateral triangle, orA quadrilateral, in particular, a rhombus.

3. Device according to any of the preceding claims, wherein the peripheral boundaries of the optoelectronic device are oriented substantially along a <1100> crystal direction of a semiconductor material comprised at least in the first doped layer.

4. Device according to any of the preceding claims, wherein the active layer comprises a multi-quantum well structure, and wherein the thickness of quantum well and quantum barrier sublayers along the sidewalls of the hole injection channels is smaller than the thickness of quantum well and quantum barrier sublayers substantially perpendicular to the direction of epitaxial growth.

5. Device according to any of the preceding claims, characterized by lateral dimensions less than 20 pm, in particular, between 2 pm and2024PF002056 . Device according to any of the preceding claims , wherein the lateral dimensions of the cavity measured at a surface of the active layer facing away from the first doped layer is between 50 nm and 2 ]im, in particular, between 100 nm and 1 m, in particular, between 200 nm and 400 nm, in particular, between 250 nm and 300 nm .7 . Device according to any of the preceding claims , wherein a depth of the cavity measured from the surface of the active layer facing away from the first doped layer is of the same order as the lateral dimensions of the cavity measured at the surface of the active layer facing away from the first doped layer .8 . Device according to any of the preceding claims , wherein a lateral distance measured from an edge of the cavity at the surface of the active layer facing away from the first doped layer to a lateral boundary of the device along an axis passing through a geometric centre of the cavity is between 0 . 3 pm and 10 pm, in particular , between 0 . 6 pm and 5 pm, in particular , between 0 . 6 pm and 3 pm.9 . Optoelectronic arrangement comprising a plurality of optoelectronic devices according to any of the preceding claims , and further comprising :At least one first contact surface connected electrically to the first doped layer ;A plurality of second contact surfaces electrically connected to the second doped layer , wherein each of the plurality of optoelectronic devices comprises one second contact surface ; wherein at least the second doped layer and the active layer of each of the plurality of optoelectronic devices is separated from each laterally adj acent optoelectronic device by a trench extending through the second doped layer, the active layer, and at least partially through the first doped layer .10 . Optoelectronic arrangement according to claim 9 , wherein at least one first contact surface is arranged within at least one trench between adj acent optoelectronic devices , and wherein the first doped layers of at least some of the plurality of optoelectronic devices are electrically connected to each other .2024PF00205 2811 . Optoelectronic arrangement according to any of claims 9 and 10 wherein at least one first group comprising at least some of the plurality of optoelectronic devices are configured to be commonly controlled and / operated .12 . Optoelectronic arrangement according to claim 11 wherein the at least one first group of optoelectronic devices comprise at least one common epitaxial layer .13 . Optoelectronic arrangement according to any of claims 11 or 12 , further comprising at least one second group of optoelectronic devices , wherein the at least one second group of optoelectronic devices is configured to be commonly operated, and wherein the first group and the at least one second group of optoelectronic devices are controlled and / or operated independently of each other .14 . Optoelectronic arrangement according to claim 13 , wherein the at least one first group of optoelectronic devices is implemented as a light emitting arrangement , and wherein at least one second group of optoelectronic devices is implemented as a light detecting arrangement .15 . Method of processing an optoelectronic device , comprising the steps : Providing a growth substrate ;Depositing a seed layer on the growth substrate ;Arranging a patterned mask on a surface of the seed layer facing away from the growth substrate , wherein the mas k comprises a plurality of rectangular shaped openings exposing parts of the seed layer , and wherein each of the plurality of rectangular shaped openings is connected to adj acent rectangular shaped openings , such that a pattern is formed;Depositing a first doped layer on the exposed parts of the seed layer such that a lateral overgrowth of the first doped layer above the patterned mask occurs , thereby forming a plurality of cavities with inclined sidewalls , wherein each of the plurality of cavities is positioned above material of the patterned mask; Depositing an active layer on a surface of the first doped layer , such that an upper surface of the active layer exhibits a2024PF00205 29 plurality of cavities with inclined sidewalls overlaid within the plurality of cavities in the first doped layer;Depositing a second doped layer on a surface of the active layer facing away from the first doped layer .16 . Method according to claim 15 , wherein the pattern formed on the patterned mas k comprises at least one of :Hexagons ;Triangles , in particular, equilateral triangles ; or Quadrilaterals , in particular , rhombuses .17 . Method according to any of claims 15 or 16 further comprising a step of planarizing a surface of the second doped layer facing away from the active region .18 . Method according to any of claims 15 to 17 , further comprising a step of arranging a plurality of second contact surfaces on a surface of the second doped layer facing away from the active region, where each of the plurality of second contact surfaces corresponds to an area covered by an underlying island in the patterned mas k .19 . Method according to claim 18 , wherein each of the plurality of second contact surfaces is arranged at a central position vertically above one of the plurality of cavities .20 . Method according to any of claims 15 to 19 , further comprising a step of removing the growth substrate , the seed layer, the patterned mas k and, optionally, part of the first doped layer .21 . Method according to any of claims 15 to 19 further comprising a step of etching into the second doped layer, the active layer and at least partially into the first doped layer to remove at least material deposited vertically above the plurality of substantially rectangular openings in the patterned mas k, wherein optionally the step of etching comprises etching vertically through the seed layer and laterally above the patterned mask, such2024PF00205 30 that individual devices are separated from the growth substrate and the seed layer .22 . Method according to any of claims 15 to 21 further comprising a5 step of arranging at least one first contact surface in contact with the first doped layer .23 . Method according to any of claims 15 to 22 , wherein the seed layer comprises GaN and / or wherein the growth substrate comprises at least0 one of sapphire or silicon; and / or wherein the growth substrate comprises the seed layer .

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