Package including package substrate including encapsulation portion having block of interconnect portions

Abstract

A package includes a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate includes an encapsulation portion, a first metallization portion coupled to a first surface of the encapsulation portion, and a second metallization portion coupled to a second surface of the encapsulation portion. The encapsulation portion includes a first interconnect portion block, a second interconnect portion block, a plurality of pillar interconnects, and an encapsulation layer at least partially encapsulating the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects includes a first plurality of pillar interconnects coupled to the first interconnect portion block and a second plurality of pillar interconnects coupled to the second interconnect portion block.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to U.S. Non-Provisional Application Serial No. 18 / 646,659, filed April 25, 2024, with the U.S. Patent and Trademark Office, and U.S. Provisional Application Serial No. 63 / 498,487, filed April 26, 2023, with the U.S. Patent and Trademark Office. U.S. Non-Provisional Application Serial No. 18 / 646,659 claims priority and benefit to U.S. Provisional Application Serial No. 63 / 498,487. The entire contents of both applications are incorporated herein by reference as fully set forth herein and for all applicable purposes. Technical Field

[0002] Various features involve packages that include integrated devices and packaging substrates. Background Technology

[0003] A package may include a package substrate and integrated devices. These components are coupled together to provide a package capable of performing various electrical functions. The way the integrated devices and the package substrate are coupled together affects the overall performance of the package. There has always been a need to provide packages with improved performance. Summary of the Invention

[0004] Various features involve packages that include integrated devices and packaging substrates.

[0005] One example provides a package including a packaging substrate and an integrated device. The packaging substrate includes an encapsulation portion, a first metallized portion coupled to a first surface of the encapsulation portion, a second metallized portion coupled to a second surface of the encapsulation portion, and a first integrated device coupled to the package substrate via a first plurality of solder interconnects. The encapsulation portion includes a first interconnect portion block, a second interconnect portion block, a plurality of pillar interconnects, and an encapsulation layer that at least partially encapsulates the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects. The second interconnect portion block is an interconnect portion block of a different type from the first interconnect portion block. The plurality of pillar interconnects includes a first plurality of pillar interconnects coupled to the first interconnect portion block; and a second plurality of pillar interconnects coupled to the second interconnect portion block.

[0006] Another example provides an apparatus including a package substrate and an integrated device. The package substrate includes an encapsulation portion, a first metallized portion coupled to a first surface of the encapsulation portion, a second metallized portion coupled to a second surface of the encapsulation portion, and a first integrated device coupled to the package substrate via a first plurality of solder interconnects. The encapsulation portion includes a first interconnect portion block, a second interconnect portion block, a plurality of pillar interconnects, and an encapsulation layer that at least partially encapsulates the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects. The second interconnect portion block is an interconnect portion block of a different type from the first interconnect portion block. The plurality of pillar interconnects includes a first plurality of pillar interconnects coupled to the first interconnect portion block and a second plurality of pillar interconnects coupled to the second interconnect portion block.

[0007] Another example provides a method for manufacturing a package. The method provides a package substrate including an encapsulation portion, a first metallized portion coupled to a first surface of the encapsulation portion, and a second metallized portion coupled to a second surface of the encapsulation portion. The encapsulation portion includes a first interconnect portion block, a second interconnect portion block, a plurality of pillar interconnects, and an encapsulation layer that at least partially encapsulates the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects. The second interconnect portion block is an interconnect portion block of a different type from the first interconnect portion block. The plurality of pillar interconnects includes a first plurality of pillar interconnects coupled to the first interconnect portion block and a second plurality of pillar interconnects coupled to the second interconnect portion block. The method couples a first integrated device to the package substrate via the first plurality of solder interconnects.

[0008] Another example provides a method for manufacturing a package substrate. The method provides a first interconnect portion block. The method provides a second interconnect portion block, wherein the second interconnect portion block is an interconnect portion block of a different type from the first interconnect portion block. The method forms a plurality of pillar interconnects, wherein the plurality of pillar interconnects includes: a first plurality of pillar interconnects coupled to the first interconnect portion block; and a second plurality of pillar interconnects coupled to the second interconnect portion block. The method forms an encapsulation layer that at least partially encapsulates the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects, forming an encapsulation portion. The method forms a first metallization portion coupled to a first surface of the encapsulation portion. The method forms a second metallization portion coupled to a second surface of the encapsulation portion. Attached Figure Description

[0009] The various features, essence, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are used for corresponding identification throughout.

[0010] Figure 1A cross-sectional view of an exemplary package including a packaging substrate having an encapsulation portion with several interconnection portion blocks is illustrated.

[0011] Figure 2 A cross-sectional view of another exemplary package is illustrated, the package substrate having an encapsulation portion with several interconnected portion blocks.

[0012] Figure 3 A plan view of an exemplary package substrate having an encapsulation portion with several interconnected portion blocks is illustrated.

[0013] Figure 4 A cross-sectional view of another exemplary package is illustrated, the package substrate having an encapsulation portion with several interconnected portion blocks.

[0014] Figure 5 A cross-sectional view of an exemplary interconnect portion block is shown.

[0015] Figure 6 A cross-sectional view of another exemplary interconnected portion block is shown.

[0016] Figure 7 A cross-sectional view of another exemplary interconnected portion block is shown.

[0017] Figure 8 A cross-sectional view of another exemplary interconnected portion block is shown.

[0018] Figure 9 A cross-sectional view of another exemplary interconnected portion block is shown.

[0019] Figure 10 An example of the electrical path of a package including a packaging substrate having an encapsulation portion with several interconnection portion blocks is illustrated.

[0020] Figure 11 An example of the electrical path of another package including a package substrate having an encapsulation portion with several interconnection portion blocks is illustrated.

[0021] Figures 12A to 12F An exemplary process for manufacturing a package including a packaging substrate having an encapsulation portion having a plurality of interconnection portion blocks is illustrated.

[0022] Figure 13 An exemplary flowchart illustrating a method for manufacturing a package including a packaging substrate having an encapsulation portion having a plurality of interconnect portion blocks is shown.

[0023] Figures 14A to 14C An example of a process for manufacturing a coreless substrate is shown.

[0024] Figure 15 An exemplary flowchart illustrating a method for manufacturing a coreless substrate is shown.

[0025] Figures 16A to 16B An example of a process for manufacturing a core substrate is shown.

[0026] Figure 17 An exemplary flowchart illustrating a method for manufacturing a core-containing substrate is shown.

[0027] Figures 18A to 18B An exemplary process for manufacturing metallized parts is illustrated.

[0028] Figure 19 An exemplary flowchart illustrating a method for manufacturing metallized portions is shown.

[0029] Figure 20 A cross-sectional view of another exemplary package is illustrated, the package substrate having an encapsulation portion with several interconnected portion blocks.

[0030] Figure 21 A cross-sectional view of another exemplary package is illustrated, the package substrate having an encapsulation portion with several interconnected portion blocks.

[0031] Figure 22 A cross-sectional view of another exemplary package is illustrated, the package substrate having an encapsulation portion with several interconnected portion blocks.

[0032] Figure 23 Examples are shown of various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein. Detailed Implementation

[0033] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0034] This disclosure describes a package including a package substrate and a first integrated device coupled to the package substrate via a first plurality of solder interconnects. The package substrate includes an encapsulation portion, a first metallized portion coupled to a first surface of the encapsulation portion, and a second metallized portion coupled to a second surface of the encapsulation portion. The encapsulation portion includes a first interconnect portion block, a second interconnect portion block, a plurality of pillar interconnects, and an encapsulation layer that at least partially encapsulates the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects. The second interconnect portion block is an interconnect portion block of a different type from the first interconnect portion block. The plurality of pillar interconnects includes first plurality of pillar interconnects coupled to the first interconnect portion block and second plurality of pillar interconnects coupled to the second interconnect portion block. As will be further described below, using an encapsulation portion including interconnect portion blocks of different types provides several technical advantages, including the ability to customize and optimize interconnects to provide a package with improved performance and lower overall manufacturing costs.

[0035] Figure 1 A cross-sectional view of a package 100 including a package substrate having an encapsulation portion comprising a plurality of interconnect blocks is illustrated. The package 100 is coupled to a board 108 via a plurality of solder interconnects 110. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The board 108 may include a printed circuit board (PCB). The package 100 includes a package substrate 101 and an integrated device 103. The integrated device 103 is coupled to the package substrate 101 via a plurality of solder interconnects 130. A plurality of pillar interconnects (not shown) may be present between the integrated device 103 and the plurality of solder interconnects 130. In some embodiments, the plurality of pillar interconnects (not shown) coupled to the integrated device 103 and the plurality of solder interconnects 130 are considered part of the integrated device 103. The integrated device 103 may be a first integrated device.

[0036] The package substrate 101 includes an encapsulation portion 102, a metallization portion 104 (e.g., a first metallization portion), and a metallization portion 106 (e.g., a second metallization portion). The metallization portion 104 may be coupled to a first surface (e.g., a top surface) of the encapsulation portion 102. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallized interconnects 142 (e.g., a first plurality of metallized interconnects). The metallization portion 104 may include redistribution portions. The plurality of metallized interconnects 142 may include a plurality of redistributed interconnects (e.g., a first plurality of redistributed interconnects). An integrated device 103 is coupled to the plurality of metallized interconnects 142 via a plurality of solder interconnects 130. A solder mask layer 148 is coupled to the metallization portion 104. The solder mask layer 148 may be part of the metallization portion 104. The metallization portion 104 helps ensure proper alignment of the connections between the integrated device and the package substrate 101.

[0037] The metallized portion 106 may be coupled to a second surface (e.g., a bottom surface) of the encapsulation portion 102. The metallized portion 106 includes at least one dielectric layer 160 and a plurality of metallized interconnects 162 (e.g., a second plurality of metallized interconnects). The metallized portion 106 may include a redistribution portion. The plurality of metallized interconnects 162 may include a plurality of redistributed interconnects (e.g., a second plurality of redistributed interconnects).

[0038] Encapsulation portion 102 is located between metallized portion 104 and metallized portion 106. Encapsulation portion 102 includes interconnect portion blocks 105 (e.g., first interconnect portion block, second interconnect portion block, third interconnect portion block), interconnect portion blocks 107 (e.g., first interconnect portion block, second interconnect portion block, third interconnect portion block), interconnect portion blocks 109 (e.g., first interconnect portion block, second interconnect portion block, third interconnect portion block), a plurality of pillar interconnects 122, and encapsulation layer 120. Encapsulation layer 120 encapsulates interconnect portion blocks 105, interconnect portion blocks 107, interconnect portion blocks 109, and the plurality of pillar interconnects 122. Encapsulation layer (e.g., 120) may include molding material, resin, and / or epoxy resin. Encapsulation layer may be a component for encapsulation. Encapsulation layer can be provided by using compression and transfer molding processes, sheet molding processes, or liquid molding processes. In some embodiments, the encapsulation layer 120 may include a material different from at least one dielectric layer 140 of the metallized portion 104 and at least one dielectric layer 160 of the metallized portion 106. In some embodiments, the encapsulation layer 120 may include a material different from at least one dielectric layer 150 of the interconnect portion block 105, the dielectric layers (e.g., 170, 172, 174) of the interconnect portion block 107, and at least one dielectric layer 190 of the interconnect portion block 109. In some embodiments, dielectric layers 150, 172, 174, and / or 190 may include prepreg and / or polyimide.

[0039] As will be further described below, interconnection block 105, interconnection block 107, and / or interconnection block 109 may include different types of interconnection blocks. Examples of interconnection block types include coreless substrate blocks, cored substrate blocks, metallized blocks, redistributed blocks, and / or die blocks including through-substrate vias. Different types of interconnection blocks may have different properties. For example, different types of interconnection blocks may include interconnects with different minimum widths (e.g., minimum linewidths), minimum pitches, and / or minimum junction pitches.

[0040] Interconnection block 105 includes at least one dielectric layer 150 and a plurality of interconnects 152. Interconnection block 105 may include a coreless substrate block (e.g., an embedded trace substrate block).

[0041] Interconnection block 107 includes a core layer 170, at least one dielectric layer 172, at least one dielectric layer 174, and a plurality of interconnects 173. Interconnection block 107 may include a core substrate block.

[0042] Interconnection block 109 includes at least one dielectric layer 190 and a plurality of interconnects 192. Interconnection block 109 may include metallized blocks (e.g., redistributed blocks).

[0043] The plurality of post interconnects 122 includes a first plurality of post interconnects 122a, a second plurality of post interconnects 122b, a third plurality of post interconnects 122c, and a fourth plurality of post interconnects 122d.

[0044] The first plurality of pillar interconnects 122a can be coupled to the metallized portion 104 and the interconnect block 105. The second plurality of pillar interconnects 122b can be coupled to the metallized portion 104 and the interconnect block 107. The third plurality of pillar interconnects 122c can be coupled to the metallized portion 104 and the interconnect block 109. The fourth plurality of pillar interconnects 122d can be coupled to the metallized portion 104 and the metallized portion 106.

[0045] Interconnect block 105 is coupled to metallized portion 106. One or more interconnects from multiple interconnects 152 may be coupled to and contact the metallized interconnects from multiple metallized interconnects 162 of metallized portion 106. Interconnect block 107 is coupled to metallized portion 106. One or more interconnects from multiple interconnects 173 may be coupled to and contact the metallized interconnects from multiple metallized interconnects 162 of metallized portion 106. Interconnect block 109 is coupled to metallized portion 106. One or more interconnects from multiple interconnects 192 may be coupled to and contact the metallized interconnects from multiple metallized interconnects 162 of metallized portion 106.

[0046] As will be further described below, power, ground, and / or different signals (e.g., input / output signals) can extend to and / or from the integrated device 103 via different interconnect blocks.

[0047] Figure 2 A cross-sectional view of a package 200 is illustrated, the package substrate having an encapsulation portion comprising a plurality of interconnect portion blocks. Package 200 is similar to package 100 and includes components similar to those of package 100. One difference lies in the different combinations of types of interconnect portion blocks included in package 200.

[0048] Package 200 includes package substrate 201 and integrated device 103. Integrated device 103 is coupled to package substrate 201 via a plurality of solder interconnects 130. A plurality of pillar interconnects (not shown) may be present between integrated device 103 and the plurality of solder interconnects 130. In some embodiments, the plurality of pillar interconnects (not shown) coupled to integrated device 103 and the plurality of solder interconnects 130 are considered as part of integrated device 103.

[0049] The packaging substrate 201 includes an encapsulation portion 102, a metallization portion 104 (e.g., a first metallization portion), and a metallization portion 106 (e.g., a second metallization portion). The metallization portion 104 may be coupled to a first surface (e.g., a top surface) of the encapsulation portion 102. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallized interconnects 142 (e.g., a first plurality of metallized interconnects). The metallization portion 104 may include a redistribution portion. The plurality of metallized interconnects 142 may include a plurality of redistributed interconnects (e.g., a first plurality of redistributed interconnects). An integrated device 103 is coupled to the plurality of metallized interconnects 142 via a plurality of solder interconnects 130. A solder mask layer 148 is coupled to the metallization portion 104. The solder mask layer 148 may be a portion of the metallization portion 104.

[0050] The metallized portion 106 may be coupled to a second surface (e.g., a bottom surface) of the encapsulation portion 102. The metallized portion 106 includes at least one dielectric layer 160 and a plurality of metallized interconnects 162 (e.g., a second plurality of metallized interconnects). The metallized portion 106 may include a redistribution portion. The plurality of metallized interconnects 162 may include a plurality of redistributed interconnects (e.g., a second plurality of redistributed interconnects).

[0051] Encapsulation portion 102 is located between metallization portion 104 and metallization portion 106. Metallization portion 104 can be coupled to a first surface of encapsulation portion 102. Metallization portion 106 can be coupled to a second surface of encapsulation portion 102. Encapsulation portion 102 includes interconnect portion blocks 105 (e.g., first interconnect portion block, second interconnect portion block, third interconnect portion block, fourth interconnect portion block), interconnect portion blocks 109 (e.g., first interconnect portion block, second interconnect portion block, third interconnect portion block, fourth interconnect portion block), interconnect portion blocks 205 (e.g., first interconnect portion block, second interconnect portion block, third interconnect portion block, fourth interconnect portion block), interconnect portion blocks 207 (e.g., first interconnect portion block, second interconnect portion block, third interconnect portion block, fourth interconnect portion block), a plurality of pillar interconnects 122, and encapsulation layer 120. Encapsulation layer 120 encapsulates interconnect portion blocks 105, interconnect portion blocks 109, interconnect portion blocks 205, interconnect portion blocks 207, and the plurality of pillar interconnects 122. In some embodiments, the encapsulation layer 120 may include a material different from at least one dielectric layer 140 of the metallization portion 104 and at least one dielectric layer 160 of the metallization portion 106. In some embodiments, the encapsulation layer 120 may include a material different from at least one dielectric layer 150 of the interconnect portion block 105, the dielectric layers (e.g., 170, 172, 174) of the interconnect portion block 207, and at least one dielectric layer 190 of the interconnect portion block 109.

[0052] Interconnection block 105 includes at least one dielectric layer 150 and a plurality of interconnects 152. Interconnection block 105 may include a coreless substrate block (e.g., an embedded trace substrate block).

[0053] Interconnection block 109 includes at least one dielectric layer 190 and a plurality of interconnects 192. Interconnection block 109 may include metallized blocks (e.g., redistributed blocks).

[0054] Interconnection block 205 includes a die substrate 250 (e.g., a silicon substrate) and a plurality of interconnects 252. The plurality of interconnects 252 may include through-substrate vias (e.g., through-silicon vias). Interconnection block 205 may include dies containing vias.

[0055] Interconnection block 207 includes a core layer 170, at least one dielectric layer 172, at least one dielectric layer 174, a plurality of interconnects 173, and passive devices 270. Interconnection block 207 may include an embedded passive substrate block. Passive device 270 may be a capacitor embedded in a core substrate. Passive device 270 may be a discrete passive device.

[0056] The plurality of column interconnects 122 may include a first plurality of column interconnects 122a, a second plurality of column interconnects 122b, a third plurality of column interconnects 122c, a fourth plurality of column interconnects 122d, and a fifth plurality of column interconnects 122e.

[0057] The first plurality of pillar interconnects 122a can be coupled to the metallized portion 104 and the interconnect block 105. The second plurality of pillar interconnects 122b can be coupled to the metallized portion 104 and the interconnect block 207. The third plurality of pillar interconnects 122c can be coupled to the metallized portion 104 and the interconnect block 109. The fourth plurality of pillar interconnects 122d can be coupled to the metallized portion 104 and the metallized portion 106. The fifth plurality of pillar interconnects 122e can be coupled to the metallized portion 104 and the interconnect block 205.

[0058] Interconnect block 105 is coupled to metallized portion 106. One or more interconnects from multiple interconnects 152 may be coupled to and contact the metallized interconnects from multiple metallized interconnects 162 of metallized portion 106. Interconnect block 109 is coupled to metallized portion 106. One or more interconnects from multiple interconnects 192 may be coupled to and contact the metallized interconnects from multiple metallized interconnects 162 of metallized portion 106. Interconnect block 205 is coupled to metallized portion 106. One or more interconnects from multiple interconnects 252 may be coupled to and contact the metallized interconnects from multiple metallized interconnects 162 of metallized portion 106. Interconnect block 207 is coupled to metallized portion 106. One or more interconnects from multiple interconnects 173 may be coupled to and contact the metallized interconnects from multiple metallized interconnects 162 of metallized portion 106.

[0059] Figure 3 A plan view of a package substrate 300 including various interconnect portion blocks is illustrated. Package substrate 300 may represent package substrate 101, package substrate 201, and / or any package substrate described in this disclosure. Package substrate 300 includes interconnect portion blocks 301, 302, 303, 304, 305, 306, 307, and 308. Each interconnect portion block may be located within an encapsulation portion (e.g., 102) of package substrate 300. Interconnect portion blocks may include coreless substrate blocks, cored substrate blocks, metallized portion blocks, redistributed portion blocks, and / or die blocks including through-substrate vias. Figure 2 As described herein, a core-based substrate may include passive devices located within the core-based substrate. The following at least Figures 5 to 9 The document further describes examples of different types of interconnection blocks.

[0060] Figure 3 An example is shown of how the integrated device 103 can be vertically overlapped with the package substrate 300. For example... Figure 3 As shown, the integrated device 103 can be vertically overlapped (e.g., partially vertically overlapped, fully vertically overlapped) with interconnect portion blocks 302, 303, 304, and 305. Different specific embodiments may allow the integrated device 103 to be vertically overlapped with the package substrate and / or the interconnect portion blocks of the package substrate in different ways.

[0061] Power, ground, and / or input / output signals to and / or from integrated device 103 may extend through one or more electrical paths, including interconnect block 301, interconnect block 302, interconnect block 303, interconnect block 304, interconnect block 305, interconnect block 306, interconnect block 307, and / or interconnect block 308. (The following is at least...) Figures 10 to 11 The example of the electrical path of the package is described in further detail.

[0062] In one example, interconnect portion block 301 may be configured to provide electrical paths for high-speed input / output signals to and / or from memory of one or more integrated devices, which may require fine linewidths and spacings as well as thin dielectric layers between metal layers. Interconnect portion block 301 may be implemented as a metallized portion block (e.g., a redistributed portion block).

[0063] In one example, interconnect block 302 and / or interconnect block 304 may be configured to provide power to one or more integrated devices, which may require thick interconnects for efficient power delivery to integrated device 103. Interconnect block 302 and / or interconnect block 304 may be implemented as laminated substrate blocks (e.g., coreless substrate blocks, cored substrate blocks).

[0064] In one example, interconnect block 303 may be configured to provide an electrical path for a power distribution network (PDN) (e.g., a PDN power rail). Interconnect block 303 may be implemented as a die block including through-substrate vias.

[0065] In one example, interconnect portion block 305 may be configured to provide an electrical path for input / output signals (e.g., I / O signals). Interconnect portion block 305 may be implemented as a partially integrated device shielding block and a peripheral region block of a package. As an example, interconnect portion block 305 may be implemented as a metallized portion block (e.g., a redistributed portion block).

[0066] In one example, interconnect portion block 306 and / or interconnect portion block 308 may be configured to provide electrical paths for high-speed input / output signals to and / or from one or more integrated devices, which may require fine linewidths and spacings, as well as thick dielectric layers between metal layers. Interconnect portion block 306 and / or interconnect portion block 308 may be implemented as metallized portion blocks (e.g., redistributed portion blocks).

[0067] In one example, interconnect block 307 may be configured to provide electrical paths for high-speed input / output signals to and / or from the memory of one or more integrated devices, which may require ultra-fine linewidths and spacing. Interconnect block 307 may be implemented as a die block or a metallized block (e.g., a redistributed block).

[0068] The use of various types of interconnect blocks allows for the customization and / or optimization of the package substrate, such that the electrical paths for different portions of one or more integrated devices include interconnects manufactured and / or formed using optimal substrate fabrication techniques that provide the best possible performance for the integrated device. The integrated device may include several cores configured for different functions. Different interconnect blocks can be used to provide electrical paths for different cores of the integrated device. Figure 3 An integrated device is illustrated. However, in some embodiments, two or more integrated devices may be coupled to the package substrate 300. In some embodiments, an interconnect portion block may be used to provide (i) a first electrical path for the first integrated device and (ii) a second electrical path for the second integrated device. Figure 3 This is merely an example of a possible configuration of the package substrate. Different specific implementations of the package substrate may include different numbers of interconnect portion blocks, different combinations of interconnect portion blocks, and / or interconnect portion blocks with different sizes and / or shapes.

[0069] Figure 4 A cross-sectional view of a package 400 is illustrated, the package substrate having an encapsulation portion including several interconnect portion blocks. Package 400 is similar to package 200 and includes similar components. One difference is that package 400 includes several integrated devices coupled to the package substrate.

[0070] Package 400 includes package substrate 401, integrated device 103, and integrated device 403. Integrated device 103 is coupled to package substrate 401 via a plurality of solder interconnects 130. A plurality of pillar interconnects (not shown) may be present between integrated device 103 and the plurality of solder interconnects 130. In some embodiments, the plurality of pillar interconnects (not shown) coupled to integrated device 103 and the plurality of solder interconnects 130 are considered as part of integrated device 103.

[0071] The integrated device 403 is coupled to the package substrate 401 via a plurality of solder interconnects 430. A plurality of pillar interconnects (not shown) may be present between the integrated device 403 and the plurality of solder interconnects 430. In some embodiments, the plurality of pillar interconnects (not shown) coupled to the integrated device 403 and the plurality of solder interconnects 430 are considered as part of the integrated device 403.

[0072] The packaging substrate 401 includes an encapsulation portion 102, a metallization portion 104 (e.g., a first metallization portion), and a metallization portion 106 (e.g., a second metallization portion). The metallization portion 104 may be coupled to a first surface (e.g., a top surface) of the encapsulation portion 102. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallized interconnects 142 (e.g., a first plurality of metallized interconnects). The metallization portion 104 may include a redistribution portion. The plurality of metallized interconnects 142 may include a plurality of redistributed interconnects (e.g., a first plurality of redistributed interconnects). The integrated device 403 is coupled to the plurality of metallized interconnects 142 via a plurality of solder interconnects 130. The integrated device 403 is coupled to the plurality of metallized interconnects 142 via a plurality of solder interconnects 430.

[0073] Metallization portion 106 may be coupled to a second surface (e.g., bottom surface) of encapsulation portion 102. Metallization portion 106 includes at least one dielectric layer 160 and a plurality of metallized interconnects 162 (e.g., a second plurality of metallized interconnects). Metallization portion 106 may include redistribution portions. The plurality of metallized interconnects 162 may include a plurality of redistributed interconnects (e.g., a second plurality of redistributed interconnects). In some embodiments, metallization portion 104 and / or metallization portion 106 may be optional. Thus, for example, in some embodiments, integrated devices (e.g., 103, 403) may be coupled to encapsulation portion 102 of package substrate 101 via a plurality of solder interconnects (e.g., 130, 430). Similarly, in some embodiments, encapsulation portion 102 of package substrate 101 may be coupled to board 108 via a plurality of solder interconnects.

[0074] Encapsulation portion 102 is located between metallization portion 104 and metallization portion 106. Metallization portion 104 can be coupled to a first surface of encapsulation portion 102. Metallization portion 106 can be coupled to a second surface of encapsulation portion 102. Encapsulation portion 102 includes interconnect portion blocks 105 (e.g., first interconnect portion block, second interconnect portion block, third interconnect portion block, fourth interconnect portion block), interconnect portion blocks 109 (e.g., first interconnect portion block, second interconnect portion block, third interconnect portion block, fourth interconnect portion block), interconnect portion blocks 205 (e.g., first interconnect portion block, second interconnect portion block, third interconnect portion block, fourth interconnect portion block), interconnect portion blocks 207 (e.g., first interconnect portion block, second interconnect portion block, third interconnect portion block, fourth interconnect portion block), a plurality of pillar interconnects 122, and encapsulation layer 120. Encapsulation layer 120 encapsulates interconnect portion blocks 105, interconnect portion blocks 109, interconnect portion blocks 205, interconnect portion blocks 207, and the plurality of pillar interconnects 122. The following text is at least Figure 11The example of electrical path through the interconnect portion block of package 400 is further described in detail.

[0075] In some embodiments, one or more integrated devices (e.g., 103, 403) described in this disclosure can be manufactured using the same technology node or two or more different technology nodes. For example, a first technology node can be used to manufacture the integrated device (e.g., 103), and a second technology node less advanced than the first technology node can be used to manufacture another chiplet (e.g., 403). In such examples, the integrated device (e.g., 103) may include components (e.g., interconnects, transistors) having a first minimum size, and another chiplet (e.g., 403) may include components (e.g., interconnects, transistors) having a second minimum size, wherein the second minimum size is larger than the first minimum size. In some embodiments, the integrated device 103 and integrated device 403 of the package can be manufactured using the same technology node or different technology nodes. In some embodiments, the chiplet (e.g., 103) and another chiplet (e.g., 403) of the package can be manufactured using the same technology node or different technology nodes.

[0076] Figures 5 to 9 Various types of interconnect blocks that can be implemented in a package substrate are illustrated. It should be noted that the interconnect blocks shown are merely examples. Different specific implementations may include interconnect blocks with different sizes, shapes, configurations, and numbers of metal layers.

[0077] Figure 5 An interconnect portion block 105 is illustrated, comprising at least one dielectric layer 150 and a plurality of interconnects 152. The interconnect portion block 105 may include a coreless substrate block (e.g., an embedded trace substrate block). The interconnect portion block 105 may be a laminated substrate block. The interconnect portion block 105 may have a different number of metal layers. The interconnect portion block 105 includes interconnects embedded in at least one dielectric layer 150 and surface interconnects located on the surface of at least one dielectric layer 150.

[0078] Figure 6 An interconnect portion block 107 is illustrated, comprising a core layer 170, at least one dielectric layer 172, at least one dielectric layer 174, and a plurality of interconnects 173. The core layer 170 may be a dielectric layer. The core layer 170 may comprise a dielectric material different from or the same as the at least one dielectric layer 172 and / or at least one dielectric layer 174. The interconnect portion block 107 may include a core substrate block. The interconnect portion block 107 may be a laminated substrate block. The interconnect portion block 107 may have a different number of metal layers.

[0079] Figure 7An interconnect portion block 207 is illustrated, comprising a core layer 170, at least one dielectric layer 172, at least one dielectric layer 174, a plurality of interconnects 173, and a passive device 270. Interconnect portion block 207 may be similar to interconnect portion block 107. The core layer 170 may be a dielectric layer. The core layer 170 may comprise a dielectric material different from or the same as the at least one dielectric layer 172 and / or at least one dielectric layer 174. The passive device 270 may be a capacitor. The passive device 270 may be located within the core layer 170 of interconnect portion block 207. The passive device 270 may be laterally surrounded by the core layer 170 of interconnect portion block 207. Terminals of the passive device 270 may be coupled to interconnects among the plurality of interconnects 173. Interconnect portion block 207 may include a core substrate block. Interconnect portion block 207 may be a laminated substrate block. Interconnect portion block 207 may be a core substrate block including passive devices. The interconnect block 207 can be an embedded passive substrate. The interconnect block 207 can have a different number of metal layers.

[0080] Figure 8 An interconnect portion block 109 is illustrated, comprising at least one dielectric layer 190 and a plurality of interconnects 192. The interconnect portion block 109 may include metallized portion blocks. The metallized portion blocks may include redistribution portions comprising redistributed interconnects (e.g., redistribution layer (RDL) interconnects). The redistributed interconnects may include portions having a U-shape or a V-shape. The terms "U-shape" and "V-shape" should be used interchangeably. The terms "U-shape" and "V-shape" may refer to the side profile shape of the interconnect and / or the redistributed interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top portion and a bottom portion. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the top portion of another U-shaped interconnect (or V-shaped interconnect). The interconnect portion block 109 may have a different number of metal layers. In some embodiments, the process for manufacturing the redistributed interconnect may form a U-shaped interconnect (or V-shaped interconnect).

[0081] Figure 9 An interconnect portion block 205 is illustrated, comprising a die substrate 250 (e.g., a silicon substrate) and a plurality of interconnects 252. The plurality of interconnects 252 may include through-substrate vias (e.g., through-silicon vias). The interconnect portion block 205 may include a die containing a via. Although not shown, the interconnect portion block 205 may include interconnects located on a first surface and / or a second surface of the die substrate 250. These interconnects may be pads that can be coupled to the through-substrate vias of the interconnect portion block 205.

[0082] The interconnect blocks described above can be manufactured in different ways and can have different minimum interconnect sizes. These interconnect blocks are ideally suited to provide interconnects as electrical paths for different types of current, signals, power, and / or ground. Different embodiments may use different combinations of the interconnect blocks described above in the encapsulation portion. In some embodiments, two or more interconnect blocks of the same type may be implemented in the encapsulation portion of the package substrate. In such instances, interconnect blocks of the same type may have different designs, such as different numbers of metal layers, while still being considered as interconnect blocks of the same type.

[0083] Furthermore, the aforementioned interconnect blocks may have different associated costs and / or associated manufacturing yields. The manufacturing yield of the interconnect blocks affects the overall cost of the interconnect blocks. In some specific implementations, these costs and / or yields may be considered when determining which interconnect blocks to implement in the package substrate of the package.

[0084] Depending on the design of the interconnect blocks, different types of interconnect blocks can have similar or different thicknesses. For example, in some implementations, an interconnect block implemented as a metallized block may have more metal layers than another interconnect block implemented as a laminated substrate block, but still have an overall thickness less than that of the laminated substrate block.

[0085] Table 1 below illustrates exemplary values ​​for interconnects and dielectric layers for different types of interconnect blocks.

[0086] As shown above, interconnects from the metallized / redistributed portions have the minimum minimum linewidth and pitch (2 / 2 means a minimum linewidth of 2 micrometers and a minimum pitch of 2 micrometers). Therefore, interconnect blocks implementing the metallized / redistributed layer properties are well-suited for high-density interconnects configured to provide electrical paths for input / output signals (I / O signals). Laminated coreless substrate technology and / or laminated cored substrate technology have even higher minimum linewidths, minimum pitches, and minimum interconnect thicknesses (e.g., relative to the metallized portions), which may be more suitable for interconnects configured to provide electrical paths for power and / or ground. Cored substrates including passive devices may include the same characteristics and / or properties as laminated cored substrates. Therefore, interconnect blocks implemented as embedded passive substrates may have minimum linewidths, minimum pitches, and / or minimum interconnect thicknesses similar to those of laminated cored substrates.

[0087] The range of minimum dimensions for a particular type of interconnect component (e.g., 2 / 2-5 / 5) can mean that an interconnect component of a certain type can be manufactured in several ways, and the minimum size can depend on the type of manufacturing process used for that particular type of interconnect component. Using the example above, the range of 2 / 2-5 / 5 means that in some instances, a minimum linewidth of 2 micrometers and a minimum pitch of 2 micrometers are possible, and in some instances, a minimum linewidth of 5 micrometers and a minimum pitch of 5 micrometers are possible.

[0088] Interconnect portion blocks of a die block including through-substrate vias may have a minimum linewidth in the range of about 5 micrometers to 150 micrometers and / or a minimum pitch in the range of about 5 micrometers to 150 micrometers. Interconnect portion blocks of a die block having through-substrate vias may have a minimum via height in the range of about 20 micrometers to 200 micrometers.

[0089] Using different types of interconnect blocks offers several advantages. First, this type of package substrate provides better yield compared to other package substrates, which helps reduce the overall cost of the package. Second, this type of package substrate allows for the use and / or selection of different substrate technologies for wiring in different areas, which also contributes to better yield. Thus, for example, more expensive substrate technologies can be used in areas requiring more expensive substrate technologies, and more cost-effective substrate technologies can be used in areas where more expensive substrate technologies are not needed. Third, this type of package substrate can be easily redesigned by replacing one or more interconnect blocks with different types of interconnect blocks, thus avoiding the need for a complete redesign of the package substrate from scratch. By using different types of interconnect blocks, interconnects on the same metal layer of the package substrate can have different thicknesses. Using different interconnect technologies allows the package substrate to be highly customizable and still cost-effective (or not expensive).

[0090] Figure 10 and Figure 11 An exemplary electrical path is illustrated between (i) one or more integrated devices in the package and (ii) the board. Figure 10 An exemplary electrical path is illustrated for a package 200 including an integrated device 103. The integrated device 103 includes cores 1032, 1034, 1036, and 1038. Each core may be configured to perform one or more functions. The core may include memory, processing units (e.g., a central processing unit, a graphics processing unit), and / or a modem. Figure 10 Examples of electrical paths 1001, 1002, 1003, 1004, 1005, and 1006 are given.

[0091] Electrical path 1001 may include an electrical path between the core 1032 of integrated device 103 and board 108. However, it should be noted that electrical path 1001 may extend to other components outside of board 108. Electrical path 1001 between core 1032 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 130, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 152 of interconnect portion block 105, (v) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (vi) solder interconnects from a plurality of solder interconnects 110, and (vii) board interconnects from a plurality of board interconnects 182.

[0092] Electrical path 1002 may include an electrical path between the core 1032 of integrated device 103 and board 108. However, it should be noted that electrical path 1002 may extend to other components outside of board 108. Electrical path 1002 between core 1032 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 130, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (v) solder interconnects from a plurality of solder interconnects 110, and (vi) board interconnects from a plurality of board interconnects 182.

[0093] Electrical path 1003 may include an electrical path between the core 1034 of integrated device 103 and board 108. However, it should be noted that electrical path 1003 may extend to other components outside of board 108. Electrical path 1003 between core 1034 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 130, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 173 of interconnect portion block 207, (v) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (vi) solder interconnects from a plurality of solder interconnects 110, and (vii) board interconnects from a plurality of board interconnects 182.

[0094] Electrical path 1004 may include an electrical path between integrated device 103 and board 108. However, it should be noted that electrical path 1004 may extend to other components beyond board 108. Electrical path 1004 between integrated device 103 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 130, (ii) metallized interconnects from a plurality of metallized interconnects 142 from metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 173 from interconnect portion block 207, (v) passive device 270, (vi) further interconnects from a plurality of interconnects 173 from interconnect portion block 207, (vii) metallized interconnects from a plurality of metallized interconnects 162 from metallized portion 106, (viii) solder interconnects from a plurality of solder interconnects 110, and (ix) board interconnects from a plurality of board interconnects 182.

[0095] Electrical path 1005 may include an electrical path between the core 1036 of integrated device 103 and board 108. However, it should be noted that electrical path 1005 may extend to other components beyond board 108. Electrical path 1005 between core 1036 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 130, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 252 of interconnect portion block 205, (v) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (vi) solder interconnects from a plurality of solder interconnects 110, and (vii) board interconnects from a plurality of board interconnects 182.

[0096] Electrical path 1006 may include an electrical path between the core 1038 of integrated device 103 and board 108. However, it should be noted that electrical path 1006 may extend to other components beyond board 108. Electrical path 1006 between core 1038 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 130, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 192 of interconnect portion block 109, (v) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (vi) solder interconnects from a plurality of solder interconnects 110, and (vii) board interconnects from a plurality of board interconnects 182.

[0097] Figure 11An exemplary electrical path is illustrated for a package 400 including integrated devices 103 and 403. Integrated device 103 includes cores 1132 and 1134. Integrated device 403 includes cores 1142 and 1144. Each core may be configured to perform one or more functions. Cores may include memory, processing units (e.g., central processing unit, graphics processing unit), and / or modems. Figure 11 Examples of electrical paths 1101, 1102, 1103, 1104, 1105, 1106, and 1107 are given.

[0098] Electrical path 1101 may include an electrical path between the core 1132 of integrated device 103 and board 108. However, it should be noted that electrical path 1101 may extend to other components outside of board 108. Electrical path 1101 between core 1132 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 130, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 152 of interconnect portion block 105, (v) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (vi) solder interconnects from a plurality of solder interconnects 110, and (vii) board interconnects from a plurality of board interconnects 182.

[0099] Electrical path 1102 may include an electrical path between integrated device 103 and board 108. However, it should be noted that electrical path 1102 may extend to other components outside of board 108. Electrical path 1102 between integrated device 103 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 130, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (v) solder interconnects from a plurality of solder interconnects 110, and (vi) board interconnects from a plurality of board interconnects 182.

[0100] Electrical path 1103 may include an electrical path between the core 1034 of integrated device 103 and board 108. However, it should be noted that electrical path 1103 may extend to other components outside board 108. Electrical path 1103 between core 1134 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 130, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 173 of interconnect portion block 207, (v) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (vi) solder interconnects from a plurality of solder interconnects 110, and (vii) board interconnects from a plurality of board interconnects 182.

[0101] Electrical path 1104 may include an electrical path between integrated device 403 and board 108. However, it should be noted that electrical path 1104 may extend to other components beyond board 108. Electrical path 1104 between integrated device 403 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 430, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 173 of interconnect portion block 207, (v) passive device 270, (vi) further interconnects from a plurality of interconnects 173 of interconnect portion block 207, (vii) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (viii) solder interconnects from a plurality of solder interconnects 110, and (ix) board interconnects from a plurality of board interconnects 182.

[0102] Electrical path 1105 may include an electrical path between the core 1142 of integrated device 403 and board 108. However, it should be noted that electrical path 1105 may extend to other components outside of board 108. Electrical path 1105 between core 1142 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 430, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 252 of interconnect portion block 205, (v) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (vi) solder interconnects from a plurality of solder interconnects 110, and (vii) board interconnects from a plurality of board interconnects 182.

[0103] Electrical path 1106 may include an electrical path between the core 1144 of integrated device 403 and board 108. However, it should be noted that electrical path 1106 may extend to other components outside of board 108. Electrical path 1106 between core 1144 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 430, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 192 of interconnect portion block 109, (v) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (vi) solder interconnects from a plurality of solder interconnects 110, and (vii) board interconnects from a plurality of board interconnects 182.

[0104] Electrical path 1107 may include an electrical path between integrated device 103 and integrated device 403. Electrical path 1107 between integrated device 103 and integrated device 403 may include (i) solder interconnects from a plurality of solder interconnects 130, (ii) metallized interconnects from a plurality of metallized interconnects 142 from metallized portion 104, and (iii) solder interconnects from a plurality of solder interconnects 430.

[0105] Integrated devices (e.g., 103, 403) may include dies (e.g., bare semiconductor dies). Integrated devices may include power management integrated circuits (PMICs). Integrated devices may include application processors. Integrated devices may include modems. Integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memories, power management processors, and / or combinations thereof. Integrated devices (e.g., 103, 403) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). Integrated devices may include input / output (I / O) hubs. Integrated devices may include transistors. Integrated devices may be examples of electronic components and / or electronic devices.

[0106] In some embodiments, the integrated device may be a chiplet. Chipslets can be manufactured using processes that offer better yields compared to other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or pitches). In some embodiments, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). As mentioned above, using several chiplets performing several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. In some embodiments, one or more chiplets and / or integrated devices (e.g., 103, 403) of the chiplets described in this disclosure can be manufactured using the same technology node or two or more different technology nodes. For example, an integrated device (e.g., 103) can be manufactured using a first technology node, and chiplets can be manufactured using a second technology node that is less advanced than the first technology node. In such examples, an integrated device (e.g., 103) may include components (e.g., interconnects, transistors) having a first minimum size, and a chiplet may include components (e.g., interconnects, transistors) having a second minimum size, wherein the second minimum size is larger than the first minimum size. In some embodiments, the integrated device 103 and integrated device 403 of the package may be manufactured using the same technology node or different technology nodes. In some embodiments, the chiplet and another chiplet of the package may be manufactured using the same technology node or different technology nodes.

[0107] A technology node can refer to a specific manufacturing process and / or technology used to manufacture integrated devices and / or chiplets. A technology node can specify the minimum possible size that can be manufactured (e.g., minimum size) (e.g., transistor size, trace width, gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Technology nodes for components with finer manufacturing details are more expensive and may have higher yield losses compared to technology nodes for components with less fine manufacturing details (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and may have higher yield losses compared to less advanced technology nodes. When all functions of a package are implemented in a single integrated device, the same technology node is used to manufacture the entire integrated device, even if some functions of the integrated device do not require manufacturing using that specific technology node. Therefore, the integrated device is locked to a single technology node. To optimize the cost of the package, some functions can be implemented in different integrated devices and / or chiplets, where different technology nodes can be used to manufacture different integrated devices and / or chiplets to reduce the overall cost. For example, functionality requiring state-of-the-art technology nodes can be implemented in an integrated device, while functionality achievable with less advanced technology nodes can be implemented in another integrated device and / or one or more chiplets. An example would be an integrated device manufactured using a first technology node (e.g., a more advanced technology node) and configured to provide computing applications, and at least one chiplet manufactured using a second technology node and configured to provide additional functionality, wherein the second technology node is less expensive than the first technology node, and wherein the second technology node manufactures a component with a minimum size larger than the minimum size of a component manufactured using the first technology node. Examples of computing applications could include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packing as many transistors as possible into the integrated device. This is why the integrated device configured for computing applications can be manufactured using the most advanced available technology nodes, while other chiplets can be manufactured using less advanced technology nodes, as these chiplets may not require as many transistors to be manufactured in the chiplet. Therefore, using a combination of different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets can reduce the overall cost of the package compared to using a single integrated device to perform all the functionality of the package.

[0108] Another advantage of dividing functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign each individual integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by changing the design of the first integrated device while keeping the design of the first chiplet unchanged. Therefore, the first chiplet can be reused along with improved and / or differently configured first integrated devices. This saves costs when manufacturing packages with improved integrated devices because the first chiplet does not need to be redesigned.

[0109] Table 2 below illustrates how different chiplets can be paired and / or configured with blocks of the package substrate. It should be noted that Table 2 is merely an example of possible chiplets and pairings with blocks of the package substrate, and other specific implementations may have different pairings, use different chiplets, and / or use different combinations of chiplets.

[0110] Table 2 illustrates examples of how different chiplets and / or different chiplet pairs can be paired with different blocks of a package substrate. For example, high-power chiplets can be paired with blocks having thicker and / or larger interconnects (e.g., coreless substrate blocks, cored substrate blocks), and medium-power or low-power chiplets can be paired with blocks having thinner and / or smaller interconnects (e.g., coreless substrate blocks, cored substrate blocks, redistribution portion blocks). In another example, high I / O speed chiplets can be paired with blocks having smaller line and pitch interconnects (e.g., redistribution portion blocks, embedded trace substrate blocks), and low-speed chiplets can be paired with blocks having larger line and pitch interconnects (e.g., coreless substrate blocks, cored substrate blocks, redistribution portion blocks). In another example, advanced technology node chiplets can be paired with blocks having smaller line and pitch interconnects (e.g., redistribution portion blocks, embedded trace substrate blocks), and loose technology node chiplets can be paired with blocks having larger line and pitch interconnects (e.g., coreless substrate blocks, cored substrate blocks, redistribution portion blocks). The term pairing a chiplet with a block can mean that the block is configured to provide at least one electrical path for the chiplet. A chiplet can be paired with more than one block and / or more than one type of block. Therefore, when a chiplet is paired with a block of a package substrate, this does not necessarily mean that the chiplet cannot be paired with another block of the package substrate. Similarly, two or more chiplets can be paired with the same block and / or the same type of block. Thus, a block can be configured to provide at least two separate electrical paths for two or more chiplets. Table 2 illustrates how different technology nodes for package substrates and / or blocks can be used to implement different technology nodes for integrated devices and / or chiplets to reduce costs and improve and / or optimize the performance of packages including integrated devices and / or chiplets.

[0111] Metallized portions (e.g., 104, 106) may include redistributed portions comprising redistributed interconnects (e.g., redistributed layer (RDL) interconnects). The redistributed interconnects may include portions having a U-shape or a V-shape. The terms "U-shape" and "V-shape" should be used interchangeably. The terms "U-shape" and "V-shape" may refer to the side profile shape of the interconnect and / or the redistributed interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top portion and a bottom portion. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the top portion of another U-shaped interconnect (or V-shaped interconnect).

[0112] The encapsulation layer (e.g., 120) may include a molded part, resin, and / or epoxy resin. The encapsulation layer may be a component for encapsulation. The encapsulation layer can be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0113] As mentioned above, the package may include several metallized portions. Any metallized portion may be a first metallized portion, and / or any metallized portion may be a second metallized portion. For example, in some embodiments, metallized portion 104 may be considered a first metallized portion, and metallized portion 106 may be considered a second metallized portion. In some embodiments, metallized portion 106 may be considered a first metallized portion, and metallized portion 104 may be considered a second metallized portion.

[0114] Figures 12A to 12F Exemplary steps for providing or manufacturing a package including a packaging substrate having an encapsulation portion with a plurality of interconnected portion blocks are illustrated. In some specific embodiments, Figures 12A to 12F The process can be used to provide or manufacture Figure 1 The package 100 or any package described in this disclosure.

[0115] It should be noted that Figures 12A to 12F The processes can be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure. Figures 12A to 12F The process can be used to manufacture one package or several packages (as part of a wafer) at a time.

[0116] like Figure 12AAs shown, Phase 1 illustrates the state after several interconnect component blocks have been provided. Examples of interconnect component blocks include interconnect component block 105, interconnect component block 107, and interconnect component block 109. Different specific implementations may use different combinations and / or numbers of interconnect component blocks. Providing interconnect component blocks may include manufacturing the interconnect component blocks. The following at least... Figures 14A to 14C , Figures 16A to 16B and Figures 18A to 18B Examples of how different types of interconnection parts can be manufactured are illustrated and described.

[0117] Phase 2 illustrates the state after interconnect blocks 105, 107, and 109 have been placed on the carrier 1200. In some embodiments, adhesives may be used to place the interconnect blocks on the carrier 1200. The carrier may include a substrate, glass, quartz, and / or carrier tape.

[0118] Phase 3 illustrates the state after forming a plurality of pillar interconnects 122 and coupling them to interconnect portion blocks (e.g., 105, 107, 109) and carrier 1200. A plating process can be used to form the plurality of pillar interconnects 122. Some of the pillar interconnects 122 can be formed and coupled to the interconnects of the interconnect portion blocks.

[0119] Phase 4 illustrates the state after the encapsulation layer 120 is formed over the carrier 1200 and the interconnect portion blocks. The encapsulation layer 120 may encapsulate interconnect portion blocks 105, 107, 109, and a plurality of pillar interconnects 122. The encapsulation layer 120 may include molding materials, resin, and / or epoxy resin. The encapsulation layer 120 may be a component for encapsulation. The encapsulation layer 120 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0120] like Figure 12B As shown, stage 5 illustrates the state after removing portions of the encapsulation layer 120 and the plurality of pillar interconnects 122. A grinding process can be used to remove the top portions of the encapsulation layer 120 and the plurality of pillar interconnects 122 to reduce the thickness of the encapsulation layer 120 and / or reduce the height of the plurality of pillar interconnects 122. Stage 5 can illustrate an encapsulation portion 102 including the encapsulation layer 120, the plurality of pillar interconnects 122, and several interconnect portion blocks.

[0121] Phase 6 illustrates the state after forming the metallized portion 104 and coupling it to the encapsulation layer 120 and the plurality of pillar interconnects 122. The metallized portion 104 is coupled to the encapsulation portion 102. The metallized portion 104 includes at least one dielectric layer 140 and a plurality of metallized interconnects 142. The plurality of metallized interconnects 142 may include a plurality of redistributed interconnects. The plurality of metallized interconnects 142 may be coupled to a plurality of pillar interconnects 122. In some specific embodiments, at least Figures 18A to 18B The process shown is used to form the metallized portion 104. The metallized portion 104 may have a different number of metal layers. For example, in some embodiments, the metallized portion 104 may have one or two metal layers. In some embodiments, the metallized portion 104 may have the same or similar properties as described in Table 1 for the redistribution layer.

[0122] Phase 7 illustrates the state after the carrier 1200 is decoupled from the encapsulation portion 102. The carrier 1200 can be removed and / or separated from the encapsulation portion 102.

[0123] like Figure 12C As shown, stage 8 illustrates the state after the encapsulation portion 102 and the metallization portion 104 have been placed on the carrier 1210. In some embodiments, an adhesive may be used to place the encapsulation portion 102 and the metallization portion 104 on the carrier 1210. The metallization portion 104 may be coupled to the carrier 1210. The carrier 1210 may be similar to the carrier 1200.

[0124] Phase 9 illustrates the state after forming the metallized portion 106 and coupling it to the encapsulation layer 120, the plurality of pillar interconnects 122, and interconnect portion blocks (e.g., 105, 107, 109). The metallized portion 106 is coupled to the encapsulation portion 102 such that the encapsulation portion 102 is located between the metallized portion 104 and the metallized portion 106. The metallized portion 106 includes at least one dielectric layer 160 and a plurality of metallized interconnects 162. The plurality of metallized interconnects 162 may include a plurality of redistributed interconnects. The plurality of metallized interconnects 162 may be coupled to the plurality of pillar interconnects 122 and interconnects from the interconnect portion blocks (e.g., 105, 107, 109). In some specific embodiments, at least Figures 18A to 18B The process shown is used to form the metallized portion 106. The metallized portion 106 may have a different number of metal layers. For example, in some embodiments, the metallized portion 106 may have one or two metal layers. In some embodiments, the metallized portion 106 may have the same or similar properties as described in Table 1 for the redistribution layer.

[0125] Phase 10 illustrates the state after the carrier 1210 is decoupled from the metallized portion 104. The carrier 1210 can be removed and / or separated from the metallized portion 104.

[0126] like Figure 12D As shown, stage 11 illustrates the state after the encapsulation portion 102, the metallization portion 104, and the metallization portion 106 have been placed on the carrier 1220. In some embodiments, an adhesive may be used to place the encapsulation portion 102, the metallization portion 104, and the metallization portion 106 onto the carrier 1220. The metallization portion 106 may be coupled to the carrier 1220. The carrier 1220 may be similar to the carrier 1200 and / or the carrier 1210.

[0127] Stage 12 illustrates the state after a solder mask layer 148 has been formed on the metallized portion 104. The solder mask layer 148 may include a plurality of openings on one or more metallized interconnects from a plurality of metallized interconnects 142. The solder mask layer 148 may be formed using a deposition process and / or a lamination process. Stage 12 may illustrate a package substrate 201 including an encapsulation portion 102, a metallized portion 104, and a metallized portion 106.

[0128] like Figure 12E As shown, stage 13 illustrates the state after the integrated device 103 is coupled to the metallized portion 104 via a plurality of solder interconnects 130. A solder reflow process can be used to couple the plurality of solder interconnects 130 to the metallized interconnects of the metallized portion 104.

[0129] Phase 14 illustrates the state after the carrier 1220 is decoupled from the metallized portion 106. The carrier 1220 can be removed and / or separated from the metallized portion 106.

[0130] like Figure 12F As shown, stage 15 illustrates the state after multiple solder interconnects 110 are coupled to the package substrate 201. A solder reflow process can be used to couple the multiple solder interconnects 110 to multiple metallized interconnects 162 of the metallized portion 106. Stage 15 can also illustrate a package 200 including an integrated device 103 and a package substrate 201, the package substrate including an encapsulation portion 102 having a plurality of interconnect blocks.

[0131] In some specific implementations, manufacturing the package involves several processes. Figure 13 An exemplary flowchart illustrating a method 1300 for providing or manufacturing a package is shown. In some specific implementations, Figure 13 Method 1300 can be used to provide or manufacture any package disclosed herein. For example, Figure 13Method 1300 can be used to manufacture package 100.

[0132] It should be noted that Figure 13 Method 1300 may combine one or more processes to simplify and / or clarify the methods for providing or manufacturing packages. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure. Figure 13 Method 1300 can be used to manufacture one package or several packages (as part of a wafer) at a time.

[0133] The method (at 1305) provides a plurality of interconnection portion blocks on a carrier. For example, a plurality of interconnection portion blocks may be provided and / or manufactured and placed on the carrier. The carrier may include a substrate, glass, quartz and / or carrier strip. Figure 12A Phase 1 illustrates and describes several example interconnect component blocks. Examples of interconnect component blocks include interconnect component block 105, interconnect component block 107, and interconnect component block 109. Different specific implementations may use different types of interconnect component blocks, different combinations of interconnect component blocks, and / or different numbers of interconnect component blocks. Providing interconnect component blocks may include manufacturing interconnect component blocks. The following at least Figures 14A to 14C , Figures 16A to 16B and Figures 18A to 18B Examples of how different types of interconnection parts can be manufactured are illustrated and described.

[0134] Figure 12A Phase 2 illustrates and describes an example of interconnecting portion blocks 105, 107, and 109 being placed on carrier 1200. In some specific embodiments, adhesives may be used to place the interconnecting portion blocks on carrier 1200.

[0135] This method (at 1310) forms multiple pillar interconnects and couples them to the interconnect block. Figure 12A Phase 3 illustrates and describes an example in which multiple pillar interconnects 122 are formed and coupled to interconnect portion blocks (e.g., 105, 107, 109) and carrier 1200. A plating process can be used to form the multiple pillar interconnects 122. Some of the pillar interconnects 122 can be formed and coupled to the interconnects of the interconnect portion blocks.

[0136] This method (at 1315) forms an encapsulation layer for encapsulating interconnect blocks and multiple pillar interconnects. Figure 12APhase 4 illustrates and describes an example of forming an encapsulation layer 120 over a carrier 1200 and interconnect portion blocks. The encapsulation layer 120 may encapsulate interconnect portion blocks 105, 107, 109, and a plurality of pillar interconnects 122. The encapsulation layer 120 may include molding materials, resins, and / or epoxy resins. The encapsulation layer 120 may be a component for encapsulation. The encapsulation layer 120 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0137] Forming an encapsulation layer may also include removing a portion of the encapsulation layer. Figure 12B Phase 5 illustrates and describes an example of the removal of portions of the encapsulation layer 120 and portions of the plurality of post interconnects 122. A grinding process can be used to remove the top portions of the encapsulation layer 120 and the top portions of the plurality of post interconnects 122 to reduce the thickness of the encapsulation layer 120 and / or reduce the height of the plurality of post interconnects 122. Figure 12B Stage 5 can be exemplified as an encapsulation portion 102 comprising an encapsulation layer 120, a plurality of pillar interconnects 122, and a plurality of interconnect blocks. The encapsulation layer forming the encapsulation interconnect blocks and the plurality of pillar interconnects can form the encapsulation portion 102.

[0138] This method (at 1320) forms a first metallized portion coupled to the encapsulation layer and multiple pillar interconnects. Figure 12B Phase 6 illustrates and describes an example where a metallized portion 104 is formed and coupled to an encapsulation layer 120 and a plurality of pillar interconnects 122. The metallized portion 104 is coupled to the encapsulation portion 102. The metallized portion 104 includes at least one dielectric layer 140 and a plurality of metallized interconnects 142. The plurality of metallized interconnects 142 may include a plurality of redistributed interconnects. The plurality of metallized interconnects 142 may be coupled to a plurality of pillar interconnects 122. In some specific embodiments, at least... Figures 18A to 18B The process shown is used to form the metallized portion 104. The metallized portion 104 may have a different number of metal layers. In some specific embodiments, the metallized portion 104 may have the same or similar properties as described in Table 1 for the redistribution layer.

[0139] After the metallized portion 104 is formed, the carrier can be removed. Figure 12B Stage 7 illustrates the state after the carrier 1200 has been decoupled from the encapsulation portion 102. The carrier 1200 can be removed and / or separated from the encapsulation portion 102.

[0140] This method (at 1325) forms a second metallized portion coupled to the encapsulation layer, multiple pillar interconnects, and interconnect portion blocks. The second metallized portion can be formed after the encapsulation layer, multiple pillar interconnects, and interconnect portion blocks are placed on another carrier. Figure 12CPhase 8 illustrates and describes an example of encapsulation portion 102 and metallization portion 104 being placed on carrier 1210. In some specific embodiments, adhesives may be used to place encapsulation portion 102 and metallization portion 104 on carrier 1210. Metallization portion 104 may be coupled to carrier 1210.

[0141] Figure 12C Phase 9 illustrates and describes an example where a metallized portion 106 is formed and coupled to an encapsulation layer 120, a plurality of pillar interconnects 122, and interconnect portion blocks (e.g., 105, 107, 109). The metallized portion 106 is coupled to the encapsulation portion 102 such that the encapsulation portion 102 is located between the metallized portion 104 and the metallized portion 106. The metallized portion 106 includes at least one dielectric layer 160 and a plurality of metallized interconnects 162. The plurality of metallized interconnects 162 may include a plurality of redistributed interconnects. The plurality of metallized interconnects 162 may be coupled to a plurality of pillar interconnects 122 and interconnects from interconnect portion blocks (e.g., 105, 107, 109). In some specific embodiments, at least... Figures 18A to 18B The process shown is used to form the metallized portion 106. The metallized portion 106 may have a different number of metal layers. In some specific embodiments, the metallized portion 106 may have the same or similar properties as described in Table 1 for the redistribution layer.

[0142] After the metallized portion 106 is formed, the carrier can be removed. Figure 12C Stage 10 illustrates the state after the carrier 1210 is decoupled from the metallization portion 104. The carrier 1210 can be removed and / or separated from the metallization portion 104. Forming and / or providing the encapsulation portion 102, the metallization portion 104, and the metallization portion 106 can form a package substrate (e.g., 101, 201, 401).

[0143] After removing the carrier, the encapsulation portion 102, the metallized portion 104, and the metallized portion 106 can be placed on another carrier. Figure 12D Phase 11 illustrates and describes an example of encapsulation portion 102, metallization portion 104, and metallization portion 106 being placed on carrier 1220. In some specific embodiments, adhesives may be used to place encapsulation portion 102, metallization portion 104, and metallization portion 106 on carrier 1220. Metallization portion 106 may be coupled to carrier 1220.

[0144] In some specific implementations, a solder resist layer can be formed on the metallized portion 104. Figure 12DStage 12 illustrates and describes an example of forming a solder mask layer 148 on the metallized portion 104. The solder mask layer 148 may include a plurality of openings on one or more metallized interconnects from a plurality of metallized interconnects 142. Figure 12D Stage 12 can be exemplified by a package substrate 201 including an encapsulation portion 102, a metallization portion 104, and a metallization portion 106.

[0145] This method (at 1330) couples one or more integrated devices to a package substrate. Figure 12E Phase 13 illustrates and describes an example of an integrated device 103 coupled to a metallized portion 104 via a plurality of solder interconnects 130. A solder reflow process can be used to couple the plurality of solder interconnects 130 to the metallized interconnects of the metallized portion 104.

[0146] Once the integrated device is coupled to the package substrate, the carrier can be removed. Figure 12E Phase 14 illustrates and describes the decoupling of the carrier 1220 from the metallized portion 106. The carrier 1220 can be removed and / or separated from the metallized portion 106.

[0147] This method (at 1335) couples multiple solder interconnects to the package substrate. Figure 12F Phase 15 illustrates and describes an example of multiple solder interconnects 110 coupled to a package substrate 201. A solder reflow process can be used to couple multiple solder interconnects 110 to multiple metallized interconnects 162 of a metallized portion 106. Figure 12F Phase 15 can be exemplified by a package 200 including an integrated device 103 and a package substrate 201, the package substrate including an encapsulation portion 102 having a plurality of interconnected portion blocks.

[0148] In some specific implementations, manufacturing a coreless substrate involves several processes. Figures 14A to 14C Exemplary processes for providing or manufacturing a coreless substrate are illustrated. The coreless substrate can be implemented as a coreless substrate block. In some specific embodiments, Figures 14A to 14C The process can be used to provide or manufacture interconnecting portion block 105. However, Figures 14A to 14C The process can be used to manufacture other interconnection portion blocks described in this disclosure.

[0149] It should be noted that Figures 14A to 14C The processes can be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture a coreless substrate. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0150] like Figure 14A As shown, stage 1 illustrates the state after the carrier 1400 is provided. The carrier 1400 may include a substrate. The carrier 1400 may include a seed layer 1402 located on a first surface of the carrier 1400 and a seed layer 1404 located on a second surface of the carrier 1400. The carrier 1400 may be a dielectric.

[0151] Phase 2 illustrates the state after interconnects are formed in and on the surface of the carrier 1400. A plurality of interconnects 1412 may be formed on (e.g., above) a first surface of the carrier 1400. A seed layer 1402 may be part of the plurality of interconnects 1412. A plurality of interconnects 1414 may be formed on (e.g., below) a second surface of the carrier 1400. A seed layer 1404 may be part of the plurality of interconnects 1414. Masking processes, plating processes, and etching processes may be used to form the plurality of interconnects 1412 and / or the plurality of interconnects 1414.

[0152] Stage 3 illustrates the state after a dielectric layer 1420 is formed on (e.g., above) the first surface of the carrier 1400 and the plurality of interconnects 1412. Stage 3 also illustrates the state after a dielectric layer 1430 is formed on (e.g., below) the second surface of the carrier 1400 and the plurality of interconnects 1414. Dielectric layers 1420 and 1430 can be formed using deposition and / or lamination processes. Dielectric layers 1420 and 1430 can be made of a different material than the carrier 1400.

[0153] Stage 4 illustrates the state after forming a plurality of cavities 1421 in dielectric layer 1420 and a plurality of cavities 1431 in dielectric layer 1430. The plurality of cavities 1421 and the plurality of cavities 1431 can be formed using an etching process (e.g., photolithography). The plurality of cavities 1421 and the plurality of cavities 1431 can be formed using a masking process, an exposure process, and / or a development process.

[0154] like Figure 14B As shown, stage 5 illustrates the state after interconnects are formed in and on the surfaces of dielectric layers 1420 and 1430. Multiple interconnects 1422 can be formed on (e.g., above) the first surface of dielectric layer 1420 and the multiple cavities 1421. Multiple interconnects 1432 can be formed on (e.g., below) the second surface of dielectric layer 1430 and the multiple cavities 1431. Masking processes, plating processes, and etching processes can be used to form the multiple interconnects 1422 and / or the multiple interconnects 1432.

[0155] Stage 6 illustrates the state after dielectric layer 1440 is formed over (e.g., above) the first surface of dielectric layer 1420 and the plurality of interconnects 1422. Stage 6 also illustrates the state after dielectric layer 1450 is formed over (e.g., below) the second surface of dielectric layer 1430 and the plurality of interconnects 1432. Dielectric layers 1440 and 1450 can be formed using deposition and / or lamination processes. Dielectric layers 1440 and / or 1450 can be the same dielectric layers as dielectric layers 1420 and / or 1430.

[0156] Phase 7 illustrates the state following the formation of a plurality of cavities 1441 in dielectric layer 1440 (which is shown as part of dielectric layer 1425) and the formation of a plurality of cavities 1451 in dielectric layer 1450 (which is shown as part of dielectric layer 1427). The plurality of cavities 1441 and 1451 can be formed using an etching process (e.g., a photolithography process). The plurality of cavities 1441 and 1451 can be formed using a masking process, an exposure process, and / or a development process. Dielectric layer 1425 may represent dielectric layer 1420 and / or dielectric layer 1440. Dielectric layer 1427 may represent dielectric layer 1430 and / or dielectric layer 1450.

[0157] like Figure 14C As shown, stage 8 illustrates the state after interconnects are formed in and over the surfaces of dielectric layers 1425 and 1427. Multiple interconnects 1442 may be formed over (e.g., above) the first surface of dielectric layer 1425 and multiple cavities 1441. Multiple interconnects 1452 may be formed over (e.g., below) the second surface of dielectric layer 1427 and multiple cavities 1451. Multiple interconnects 1442 and / or multiple interconnects 1452 may be formed using masking processes, plating processes, and etching processes. Multiple interconnects 1422 and / or multiple interconnects 1442 may be represented by multiple interconnects 1424, as shown in stage 9. Multiple interconnects 1432 and / or multiple interconnects 1452 may be represented by multiple interconnects 1426, as shown in stage 9.

[0158] Phase 9 illustrates the states after (i) decoupling of interconnect block 105a from carrier 1400 and (ii) decoupling of interconnect block 105b from carrier 1400. Interconnect block 105a can be implemented as a coreless substrate or a coreless substrate block. Interconnect block 105b can be implemented as a coreless substrate or a coreless substrate block.

[0159] In some specific implementations, manufacturing a coreless substrate involves several processes. Figure 15An exemplary flowchart illustrating a method 1500 for providing or manufacturing a coreless substrate is shown. In some specific embodiments, Figure 15 Method 1500 can be used to provide or manufacture any coreless substrate and / or coreless substrate block of this disclosure. For example, Figure 15 Method 1500 can be used to manufacture interconnect block 105.

[0160] It should be noted that Figure 15 Method 1500 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a coreless substrate. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure. Figure 15 Method 1500 can be used to manufacture one or more substrates (as part of a wafer) at a time.

[0161] This method (at 1505) provides a carrier with a seed layer. Figure 14A Phase 1 illustrates and describes an example of the provided carrier 1400. The carrier 1400 may include a substrate. The carrier 1400 may include a seed layer 1402 located on a first surface of the carrier 1400 and a seed layer 1404 located on a second surface of the carrier 1400. The carrier 1400 may be a dielectric.

[0162] The method (at 1510) forms interconnects on one or both sides of the carrier. Figure 14A Phase 2 illustrates and describes an example of forming interconnects in and on the surface of carrier 1400. A plurality of interconnects 1412 may be formed on (e.g., above) a first surface of carrier 1400. A seed layer 1402 may be part of the plurality of interconnects 1412. A plurality of interconnects 1414 may be formed on (e.g., below) a second surface of carrier 1400. A seed layer 1404 may be part of the plurality of interconnects 1414. Masking processes, plating processes, and etching processes may be used to form the plurality of interconnects 1412 and / or the plurality of interconnects 1414.

[0163] The method (at 1515) forms at least one dielectric layer over the interconnect, seed layer and carrier. Figure 14A Phase 3 illustrates and describes an example of forming a dielectric layer 1420 on (e.g., above) the first surface of the carrier 1400 and a plurality of interconnects 1412. Figure 14APhase 3 also illustrates and describes the formation of a dielectric layer 1430 on (e.g., below) the second surface of the carrier 1400 and the plurality of interconnects 1414. The dielectric layers 1420 and 1430 can be formed using deposition and / or lamination processes. The dielectric layers 1420 and 1430 can be made of a different material than the carrier 1400. Forming at least one dielectric layer may also include forming a cavity within the dielectric layer. Figure 14A Stage 4 illustrates and describes the formation of a plurality of cavities 1421 in dielectric layer 1420 and a plurality of cavities 1431 in dielectric layer 1430. The plurality of cavities 1421 and the plurality of cavities 1431 can be formed using an etching process (e.g., a photolithography process). The plurality of cavities 1421 and the plurality of cavities 1431 can be formed using a masking process, an exposure process, and / or a development process.

[0164] This method (at 1520) forms interconnects within and on top of the dielectric layer. Figure 14B Phase 5 illustrates and describes an example of forming interconnects in and on the surfaces of dielectric layers 1420 and 1430. Multiple interconnects 1422 may be formed on (e.g., above) the first surface of dielectric layer 1420 and multiple cavities 1421. Multiple interconnects 1432 may be formed on (e.g., below) the second surface of dielectric layer 1430 and multiple cavities 1431. Masking processes, plating processes, and etching processes may be used to form the multiple interconnects 1422 and / or the multiple interconnects 1432.

[0165] The method (at 1525) forms at least one dielectric layer over the interconnect and the dielectric layer. Figure 14B Phase 6 illustrates and describes an example of forming a dielectric layer 1440 on (e.g., above) a first surface of dielectric layer 1420 and a plurality of interconnects 1422. Figure 14B Phase 6 also illustrates and describes an example of forming a dielectric layer 1450 above (e.g., below) the second surface of the dielectric layer 1430 and a plurality of interconnects 1432. Dielectric layers 1440 and 1450 can be formed using deposition and / or lamination processes. Dielectric layers 1440 and / or 1450 can be the same dielectric layers as dielectric layers 1420 and / or 1430. Forming at least one dielectric layer may also include forming cavities within the dielectric layer. Figure 14BStage 7 illustrates and describes examples of forming a plurality of cavities 1441 in dielectric layer 1440 (which is shown as part of dielectric layer 1425) and forming a plurality of cavities 1451 in dielectric layer 1450 (which is shown as part of dielectric layer 1427). Etching processes (e.g., photolithography) can be used to form the plurality of cavities 1441 and 1451. Masking processes, exposure processes, and / or developing processes can be used to form the plurality of cavities 1441 and 1451. Dielectric layer 1425 may represent dielectric layer 1420 and / or dielectric layer 1440. Dielectric layer 1427 may represent dielectric layer 1430 and / or dielectric layer 1450.

[0166] This method (at 1530) forms interconnects within and on top of the dielectric layer. Figure 14C Stage 8 illustrates and describes the formation of interconnects within and above the surfaces of dielectric layers 1440 and 1450. Multiple interconnects 1442 may be formed above (e.g., above) the first surface of dielectric layer 1440 and multiple cavities 1441. Multiple interconnects 1452 may be formed above (e.g., below) the second surface of dielectric layer 1450 and multiple cavities 1451. Multiple interconnects 1442 and / or multiple interconnects 1452 may be formed using masking processes, plating processes, and etching processes. Multiple interconnects 1422 and / or multiple interconnects 1442 may be represented by multiple interconnects 1424, as shown in Stage 9. Multiple interconnects 1432 and / or multiple interconnects 1452 may be represented by multiple interconnects 1426, as shown in... Figure 14C As shown in stage 9.

[0167] This method (at 1535) decouples the carrier and removes a portion of the seed layer. Figure 14C Phase 9 illustrates and describes examples of (i) decoupling interconnect block 105a from carrier 1400 and (ii) decoupling interconnect block 105b from carrier 1400. Interconnect block 105a may be implemented as a coreless substrate or a coreless substrate block. Interconnect block 105b may be implemented as a coreless substrate or a coreless substrate block.

[0168] In some specific implementations, manufacturing a core substrate involves several processes. Figures 16A to 16B Exemplary steps for providing or manufacturing a core-based substrate are illustrated. The core-based substrate may be implemented as a core-based substrate block. In some embodiments, the core-based substrate may include passive devices. In some embodiments, Figures 16A to 16B The processes described above can be used to provide or manufacture interconnect portion block 107 and / or interconnect portion block 207. However, Figures 16A to 16B The process can be used to manufacture other interconnection portion blocks described in this disclosure.

[0169] It should be noted that Figures 16A to 16B The processes can be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture a core substrate. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0170] like Figure 16A As shown, stage 1 illustrates the state after the core layer 1600 is provided. The core layer 1600 may include a seed layer 1602 located on a first surface of the core layer 1600 and a seed layer 1604 located on a second surface of the core layer 1600. The core layer 1600 may be a dielectric.

[0171] Stage 2 illustrates the state after multiple cavities 1605 have been formed through the core layer 1600, seed layer 1602, and seed layer 1604. The multiple cavities 1605 can be formed using etching and / or laser processes.

[0172] Phase 3 illustrates the state after interconnects are formed in and on the surface of core layer 1600. Multiple core interconnects 1622 can be formed in multiple cavities 1605. Multiple interconnects 1612 can be formed on (e.g., above) a first surface of core layer 1600. Seed layer 1602 can be part of the multiple interconnects 1612. Multiple interconnects 1614 can be formed on (e.g., below) a second surface of core layer 1600. Seed layer 1604 can be part of the multiple interconnects 1614. Masking processes, plating processes, and / or etching processes can be used to form the multiple core interconnects 1622, the multiple interconnects 1612, and / or the multiple interconnects 1614. In some embodiments, a passive device (e.g., 270) can be placed in one of the cavities from the multiple cavities 1605 before the interconnects are formed. When the passive device is placed in the cavity, a dielectric layer can be formed around the passive device before the interconnects are formed. In some specific implementations, interconnects can be formed so that some interconnects contact the terminals of passive devices.

[0173] Stage 4 illustrates the state after a dielectric layer 1620 is formed on (e.g., above) the first surface of the core layer 1600 and the plurality of interconnects 1612. Stage 4 also illustrates the state after a dielectric layer 1630 is formed on (e.g., below) the second surface of the core layer 1600 and the plurality of interconnects 1614. Dielectric layers 1620 and 1630 can be formed using deposition and / or lamination processes. Dielectric layers 1620 and 1630 can be made of a different material than the core layer 1600.

[0174] like Figure 16B As shown, stage 5 illustrates the state after forming a plurality of cavities 1621 in dielectric layer 1620 and a plurality of cavities 1631 in dielectric layer 1630. The plurality of cavities 1621 and the plurality of cavities 1631 can be formed using an etching process (e.g., a photolithography process). The plurality of cavities 1621 and the plurality of cavities 1631 can be formed using a masking process, an exposure process, and / or a development process.

[0175] Phase 6 illustrates the state after interconnects are formed in and on the surfaces of dielectric layers 1620 and 1630. Multiple core interconnects 1622 can be formed on (e.g., above) the first surface of dielectric layer 1620 and multiple cavities 1621. Multiple interconnects 1632 can be formed on (e.g., below) the second surface of dielectric layer 1630 and multiple cavities 1631. Multiple core interconnects 1622 and / or multiple interconnects 1632 can be formed using masking processes, plating processes, and / or etching processes.

[0176] Stage 6 can be illustrated as an interconnect portion block implemented as a core substrate. Stage 6 can be illustrated as an example of interconnect portion block 107. Different specific implementations may use different processes to form the metal layers and / or interconnects. It should be noted that... Figures 16A to 16B Stages 4 to 6 can be repeated iteratively to form additional metal layers.

[0177] In some specific implementations, manufacturing a core substrate involves several processes. Figure 17 An exemplary flowchart illustrating a method 1700 for providing or manufacturing a substrate with a core is shown. In some specific embodiments, Figure 17 Method 1700 can be used to provide or manufacture any core-containing substrate and / or core-containing substrate block of this disclosure. For example, Figure 17 Method 1700 can be used to manufacture interconnect block 107 and / or interconnect block 207.

[0178] It should be noted that Figure 17 Method 1700 may combine one or more processes to simplify and / or clarify the methods for providing or manufacturing a core-containing substrate. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure. Figure 17 Method 1700 can be used to manufacture one or more substrates (as part of a wafer) at a time.

[0179] The method (at 1705) provides a core layer having at least one seed layer. Figure 16APhase 1 illustrates and describes an example of the provided core layer 1600. The core layer 1600 may include a seed layer 1602 located on a first surface of the core layer 1600 and a seed layer 1604 located on a second surface of the core layer 1600. The core layer 1600 may be a dielectric.

[0180] This method (at 1710) forms a cavity in the core layer. Figure 16A Stage 2 illustrates and describes an example of forming multiple cavities 1605 through the core layer 1600, seed layer 1602, and seed layer 1604. Multiple cavities 1605 can be formed using etching and / or laser processes.

[0181] This method (at 1715) forms interconnects in / on the core layer. Figure 16A Phase 3 illustrates and describes an example of forming interconnects within and on the surface of core layer 1600. Multiple core interconnects 1622 can be formed in multiple cavities 1605. Multiple interconnects 1612 can be formed on (e.g., above) a first surface of core layer 1600. Seed layer 1602 can be part of multiple interconnects 1612. Multiple interconnects 1614 can be formed on (e.g., below) a second surface of core layer 1600. Seed layer 1604 can be part of multiple interconnects 1614. Masking processes, plating processes, and / or etching processes can be used to form the multiple core interconnects 1622, multiple interconnects 1612, and / or multiple interconnects 1614. In some embodiments, a passive device (e.g., 270) can be placed in one of the cavities from the multiple cavities 1605 before forming the interconnects. When the passive device is placed in the cavity, a dielectric layer can be formed around the passive device before forming the interconnects. In some specific implementations, interconnects can be formed so that some interconnects contact the terminals of passive devices.

[0182] This method (at 1720) forms at least one dielectric layer. Figure 16A Phase 4 illustrates and describes an example of forming a dielectric layer 1620 on (e.g., above) the first surface of the core layer 1600 and a plurality of interconnects 1612. Figure 16A Phase 4 also illustrates and describes an example of forming a dielectric layer 1630 on (e.g., below) the second surface of the core layer 1600 and a plurality of interconnects 1614. Dielectric layers 1620 and 1630 can be formed using deposition and / or lamination processes. Dielectric layers 1620 and 1630 can be made of a different material than the core layer 1600. Forming at least one dielectric layer may include forming a cavity within the dielectric layer. Figure 16BStage 5 illustrates and describes examples of forming a plurality of cavities 1621 in dielectric layer 1620 and a plurality of cavities 1631 in dielectric layer 1630. The plurality of cavities 1621 and the plurality of cavities 1631 can be formed using an etching process (e.g., a photolithography process). The plurality of cavities 1621 and the plurality of cavities 1631 can be formed using a masking process, an exposure process, and / or a development process.

[0183] This method (at 1725) forms the interconnect. Figure 16B Stage 6 illustrates and describes an example of forming interconnects in and on the surfaces of dielectric layers 1620 and 1630. Multiple core interconnects 1622 may be formed on (e.g., above) the first surface of dielectric layer 1620 and multiple cavities 1621. Multiple interconnects 1632 may be formed on (e.g., below) the second surface of dielectric layer 1630 and multiple cavities 1631. Multiple core interconnects 1622 and / or multiple interconnects 1632 may be formed using masking processes, plating processes, and / or etching processes. It should be noted that additional dielectric layers and additional interconnects on additional metal layers can be formed by iteratively repeating the formation of the dielectric layer (at 1720) and the formation of the interconnects (at 1725).

[0184] In some specific implementations, manufacturing the metallized parts involves several processes. Figures 18A to 18B Exemplary steps for providing or manufacturing metallized portions and / or blocks of metallized portions are illustrated. In some specific implementations, Figures 18A to 18B The process can be used to provide or manufacture metallized part blocks and / or metallized parts (e.g., 104, 106). Figures 18A to 18B The process will be described as manufacturing interconnect portion blocks 109 (e.g., metallized portion blocks). However, Figures 18A to 18B The process can be used to manufacture any metallized portion described in this disclosure.

[0185] It should be noted that Figures 18A to 18B The processes can be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the substrate. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0186] like Figure 18AAs shown, stage 1 illustrates the state after the carrier 1800 is provided. A seed layer 1801 and interconnects 1802 may be located on the carrier 1800. Interconnects 1802 may be located on the seed layer 1801. Interconnects 1802 can be formed using plating and etching processes. In some embodiments, the carrier 1800 may be provided with a seed layer 1801 and a metal layer patterned to form interconnects 1802. Interconnects 1802 may represent at least some of the interconnects from a plurality of interconnects 192.

[0187] Phase 2 illustrates the state after the dielectric layer 1820 is formed over the carrier 1800, seed layer 1801, and interconnect 1802. The dielectric layer 1820 can be formed using deposition and / or lamination processes. The dielectric layer 1820 may include prepreg and / or polyimide. The dielectric layer 1820 may include a photoimageable dielectric. However, different materials may be used for the dielectric layer in different embodiments.

[0188] Stage 3 illustrates the state after multiple cavities 1810 are formed in the dielectric layer 1820. Multiple cavities 1810 can be formed using photolithography or laser processes. Multiple cavities 1810 can be formed using masking, exposure, and / or development processes.

[0189] Phase 4 illustrates the state after interconnects 1812 are formed in and over the dielectric layer 1820 (including in and over the plurality of cavities 1810). For example, vias, pads, and / or traces may be formed. Plating processes may be used to form the interconnects.

[0190] Phase 5 illustrates the state after the dielectric layer 1822 has been formed over the dielectric layer 1820 and the interconnect 1812. The dielectric layer 1822 can be formed using deposition and / or lamination processes. The dielectric layer 1822 may include prepreg and / or polyimide. The dielectric layer 1822 may include a photoimageable dielectric. However, different materials may be used for the dielectric layer in different embodiments.

[0191] like Figure 18B As shown, stage 6 illustrates the state after multiple cavities 1830 are formed in the dielectric layer 1822. Multiple cavities 1830 can be formed using photolithography or laser processes. Multiple cavities 1830 can be formed using masking, exposure, and / or development processes.

[0192] Stage 7 illustrates the state after interconnects 1814 are formed in and over the dielectric layer 1822 (including in and over the plurality of cavities 1830). For example, vias, pads, and / or traces may be formed. Plating processes may be used to form the interconnects.

[0193] Phase 8 illustrates the state after the carrier 1800 is decoupled (e.g., separated, removed, ground away) from the dielectric layer 1820 and the seed layer 1801, and a portion of the seed layer 1801 is removed (e.g., etched away), leaving an interconnect portion block 109 (e.g., a metallized portion block) comprising at least one dielectric layer 190 and a plurality of interconnects 192. At least one dielectric layer 190 may represent dielectric layer 1820 and / or dielectric layer 1822. The plurality of interconnects 192 may represent interconnects 1802, 1812, and / or 1814.

[0194] Figures 18A to 18B An example is shown of forming metallized portions on a carrier. In some embodiments, metallized portions and / or blocks of metallized portions can be fabricated on the surface of the encapsulation portion, which includes an encapsulation layer and interconnects, thereby bypassing the need for a carrier.

[0195] In some specific implementations, manufacturing the metallized parts involves several processes. Figure 19 An exemplary flowchart illustrating a method 1900 for providing or manufacturing a metallized portion is shown. The metallized portion may be implemented as a metallized portion block. In some specific implementations, Figure 19 Method 1900 can be used to provide or manufacture the metallized portions of this disclosure. For example, Figure 19 Method 1900 can be used to manufacture metallized portion 104 and / or metallized portion 106. However, Figure 19 Method 1900 will be described as manufacturing interconnection block 109.

[0196] It should be noted that Figure 19 Method 1900 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture metallized portions. In some implementations, the order of the processes may be changed or modified.

[0197] The method (at 1905) provides a carrier (e.g., 1800). Different specific embodiments may use different materials for the carrier 1800. The carrier 1800 may include a seed layer (e.g., 1801). The seed layer 1801 may include a metal (e.g., copper). The carrier may include a substrate, glass, quartz, and / or a carrier strip. Figure 18A Phase 1 illustrates and describes an example of the carrier with a seed layer provided.

[0198] The method (at 1910) forms and patterns interconnects over a carrier 1800 and a seed layer 1801. A metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some embodiments, the carrier and seed layer may include a metal layer. The metal layer is located over the seed layer and may be patterned to form the interconnects (e.g., 192). Figure 18A Stage 1 illustrates and describes an example of forming and patterning interconnects on a seed layer and a carrier. It should be noted that, instead of a carrier, interconnects may be formed on a surface including an encapsulation layer and an encapsulation portion (e.g., 102) of the interconnect, such as when metallization portion 104 and / or metallization portion 106 are manufactured.

[0199] This method (at 1915) forms / provides a dielectric layer 1820 over a seed layer 1801, a carrier 1800, and an interconnect 1802. The dielectric layer 1820 can be formed using deposition and / or lamination processes. The dielectric layer 1820 may include a prepreg and / or polyimide. The dielectric layer 1820 may include a photoimageable dielectric. Forming the dielectric layer 1820 may also include forming a plurality of cavities (e.g., 1810) within the dielectric layer 1820. The plurality of cavities can be formed using photolithography or laser processes. The plurality of cavities 1810 can be formed using masking processes, exposure processes, and / or development processes. Figure 18A Examples of forming a dielectric layer and forming a cavity in the dielectric layer are illustrated and described in stages 2 and 3.

[0200] This method (at 1920) forms interconnects within and over a dielectric layer. For example, interconnects 1812 may be formed within and over dielectric layer 1820. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer over and / or within the dielectric layer. Forming the interconnects may also include forming the interconnects within cavities of the dielectric layer. Figure 18A Stage 4 illustrates and describes an example of forming interconnects within and on a dielectric layer.

[0201] This method (at 1925) forms / provides a dielectric layer 1822 over a dielectric layer 1820 and an interconnect 1812. The dielectric layer 1822 can be formed using deposition and / or lamination processes. The dielectric layer 1822 may include a prepreg and / or polyimide. The dielectric layer 1822 may include a photoimageable dielectric. Forming the dielectric layer 1822 may also include forming a plurality of cavities (e.g., 1830) within the dielectric layer 1822. The plurality of cavities can be formed using photolithography or laser processes. The plurality of cavities 1830 can be formed using masking processes, exposure processes, and / or development processes. Figures 18A to 18BStages 5 and 6 illustrate and describe examples of forming a dielectric layer and forming cavities within the dielectric layer.

[0202] This method (at 1930) forms interconnects within and over a dielectric layer. For example, interconnects 1814 may be formed within and over dielectric layer 1822. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer over and / or within the dielectric layer. Forming the interconnects may also include forming the interconnects within cavities of the dielectric layer. Figure 18B Stage 7 illustrates and describes an example of forming interconnects within and on a dielectric layer. This method can form additional dielectric layers and additional interconnects, as described in 1925 and 1930.

[0203] In some implementations, once all dielectric layers and additional interconnects are formed, the method can (at 1935) decouple the carrier (e.g., 1800) from the seed layer (e.g., 1801). The carrier 1800 can be separated and / or ground away. The method can also (at 1935) remove portions of the seed layer (e.g., 1801). Etching processes can be used to remove portions of the seed layer 1801. Figure 18B Stage 8 illustrates and describes examples of decoupling the carrier and removing the seed layer.

[0204] Figure 20 An exemplary electrical path is illustrated for a package 2000 including a packaging substrate having an encapsulation portion with interconnection portions. The package 2000 is similar to... Figure 11 Package 1100. Package 2000 includes integrated device 103, integrated device 403, integrated device 2003, and integrated device 2013. Package 2000 also includes a package substrate 401, such as in at least Figure 4 and Figure 11 As described in [the text].

[0205] Integrated device 2003 is coupled to integrated device 403 via a plurality of solder interconnects 2030. Integrated device 2013 is coupled to integrated device 2003 via a plurality of solder interconnects 2070. In some embodiments, the front side of integrated device 2003 faces the back side of integrated device 403. In some embodiments, the back side of integrated device 2003 faces the back side of integrated device 403. In some embodiments, the front side of integrated device 2013 faces the back side of integrated device 2013. In some embodiments, the back side of integrated device 2013 faces the back side of integrated device 2013. In some embodiments, the front side of integrated device 2013 faces the front side of integrated device 2013. In some embodiments, the back side of integrated device 2013 faces the front side of integrated device 2013. Figure 20 Examples of stacked integrated devices that may be defined by integrated device 403, integrated device 2003 and / or integrated device 2013 are shown.

[0206] Figure 20 Examples of electrical paths 1101, 1102, 1103, 1104, 1105, 1106, 1107, and 2007 are provided. Electrical paths 1101, 1102, 1103, 1104, 1105, 1106, and 1107 can be used with… Figure 11 The electrical paths illustrated and described are similar.

[0207] Electrical path 2007 can be an electrical path between integrated device 403 and integrated device 2013. Electrical path 2007 between integrated device 403 and integrated device 2013 may include (i) solder interconnects from a plurality of solder interconnects 2030, (ii) interconnects from integrated device 2003, and (iii) solder interconnects from a plurality of solder interconnects 2070. Depending on how integrated device 2003 is coupled to integrated device 403 and / or how integrated device 2013 is coupled to integrated device 2003, electrical path 2007 may extend through the back side of the integrated device and / or the front side of another integrated device. For example, electrical path 2007 may extend through the back side of integrated device 403, through solder interconnects from a plurality of solder interconnects 2030, through the front side of integrated device 2003, through the back side of integrated device 2003, through solder interconnects from a plurality of solder interconnects 2070, and through the front side of integrated device 2013. Electrical path 2007 can be configured to be electrically coupled to electrical path 1104, electrical path 1105, electrical path 1106 and / or electrical path 1107.

[0208] Figure 21 An exemplary electrical path is illustrated for a package 2100 including a packaging substrate having an encapsulation portion with interconnection portions. Package 2100 is similar to... Figure 11 Package 1100. Package 2100 includes integrated device 2102, integrated device 2103, and integrated device 2105. Package 2100 also includes a package substrate 401, such as in at least Figure 4 and Figure 11 As described in [the text].

[0209] Integrated device 2102 is coupled to package substrate 401 via multiple solder interconnects 2120. Integrated device 2103 is coupled to package substrate 401 via multiple solder interconnects 2130. Integrated device 2105 is coupled to package substrate 401 via multiple solder interconnects 2150. Integrated devices 2102, 2103, and 2105 are coupled to the metallized portion 104 of package substrate 401.

[0210] As an example, in some embodiments, integrated device 2102 may be a first chiplet, and integrated device 2105 may be a second chiplet. Integrated device 2103 may include memory, such as SRAM. In some embodiments, the electrical path to integrated device 2103 may include a core-based substrate block and / or a coreless substrate block. In some embodiments, integrated device 2102 may include a loose technology node chiplet. In some embodiments, the electrical path to integrated device 2102 may include an embedded trace substrate block and / or a core-based substrate block. In some embodiments, integrated device 2105 may include an advanced technology node chiplet. In some embodiments, the electrical path to integrated device 2105 may include a metallized portion block (e.g., a redistributed portion block).

[0211] Figure 21 Examples of electrical paths 2111, 2112, 2113, 2114, 2115, 2116, 2117, and 2119 are given.

[0212] Electrical path 2111 may include an electrical path between integrated device 2103 and board 108. However, it should be noted that electrical path 2111 may extend to other components outside of board 108. Electrical path 2111 between integrated device 2103 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 2130, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 152 of interconnect portion block 105, (v) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (vi) solder interconnects from a plurality of solder interconnects 110, and (vii) board interconnects from a plurality of board interconnects 182.

[0213] Electrical path 2112 may include an electrical path between integrated device 2103 and board 108. However, it should be noted that electrical path 2112 may extend to other components outside of board 108. Electrical path 2112 between integrated device 2103 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 2130, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (v) solder interconnects from a plurality of solder interconnects 110, and (vi) board interconnects from a plurality of board interconnects 182.

[0214] Electrical path 2113 may include an electrical path between integrated device 2102 and board 108. However, it should be noted that electrical path 2113 may extend to other components outside of board 108. Electrical path 2113 between integrated device 2102 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 2120, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 173 of interconnect portion block 207, (v) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (vi) solder interconnects from a plurality of solder interconnects 110, and (vii) board interconnects from a plurality of board interconnects 182.

[0215] Electrical path 2114 may include an electrical path between integrated device 2105 and board 108. However, it should be noted that electrical path 2114 may extend to other components outside of board 108. Electrical path 2114 between integrated device 2105 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 2150, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 173 of interconnect portion block 207, (v) passive device 270, (vi) further interconnects from a plurality of interconnects 173 of interconnect portion block 207, (vii) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (viii) solder interconnects from a plurality of solder interconnects 110, and (ix) board interconnects from a plurality of board interconnects 182.

[0216] Electrical path 2115 may include an electrical path between integrated device 2105 and board 108. However, it should be noted that electrical path 2115 may extend to other components outside of board 108. Electrical path 2115 between integrated device 2105 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 2150, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 252 of interconnect portion block 205, (v) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (vi) solder interconnects from a plurality of solder interconnects 110, and (vii) board interconnects from a plurality of board interconnects 182.

[0217] Electrical path 2116 may include an electrical path between integrated device 2105 and board 108. However, it should be noted that electrical path 2116 may extend to other components outside of board 108. Electrical path 2116 between integrated device 2105 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 2150, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) pillar interconnects from a plurality of pillar interconnects 122, (iv) interconnects from a plurality of interconnects 192 of interconnect portion block 109, (v) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (vi) solder interconnects from a plurality of solder interconnects 110, and (vii) board interconnects from a plurality of board interconnects 182.

[0218] Electrical path 2117 may include an electrical path between integrated device 2102 and integrated device 2105. Electrical path 2117 between integrated device 2102 and integrated device 2105 may include (i) solder interconnects from a plurality of solder interconnects 2120, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, and (iii) solder interconnects from a plurality of solder interconnects 2150.

[0219] Electrical path 2119 may include an electrical path between integrated device 2102 and integrated device 2103. Electrical path 2119 between integrated device 2102 and integrated device 2103 may include (i) solder interconnects from a plurality of solder interconnects 2120, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, and (iii) solder interconnects from a plurality of solder interconnects 2130.

[0220] Figure 22An exemplary electrical path is illustrated for a package 2200 including a packaging substrate having an encapsulation portion with interconnect portions. Package 2200 and... Figure 21 The package 2200 is similar to package 2100. Package 2200 also includes an interposer 2201, integrated devices 2202, 2203, and 2205. Package 2200 also includes a package substrate 401, such as in at least Figure 4 and Figure 11 As described in [the text].

[0221] Interposer 2201 is located between package substrate 401 and integrated devices (e.g., 2202, 2203, 2205). Interposer 2201 may include interposer substrate 2210 (e.g., silicon substrate, silicon interposer substrate) and multiple interconnects 2222 (e.g., multiple interposer interconnects). The multiple interconnects 2222 may include via interconnects. In some embodiments, the multiple interconnects 2222 may also include trace interconnects and pad interconnects. Interposer 2201 is coupled to package substrate 401 through multiple solder interconnects 2240. Interposer 2201 may be coupled to the metallization portion 104 of package substrate 401.

[0222] Integrated device 2202 is coupled to interposer 2201 via multiple solder interconnects 2220. Integrated device 2203 is coupled to interposer 2201 via multiple solder interconnects 2230. Integrated device 2205 is coupled to interposer 2201 via multiple solder interconnects 2250.

[0223] Figure 22 Examples of electrical paths 2211, 2212, 2213, 2214, 2215, 2216, 2217 and 2219 are given.

[0224] Electrical path 2211 may include an electrical path between integrated device 2203 and board 108. However, it should be noted that electrical path 2211 may extend to other components outside of board 108. Electrical path 2211 between integrated device 2203 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 2230, (ii) at least one interconnect from a plurality of interconnects 2222, (iii) solder interconnects from a plurality of solder interconnects 2240, (iv) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (v) pillar interconnects from a plurality of pillar interconnects 122, (vi) interconnects from a plurality of interconnects 152 of interconnect portion block 105, (vii) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (viii) solder interconnects from a plurality of solder interconnects 110, and (ix) board interconnects from a plurality of board interconnects 182.

[0225] Electrical path 2212 may include an electrical path between integrated device 2203 and board 108. However, it should be noted that electrical path 2212 may extend to other components outside of board 108. Electrical path 2212 between integrated device 2203 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 2230, (ii) at least one interconnect from a plurality of interconnects 2222, (iii) solder interconnects from a plurality of solder interconnects 2240, (iv) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (v) pillar interconnects from a plurality of pillar interconnects 122, (vi) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (vii) solder interconnects from a plurality of solder interconnects 110, and (viii) board interconnects from a plurality of board interconnects 182.

[0226] Electrical path 2213 may include an electrical path between integrated device 2202 and board 108. However, it should be noted that electrical path 2213 may extend to other components outside of board 108. Electrical path 2213 between integrated device 2202 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 2220, (ii) at least one interconnect from a plurality of interconnects 2222, (iii) solder interconnects from a plurality of solder interconnects 2240, (iv) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (v) pillar interconnects from a plurality of pillar interconnects 122, (vi) interconnects from a plurality of interconnects 173 of interconnect portion block 207, (vii) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (viii) solder interconnects from a plurality of solder interconnects 110, and (ix) board interconnects from a plurality of board interconnects 182.

[0227] Electrical path 2214 may include an electrical path between integrated device 2205 and board 108. However, it should be noted that electrical path 2214 may extend to other components outside of board 108. The electrical path 2214 between the integrated device 2205 and the board 108 may include (i) solder interconnects from a plurality of solder interconnects 2250, (ii) at least one interconnect from a plurality of interconnects 2222, (iii) solder interconnects from a plurality of solder interconnects 2240, (iv) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (v) pillar interconnects from a plurality of pillar interconnects 122, (vi) interconnects from a plurality of interconnects 173 of interconnect portion block 207, (vii) passive device 270, (viii) further interconnects from a plurality of interconnects 173 of interconnect portion block 207, (ix) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (x) solder interconnects from a plurality of solder interconnects 110, and (xi) board interconnects from a plurality of board interconnects 182.

[0228] Electrical path 2215 may include an electrical path between integrated device 2205 and board 108. However, it should be noted that electrical path 2215 may extend to other components outside of board 108. Electrical path 2215 between integrated device 2205 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 2250, (ii) at least one interconnect from a plurality of interconnects 2222, (iii) solder interconnects from a plurality of solder interconnects 2240, (iv) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (v) pillar interconnects from a plurality of pillar interconnects 122, (vi) interconnects from a plurality of interconnects 252 of interconnect portion block 205, (vii) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (viii) solder interconnects from a plurality of solder interconnects 110, and (ix) board interconnects from a plurality of board interconnects 182.

[0229] Electrical path 2216 may include an electrical path between integrated device 2205 and board 108. However, it should be noted that electrical path 2216 may extend to other components outside of board 108. Electrical path 2216 between integrated device 2205 and board 108 may include (i) solder interconnects from a plurality of solder interconnects 2250, (ii) at least one interconnect from a plurality of interconnects 2222, (iii) solder interconnects from a plurality of solder interconnects 2240, (iv) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (v) pillar interconnects from a plurality of pillar interconnects 122, (vi) interconnects from a plurality of interconnects 192 of interconnect portion block 109, (vii) metallized interconnects from a plurality of metallized interconnects 162 of metallized portion 106, (viii) solder interconnects from a plurality of solder interconnects 110, and (ix) board interconnects from a plurality of board interconnects 182.

[0230] Electrical path 2217 may include an electrical path between integrated device 2202 and integrated device 2205. Electrical path 2217 between integrated device 2202 and integrated device 2205 may include (i) solder interconnects from a plurality of solder interconnects 2220, (ii) at least one interconnect from a plurality of interconnects 2222, and (iii) solder interconnects from a plurality of solder interconnects 2250.

[0231] Electrical path 2219 may include an electrical path between integrated device 2202 and integrated device 2203. Electrical path 2219 between integrated device 2202 and integrated device 2203 may include (i) solder interconnects from a plurality of solder interconnects 2220, (ii) at least one interconnect from a plurality of interconnects 2222, and (iii) solder interconnects from a plurality of solder interconnects 2230.

[0232] It should be noted that the use of interposer 2201 is not limited to package 2200. Interposer 2201 can be implemented in other packages (including other packages described and illustrated in this disclosure) in a similar manner.

[0233] It should be noted that in some specific implementations, the integrated device may be coupled to another component, such as a package substrate or another integrated device, via multiple pillar interconnects and multiple solder interconnects. Therefore, when an integrated device is shown and described as being coupled to another component via multiple solder interconnects, the integrated device may be coupled to the other component via multiple pillar interconnects and multiple solder interconnects.

[0234] It should be noted that the electrical paths shown are exemplary. Different embodiments may have different electrical paths. Different embodiments may have different numbers of electrical paths. In some embodiments, an electrical path may represent a single electrical path from a plurality of electrical paths between two or more components.

[0235] Figure 23 Examples are illustrated of various electronic devices that may integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-packages (SiP), or system-on-a-chip (SoC). For example, mobile phone device 2302, laptop computer device 2304, fixed-location terminal device 2306, wearable device 2308, or motor vehicle 2310 may include device 2300 as described herein. For example, device 2300 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 23 The devices 2302, 2304, 2306, and 2308, as well as vehicle 2310, illustrated herein are merely exemplary. Other electronic devices may also feature device 2300, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0236] Figures 1 to 11 , Figures 12A to 12F , Figure 13 , Figures 14A to 14C , Figure 15 , Figures 16A to 16B , Figure 17 , Figures 18A to 18B and / or Figures 19 to 23 One or more of the illustrated components, processes, features, and / or functions may be rearranged and / or combined into a single component, process, feature, or function, or may be embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figures 1 to 11 , Figures 12A to 12F , Figure 13 , Figures 14A to 14C , Figure 15 , Figures 16A to 16B , Figure 17 , Figures 18A to 18B and / or Figures 19 to 23 The corresponding descriptions herein are not limited to dies and / or ICs. In some specific implementations, Figures 1 to 11 , Figures 12A to 12F , Figure 13 , Figures 14A to 14C , Figure 15 , Figures 16A to 16B , Figure 17 , Figures 18A to 18B and / or Figures 19 to 23 The descriptions and their corresponding information can be used to manufacture, create, supply, and / or produce devices and / or integrated devices. In some specific implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0237] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0238] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any specific implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, then object A and object C can still be considered coupled to each other, even if they are not in direct physical contact. An object coupled to another object may be coupled to at least a portion of another object. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term "encapsulation" means that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be above a component located at the bottom. A top component may be considered a bottom component, and vice versa. As described in this disclosure, a first component located "above" a second component may mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term "above" as used in this application in the context of one component being above another component may be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "above the second component" can mean: (1) the first component is above the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component may be partially or entirely located in the second component. The terms "about 'value X'" or "approximately value X" as used in this disclosure mean within 10% of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. "A plurality of" components may include all possible components or only some of all possible components.For example, if a device comprises ten components, the term "multiple components" can refer to all ten components or only some of those ten components.

[0239] In some embodiments, an interconnect is a component or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0240] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structural diagrams, or block diagrams. Although work diagrams may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The process terminates when its operations are completed.

[0241] Further examples are described below to facilitate understanding of the invention.

[0242] Aspect 1: A package comprising a package substrate and a first integrated device coupled to the package substrate via a first plurality of solder interconnects. The package substrate includes an encapsulation portion, a first metallized portion coupled to a first surface of the encapsulation portion, and a second metallized portion coupled to a second surface of the encapsulation portion. The encapsulation portion includes: a first interconnect portion block; a second interconnect portion block, wherein the second interconnect portion block is an interconnect portion block of a different type from the first interconnect portion block; a plurality of pillar interconnects, wherein the plurality of pillar interconnects includes: a first plurality of pillar interconnects coupled to the first interconnect portion block; a second plurality of pillar interconnects coupled to the second interconnect portion block; and an encapsulation layer at least partially encapsulating the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects.

[0243] Aspect 2: The package according to aspect 1, wherein the first interconnect portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallized portion block, or a die block including through-substrate vias.

[0244] Aspect 3: The package according to aspects 1 to 2, wherein the second interconnect portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallized portion block, or a die block including through-substrate vias.

[0245] Aspect 4: The package according to aspects 1 to 3, wherein the first metallized portion includes a first plurality of metallized interconnects having a first minimum width and a first minimum spacing, and wherein the second metallized portion includes a second plurality of metallized interconnects having a second minimum width and a second minimum spacing.

[0246] Aspect 5: The package according to aspects 1 to 4, wherein the first integrated device is coupled to the first metallized portion of the package substrate via the first plurality of solder interconnects.

[0247] Aspect 6: The package according to aspect 5, wherein the first integrated device includes a first core and a second core, wherein a first electrical path for a first signal to the first core of the first integrated device includes the first interconnect portion block, and wherein a second electrical path for a second signal to the second core of the first integrated device includes the second interconnect portion block.

[0248] Aspect 7: The package according to aspects 5 to 6 further includes a second integrated device coupled to the first metallized portion of the package substrate via a second plurality of solder interconnects.

[0249] Aspect 8: The package according to aspect 7, wherein a first electrical path for a first signal to the first integrated device includes the first interconnect portion block, and wherein a second electrical path for a second signal to the second integrated device includes the second interconnect portion block.

[0250] Aspect 9: The package according to aspect 7, wherein a first electrical path for a first signal between the second metallized portion and the first integrated device includes interconnects from the first interconnect portion block, pillar interconnects from the first plurality of pillar interconnects, metallized interconnects from the first metallized portion, and a first solder interconnect from the first plurality of solder interconnects, and wherein a second electrical path for a second electrical signal between the second metallized portion and the second integrated device includes interconnects from the second interconnect portion block, pillar interconnects from the second plurality of pillar interconnects, other metallized interconnects from the first metallized portion, and a second solder interconnect from the second plurality of solder interconnects.

[0251] Aspect 10: The package according to aspects 1 to 7 further includes a third interconnect portion block located in the encapsulation portion, wherein the plurality of pillar interconnects includes a third plurality of pillar interconnects coupled to the third interconnect portion block.

[0252] Aspect 11: The package according to aspect 10, wherein the first interconnect portion block includes a coreless substrate block, wherein the second interconnect portion block includes a cored substrate block, and wherein the third interconnect portion block includes a metallized portion block.

[0253] Aspect 12: The package according to aspects 10 to 11, wherein a first electrical path for a first electrical signal between the second metallized portion and the first integrated device includes interconnects from the first interconnect portion block, pillar interconnects from the first plurality of pillar interconnects, a first metallized interconnect from the first metallized portion, and a first solder interconnect from the first plurality of solder interconnects; wherein a second electrical path for a second electrical signal between the second metallized portion and the first integrated device includes interconnects from the second interconnect portion block, pillar interconnects from the second plurality of pillar interconnects, a second metallized interconnect from the first metallized portion, and a second solder interconnect from the first plurality of solder interconnects; and wherein a third electrical path for a third electrical signal between the second metallized portion and the first integrated device includes interconnects from the third interconnect portion block, pillar interconnects from the third plurality of pillar interconnects, a third metallized interconnect from the first metallized portion, and a third solder interconnect from the first plurality of solder interconnects.

[0254] Aspect 13: The package according to aspect 12, wherein the interconnects from the metallized portion block are thinner than (i) the interconnects from the coreless substrate block and (ii) the interconnects from the cored substrate block.

[0255] Aspect 14: The package according to aspects 1 to 13, wherein the first interconnect portion block includes a first number of metal layers, and wherein the second interconnect portion block includes a second number of metal layers different from the first number of metal layers.

[0256] Aspect 15: The package according to aspects 1 to 7, wherein a first electrical path for a first electrical signal between the second metallized portion and the first integrated device includes interconnects from the first interconnect portion block, pillar interconnects from the first plurality of pillar interconnects, metallized interconnects from the first metallized portion, and a first solder interconnect from the first plurality of solder interconnects, wherein a second electrical path for a second electrical signal between the second metallized portion and the first integrated device includes interconnects from the second interconnect portion block, pillar interconnects from the second plurality of pillar interconnects, other metallized interconnects from the first metallized portion, and a second solder interconnect from the first plurality of solder interconnects.

[0257] Aspect 16: The package according to aspects 1 to 7, wherein a first electrical path for a first electrical signal between the second metallized portion and the first integrated device includes interconnects from the first interconnect portion block, pillar interconnects from the first plurality of pillar interconnects, metallized interconnects from the first metallized portion, and a first solder interconnect from the first plurality of solder interconnects, wherein a second electrical path for power between the second metallized portion and the first integrated device includes interconnects from the second interconnect portion block, pillar interconnects from the second plurality of pillar interconnects, other metallized interconnects from the first metallized portion, and a second solder interconnect from the first plurality of solder interconnects.

[0258] Aspect 17: The package according to aspect 16, wherein the second electrical path further includes a passive device located in the second interconnect portion block.

[0259] Aspect 18: The package according to aspect 16, wherein the first interconnect portion block includes a metallized portion block, and wherein the second interconnect portion block includes a laminated substrate block.

[0260] Aspect 19: The package according to aspect 16, wherein the third electrical path for grounding between the second metallized portion and the first integrated device includes other interconnects from the second interconnect portion block, another pillar interconnect from the second plurality of pillar interconnects, other metallized interconnects from the first metallized portion, and a third solder interconnect from the first plurality of solder interconnects.

[0261] Aspect 20: The package according to aspect 1 further includes a second integrated device coupled to the package via a second plurality of solder interconnects.

[0262] Aspect 21: The package according to aspect 20, wherein the first integrated device is a first chiplet including a first technology node, and wherein the second integrated device is a second chiplet including a second technology node.

[0263] Aspect 22: The package according to aspect 1 further includes a second integrated device coupled to the first integrated device via a second plurality of solder interconnects.

[0264] Aspect 23: The package according to aspect 22, wherein the first integrated device is a first chiplet including a first technology node, wherein the second integrated device is a second chiplet including a second technology node, wherein the first interconnect portion block is configured to provide a first electrical path for the first integrated device, and wherein the second interconnect portion block is configured to provide a second electrical path for the second integrated device.

[0265] Aspect 24: The package according to aspects 1 to 23 further includes an interposer layer coupled to the package substrate via a second plurality of solder interconnects, wherein the first integrated device is coupled to the package substrate via the interposer layer such that the first plurality of solder interconnects are coupled to the interposer layer.

[0266] Aspect 25: The package according to aspects 1 to 24, wherein the package is implemented in a device selected from the group consisting of: music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, fixed-location terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device, and device in motor vehicle.

[0267] Aspect 26: A method for manufacturing a package. The method provides a first interconnect portion block. The method provides a second interconnect portion block, wherein the second interconnect portion block is an interconnect portion block of a different type from the first interconnect portion block. The method forms a plurality of pillar interconnects, wherein the plurality of pillar interconnects includes: a first plurality of pillar interconnects coupled to the first interconnect portion block; and a second plurality of pillar interconnects coupled to the second interconnect portion block. The method forms an encapsulation layer that at least partially encapsulates the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects, wherein forming the encapsulation layer forms an encapsulation portion. The method forms a first metallization portion coupled to a first surface of the encapsulation portion. The method forms a second metallization portion coupled to a second surface of the encapsulation portion. The encapsulation portion, the first metallization portion, and the second metallization portion form a package substrate. The method couples a first integrated device to the package substrate via a first plurality of solder interconnects.

[0268] Aspect 27: According to the method of aspect 26, the first interconnect portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallized portion block, or a die block including through-substrate vias.

[0269] Aspect 28: The method according to aspects 26 to 27, wherein the second interconnect portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallized portion block, or a die block including through-substrate vias.

[0270] Aspect 29: The method according to aspects 26 to 28 further includes coupling a second integrated device to the package substrate via a second plurality of solder interconnects.

[0271] Aspect 30: The method according to aspect 29, wherein a first electrical path for a first signal to the first integrated device includes the first interconnect portion block, and wherein a second electrical path for a second signal to the second integrated device includes the second interconnect portion block.

[0272] Aspect 31: A method for manufacturing a package substrate. The method provides a first interconnect portion block. The method provides a second interconnect portion block, wherein the second interconnect portion block is an interconnect portion block of a different type from the first interconnect portion block. The method forms a plurality of pillar interconnects, wherein the plurality of pillar interconnects includes: a first plurality of pillar interconnects coupled to the first interconnect portion block; and a second plurality of pillar interconnects coupled to the second interconnect portion block. The method forms an encapsulation layer that at least partially encapsulates the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects, wherein forming the encapsulation layer forms an encapsulation portion. The method forms a first metallized portion coupled to a first surface of the encapsulation portion. The method forms a second metallized portion coupled to a second surface of the encapsulation portion.

[0273] Aspect 32: According to the method of aspect 31, the first interconnect portion block includes a first coreless substrate block, a first cored substrate block, a first embedded passive substrate block, a first metallized portion block, or a first die block including a through-substrate via, wherein the second interconnect portion block includes a second coreless substrate block, a second cored substrate block, a second embedded passive substrate block, a second metallized portion block, or a second die block including a through-substrate via.

[0274] Aspect 33: A method for manufacturing a package. The method provides a package substrate including an encapsulation portion, a first metallized portion coupled to a first surface of the encapsulation portion, and a second metallized portion coupled to a second surface of the encapsulation portion. The encapsulation portion includes: a first interconnect portion block; a second interconnect portion block, wherein the second interconnect portion block is an interconnect portion block of a different type from the first interconnect portion block; and a plurality of pillar interconnects, wherein the plurality of pillar interconnects includes: a first plurality of pillar interconnects coupled to the first interconnect portion block; and a second plurality of pillar interconnects coupled to the second interconnect portion block. The encapsulation portion further includes an encapsulation layer that at least partially encapsulates the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects. The method couples a first integrated device to the package substrate via a first plurality of solder interconnects.

[0275] Aspect 34: According to the method of aspect 33, the first interconnect portion block includes a first coreless substrate block, a first cored substrate block, a first embedded passive substrate block, a first metallized portion block, or a first die block including a through-substrate via, wherein the second interconnect portion block includes a second coreless substrate block, a second cored substrate block, a second embedded passive substrate block, a second metallized portion block, or a second die block including a through-substrate via.

[0276] Aspect 35: The method according to aspects 33 to 34 further includes coupling a second integrated device to the package substrate via a second plurality of solder interconnects.

[0277] Aspect 36: An apparatus comprising a package according to aspects 1 to 24, wherein the apparatus is one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and an apparatus in a motor vehicle.

[0278] Aspect 37: A package comprising a package substrate and a first integrated device coupled to the package substrate via a first plurality of solder interconnects. The package substrate includes an encapsulation portion. The encapsulation portion includes: a first interconnect portion block; a second interconnect portion block, wherein the second interconnect portion block is an interconnect portion block of a different type from the first interconnect portion block; a plurality of pillar interconnects, wherein the plurality of pillar interconnects includes: a first plurality of pillar interconnects coupled to the first interconnect portion block; a second plurality of pillar interconnects coupled to the second interconnect portion block; and an encapsulation layer that at least partially encapsulates the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects.

[0279] Aspect 38: The package according to aspect 37, wherein the first interconnect portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallized portion block, or a die block including a through-substrate via.

[0280] Aspect 39: The package according to aspects 37 to 38, wherein the second interconnect portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallized portion block, or a die block including through-substrate vias.

[0281] Aspect 40: The package according to aspects 37 to 39, wherein the package substrate further includes a first metallized portion coupled to a first surface of the encapsulation portion and / or a second metallized portion coupled to a second surface of the encapsulation portion, wherein the first metallized portion includes a first plurality of metallized interconnects having a first minimum width and a first minimum spacing, and wherein the second metallized portion includes a second plurality of metallized interconnects having a second minimum width and a second minimum spacing.

[0282] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be exemplary and not to limit the scope of the appended claims. Therefore, the teachings herein can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package, the package comprising: Packaging substrate, the packaging substrate comprising: (i) An encapsulation portion, said encapsulation portion comprising: First interconnection block; A second interconnect portion block, wherein the second interconnect portion block is an interconnect portion block of a different type from the first interconnect portion block; Multiple post interconnects, wherein the multiple post interconnects include: A plurality of pillar interconnects, the plurality of pillar interconnects being coupled to the first interconnect portion block; and A second plurality of pillar interconnects, the second plurality of pillar interconnects being coupled to the second interconnect portion block; and An encapsulation layer that at least partially encapsulates the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects; (ii) a first metallization portion, the first metallization portion being coupled to a first surface of the encapsulation portion; and (iii) a second metallization portion, the second metallization portion being coupled to a second surface of the encapsulation portion; and A first integrated device is coupled to the package substrate via a first plurality of solder interconnects.

2. The package according to claim 1, wherein the first interconnect portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallized portion block, or a die block including through-substrate vias.

3. The package according to claim 1, wherein the second interconnect portion block includes a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallized portion block, or a die block including through-substrate vias.

4. The packaging component according to claim 1, The first metallized portion includes a first plurality of metallized interconnects, the first plurality of metallized interconnects having a first minimum width and a first minimum spacing, and The second metallized portion includes a second plurality of metallized interconnects, the second plurality of metallized interconnects having a second minimum width and a second minimum spacing.

5. The package of claim 1, wherein the first integrated device is coupled to the first metallized portion of the package substrate via the first plurality of solder interconnects.

6. The packaging component according to claim 5, The first integrated device includes a first core and a second core. The first electrical path for the first signal to the first core of the first integrated device includes the first interconnect block, and The second electrical path for the second signal to the second core of the first integrated device includes the second interconnect portion block.

7. The package of claim 5, further comprising a second integrated device coupled to the first metallized portion of the package substrate via a second plurality of solder interconnects.

8. The package according to claim 7, The first electrical path for the first signal to the first integrated device includes the first interconnect portion block, and The second electrical path for the second signal to the second integrated device includes the second interconnect portion block.

9. The package according to claim 7, The first electrical path for the first signal between the second metallized portion and the first integrated device includes interconnects from the first interconnect portion block, pillar interconnects from the first plurality of pillar interconnects, metallized interconnects from the first metallized portion, and first solder interconnects from the first plurality of solder interconnects. The second electrical path for the second electrical signal between the second metallized portion and the second integrated device includes interconnects from the second interconnect portion block, pillar interconnects from the second plurality of pillar interconnects, other metallized interconnects from the first metallized portion, and second solder interconnects from the second plurality of solder interconnects.

10. The package of claim 1, further comprising a third interconnect portion block located within the encapsulation portion, wherein the plurality of pillar interconnects includes a third plurality of pillar interconnects coupled to the third interconnect portion block.

11. The package according to claim 10, The first interconnection block includes a coreless substrate block. The second interconnection block includes a core substrate block, and The third interconnect portion block includes a metallized portion block.

12. The package according to claim 10, The first electrical path for the first electrical signal between the second metallized portion and the first integrated device includes interconnects from the first interconnect portion block, pillar interconnects from the first plurality of pillar interconnects, first metallized interconnects from the first metallized portion, and first solder interconnects from the first plurality of solder interconnects. The second electrical path for the second electrical signal between the second metallized portion and the first integrated device includes interconnects from the second interconnect portion block, pillar interconnects from the second plurality of pillar interconnects, second metallized interconnects from the first metallized portion, and second solder interconnects from the first plurality of solder interconnects. The third electrical path for the third electrical signal between the second metallized portion and the first integrated device includes interconnects from the third interconnect portion block, pillar interconnects from the third plurality of pillar interconnects, third metallized interconnects from the first metallized portion, and third solder interconnects from the first plurality of solder interconnects.

13. The package of claim 12, wherein the interconnects from the metallized portion block are thinner than (i) the interconnects from the coreless substrate block and (ii) the interconnects from the cored substrate block.

14. The package according to claim 1, The first interconnect portion block includes a first number of metal layers, and The second interconnect portion block includes a second number of metal layers, which is different from the first number of metal layers.

15. The package according to claim 1, The first electrical path for the first electrical signal between the second metallized portion and the first integrated device includes interconnects from the first interconnect portion block, pillar interconnects from the first plurality of pillar interconnects, metallized interconnects from the first metallized portion, and first solder interconnects from the first plurality of solder interconnects. The second electrical path for the second electrical signal between the second metallized portion and the first integrated device includes interconnects from the second interconnect portion block, pillar interconnects from the second plurality of pillar interconnects, other metallized interconnects from the first metallized portion, and second solder interconnects from the first plurality of solder interconnects.

16. The package according to claim 1, The first electrical path for the first electrical signal between the second metallized portion and the first integrated device includes interconnects from the first interconnect portion block, pillar interconnects from the first plurality of pillar interconnects, metallized interconnects from the first metallized portion, and first solder interconnects from the first plurality of solder interconnects. The second electrical path for power between the second metallized portion and the first integrated device includes interconnects from the second interconnect portion block, pillar interconnects from the second plurality of pillar interconnects, other metallized interconnects from the first metallized portion, and second solder interconnects from the first plurality of solder interconnects.

17. The package of claim 16, wherein the second electrical path further comprises a passive device located in the second interconnect portion block.

18. The package according to claim 16, The first interconnect portion block includes a metallized portion block, and The second interconnection block includes a laminated substrate block.

19. The package of claim 16, wherein the third electrical path for grounding between the second metallized portion and the first integrated device comprises other interconnects from the second interconnect portion block, another pillar interconnect from the second plurality of pillar interconnects, other metallized interconnects from the first metallized portion, and a third solder interconnect from the first plurality of solder interconnects.

20. The package of claim 1, further comprising a second integrated device coupled to the package via a second plurality of solder interconnects.

21. The package according to claim 20, The first integrated device is a first small chip including a first technology node, and The second integrated device is a second small chip that includes a second technology node.

22. The package of claim 1, further comprising a second integrated device coupled to the first integrated device via a second plurality of solder interconnects.

23. The package according to claim 22, The first integrated device is a first chip comprising a first technology node. The second integrated device is a second chip that includes a second technology node. The first interconnect portion block is configured to provide a first electrical path for the first integrated device, and The second interconnect block is configured to provide a second electrical path for the second integrated device.

24. The package of claim 1, further comprising an interposer layer coupled to the package substrate via a second plurality of solder interconnects, wherein the first integrated device is coupled to the package substrate via the interposer layer such that the first plurality of solder interconnects are coupled to the interposer layer.

25. The package of claim 1, wherein the package is implemented in a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

26. A method for manufacturing a package, the method comprising: Provide the first interconnection section block; A second interconnect portion block is provided, wherein the second interconnect portion block is an interconnect portion block of a different type from the first interconnect portion block; Forming a plurality of post interconnects, wherein the plurality of post interconnects includes: A plurality of pillar interconnects, the plurality of pillar interconnects being coupled to the first interconnect portion block; and A second plurality of pillar interconnects, the second plurality of pillar interconnects being coupled to the second interconnect portion block; and An encapsulation layer is formed, which at least partially encapsulates the first interconnect portion block, the second interconnect portion block, and the plurality of pillar interconnects, wherein forming the encapsulation layer forms an encapsulation portion; A first metallization portion is formed, the first metallization portion being coupled to a first surface of the encapsulation portion; and A second metallized portion is formed, and the second metallized portion is coupled to the second surface of the encapsulation portion. The encapsulation portion, the first metallized portion, and the second metallized portion form a packaging substrate; and The first integrated device is coupled to the package substrate via a first plurality of solder interconnects.

27. The method of claim 26, wherein the first interconnect portion block comprises a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallized portion block, or a die block including through-substrate vias.

28. The method of claim 26, wherein the second interconnect portion block comprises a coreless substrate block, a cored substrate block, an embedded passive substrate block, a metallized portion block, or a die block including through-substrate vias.

29. The method of claim 26, further comprising coupling a second integrated device to the package substrate via a second plurality of solder interconnects.

30. The method according to claim 29, The first electrical path for the first signal to the first integrated device includes the first interconnect portion block, and The second electrical path for the second signal to the second integrated device includes the second interconnect portion block.

Images