Aligning multi-chip device

Abstract

Embodiments herein describe arranging TX and RX circuits in an IC such that a rotating IC and a mirrored IC are aligned when connected in a multi-chip device. In one embodiment, a TX circuit (e.g., a TX physical layer or PHY) is arranged in one row, while an RX circuit (e.g., an RX physical layer or PHY) is arranged in another row. In this way, when the IC is rotated or mirrored, at least one TX PHY is aligned with an RX PHY on another IC. In this way, non-crossing chip-to-chip connections may be formed through the interposer.

Description

Technical Field

[0001] Examples of this disclosure generally relate to aligning transmit (TX) and receive (RX) circuits between integrated circuits (ICs) in a multi-chip device. Background Technology

[0002] Many devices comprise multiple ICs (or dies or chips) interconnected on a substrate or interposer. That is, chip-to-chip connections can be used to form 1×2, 1×3, 1×4, etc., devices. Typically, each IC in the IC group is a different tapeout (e.g., different mask sets are used for each IC in a multi-chip device). One reason for this is to ensure alignment of the RX and TX circuitry used for chip-to-chip connections. That is, chip-to-chip connections do not cross over when navigating through the interposer. Therefore, using different tapeouts and mask sets, even if the ICs may have substantially the same hardware components (e.g., hardware modules), is expensive. Summary of the Invention

[0003] One embodiment of this document is an apparatus comprising: an interposer; a first IC disposed on the interposer, wherein the first IC includes a first row of transmit physical layers (TX PHY) parallel to the periphery of the first IC and a second row of receive physical layers (RX PHY) parallel to the periphery of the first IC; and a second IC disposed on the interposer, wherein the second IC includes a third row of TX PHYs parallel to the periphery of the second IC and a fourth row of RX PHYs parallel to the periphery of the second IC. The apparatus further includes chip-to-chip connections that couple corresponding RX PHYs in the RX PHYs of the first IC to the TX PHYs of the second IC within the interposer, and vice versa.

[0004] Another embodiment of this document is a method comprising transmitting data from a first IC to a second IC using a chip-to-chip connection in an interposer layer, wherein the first IC and the second IC are disposed on the interposer layer and the first IC receives data at the second IC. The first IC includes a first row of transmit physical layers (TX PHY) parallel to the periphery of the first IC and a second row of receive physical layers (RX PHY) parallel to the periphery of the first IC, and the second IC includes a third row of TX PHYs parallel to the periphery of the second IC and a fourth row of RX PHYs parallel to the periphery of the second IC. Furthermore, the chip-to-chip connection couples a corresponding RX PHY in the first IC to a TX PHY in the second IC, and vice versa.

[0005] Another embodiment of this document is an apparatus comprising: an interposer; a first FPGA disposed on the interposer, wherein the first FPGA includes a first circuit design; and a second FPGA disposed on the interposer, wherein the second FPGA includes a second circuit design as a mirror image of the first circuit design. Furthermore, the interposer provides connectivity between the first FPGA and the second FPGA.

[0006] Another embodiment of this document is an apparatus comprising: an interposer; a first FPGA disposed on the interposer, wherein the first FPGA includes a first circuit design; and a second FPGA disposed on the interposer, wherein the second FPGA includes the first circuit design and is rotatable relative to the first FPGA. Furthermore, the interposer provides a connection between the first FPGA and the second FPGA.

[0007] Other implementations can be expressed in the following non-limiting embodiments.

[0008] Example 1. An apparatus comprising: an interposer layer; and a first IC disposed on the interposer layer and including a first row transmit physical layer (TX PHY) parallel to the periphery of the first IC and a second row receive physical layer (RX PHY) parallel to the periphery of the first IC; a second IC disposed on the interposer layer and including a third row TX PHY parallel to the periphery of the second IC and a fourth row RX PHY parallel to the periphery of the second IC; and a chip-to-chip connection in the interposer layer that couples a corresponding RX PHY in the RX PHY of the first IC to the TX PHY of the second IC, and couples a corresponding RX PHY in the RX PHY of the second IC to the TX PHY of the first IC.

[0009] Example 2. The device according to Example 1, wherein the chip-to-chip connections are non-crossing.

[0010] Example 3. The device according to Example 2, wherein each TXPHY in the first IC is aligned in the same column as an RXPHY in the second IC, and each TXPHY in the first IC is aligned in the same column as an RXPHY in the first IC.

[0011] Example 4. The device according to Example 1, wherein the first row is different from the second row, and the third row is different from the fourth row.

[0012] Example 5. The device according to Example 1, wherein the first IC has a circuit layout that is a mirror image of the circuit layout of the second IC.

[0013] Example 6. The device according to Example 5, wherein the first IC and the second IC do not perform bit reordering on the bits received by the chip-to-chip connection.

[0014] Example 7. The device according to Example 1, wherein the first IC has the same circuit layout as the second IC, wherein the circuit layout of the first IC is rotated 180 degrees relative to the circuit layout of the second IC.

[0015] Example 8. The device according to Example 7, wherein the first IC and the second IC are configured to perform bit reordering on bits received by the chip-to-chip connection.

[0016] Example 9. The device according to Example 1, the device further includes: a third IC, the third IC being disposed on the interposer layer, and including a fifth row of TX PHYs parallel to the periphery of the third IC and a sixth row of RX PHYs parallel to the periphery of the third IC, wherein the chip-to-chip connection couples a corresponding RX PHY in the RX PHY of the third IC to a TX PHY in the first IC, and couples a corresponding RX PHY in the RX PHY of the first IC to a TX PHY in the third IC.

[0017] Example 10. The device according to Example 9, the device further includes: a fourth IC, the fourth IC being disposed on the interposer layer, and including a seventh row of TX PHYs parallel to the periphery of the fourth IC and an eighth row of RX PHYs parallel to the periphery of the fourth IC, wherein the first IC, the second IC, the third IC and the fourth IC are configured in a 2×2 configuration, wherein the chip-to-chip connection couples a corresponding RX PHY in the RX PHY of the fourth IC to a TX PHY in the second IC, and couples a corresponding RX PHY in the RX PHY of the second IC to a TX PHY in the fourth IC, and wherein the chip-to-chip connection couples a corresponding RX PHY in the RX PHY of the fourth IC to a TX PHY in the third IC, and couples a corresponding RX PHY in the RX PHY of the third IC to a TX PHY in the fourth IC.

[0018] Example 11. A method comprising: transmitting data from a first IC to a second IC using a chip-to-chip connection in an interposer, wherein the first IC and the second IC are disposed on the interposer; and receiving the data at the second IC, wherein the first IC includes a first row of transmit physical layers (TXPHY) parallel to the periphery of the first IC and a second row of receive physical layers (RXPHY) parallel to the periphery of the first IC, and wherein the second IC includes a third row of TXPHY parallel to the periphery of the second IC and a fourth row of RXPHY parallel to the periphery of the second IC, and wherein the chip-to-chip connection couples a corresponding RXPHY in the RXPHY of the first IC to the TXPHY of the second IC, and couples a corresponding RXPHY in the RXPHY of the second IC to the TXPHY of the first IC.

[0019] Example 12. The method described in Example 11, wherein the chip-to-chip connections are non-crossing.

[0020] Example 13. According to the method of Example 11, each TX PHY in the first IC is aligned in the same column as an RX PHY in the second IC, and each TX PHY in the first IC is aligned in the same column as an RX PHY in the first IC.

[0021] Example 14. According to the method of Example 11, wherein the first IC has a circuit layout that is a mirror image of the circuit layout of the second IC.

[0022] Example 15. According to the method of Example 14, wherein the first IC and the second IC do not perform bit reordering on the bits received by the chip-to-chip connection.

[0023] Example 16. According to the method of Example 11, wherein the first IC has the same circuit layout as the second IC, wherein the circuit layout of the first IC is rotated 180 degrees relative to the circuit layout of the second IC.

[0024] Example 17. According to the method of Example 16, the method further includes performing bit reordering on the data received by the second IC.

[0025] Example 18. According to the method of Example 11, the method further includes: sending data from the first IC to a third IC disposed on the interposer layer, wherein the third IC includes a fifth row of TX PHYs parallel to the periphery of the third IC and a sixth row of RX PHYs parallel to the periphery of the third IC, wherein the chip-to-chip connection couples a corresponding RX PHY in the RX PHY of the third IC to the TX PHY of the first IC, and couples a corresponding RX PHY in the RX PHY of the first IC to the TX PHY of the third IC.

[0026] Example 19. An apparatus comprising: an interposer layer; and a first FPGA disposed on the interposer layer and including a first circuit design; and a second FPGA disposed on the interposer layer and including a second circuit design, the second circuit design being a mirror image of the first circuit design, wherein the interposer layer provides a connection between the first FPGA and the second FPGA.

[0027] Example 20. An apparatus comprising: an interposer layer; and a first FPGA disposed on the interposer layer and including a first circuit design; and a second FPGA disposed on the interposer layer and including the first circuit design, wherein the second FPGA is rotatable relative to the first FPGA, and wherein the interposer layer provides a connection between the first FPGA and the second FPGA. Attached Figure Description

[0028] To gain a more detailed understanding of the features described above, a more specific description of the brief summary can be obtained by referring to the exemplary embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical exemplary embodiments and should not be considered as limiting the scope of the description.

[0029] Figure 1 The illustration shows a chip-to-chip connection for devices with different ICs, according to an example.

[0030] Figure 2 The illustration shows a chip-to-chip connection of a device with a mirrored IC, according to an example.

[0031] Figure 3 The illustration shows a chip-to-chip connection for a device with a rotating IC, according to an example.

[0032] Figure 4 The illustration shows a chip-to-chip connection of a device with mirrored ICs, which have aligned TX and RX circuits, according to an example.

[0033] Figure 5 The illustration shows a chip-to-chip connection of a device with rotating ICs according to an example, these rotating ICs having aligned TX and RX circuits.

[0034] Figure 6 This is a flowchart for operating a multi-chip device, based on an example.

[0035] Figure 7 The illustration shows a 2×2 configuration of ICs on the intermediary layer according to the example.

[0036] For ease of understanding, the same reference numerals are used where possible to denote common elements in the accompanying figures. It is conceivable that elements of one example can be advantageously incorporated into other examples. Detailed Implementation

[0037] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and elements with similar structures or functions are indicated by similar reference numerals in all the drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended to provide an exhaustive description of the embodiments herein, nor are they intended to limit the scope of the claims. Furthermore, the illustrated examples need not possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so illustrated or so explicitly described.

[0038] This document describes an implementation of arranging TX and RX circuits in an IC such that a rotated IC and a mirrored IC are aligned when connected in a multi-chip device. In one implementation, the TX circuitry (e.g., the TX physical layer or PHY) is arranged in one row, while the RX circuitry (e.g., the RX physical layer or PHY) is arranged in another row. This ensures that when the IC is rotated or mirrored, at least one TX PHY is aligned with the RX PHY on the other IC. This allows for non-crossing chip-to-chip connections to be formed through an interposer. For a rotated IC, the TX and RX PHYs are aligned, but the bits may need to be out of order. Software or hardware can reorder these bits before processing the data received from the IC in the receiving IC.

[0039] Figure 1 The illustration shows a chip-to-chip connection 120 for a device 100 with different ICs, according to an example. In this example, device 100 includes an interposer 105 on which two ICs (i.e., IC 110 and IC 115) are disposed. Interposer 105 provides a chip-to-chip connection 120 between ICs 110 and 115. For example, interposer 105 may be a silicon interposer comprising one or more layers, which include traces for forming the connection 120. In one embodiment, ICs 110 and 115 may be mounted onto interposer 105 using, for example, copper pillars, and then the copper pillars electrically couple ICs 110 and 115 to the connection 120, these connections routing electrical signals from one IC to another.

[0040] In this implementation, ICs 110 and 115 are formed from different tape-outs (e.g., different sets of masks). ICs 110 and 115 can be application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), etc. In one implementation, ICs 110 and 115 can have the same or very similar functions, hardware modules, or hardware blocks. However, different tape-outs can be used to form two ICs 110 and 115 such that they have aligned RX and TX circuitry when positioned side-by-side on the interposer layer 105.

[0041] exist Figure 1The enlarged view shows the alignment between RX PHY 125 and TX PHY 130 in more detail. In this example, RX PHYs 125A and 125B, and TX PHYs 130A and 130B are in IC 110, while RX PHYs 125C and 125D, and TX PHYs 130C and 130C are in IC 115. Chip-to-chip connections 120 in interposer 105 connect RX PHYs 125A and 125B in IC 110 to their corresponding TX PHYs 130C and 130C in IC 115, and connect RX PHYs 125C and 125D in IC 115 to their corresponding TX PHYs 130A and 130C in IC 110. As shown, connections 120 are non-crossing within interposer 105. If connection 120 is to cross, this means that connection 120 will have to use multiple layers for routing (e.g., one cross connection in a crossover must be routed on a different layer in interposer 105). However, there are typically very few layers in an interposer (e.g., three layers), meaning that the options for routing the crossover chip-to-chip connections in interposer 105 are limited. If multiple tape-outs are used to form ICs 110 and 115, the TX and RX circuits can be aligned as shown, even though having multiple tape-outs would significantly increase manufacturing costs.

[0042] Preferably, if ICs 110 and 115 have substantially the same hardware module, it will be cost-effective to use a single fabrication for both ICs 110 and 115 while still aligning the TX and RX circuits. This will... Figure 4 and Figure 5 The discussion is ongoing.

[0043] Figure 2 The illustration shows a chip-to-chip connection 220 for a device 200 with mirrored ICs, according to an example. Specifically, device 200 includes an interposer 105 on which ICs 210 and 215 are disposed. In this example, IC 210 is a mirror image of IC 215. In other words, the circuit layout of IC 215 is a mirror image of the circuit layout of IC 210. This is illustrated by the character "F," where the "F" in IC 210 is a mirror image of the "F" in IC 215.

[0044] To create a mirrored circuit layout for two ICs, after designing one IC, the chip designer can instruct a software design application to mirror the design to generate a mirrored circuit layout for the other IC. This can be done by designing two different IC designs (such as...). Figure 1 The design process for ICs 110 and 115 is much easier. However, Figure 2The enlarged diagram illustrates how the mirrored circuit layout caused misalignment of the TX and RX circuits in ICs 210 and 215.

[0045] In this example, RX PHYs 225A and 225B and TX PHYs 230A and 230B are in IC 210, while RX PHYs 225C and 225D and TX PHYs 230C and 230C are in IC 215. Further, Figure 2 The illustration shows the mirror text “TX” and “RX” relative to the TX PHYs 230C and 230D and the RX PHYs 225C and 225D in IC 215, as well as the TX PHYs 230A and 230B and the RX PHYs 225A and 225B. This further illustrates the mirror chip layout of IC 210 and IC 215.

[0046] Chip-to-chip connections 220 in interposer 105 connect the RX PHYs 225A and 225B in IC 210 to their corresponding TX PHYs 230C and 230C in IC 215, and the RX PHYs 225C and 225D in IC 215 to their corresponding TX PHYs 230A and 230C in IC 210. As shown, connections 220 cross within interposer 105. This means that multiple layers within interposer 105 must be used to route connections 220. However, as discussed above, there are typically very few layers in interposer 105, meaning that the options for routing the cross-chip-to-chip connections within interposer 105 are limited. Thus, due to the limited routing space in interposer 105 (or the necessity of using a more expensive interposer with more layers), it may be impossible to use interposer 105 to connect mirrored ICs 210 and 215.

[0047] Figure 3 The illustration shows a chip-to-chip connection of a device 300 with rotating ICs according to an example. Specifically, device 300 includes an interposer 105 on which ICs 310A and 310B are disposed. In this example, IC 310A has the same circuit layout or circuit design as IC 310B, but has been rotated 180 degrees when disposed on interposer 105. In other words, IC 310 can be formed using the same wafer fabrication or the same mask set. Thus, ICs 310 can be completely identical, but one chip is rotated 180 degrees relative to the other. This is illustrated by the character "F," where the "F" in IC 310A is rotated 180 degrees relative to the "F" in IC 310B.

[0048] Figure 3The enlarged diagram illustrates that using the same IC (rotated) means the TX and RX circuits in ICs 310A and 310B are aligned. In this example, RX PHYs 325A and 325B and TX PHYs 330A and 330B are in IC 310A, while RX PHYs 325C and 325D and TX PHYs 330C and 330C are in IC 310B. Furthermore, Figure 3 The illustration shows the rotated text “TX” and “RX” relative to the TX PHYs 230C and 230D and the RX PHYs 225C and 225D in IC 310B, as well as the TX PHYs 230A and 230B and the RX PHYs 225A and 225B. That is, the text “TX” and “RX” in IC 310A are rotated 180 degrees relative to the text in IC 310B.

[0049] Chip-to-chip connections 320 in interposer 105 connect the RX PHYs 325A and 325B in IC 310A to their corresponding TX PHYs 330C and 330C in IC 310B, and the RX PHYs 325C and 325D in IC 310B to their corresponding TX PHYs 330A and 330C in IC 310A. As shown, connections 320 are non-crossing within interposer 105, providing the advantages discussed above. This means that multiple layers within interposer 105 are not required to route connections 220. Therefore, this arrangement of RX PHYs 325 and TX PHYs 330 provides aligned circuitry when using identical but rotated ICs. However... Figure 4 and Figure 5 The implementation scheme described herein provides different arrangements for mirrored ICs (e.g., Figure 2 ) and rotating ICs (e.g., Figure 3 Both provide aligned TX and RX circuits.

[0050] Figure 4 The illustration shows a chip-to-chip connection of a device 400 with mirrored ICs, according to an example. These mirrored ICs have aligned TX and RX circuitry. Specifically, device 400 includes an interposer 105 on which ICs 410 and 415 are disposed. In this example, IC 410 is a mirror image of IC 415. In other words, the circuit layout of IC 415 is a mirror image of the circuit layout of IC 410. This is illustrated by the character "F," where the "F" in IC 410 is a mirror image of the "F" in IC 415. As discussed above, mirroring circuit layouts can be more efficient than designing two different IC designs (e.g.,...). Figure 1 The design process for ICs 110 and 115 is much easier.

[0051] and Figure 2 Placing two mirrored ICs side-by-side causes misalignment and discrepancies in the TX and RX circuits. Figure 4 The enlarged view illustrates the mirrored TX and RX circuit alignment in ICs 410 and 415. In this example, RX PHYs 425A and 425B and TX PHYs 430A and 430B are in IC 410, while RX PHYs 425C and 425D and TX PHYs 430C and 430C are in IC 415. Furthermore, Figure 4 The illustration shows the mirror text “TX” and “RX” relative to the TX PHYs 430C and 430D and the RX PHYs 425C and 425D in IC 415, as well as the TX PHYs 430A and 430B and the RX PHYs 425A and 425B. This further illustrates the mirror chip layout of IC 410 and IC 415.

[0052] It is worth noting that, instead of in Figure 2 Arrange the RX PHY and TX PHY in the columns. Figure 4 In ICs 410 and 415, the RX PHY and TX PHY are arranged in a row. This way, when the circuit layout is mirrored, at least one RX PHY 425 in one IC is aligned with the TX PHY 430 in the other IC. Arranging the RX PHY and TX PHY in a row around the periphery of ICs 410 and 415 results in alignment of the RX PHY and TX PHY when the ICs are arranged side-by-side in device 400. In other words, the RX PHY is arranged in a first row parallel to the periphery of the IC, and the TX PHY is arranged in a different second row parallel to the periphery of the IC. Although... Figure 4 The diagram shows that the row containing RX PHY 425 is closer to the periphery of ICs 410 and 415 than the row containing TX PHY 430, but this can be reversed so that the row containing TX PHY 430 is closer to the periphery.

[0053] Figure 5The illustration shows a chip-to-chip connection of a device 500 with rotating ICs according to an example, these rotating ICs having aligned TX and RX circuitry. Specifically, device 500 includes an interposer 105 on which ICs 510A and 510B are disposed. In this example, IC 510A has the same circuit layout or design as IC 510B, but has been rotated 180 degrees when disposed on interposer 105. In other words, IC 510 can be formed using the same tape-out or the same mask set. Thus, ICs 510 can be completely identical, but one chip is rotated 180 degrees relative to the other. This is illustrated by the character "F," where the "F" in IC 510A is rotated 180 degrees relative to the "F" in IC 510B.

[0054] Figure 5 The enlarged diagram illustrates that using the same IC (rotated) means the TX and RX circuits in ICs 510A and 510B are aligned. In this example, RX PHYs 525A and 525B and TX PHYs 530A and 530B are in IC 510A, while RX PHYs 525C and 525D and TX PHYs 530C and 530C are in IC 510B. Furthermore, Figure 5 The illustration shows the rotated text “TX” and “RX” relative to the TX PHYs 530C and 530D and the RX PHYs 525C and 525D in IC 510B, as well as the TX PHYs 530A and 530B and the RX PHYs 525A and 525B. That is, the text “TX” and “RX” in IC 510A are rotated 180 degrees relative to the text in IC 510B.

[0055] Chip-to-chip connections 520 in interposer 105 connect the RX PHYs 525A and 525B in IC 510A to their corresponding TX PHYs 530C and 530C in IC 510B, and the RX PHYs 525C and 525D in IC 510B to their corresponding TX PHYs 530A and 530C in IC 510A. As shown, connections 520 are non-crossing within interposer 105, providing the advantages discussed above. This means that multiple layers within interposer 105 are not required to route connections 20. Therefore, similar to... Figure 3 , Figure 5 The arrangement of RX PHY 525 and TX PHY 530 provides alignment circuitry when using the same but rotated IC. In other words, when RX PHY 525 and TX PHY 530 are arranged in a row around IC 510, they remain aligned even when IC 510A is rotated 180 degrees relative to IC 510B, just like in... Figure 3 The column arrangement of the TX and RX PHYs in the IC 310 diagram is the same. Thus, Figure 4 and Figure 5 The illustration shows the arrangement of the RX PHY and TX PHY in a row at the periphery of the IC, resulting in the alignment of the TX and RX circuits of both the mirrored IC and the rotated IC (e.g., non-cross-chip-to-chip connections in interposer 105).

[0056] However, although the TX and RX circuits are aligned when IC 510 is rotated relative to each other, the bits sent between RX PHY 525 and TXPHY 530 may be out of order. This is because, upon rotation, the RX PHY and TX PHY in IC 510A will be aligned with different RX PHY and TX PHY in IC 510B. That is, with Figure 4 The IC implementations in the mirror are different. The RX PHY and TX PHY in IC510A are aligned differently from those in IC510B. This may result in bits sent by the TX PHY and received by the RX PHY being in the wrong order.

[0057] However, bit misordering occurs in the chip-to-chip interface (for various reasons). Various bit reordering techniques exist that can be used to reorder bits after they have been received by the RX PHY 525. That is, bits can be reordered by hardware or software elements in the receiving IC before the data is subsequently processed by other circuitry in the receiving IC.

[0058] Although Figure 4 and Figure 5 The illustration shows a 1×2 arrangement (e.g., one column and two rows of ICs), but in other embodiments, the device may have a 1×3 or 1×4 arrangement. In this case, some of the ICs may have chip-to-chip connections with two of the ICs (e.g., using top and bottom sides).

[0059] In one implementation scheme Figure 4 and Figure 5 The IC in this context can be an ASIC, FPGA, SoC, etc. For example, for FPGAs, two FPGAs with different circuit designs or layouts are typically connected to the same interposer layer using two different fabrications. Therefore, being able to attach two FPGAs using a mirror image of their circuit layout, or rotating two FPGAs with the same circuit layout as described herein, can be particularly advantageous because it reduces the complexity of generating mask sets for the two fabrications, or makes it possible to use only one fabrication.

[0060] Figure 6This is a flowchart of a method 600 for operating a multi-chip device, based on an example. At block 605, a first IC transmits data to a second IC using a chip-to-chip connection in an interposer, wherein the first IC and the second IC are disposed on the interposer. Further, the TX PHY and RX PHY on the first IC and the second IC can be configured as follows: Figure 4 and Figure 5 The arrangement shown includes a first IC comprising a first row of TX PHYs parallel to the periphery of the first IC and a second row of RX PHYs parallel to the periphery of the first IC, and a second IC comprising a third row of TX PHYs parallel to the periphery of the second IC and a fourth row of RX PHYs parallel to the periphery of the second IC. Furthermore, chip-to-chip connections couple corresponding RX PHYs in the first IC to TX PHYs in the second IC, and vice versa.

[0061] At block 610, the second IC receives data from the first IC using a chip-to-chip connection in the interposer layer. Furthermore, the second IC can send data to the first IC in parallel or at different times using the chip-to-chip connection.

[0062] Figure 7 The illustration shows a 2×2 configuration of IC 705 on an interposer 700 according to an example. In this top view, IC 705 is positioned in corresponding corners of the interposer 700. The interposer 700 provides connectivity between adjacent ICs 705. For example, the interposer 700 may be a silicon interposer comprising one or more layers, which include traces for forming connections 710. In one embodiment, IC 705 can be mounted onto the interposer using solder balls, which then electrically couple IC 705 to connections 710, these connections recording electrical signals from one IC 705 to adjacent ICs 705.

[0063] Unlike a 1×2, 1×3, or 1×4 arrangement where at least some of the ICs communicate with adjacent ICs only on one side, in Figure 7 In the 2×2 configuration shown, each IC 705 communicates with two adjacent ICs using both sides. For example, IC 705C communicates with IC 705D using a horizontal connection 710B and with IC 705A using a vertical connection 710A. Therefore, the 2×2 configuration effectively doubles the number of chip-to-chip connections that some ICs in a 1×2, 1×3, or 1×4 arrangement could have compared to those that only use one side for communication.

[0064] Figure 7 IC 705 in the middle can be used Figure 4 and Figure 5The diagram illustrates the arrangement of the TX PHY and RX PHY, with the TX PHY and RX PHY positioned on rows surrounding IC 705. This allows the TX PHY and RX PHY to be aligned regardless of whether IC 705 is mirrored or rotated, forming a non-cross-connection 710 within the interposer layer 105.

[0065] In this embodiment, the interposer 700 has a surface area exceeding the mask limitations of the manufacturing technology used to manufacture the interposer. The size of the IC 705 is limited by the mask limitations, which restrict the amount of area that can be exposed and processed using the mask. Currently, for a monolithic die, the maximum size is limited to 33mm to 26mm as a mask limitation. Therefore, the width and height of the IC 705 are limited by this mask limitation.

[0066] In order for the interposer 700 to support multiple ICs 705 with dimensions equal to or just below the mask limit, the interposer must have a surface area exceeding the mask limit. This means that the interposer 700 cannot be fabricated using a single exposure process. Instead, the interposer 700 includes vertical seams 720 and horizontal seams 730, where multiple exposure areas slightly overlap. This allows the interposer to still have traces to form connections 710 and sufficient surface area to support a 2×2 configuration of ICs 705.

[0067] In one implementation, interposer 700 has a total surface area three times the size of the mask limit (e.g., maximum mask field). Furthermore, unlike interposers supporting 1×2, 1×3, and 1×4 configurations that may only have horizontal seams, interposer 700 has both a horizontal seam 730 and a vertical seam 720.

[0068] Reference has been made to the embodiments presented in this disclosure. However, the scope of this disclosure is not limited to the specifically described embodiments. Rather, any combination of the described features and elements (whether or not it relates to different embodiments) is contemplated as an implementation and practice of the contemplated embodiments. Furthermore, while the embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether a particular advantage is achieved through a given embodiment does not limit the scope of this disclosure. Therefore, the foregoing aspects, features, embodiments, and advantages are illustrative only and should not be considered as elements or limitations of the appended claims unless expressly recited in the claims.

[0069] As those skilled in the art will understand, the embodiments disclosed herein may be embodied as systems, methods, or computer program products. Therefore, aspects may take the form of entirely hardware implementations, entirely software implementations (including firmware, resident software, microcode, etc.), or implementations combining software and hardware aspects, all of which may generally be referred to herein as “circuit,” “module,” or “system.” Furthermore, aspects may take the form of computer program products embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0070] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be (e.g., but not limited to) an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (not an exhaustive list) of computer-readable storage media will include: electrical connections having one or more wires, portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium is any tangible medium that can contain or store programs for use by or in connection with an instruction execution system, apparatus, or device.

[0071] Computer-readable signal media may include propagated data signals having computer-readable program code embodied therein (e.g., in baseband or as part of a carrier wave). Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. Computer-readable signal media may be any computer-readable medium that is not a computer-readable storage medium and can convey, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device.

[0072] Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, fiber optic cable, RF, or any suitable combination of the foregoing.

[0073] Computer program code used to perform operations relating to the aspects of this disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Java, Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as the "C" programming language or similar programming languages). The program code may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet through an Internet service provider).

[0074] Various aspects of this disclosure are described below with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments presented in this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executable via the processor of the computer or other programmable data processing apparatus, create components for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0075] These computer program instructions may also be stored in a computer-readable medium that can instruct a computer, other programmable data processing apparatus or other device to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing including instructions that implement the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0076] Computer program instructions may also be loaded onto a computer, other programmable data processing apparatus or other equipment to cause a series of operational steps to be performed on the computer, other programmable apparatus or other equipment to produce a computer-implemented method, such that the instructions, which execute on the computer or other programmable apparatus, provide a process for implementing the function / action specified in one or more boxes of a flowchart and / or block diagram.

[0077] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible specific implementations of systems, methods, and computer program products according to various examples of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions indicated in the blocks may not occur in the order shown in the figures. For example, depending on the functionality involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0078] While the foregoing is directed to specific examples, other and additional examples may be devised without departing from the basic scope of the invention, the scope of which is defined by the appended claims.

Claims

1. An apparatus, said apparatus comprising: Intermediate layer; and A first IC is disposed on the intermediary layer and includes a first row transmit physical layer (TX PHY) parallel to the periphery of the first IC and a second row receive physical layer (RX PHY) parallel to the periphery of the first IC. and The second IC is disposed on the interposer layer and includes a third row of TX PHY parallel to the periphery of the second IC and a fourth row of RX PHY parallel to the periphery of the second IC. Chip-to-chip connection, wherein the chip-to-chip connection in the intermediary layer couples the corresponding RX PHY in the RX PHY of the first IC to the TX PHY in the second IC, and couples the corresponding RX PHY in the RX PHY of the second IC to the TX PHY in the first IC.

2. The device according to claim 1, wherein, The chip-to-chip connections are non-crossing.

3. The device according to claim 2, wherein, Each TX PHY in the first IC is aligned in the same column as an RX PHY in the second IC, and each TX PHY in the first IC is aligned in the same column as an RX PHY in the first IC.

4. The device according to claim 1, wherein, The first IC has a circuit layout that is a mirror image of the circuit layout of the second IC.

5. The device according to claim 4, wherein, The first IC and the second IC do not perform bit reordering on the bits received by the chip-to-chip connection.

6. The device according to claim 1, wherein, The first IC has the same circuit layout as the second IC, wherein the circuit layout of the first IC is rotated 180 degrees relative to the circuit layout of the second IC.

7. The device according to claim 6, wherein, The first IC and the second IC are configured to perform bit reordering on bits received by the chip-to-chip connection.

8. The device according to claim 1, further comprising: A third IC, disposed on the interposer layer, includes a fifth row of TX PHYs parallel to the periphery of the third IC and a sixth row of RX PHYs parallel to the periphery of the third IC, wherein the chip-to-chip connection couples a corresponding RX PHY in the RX PHY of the third IC to a TX PHY in the first IC, and couples a corresponding RX PHY in the RX PHY of the first IC to a TX PHY in the third IC.

9. The device according to claim 8, further comprising: A fourth IC, disposed on the interposer layer, includes a seventh row of TX PHY parallel to the periphery of the fourth IC and an eighth row of RX PHY parallel to the periphery of the fourth IC, wherein the first IC, the second IC, the third IC, and the fourth IC are configured in a 2×2 configuration. The chip-to-chip connection couples the corresponding RX PHY in the RX PHY of the fourth IC to the TX PHY of the second IC, and couples the corresponding RX PHY in the RX PHY of the second IC to the TX PHY of the fourth IC. The chip-to-chip connection couples the corresponding RX PHY in the fourth IC to the TX PHY in the third IC, and couples the corresponding RX PHY in the third IC to the TX PHY in the fourth IC.

10. A method comprising: Data is transmitted from a first IC to a second IC using a chip-to-chip connection in an intermediary layer, wherein the first IC and the second IC are disposed on the intermediary layer; as well as Receive the data from the second IC. The first IC includes a first row transmit physical layer (TX PHY) parallel to the periphery of the first IC and a second row receive physical layer (RX PHY) parallel to the periphery of the first IC. The second IC includes a third row of TX PHY parallel to the periphery of the second IC and a fourth row of RX PHY parallel to the periphery of the second IC. The chip-to-chip connection couples the corresponding RX PHY in the RX PHY of the first IC to the TX PHY in the second IC, and couples the corresponding RX PHY in the RX PHY of the second IC to the TX PHY in the first IC.

11. The method according to claim 10, wherein, The chip-to-chip connections are non-crossing.

12. The method of claim 10, wherein, Each TX PHY in the first IC is aligned in the same column as an RX PHY in the second IC, and each TX PHY in the first IC is aligned in the same column as an RX PHY in the first IC.

13. The method according to claim 10, wherein, The first IC has a circuit layout that is a mirror image of the circuit layout of the second IC, and wherein the first IC and the second IC do not perform bit reordering on the bits received by the chip-to-chip connection.

14. The method according to claim 10, further comprising: The data received by the second IC is bit reordered, wherein the first IC has the same circuit layout as the second IC, and wherein the circuit layout of the first IC is rotated 180 degrees relative to the circuit layout of the second IC.

15. The method according to claim 10, further comprising: Data is transmitted from the first IC to a third IC disposed on the interposer layer, wherein the third IC includes a fifth row of TX PHYs parallel to the periphery of the third IC and a sixth row of RX PHYs parallel to the periphery of the third IC, wherein the chip-to-chip connection couples the corresponding RX PHYs in the third IC to the TX PHYs in the first IC, and couples the corresponding RX PHYs in the first IC to the TX PHYs in the third IC.

16. An apparatus, said apparatus comprising: Intermediate layer; and A first FPGA is disposed on the interposer layer and includes a first circuit design; and A second FPGA is disposed on the interposer layer, the interposer layer providing a connection between the first FPGA and the second FPGA, the second FPGA including a second circuit design, the second circuit design being (a) a mirror image of the first circuit design or (b) rotated relative to the first FPGA.

Images