Monolithic integrated bulk acoustic wave (BAW) resonator

Abstract

Techniques are disclosed for an integrated circuit (IC) that includes one or more transistors on a substrate and an interconnect structure on the one or more transistors. The interconnect structure includes a semiconductor structure embedded in the interconnect structure. In one aspect, a semiconductor structure includes a cavity structure, a piezoelectric layer over the cavity structure, an upper conductive structure on the piezoelectric layer, and a first contact structure on the upper conductive structure. In one aspect, a cavity structure includes a bottom portion that is a portion of a first etch stop layer over a substrate; a top portion that is part of the second etch stop layer over the first etch stop layer; the one or more side walls are connected with the bottom and the top of the cavity structure; and a cavity between the top and bottom of the cavity structure and surrounded by one or more sidewalls.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor structures, and more specifically, to semiconductor structures including monolithic integrated acoustic wave (BAW) resonators. Background Technology

[0002] Integrated circuits (ICs) are becoming increasingly prevalent in electronic devices. An IC can be implemented as a bare IC die (or IC chip, or simply a die or chip) on which a set of electronic circuits is integrated. In some applications, ICs can be configured to form filters or oscillators based on resonators to enable IC operation.

[0003] Figure 1A is a simplified circuit diagram illustrating an oscillator 100 according to the related art of this disclosure. The oscillator 100 includes an input terminal 102, an output terminal 104, an amplifier 110, and a resonator 120. The amplifier 110 has a transconductance gm. The input of the amplifier 110 is coupled to the input terminal 102, and the output of the amplifier 110 is coupled to the output terminal 104. The resonator 120 has a resonant frequency fr and is coupled between the input terminal 102 and the output terminal 104. The amplifier 110 and the resonator 120 can form a positive feedback configuration.

[0004] Figure 1B is a simplified diagram 150 illustrating the spectrum of the signal at the output terminal 104 of the oscillator 100 depicted in Figure 1A according to the relevant art of this disclosure. The horizontal axis of Figure 150 represents frequency, and the vertical axis of Figure 150 represents signal strength in decibels per milliwatt (dBm). As shown in Figure 1B, most frequency components of the signal at the output terminal 104 can be located at the resonant frequency fr of the resonator 120. The efficiency of the oscillator 100 outputting a signal at frequency fr can be measured by the quality factor (Q factor). Generally, the higher the Q factor, the greater the energy of the frequency components at frequency fr in the signal at the output terminal 104. However, the Q factor of the oscillator (or filter) can depend not only on the Q factor of the resonator but also on the degradation caused by parasitic effects (e.g., parasitic resistance, parasitic inductance, and / or parasitic capacitance) of the various passive components used to form the oscillator or filter and the conductive paths connecting the resonator to other parts of the oscillator or filter.

[0005] Therefore, there is a need for an improved resonator and an improved manufacturing method for forming the resonator, which can reduce the degradation of the Q factor of the resulting oscillator or filter. Summary of the Invention

[0006] The following is a simplified overview relating to one or more aspects disclosed herein. Therefore, this overview should not be considered an exhaustive overview relating to all aspects of the conception, nor should it be considered to identify key or decisive elements relating to all aspects of the conception or to depict the scope associated with any particular aspect. Thus, the sole purpose of the following overview is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed descriptions presented below.

[0007] In one aspect, an integrated circuit (IC) includes: one or more transistors on a substrate; and an interconnect structure on the one or more transistors, the interconnect structure including a plurality of interconnect layers, a plurality of interlayer dielectric layers, and a semiconductor structure embedded in the interconnect structure, wherein the semiconductor structure includes: a cavity structure including: a bottom part of a first etch stop layer; a top part of a second etch stop layer above the first etch stop layer; one or more sidewalls connecting the bottom and top of the cavity structure; and a cavity between the top and bottom of the cavity structure and surrounded by the one or more sidewalls; a piezoelectric layer above the cavity structure; an upper conductive structure on the piezoelectric layer; and a first contact structure on the upper conductive structure.

[0008] In one aspect, a method of manufacturing an integrated circuit (IC) includes: forming one or more transistors on a substrate; and forming an interconnect structure on the one or more transistors, the interconnect structure including a plurality of interconnect layers, a plurality of interlayer dielectric layers, and a semiconductor structure embedded in the interconnect structure, the forming of the interconnect structure including: forming a piezoelectric layer over a first etch stop layer and a second etch stop layer, the first etch stop layer being over the substrate and the second etch stop layer being over the first etch stop layer; forming an upper conductive structure on the piezoelectric layer; forming a cavity structure after forming the upper conductive structure, the cavity structure including: a bottom part of the first etch stop layer; a top part of the second etch stop layer; one or more sidewalls connecting the bottom and top of the cavity structure; and a cavity between the top and bottom of the cavity structure and surrounded by the one or more sidewalls; and forming a first contact structure on the upper conductive structure.

[0009] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0010] The accompanying drawings are provided to help describe various aspects of this disclosure, and are provided for illustrative purposes only and not to limit the aspects.

[0011] Figure 1A is a simplified circuit diagram illustrating an oscillator according to the relevant technology of this disclosure.

[0012] Figure 1B is a simplified diagram illustrating the spectrum of the signal at the output terminal of the oscillator depicted in Figure 1A according to the relevant technology of this disclosure.

[0013] Figures 2A to 2B Example circuit modules according to various aspects of this disclosure are illustrated.

[0014] Figure 3 This is a cross-sectional view of a portion of an IC chip according to various aspects of this disclosure.

[0015] Figures 4A to 4D This is a cross-sectional view of an example component of an IC chip according to various aspects of this disclosure.

[0016] Figures 5A to 5D This is a top view illustrating an example layout of the cavity, lower conductive structure, piezoelectric layer, and upper conductive structure of a resonator according to various aspects of this disclosure.

[0017] Figure 6A This is a cross-sectional view of a semiconductor structure according to various aspects of this disclosure, showing an example BAW resonator of an IC chip.

[0018] Figures 6B to 6C This is a top view illustrating an exemplary layout of the cavity, piezoelectric layer, and upper conductive structure of a resonator according to various aspects of this disclosure.

[0019] Figure 7A This is an example based on various aspects of this disclosure. Figure 5C and Figure 6C A graph showing the relationship between the resonant frequency of an example resonator and the finger spacing.

[0020] picture 7B This is an example based on various aspects of this disclosure. Figure 5C and Figure 6C A graph showing the frequency response of an example resonator with a specific layout.

[0021] Figure 8A This is a cross-sectional view of a semiconductor structure according to various aspects of this disclosure, which shows an example resonator of an IC chip.

[0022] Figures 8B to 8D This is a top view illustrating an exemplary layout of the cavity, piezoelectric layer, and upper conductive structure of a resonator according to various aspects of this disclosure.

[0023] Figure 8E This is an example based on various aspects of this disclosure. Figure 8C and Figure 8D A graph showing the frequency response of an example resonator with a specific layout.

[0024] Figures 9A to 9K Example partial methods for manufacturing semiconductor structures according to various aspects of this disclosure are illustrated.

[0025] Figures 9L to 9M Together Figures 9A to 9I Example partial methods for manufacturing semiconductor structures according to various aspects of this disclosure are illustrated.

[0026] Figure 10 Methods for manufacturing ICs including semiconductor structures according to various aspects of this disclosure are illustrated.

[0027] Figure 11 Examples of mobile devices according to various aspects of this disclosure are illustrated.

[0028] Figure 12 Various electronic devices that can be integrated with ICs according to various aspects of this disclosure are illustrated. Detailed Implementation

[0029] Various aspects of this disclosure are provided below in the description and accompanying drawings of various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of this disclosure. Additionally, well-known elements of this disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of this disclosure.

[0030] The terms “exemplary” and / or “example” are used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” and / or “example” is not necessarily to be construed as superior to or better than other aspects. Similarly, the term “aspects of this disclosure” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed.

[0031] Those skilled in the art will understand that any of a variety of different techniques and methods can be used to represent the information and signals described below. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the following description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof, depending in part on the specific application, in part on the desired design, in part on the corresponding technology, and so on.

[0032] Furthermore, many aspects are described according to a sequence of actions to be performed by elements of, for example, a computing device. It will be appreciated that the various actions described herein can be performed by a specific circuit (e.g., an application-specific integrated circuit (ASIC)), by program instructions executed by one or more processors, or by a combination of both. Additionally, the sequence of actions described herein can be considered to be entirely embodied in any form of non-transitory computer-readable storage medium storing a corresponding set of computer instructions that, when executed, will cause or command the associated processor of the device to perform the functionality described herein. Therefore, various aspects of this disclosure can be embodied in a variety of different forms, all of which are contemplated within the scope of the claimed subject matter. Furthermore, for each aspect described herein, any corresponding form of any such aspect can be described herein as, for example, "logic configured to perform the described actions."

[0033] In some configurations, an oscillator or filter may be used for the operation of the IC. In some configurations, the resonator used for the oscillator may be a crystal-based resonator (e.g., a quartz crystal resonator) or a microelectromechanical system (MEMS)-based resonator (e.g., a surface acoustic wave (SAW) resonator or a bulk acoustic wave (BAW) resonator).

[0034] In some configurations, crystal-based resonators may be expandable and may require extremely precise crystal dimensions. In other configurations, crystal-based resonators may be very susceptible to mechanical shock and therefore may not be suitable for many applications.

[0035] In some configurations, while many IC chips can be fabricated using complementary metal-oxide-semiconductor (CMOS)-based processes, most MEMS-based resonators can be fabricated using processes that are not fully compatible with CMOS-based processes. Therefore, in many applications, MEMS components (e.g., MEMS-based resonators) are typically not located on the same IC chip as their CMOS counterparts. For example, an amplifier for an oscillator or filter can be embedded within an IC chip, but the resonator used to form the oscillator or filter can also be located externally to the IC chip.

[0036] Figure 2A Example circuit module 200A according to various aspects of this disclosure is illustrated. For example... Figure 2AAs shown, circuit module 200A may include an IC chip 210 and a resonator 220A mounted on a package substrate 230. The package substrate 230 may include embedded wires 232. The IC chip 210 may be electrically coupled to the wires 232 via bumps (not labeled), and the resonator 220A may be electrically coupled to the wires 232 via bonding leads (not labeled). In some aspects, some electrical components in the resonator 220A and the IC chip 210 may form an oscillator or filter for the operation of the IC chip 210. The bonding leads, wires 232, and bumps may effectively introduce parasitic devices 240A (e.g., parasitic inductance) between the IC chip 210 and the resonator 220A.

[0037] Figure 2B Another example circuit module 200B according to various aspects of this disclosure is illustrated. For example... Figure 2B As shown, circuit module 200B may include an IC chip 210 and a resonator 220B mounted on a package substrate 230. Package substrate 230 may include embedded wires 234. The IC chip 210 may be electrically coupled to wires 234 via a first bump (not labeled), and the resonator 220B may be electrically coupled to wires 234 via a second bump (not labeled). In some aspects, some electrical components in the resonator 220B and IC chip 210 may form an oscillator or filter for the operation of IC chip 210. The second bump, wires 234, and first bump may also effectively introduce parasitic devices 240B (e.g., parasitic inductance) between IC chip 210 and resonator 220B.

[0038] In some respects, as illustrated by example circuit modules 200A and 200B, parasitic devices 240A and 240B can cause additional losses between the resonator and the IC chip, and can lead to Q-factor degradation in the resulting oscillator or filter. This can result in a degraded performance of the resulting oscillator or filter. Furthermore, separately forming the resonator and IC chip may increase the size of the final package. This can increase manufacturing time and cost in at least aspects including, for example, chip fabrication, chip testing, package assembly, and package testing.

[0039] According to this application, the MEMS-based resonator can be a monolithically integrated BAW resonator, which is integrated into an IC chip to solve the aforementioned problems regarding resonators located outside the IC chip. In some aspects, the monolithically integrated BAW resonator can be formed based on modifying the manufacturing process of metal-insulator-metal (MIM) capacitors (or metal-oxide-metal (MOM) capacitors) in CMOS manufacturing processes.

[0040] Figure 3This is a cross-sectional view of a portion of an IC chip 300 according to various aspects of this disclosure. The IC chip 300 illustrates a simplified example of an IC chip, used to illustrate an example MIM capacitor 310, an example BAW resonator 320, and an example solid-state mounted resonator (SMR) type improved BAW resonator (also referred to herein as an "SMR-BAW resonator") 330. In some aspects, various elements of the IC chip 300 may have... Figure 3 The examples shown have different shapes and arrangements, and besides Figure 3 In addition to the examples shown, other components or configurations for IC chips can also be used.

[0041] IC chip 300 may include a substrate 302. IC chip 300 may include various components formed on substrate 302, such as features depicted as source, channel, and drain of a transistor (shaded as “S / channel / D”), gate of a transistor (shaded as “gate”), polysilicon wiring (shaded as “polysilicon wiring”), and shallow trench isolation (STI) structures (shaded as “STI”). IC chip 300 may include contact structures (shaded as “contacts”) coupled to components formed on substrate 302, such as drain, source, polysilicon wiring, and gate (not shown). An interlayer dielectric (ILD) layer 304 (shaded as “ILD”) fills the spaces between the contact structures and covers the components formed on substrate 302.

[0042] In some aspects, portions of the manufacturing process used to manufacture the portion from substrate 302 up to ILD layer 304 are collectively referred to in this disclosure as front-end process (FEOL) processes. In some aspects, portions of the manufacturing process used to manufacture the remaining portion of IC chip 300 above ILD layer 304 are collectively referred to in this disclosure as back-end process (BEOL) processes.

[0043] Above ILD layer 304, multiple etch stop layers (shaded with "etch stop") and ILD layers (shaded with "ILD" above ILD layer 304) can be formed on top of each other. Furthermore, interconnect structures can be formed by stacking multiple vias and wires (shaded with "BEOL metal / via") formed in the respective ILD layers. In some aspects, some etch stop layers can be omitted or removed during the BEOL process. Additionally, a top metal layer (shaded with "top metal") can be formed in the uppermost ILD layer. The top metal layer can be configured as a substrate for forming bump pads on which the bump structure (not shown) of the IC chip 300 can also be formed.

[0044] The IC chip 300 may include a first etch stop layer 342 and a second etch stop layer 344 within a region (or simply BEOL portion) of the IC chip 300 formed based on a BEOL process. A first ILD layer 352 is located between the first etch stop layer 342 and the second etch stop layer 344, and a second ILD layer 354 is located on the second etch stop layer 344. In some aspects, the etch stop layer may include silicon nitride (e.g., SiN). In some aspects, the ILD layer may include silicon oxide (e.g., SiO2).

[0045] In some aspects, the MIM capacitor 310 may be formed on the first ILD layer 352 and within the second ILD layer 354 on the second etch stop layer 344. In some aspects, the BAW resonator 320 may be formed based on the first etch stop layer 342, the first ILD layer 352, and the second etch stop layer 344, and partially embedded in the second ILD layer 354. In some aspects, the SMR-BAW resonator 330 may be formed based on the first etch stop layer 342, the first ILD layer 352, and the second etch stop layer 344, and partially embedded in the second ILD layer 354. (See reference...) Figures 4A to 4C Details of the MIM capacitor 310, BAW resonator 320, and SMR-BAW resonator 330 are shown.

[0046] In some respects, resonators based on BAW resonator 320 and / or SMR-BAW resonator 330 can be formed by modifying the manufacturing process used to fabricate MIM capacitor 310 (or MOM capacitor). Therefore, resonators based on BAW resonator 320 and / or SMR-BAW resonator 330 can be monolithically integrated into IC chip 300 and are compatible with CMOS manufacturing processes (e.g., as part of a BEOL process). Monolithically integrated resonators as described in this disclosure can replace relatively more expensive crystal resonators. Furthermore, by integrating the resonator into the IC chip, the resulting design can have a smaller package, such as a simplified packaging process (e.g., based on conventional CMOS packages, such as flip-chip packages, copper pillar bump (CuP) packages, or quad flat no-lead (QFN) packages, without additional bonding), fewer parasitic effects (e.g., less Q-factor degradation), and lower manufacturing costs.

[0047] Figure 4A This is a cross-sectional view of a semiconductor structure 400A according to various aspects of the present disclosure, which shows an example MIM capacitor of an IC chip, such as the MIM capacitor 310 of IC chip 300. Figure 4A Zhongyu Figure 3 Components that are identical or similar to those in the figure may be depicted using the same shading and given the same reference numerals, and therefore their detailed description may be omitted.

[0048] Semiconductor structure 400A can be Figure 3 It is a part of the IC chip 300 and may include a FEOL portion 410, which corresponds to a portion of the IC chip 300 manufactured based on the FEOL process (e.g., including a substrate 302 and various components formed thereon). Above the FEOL portion 410, there are multiple etch stop layers and ILD layers, including at least a first etch stop layer 342, a second etch stop layer 344, a first ILD layer 352, and a second ILD layer 354.

[0049] Semiconductor structure 400A includes a lower metal 422 on a first ILD layer 352, a capacitor dielectric 424 on the lower metal 422, and an upper metal 426 on the capacitor dielectric 424. Another etch stop layer 428 may cover the sides and top of the lower metal 422, capacitor dielectric 424, and upper metal 426, and may be coupled to a second etch stop layer 344. The lower metal 422, capacitor dielectric 424, and upper metal 426 may be configured as the main portion of a MIM capacitor 310.

[0050] Semiconductor structure 400A may include a first contact structure (e.g., a via) 432 that passes through the second ILD layer 354 and the etch stop layer 428 and is coupled to the upper metal 426. Semiconductor structure 400A may include a second contact structure (e.g., another via) 434 that passes through the second ILD layer 354 and the etch stop layer 428 and is coupled to the lower metal 422.

[0051] In some aspects, the lower metal 422 and the upper metal 426 may comprise copper, titanium nitride, platinum, aluminum, or any combination thereof. In some aspects, the capacitor dielectric 424 may comprise SiO2, aluminum nitride (e.g., AlN), or any combination thereof.

[0052] Figure 4B This is a cross-sectional view of a semiconductor structure 400B according to various aspects of the present disclosure, which shows an example BAW resonator of an IC chip, such as BAW resonator 320 of IC chip 300. Figure 4B Zhongyu Figure 3 Components that are identical or similar to those in the figure may be depicted using the same shading and given the same reference numerals, and therefore their detailed description may be omitted.

[0053] Semiconductor structure 400B can be Figure 3 It is part of the IC chip 300 and may include, as referenced Figure 4AThe illustrated FEOL portion 410. Above the FEOL portion 410, there are multiple etch stop layers and ILD layers, including at least a first etch stop layer 342, a second etch stop layer 344, a first ILD layer 352, and a second ILD layer 354.

[0054] Semiconductor structure 400B includes a cavity structure 440, a lower conductive structure 452 above the cavity structure 440, a piezoelectric layer 454 on the lower conductive structure 452 and above the cavity structure 440, and an upper conductive structure 456 on the piezoelectric layer 454. Another etch stop layer 458 may cover the sides and top of the lower conductive structure 452, the piezoelectric layer 454, and the upper conductive structure 456, and may be coupled to a second etch stop layer 344. The cavity structure 440, the lower conductive structure 452, the piezoelectric layer 454, and the upper conductive structure 456 may be configured as the main part of a BAW resonator 320.

[0055] In some aspects, the lower conductive structure 452 and the upper conductive structure 456 may comprise copper, titanium nitride, platinum, aluminum, or any combination thereof. In some aspects, the piezoelectric layer 454 may comprise aluminum nitride (e.g., AlN), scandium aluminum nitride (e.g., AlScN), or any combination thereof. In some aspects, depending on the design of the resonator, the lower conductive structure 452 and / or the upper conductive structure 456 may be patterned to achieve a desired resonant frequency and / or Q factor.

[0056] Furthermore, the cavity structure 440 may include a bottom 442 as part of a first etch stop layer 342, a top 444 as part of a second etch stop layer 344 above the first etch stop layer 342, and one or more sidewalls 446 connecting the bottom 442 and the top 444 of the cavity structure 440. The cavity structure 440 may include a cavity 448 between the top 444 and the bottom 442 and surrounded by one or more sidewalls 446. In some aspects, the cavity 448 may be filled with air. In some aspects, the top 444, bottom 442, and one or more sidewalls 446 of the cavity structure 440 may include silicon nitride (e.g., SiN). In some aspects, since SiN has a temperature coefficient of frequency (TCF) of 3.27 ppm / °C, the top 444 of the cavity structure 440 may be configured as a TCF compensation structure for the BAW resonator 320 to compensate for the TCF (typically negative) of the piezoelectric layer 454.

[0057] Semiconductor structure 400B may include a first contact structure (e.g., a via) 462 that passes through the second ILD layer 354 and the etch stop layer 458 and is coupled to the upper conductive structure 456. Semiconductor structure 400B may include a second contact structure (e.g., another via) 464 that passes through the second ILD layer 354 and the etch stop layer 458 and is coupled to the lower conductive structure 452.

[0058] In some respects, depending on the design of the resonator, the lower conductive structure 452 may be omitted. In some respects, due to the omission of the lower conductive structure 452, the second contact structure (e.g., another via) 464 may be coupled to the piezoelectric layer 454, the upper conductive structure 456, or may not be electrically coupled to the piezoelectric layer 454 or the upper conductive structure 456.

[0059] Figure 4C This is a cross-sectional view of a semiconductor structure 400C according to various aspects of the present disclosure, which shows an example SMR-BAW resonator of an IC chip, such as the SMR-BAW resonator 330 of IC chip 300. Figure 4C Zhongyu Figure 4B Components that are identical or similar to those in the figure may be depicted using the same shading and given the same reference numerals, and therefore their detailed description may be omitted.

[0060] Semiconductor structure 400C can be Figure 3 It is part of the IC chip 300 and may include, as referenced Figure 4A The illustrated FEOL portion 410. Above the FEOL portion 410, there are multiple etch stop layers and ILD layers, including a first etch stop layer 342, a second etch stop layer 344, a first ILD layer 352, and a second ILD layer 354.

[0061] Compared to semiconductor structure 400B, semiconductor structure 400C also includes an acoustic reflection structure 470 above the upper conductive structure 456. In some aspects, the acoustic reflection structure 470 may include a refractory material layer, and the refractory material may include tungsten, titanium, tantalum oxide, or any combination thereof. In some aspects, the acoustic reflection structure 470 may be a Bragg reflector.

[0062] Figure 4D This is a cross-sectional view of a semiconductor structure 400D according to various aspects of this disclosure, which shows an example BAW resonator of an IC chip. Figure 4D Zhongyu Figure 4B Components that are identical or similar to those in the figure may be depicted using the same shading and given the same reference numerals, and therefore their detailed description may be omitted.

[0063] Compared to semiconductor structure 400B, the cavity structure 440 of semiconductor structure 400D further includes an intermediate etch stop layer 443 and a dielectric layer 447 between the top 444 of the cavity structure 440 and the intermediate etch stop layer 443. The cavity is located between the intermediate etch stop layer 443 and the bottom 442 of the cavity structure 440. In some aspects, the combination of the top 444 of the cavity structure 440, the intermediate etch stop layer 443, and the dielectric layer 447 disposed therebetween can be configured as a TCF compensation structure for a BAW resonator. In some aspects, the intermediate etch stop layer 443 may comprise silicon nitride (e.g., SiN). In some aspects, the dielectric layer 447 may comprise silicon oxide (e.g., SiO2).

[0064] Figure 5A This is a top view of an exemplary layout 500A illustrating the cavity structure 508, lower conductive structure 512, piezoelectric layer 514, and upper conductive structure 516 of a resonator according to various aspects of this disclosure. In some aspects, based on Figure 5A The resonator can correspond to the one based on Figure 4B The resonator of semiconductor structure 400B; cavity 508 can correspond to cavity 448; lower conductive structure 512 can correspond to lower conductive structure 452; piezoelectric layer 514 can correspond to piezoelectric layer 454; and upper conductive structure 516 can correspond to upper conductive structure 456.

[0065] In this example, the lower conductive structure 512 may include a lower patterned portion aligned above the cavity 508 and a lower anchoring portion 512A coupled to the lower patterned portion. The upper conductive structure 516 may include an upper patterned portion aligned above the cavity 508 and overlapping the lower patterned portion of the lower conductive structure 512. The upper conductive structure 516 may also include an upper anchoring portion 516A coupled to the upper patterned portion. In some aspects, the lower patterned portion of the lower conductive structure 512 may have a lower patch pattern (e.g., a rectangular patch), and the upper patterned portion of the upper conductive structure 516 may have an upper patch pattern (e.g., a rectangular patch). In some aspects, Figure 4B The first contact structure 462 can be coupled to the upper anchoring portion 516A, and Figure 4B The second contact structure 464 can be coupled to the lower anchoring portion 512A.

[0066] Figure 5B This is a top view of another example layout 500B illustrating the cavity structure 508, lower conductive structure 522, piezoelectric layer 524, and upper conductive structure 526 of a resonator according to various aspects of this disclosure. In some aspects, based on Figure 5B The resonator can correspond to the one based on Figure 4BThe resonator of semiconductor structure 400B; cavity 508 can correspond to cavity 448; lower conductive structure 522 can correspond to lower conductive structure 452; piezoelectric layer 524 can correspond to piezoelectric layer 454; and upper conductive structure 526 can correspond to upper conductive structure 456.

[0067] In this example, the lower conductive structure 522 may include a lower finger-like portion aligned above the cavity 508 and a lower anchoring portion 522A coupled to the lower finger-like portion. The upper conductive structure 526 may include an upper finger-like portion aligned above the cavity 508 without overlapping the lower finger-like portion of the lower conductive structure 522. The upper conductive structure 526 may also include an upper anchoring portion 526A coupled to the upper finger-like portion. In some aspects, Figure 4B The first contact structure 462 can be coupled to the upper anchoring portion 526A, and Figure 4B The second contact structure 464 can be coupled to the lower anchoring portion 522A.

[0068] Figure 5C This is a top view of an exemplary layout 500C illustrating the cavity structure 508, lower conductive structure 532, piezoelectric layer 534, and upper conductive structure 536 of a resonator according to various aspects of this disclosure. In some aspects, based on Figure 5C The resonator can correspond to the one based on Figure 4B The resonator of semiconductor structure 400B; cavity 508 can correspond to cavity 448; lower conductive structure 532 can correspond to lower conductive structure 452; piezoelectric layer 534 can correspond to piezoelectric layer 454; and upper conductive structure 536 can correspond to upper conductive structure 456.

[0069] In this example, the lower conductive structure 532 may include a lower patterned portion aligned above the cavity 508 and a lower anchoring portion 532A coupled to the lower patterned portion. The upper conductive structure 536 may include an upper patterned portion aligned above the cavity 508 and at least partially overlapping the lower patterned portion of the lower conductive structure 532. The upper conductive structure 536 may also include an upper anchoring portion 536A coupled to the upper patterned portion. In some aspects, the lower patterned portion of the lower conductive structure 532 may have a lower finger-like pattern, and the upper patterned portion of the upper conductive structure 536 may have an upper finger-like pattern. In some aspects, Figure 4B The first contact structure 462 can be coupled to the upper anchoring portion 536A, and Figure 4B The second contact structure 464 can be coupled to the lower anchoring portion 532A.

[0070] Figure 5D This is a top view of an exemplary layout 500D illustrating the cavity structure 508, lower conductive structure 542, piezoelectric layer 544, and upper conductive structure 546 of a resonator according to various aspects of this disclosure. In some aspects, based on Figure 5D The resonator can correspond to the one based on Figure 4B The resonator of semiconductor structure 400B; cavity 508 can correspond to cavity 448; lower conductive structure 542 can correspond to lower conductive structure 452; piezoelectric layer 544 can correspond to piezoelectric layer 454; and upper conductive structure 546 can correspond to upper conductive structure 456.

[0071] In this example, the lower conductive structure 542 may include a lower patterned portion aligned above the cavity 508 and a lower anchoring portion 532A coupled to the lower patterned portion. The upper conductive structure 546 may include an upper patterned portion aligned above the cavity 508 and at least partially overlapping the lower patterned portion of the lower conductive structure 542. The upper conductive structure 546 may also include an upper anchoring portion 546A coupled to the upper patterned portion. In some aspects, the lower patterned portion of the lower conductive structure 542 may have a lower patch pattern (e.g., a rectangular patch), and the upper patterned portion of the upper conductive structure 546 may have an upper finger pattern. In some aspects, Figure 4B The first contact structure 462 can be coupled to the upper anchoring portion 546A, and Figure 4B The second contact structure 464 can be coupled to the lower anchoring portion 542A.

[0072] Furthermore, the resonant behavior of the resulting resonator can be tuned by changing its size and material. For example, refer to... Figure 5C and Figure 5D The resonant behavior of the resonator based on example layout 500C or example layout 500D can be tuned based on the finger spacing (labeled "Wp") of the upper conductive structure 536 or 546, the thickness of the piezoelectric layer 534 or 544, the thickness of the upper conductive structure 536 or 546, the thickness of the lower conductive structure 532 or 542, or any combination thereof.

[0073] Figure 6A This is a cross-sectional view of a semiconductor structure 600A according to various aspects of this disclosure, which shows an example BAW resonator of an IC chip. Figure 6A The BAW resonator in the middle can be based on Figure 4B A variation of the BAW resonator in [the text]. Figure 6A Zhongyu Figure 4B Components that are identical or similar to those in the figure may be depicted using the same shading and given the same reference numerals, and therefore their detailed description may be omitted.

[0074] Compared to semiconductor structure 400B, semiconductor structure 600A does not include lower conductive structure 452. Therefore, piezoelectric layer 454 is on top 444 of cavity structure 440.

[0075] Figure 6BThis is a top view illustrating an example layout 600B of the cavity 608, piezoelectric layer 614, and upper conductive structure 616 of a resonator according to various aspects of this disclosure. In some aspects, based on Figure 6B The resonator can correspond to the one based on Figure 6A The resonator of semiconductor structure 600A; cavity 608 can correspond to cavity 448; piezoelectric layer 614 can correspond to piezoelectric layer 454; and upper conductive structure 616 can correspond to upper conductive structure 456.

[0076] In this example, the upper conductive structure 616 may include an upper patterned portion aligned above the cavity 608 and an upper anchoring portion 616A coupled to the upper patterned portion. In some aspects, the upper patterned portion of the upper conductive structure 626 may have an upper patch pattern (e.g., a rectangular patch). In some aspects, Figure 6A The first contact structure 462 can be coupled to the upper anchoring portion 616A. In some respects, Figure 6A The second contact structure 464 can be coupled to the piezoelectric layer 614.

[0077] Figure 6C This is a top view of an exemplary layout 600C illustrating the cavity structure 608, piezoelectric layer 624, and upper conductive structure 626 of a resonator according to various aspects of this disclosure. In some aspects, based on Figure 6C The resonator can correspond to the one based on Figure 6A The resonator of semiconductor structure 600A; cavity 608 can correspond to cavity 448; piezoelectric layer 624 can correspond to piezoelectric layer 454; and upper conductive structure 626 can correspond to upper conductive structure 456.

[0078] In this example, the upper conductive structure 626 may include an upper patterned portion aligned above the cavity 608 and an upper anchoring portion 626A coupled to the upper patterned portion. In some aspects, the upper patterned portion of the upper conductive structure 626 may have an upper finger-like pattern. In some aspects, Figure 6A The first contact structure 462 can be coupled to the upper anchoring portion 626A. In some respects, Figure 6A The second contact structure 464 can be coupled to the piezoelectric layer 624.

[0079] Furthermore, the resonant behavior of the resulting resonator can be tuned by changing its size and material. For example, refer to... Figure 6C The resonant behavior of the resonator based on example layout 600C can be tuned based on the finger spacing (labeled "Wp") of the upper conductive structure 626, the thickness of the piezoelectric layer 624, the thickness of the upper conductive structure 626, or any combination thereof.

[0080] Figure 7AThis is an example based on various aspects of this disclosure. Figure 5C The layout of 500C and Figure 6C Figure 710 shows the relationship between the resonant frequency and the finger spacing of the example resonator of layout 600C. The horizontal axis represents the finger spacing Wp in micrometers (μm), and the vertical axis represents the resonant frequency in megahertz (MHz). The thickness of the piezoelectric layer 534 or 624 is set to 2 μm.

[0081] like Figure 7A As shown, curve 722 corresponds to the curve based on... Figure 5C The resonator, wherein the lower conductive structure 532 and the upper conductive structure 536 have thinner thicknesses. Curve 724 corresponds to the resonator based on... Figure 5C The resonator, wherein the lower conductive structure 532 and the upper conductive structure 536 have a greater thickness. Curve 726 corresponds to the resonator based on... Figure 6C The resonator.

[0082] Figure 7B This is an example based on various aspects of this disclosure. Figure 5C The layout of 500C and Figure 6C Figure 760 shows the frequency response of an example resonator with layout 600C. The horizontal axis represents frequency in megahertz (MHz), and the vertical axis represents the transconductance (Y21) of the resulting resonator in dBm. Additionally, the finger spacing Wp can be set to 50 μm.

[0083] like Figure 7B As shown, curve 772 corresponds to the curve based on... Figure 5C The resonator, wherein the lower conductive structure 532 and the upper conductive structure 536 have thinner thicknesses. Curve 774 corresponds to the resonator based on... Figure 5C The resonator, wherein the lower conductive structure 532 and the upper conductive structure 536 have greater thicknesses. Curve 776 corresponds to the resonator based on... Figure 6C The resonator.

[0084] Therefore, the resonant frequency and frequency response of the resonator illustrated in this disclosure can be determined based on the presence or absence of the lower conductive structure, the shape of the pattern of the upper or lower conductive structure, the thickness of the conductive structure, the thickness of the piezoelectric layer, the material of the piezoelectric layer, the finger spacing of the conductive structure, or any combination thereof.

[0085] Figure 8A This is a cross-sectional view of a semiconductor structure 800A according to various aspects of this disclosure, which shows an example resonator of an IC chip. Figure 8A The resonator in the middle can have based on Figure 4B A variant configuration of the BAW resonator in the diagram. Figure 8A Zhongyu Figure 4BComponents that are identical or similar to those in the figure may be depicted using the same shading and given the same reference numerals, and therefore their detailed description may be omitted.

[0086] Compared to semiconductor structure 400B, semiconductor structure 800A does not include lower conductive structure 452. Therefore, piezoelectric layer 454 is on top 444 of cavity structure 440. Furthermore, upper conductive structure 456 can be patterned to include different portions coupled to first contact structure 462 and second contact structure 464 (and possibly one or more other contact structures), respectively.

[0087] Figure 8B This is a top view illustrating an example layout 800B of a resonator cavity structure according to various aspects of this disclosure, including a cavity 808, a piezoelectric layer 814, and an upper conductive structure (e.g., a combination of two portions 816 and 826). In some aspects, based on Figure 8B The resonator can correspond to the one based on Figure 8A The resonator of semiconductor structure 800A; cavity 808 can correspond to cavity 448; piezoelectric layer 814 can correspond to piezoelectric layer 454; and the combination of two parts 816 and 826 can correspond to upper conductive structure 456.

[0088] In this example, the upper conductive structure may include: a first portion 816 having a first upper patterned portion aligned above the cavity 808 and a first upper anchoring portion 816A coupled to the first upper patterned portion; and a second portion 826 having a second upper patterned portion aligned above the cavity 808 and a second upper anchoring portion 826A coupled to the second upper patterned portion. In some aspects, the first upper patterned portion and the second upper patterned portion are arranged so as not to overlap each other. In some aspects, Figure 8A The first contact structure 462 can be coupled to the first upper anchoring portion 816A. In some aspects, Figure 8A The second contact structure 464 can be coupled to the second upper anchoring portion 826A.

[0089] Similar to a reference Figures 5A to 6C The illustrated resonator design is based on Figure 8B The resonant behavior of the obtained resonator can be tuned by changing the size and material of the resonator, such as the shape of the pattern of the conductive structure, the thickness of the conductive structure, the thickness of the piezoelectric structure, the material of the piezoelectric layer, the spacing of the fingers of the conductive structure, or any combination thereof.

[0090] Figure 8CThis is a top view illustrating an example layout 800C of a cavity 808, a piezoelectric layer 814, and an upper conductive structure (e.g., a combination of multiple portions 832, 834, 835, 836, and 837) of a resonator according to various aspects of this disclosure. In some aspects, based on a lame-mode resonator design, based on Figure 8C The resonator can correspond to the one based on Figure 8A The resonator is a semiconductor structure 800A. In some aspects, cavity 808 may correspond to cavity 448; piezoelectric layer 814 may correspond to piezoelectric layer 454; and upper conductive structure (including portions 832, 834, 835, 836 and 837) may correspond to upper conductive structure 456.

[0091] In this example, the upper conductive structure may include a portion 832 arranged to align a vibration pattern above the cavity and above the piezoelectric layer 814. In some aspects, the vibration pattern may include a plurality of mechanical tethers 833. In some aspects, the vibration pattern may include a window 842 formed therein. The upper conductive structure may also include portions 834, 835, 836, and 837 configured as a plurality of input / output terminals capacitively coupled to the vibration pattern. For example, 834 may be configured as a non-inverting input terminal; portion 835 may be configured as an inverting input terminal; portion 836 may be configured as a non-inverting output terminal; and portion 837 may be configured as an inverting output terminal.

[0092] Figure 8D This is a top view illustrating an exemplary layout 800D of the cavity 808, piezoelectric layer 814, and upper conductive structure (e.g., a combination of multiple portions 832, 834, 835, 836, and 837) of a resonator according to various aspects of this disclosure. In some aspects, Figure 8D The resonator in the design can be based on the Lame mode resonator, and can be based on... Figure 8C A variation of the resonator. Compared to example layout 800C, the vibration pattern of portion 832 in example layout 800D may include a window 842 formed therein, and the window 844 may have a shape different from that of window 842. In some aspects, based on Figure 8C and Figure 8D The resonant behavior of the obtained resonator may differ due to the different shapes of windows 842 and 844 in the vibration pattern.

[0093] Figure 8E This is an example based on various aspects of this disclosure. Figure 8C The layout of 800C and Figure 8DFigure 860 shows the frequency response of an example resonator with layout 800D. The horizontal axis represents frequency in megahertz (MHz), and the vertical axis represents the transconductance (Y21) of the resulting resonator in dBm.

[0094] like Figure 8E As shown, curve 872 corresponds to the curve based on... Figure 8C The resonator, and curve 874 corresponds to the resonator based on Figure 8D The resonator. Therefore, the resonant frequency and frequency response of the resonator illustrated in this disclosure can also be determined based on the shape of the pattern of the conductive structure (such as the presence and shape of the window formed therein).

[0095] Figures 9A to 9K Examples of methods for manufacturing semiconductor structures (such as...) according to various aspects of this disclosure are illustrated. Figure 4B The example part of the method is a semiconductor structure 400B. An IC (e.g., IC chip 300) may include one or more transistors on a substrate and interconnect structures on the one or more transistors. In some aspects, the interconnect structure may include multiple interconnect layers, multiple interlayer dielectric layers, and a semiconductor structure (such as semiconductor structure 400B or semiconductor structure 900K) embedded in the interconnect structure.

[0096] like Figure 9A As shown, a semiconductor structure 900A is formed. The semiconductor structure 900A includes a FEOL portion 910, which corresponds to a portion of an IC chip manufactured based on the FEOL process. In some aspects, the FEOL portion 910 may include a substrate and one or more electrical components formed on the substrate. Above the FEOL portion 910, there are multilayer etch stop layers and ILD layers formed based on at least a portion of the BEOL process. The portion of the semiconductor structure 900A above the FEOL portion 910 may include at least a first etch stop layer 922, a second etch stop layer 924, one or more other etch stop layers 926, a first ILD layer 352, and a second ILD layer 928. Furthermore, interconnect structures 929 may be formed by stacking multiple vias and wires in the respective ILD layer formations. In some aspects, the etch stop layer may include silicon nitride (e.g., SiN). In some aspects, the ILD layer may include silicon oxide (e.g., SiO2).

[0097] like Figure 9B As shown, a semiconductor structure 900B is formed based on a semiconductor structure 900A by forming a lower conductive structure 952 on the second etch stop layer 924. In some aspects, the lower conductive structure 952 may include copper, titanium nitride, platinum, aluminum, or any combination thereof. In some aspects, forming the lower conductive structure 952 may include depositing a conductive material layer on the second etch stop layer 924 and then patterning the conductive material layer.

[0098] like Figure 9C As shown, a semiconductor structure 900C is formed based on a semiconductor structure 900B by forming a piezoelectric layer 954 on the lower conductive structure 952. In some aspects, the piezoelectric layer 954 may comprise aluminum nitride (e.g., AlN), scandium aluminum nitride (e.g., AlScN), or any combination thereof. In some aspects, forming the piezoelectric layer 954 may include depositing a piezoelectric material layer on the lower conductive structure 952 and then patterning the conductive material layer.

[0099] In some respects, when the lower conductive structure 952 is omitted, the corresponding [structure / component] can be omitted. Figure 9B The process involves forming a piezoelectric layer 954 on the second etch stop layer 924.

[0100] like Figure 9D As shown, a semiconductor structure 900D is formed based on a semiconductor structure 900C by forming an upper conductive structure 956 on a piezoelectric layer 954. In some aspects, the upper conductive structure 956 may include copper, titanium nitride, platinum, aluminum, or any combination thereof. In some aspects, forming the upper conductive structure 956 may include depositing a conductive material layer on the piezoelectric layer 954 and then patterning the conductive material layer.

[0101] In some respects, corresponding to Figures 9B to 9D The operation can be at least partially based on the manufacturing process used to produce MIM capacitors or MOM capacitors. In some respects, corresponding to Figures 9B to 9D The operation can be based on a manufacturing process similar to that used for manufacturing MIM capacitors or MOM capacitors. In some aspects, corresponding to Figures 9B to 9D The operation can occur after the MIM capacitor or MOM capacitor (if any) is formed on the second ILD layer 928, and the MIM capacitor or MOM capacitor can be corresponding to Figures 9B to 9D The operation is preceded by an etch-stop material (e.g., SiN) layer.

[0102] like Figure 9E As shown, a semiconductor structure 900E is formed based on a semiconductor structure 900D by forming one or more openings 932 that pass at least through the second etch stop layer 924 and the second ILD layer 928 while maintaining the stack integrity of the lower conductive structure 952, the piezoelectric layer 954, and the upper conductive structure 956. In some aspects, the one or more openings 932 may be formed based on an anisotropic etching process or an isotropic etching process.

[0103] In some respects, one or more openings 932 may define a portion of the first etch stop layer 922 within the area exposed by the one or more openings 932 as a cavity structure to be formed (e.g., Figure 9IThe bottom 942 of the cavity structure 940 in the middle; and the portion of the second etch stop layer 924 surrounded by one or more openings 932 is defined as the top 944 of the cavity structure to be formed.

[0104] like Figure 9F As shown, a semiconductor structure 900F is formed based on a semiconductor structure 900E by performing etch-stop material (e.g., SiN) deposition to fill one or more openings 932. The etch-stop material deposition also forms an etch-stop layer (not labeled) covering the top portion of the interconnect structure 929 and an etch-stop layer 958 covering the sides and top of the lower conductive structure 952, the piezoelectric layer 954, and the upper conductive structure 956.

[0105] In some aspects, the etch-stop material deposition at least partially fills one or more openings 932 and transforms them into one or more sidewalls 946 of the cavity structure to be formed. The one or more sidewalls 946 may connect the bottom 942 and the top 944 of the cavity structure to be formed.

[0106] like Figure 9G As shown, a semiconductor structure 900G is formed based on a semiconductor structure 900F by forming one or more openings 934 that at least penetrate through a second etch stop layer 924. In some aspects, the one or more openings 934 are within an internal region defined by one or more sidewalls 946. In some aspects, the formation of the one or more openings 934 may be based on an anisotropic etching process.

[0107] like Figure 9H As shown, a semiconductor structure 900H is formed based on a semiconductor structure 900F by performing an etching process based on moving an etchant through one or more openings 934 to remove a portion of the second ILD layer 928 within the region defined by a bottom 942, a top 944, and one or more sidewalls 946. In some aspects, the etchant may include dilute hydrogen fluoride (HF). In some aspects, the etching process may be an isotropic etching process. In some aspects, due to the removal of a portion of the second ILD layer 928, a cavity 948 of the cavity structure to be formed is created. In some aspects, the cavity 948 may be filled with air.

[0108] like Figure 9I As shown, a semiconductor structure 900I is formed based on a semiconductor structure 900H by performing etch-stop material (e.g., SiN) deposition to seal one or more openings 934. After sealing one or more openings 934, a cavity structure 940 is completed.

[0109] like Figure 9JAs shown, a semiconductor structure 900J is formed based on the semiconductor structure 900I by forming one or more ILD layers and / or one or more etch stop layers above the semiconductor structure 900I, and by forming one or more openings 936 through the one or more ILD layers and / or one or more etch stop layers above the semiconductor structure 900I. Based on the resonator design, the one or more openings can expose the interconnect structure 929 as well as the lower conductive structure 952, the piezoelectric layer 954 and / or the upper conductive structure 956.

[0110] like Figure 9K As shown, a semiconductor structure 900K is formed based on a semiconductor structure 900J by filling one or more openings 936 with one or more conductive materials to form contact structures 962, 964, and 966. In some aspects, the one or more conductive materials may include copper, aluminum, or any combination thereof.

[0111] In this example, the semiconductor structure 900K can correspond to Figure 4B The semiconductor structure 400B is shown. For example, the cavity structure 940, the lower conductive structure 952, the piezoelectric layer 954, the upper conductive structure 956, the contact structure 962, and the contact structure 964 can respectively correspond to Figure 4B The cavity structure 440, the lower conductive structure 452, the piezoelectric layer 454, the upper conductive structure 456, the contact structure 462, and the contact structure 464 are included.

[0112] In some examples, in order to form something similar Figure 4D The semiconductor structure 400D shown can have an intermediate etch stop layer 443 and a dielectric layer 447 formed between the top 444 of the cavity structure 440 during the formation of the semiconductor structure 900A. In some aspects, the second ILD layer 928 can be partially etched, the intermediate etch stop layer 443 can be deposited, the dielectric layer 447 can be deposited and patterned on the intermediate etch stop layer 443, and a second etch stop layer 924 can be formed above the intermediate etch stop layer 443, and the dielectric layer 447 can be deposited thereon.

[0113] In some respects, the intermediate etch stop layer 443, the dielectric layer 447, and / or the second etch stop layer 924 can be formed based on a feedforward deposition method for controlling their thickness, allowing for better frequency tunability and temperature compensation, and enabling more stringent processing by tracking the deposition thickness online and making on-the-fly adjustments to other incoming wafers. For example, the thickness of the piezoelectric layer 954 on the current wafer can be measured to adjust the deposition parameters for the intermediate etch stop layer 443, the dielectric layer 447, and / or the second etch stop layer 924 for forming the next wafer.

[0114] In some examples, in order to be based on Figure 6AThe semiconductor structure shown is 600A or Figure 8A The semiconductor structure 800A shown forms a semiconductor structure, and the corresponding part can be omitted. Figure 9B The process, and can be modified accordingly. Figure 9J The process is used to provide the desired location of the contact structure.

[0115] Figures 9L to 9M Together Figures 9A to 9I Examples of methods for manufacturing semiconductor structures (such as...) according to various aspects of this disclosure are illustrated. Figure 4C The example part of the method is a semiconductor structure 400C. An IC (e.g., IC chip 300) may include one or more transistors on a substrate and interconnect structures on the one or more transistors. In some aspects, the interconnect structure may include multiple interconnect layers, multiple interlayer dielectric layers, and a semiconductor structure (such as semiconductor structure 400C or semiconductor structure 900M) embedded in the interconnect structure.

[0116] like Figure 9L As shown, a semiconductor structure 900L is formed based on the semiconductor structure 900I by forming an acoustic reflection structure 970 above the upper conductive structure 956 and the etch stop layer 958, forming one or more ILD layers and / or one or more etch stop layers above the semiconductor structure 900I, and forming one or more openings 936 through the acoustic reflection structure 970, the one or more ILD layers and / or one or more etch stop layers above the semiconductor structure 900I. Based on the resonator design, one or more openings can expose the interconnect structure 929 and the lower conductive structure 952, the piezoelectric layer 954 and / or the upper conductive structure 956.

[0117] In some aspects, the acoustic reflection structure 970 can be formed by depositing a layer of refractory material, and the refractory material may include tungsten, titanium, tantalum oxide, or any combination thereof. In some aspects, the acoustic reflection structure 970 may be a Bragg reflector.

[0118] like Figure 9M As shown, a semiconductor structure 900M is formed based on a semiconductor structure 900L by filling one or more openings 936 with one or more conductive materials to form contact structures 962, 964, and 966. In some aspects, the one or more conductive materials may include copper, aluminum, or any combination thereof.

[0119] In this example, the semiconductor structure 900M can correspond to Figure 4C The semiconductor structure 400C is shown. For example, the cavity structure 940, the lower conductive structure 952, the piezoelectric layer 954, the upper conductive structure 956, the contact structure 962, and the contact structure 964 can respectively correspond to Figure 4CThe cavity structure 440, lower conductive structure 452, piezoelectric layer 454, upper conductive structure 456, contact structure 462, and contact structure 464 are included. Furthermore, the acoustic reflection structure 970 can correspond to... Figure 4C The acoustic reflection structure 470 in the middle.

[0120] Figure 10 A method 1000 for manufacturing an IC including a semiconductor structure (such as semiconductor structure 400B or 400C and variations thereof) according to various aspects of this disclosure is illustrated.

[0121] At operation 1002, one or more transistors are formed on the substrate.

[0122] At operation 1006, an interconnect structure is formed on one or more transistors. In some aspects, the interconnect structure may include multiple interconnect layers, multiple interlayer dielectric layers, and a semiconductor structure embedded in the interconnect structure. Operation 1006 may also include at least operations 1010 to 1040 for forming the interconnect structure.

[0123] At operation 1010, a piezoelectric layer (e.g., piezoelectric layer 454) is formed over a first etch stop layer (e.g., first etch stop layer 342) and a second etch stop layer (e.g., second etch stop layer 344), the first etch stop layer being over a substrate (e.g., substrate 302, as part of FEOL portion 410) and the second etch stop layer being over the first etch stop layer.

[0124] At operation 1020, an upper conductive structure (e.g., upper conductive structure 456) is formed on the piezoelectric layer. In some aspects, the piezoelectric layer may include aluminum nitride, scandium aluminum nitride, or any combination thereof.

[0125] At operation 1030, a cavity structure (e.g., cavity structure 440) is formed after the formation of the upper conductive structure. In some aspects, the cavity structure may include a bottom (e.g., bottom 442) as part of a first etch stop layer, a top (e.g., top 444) as part of a second etch stop layer, one or more sidewalls (e.g., one or more sidewalls 446) connecting the bottom and top of the cavity structure, and a cavity (e.g., cavity 448) between the top and bottom of the cavity structure and surrounded by one or more sidewalls. In some aspects, the cavity may be filled with air.

[0126] In some aspects, the cavity structure can be formed based on forming one or more first openings through the second etch stop layer and the interlayer dielectric layer (e.g., the first ILD layer 352) between the first and second etch stop layers, and the one or more first openings can expose a portion of the first etch stop layer. The one or more first openings are then at least partially filled with an etch stop material to form one or more sidewalls. One or more second openings can be formed through the second etch stop layer, wherein the one or more second openings are within an internal region defined by the one or more sidewalls. An etching process can be performed based on moving etchant through the one or more second openings to remove portions of the interlayer dielectric layer within the region defined by the bottom, top, and one or more sidewalls. In some aspects, the formation of the one or more second openings can be based on an anisotropic etching process.

[0127] Subsequently, to form the cavity structure, the one or more second openings can be sealed with an etch-stop material. In some aspects, a third etch-stop layer (e.g., 428) can be formed over the upper conductive structure, while one or more sidewalls are formed based on the same deposition process. In some aspects, the first etch-stop layer, the second etch-stop layer, the third etch-stop layer, and the etch-stop material may comprise silicon nitride.

[0128] At operation 1040, a first contact structure (e.g., first contact structure 462) is formed on the upper conductive structure. In some aspects, at operation 1040, a second contact structure (e.g., second contact structure 464) may also be formed on the upper conductive structure.

[0129] In some respects, prior to operation 1010, a lower conductive layer may be formed on the second etch stop layer, such that the lower conductive structure is between the piezoelectric layer and the top of the cavity structure.

[0130] In some aspects, an acoustic reflection structure (e.g., acoustic reflection structure 470) may be formed above the upper conductive structure prior to operation 1040. In some aspects, the acoustic reflection structure includes a refractory material layer, and the refractory material includes tungsten, titanium, tantalum oxide, or any combination thereof.

[0131] In some aspects, prior to operation 1040 or concurrently with operations 1010 and 1020, a MIM capacitor or MOM capacitor may be formed on an interlayer dielectric layer (e.g., a first ILD layer 352) and this interlayer dielectric layer is on a first etch stop layer. In some aspects, a MIM capacitor or MOM capacitor may be formed in another interlayer dielectric layer (e.g., a second ILD layer 354) and this other interlayer dielectric layer is on a second etch stop layer.

[0132] In some respects, based on such Figure 5A , Figure 5C and Figure 5D The design shown includes forming a lower conductive structure, which may include a patterned lower conductive layer to become a lower conductive structure, the lower conductive structure including a lower patterned portion aligned above the cavity and a lower anchoring portion coupled to the lower patterned portion. In some aspects, forming an upper conductive structure may include a patterned upper conductive layer to become an upper conductive structure, the upper conductive structure including an upper patterned portion aligned above the cavity and at least partially overlapping the lower patterned portion, and an upper anchoring portion coupled to the upper patterned portion. In some aspects, the lower patterned portion may have a lower patch pattern or a lower finger pattern, and the upper patterned portion may have an upper patch pattern or an upper finger pattern. In some aspects, a first contact structure may be coupled to the upper anchoring portion. In some aspects, a second contact structure may be coupled to the lower anchoring portion.

[0133] In some respects, based on such Figure 5B The design shown may include a patterned lower conductive layer to form the lower conductive structure, which includes a lower finger-like portion aligned above the cavity and a lower anchoring portion coupled to the lower finger-like portion. In some aspects, forming the upper conductive structure may include a patterned upper conductive layer to form the upper conductive structure, which includes an upper finger-like portion aligned above the cavity without overlapping the lower finger-like portion, and an upper anchoring portion coupled to the upper finger-like portion. In some aspects, a first contact structure may be coupled to the upper anchoring portion. In some aspects, a second contact structure may be coupled to the lower anchoring portion.

[0134] In some respects, based on such Figure 6B and Figure 6C The design shown, forming the upper conductive structure, may include a patterned upper conductive layer to become the upper conductive structure, which includes an upper patterned portion aligned above the cavity and at least partially overlapping with the upper patterned portion, and an upper anchoring portion coupled to the upper patterned portion. In some aspects, the upper patterned portion may have an upper patch pattern or an upper finger pattern. In some aspects, a first contact structure may be coupled to the upper anchoring portion. In some aspects, a second contact structure may be coupled to the piezoelectric plate layer.

[0135] In some respects, based on such Figure 8B The design shown, forming an upper conductive structure, may include a patterned upper conductive layer to become an upper conductive structure, the upper conductive structure including a first upper patterned portion aligned above the cavity, a first upper anchoring portion coupled to the first upper patterned portion, a second upper patterned portion aligned above the cavity without overlapping the first upper patterned portion, and a second upper anchoring portion coupled to the second upper patterned portion. In some aspects, a first contact structure may be coupled to the first upper anchoring portion. In some aspects, a second contact structure may be coupled to the second upper anchoring portion.

[0136] In some respects, based on such Figure 8C and Figure 8D The design shown, forming the upper conductive structure, may include a patterned upper conductive layer to become the upper conductive structure, which includes a vibrational pattern aligned above the cavity and above the piezoelectric plate layer, and a plurality of input / output terminals capacitively coupled to the vibrational pattern. In some aspects, the semiconductor structure may include a plurality of contact structures (including a first contact structure and / or a second contact structure) respectively coupled to the plurality of input / output terminals.

[0137] As will be understood, the technical advantage of method 1000 is that it forms a monolithic integrated resonator based on a MIM / MOM manufacturing process and compatible with CMOS manufacturing processes. Therefore, the monolithic integrated resonator as described in this disclosure can replace the relatively more expensive crystal resonator. Furthermore, by integrating the resonator into the IC chip, the resulting design can have a smaller package, such as simplified packaging processes (e.g., based on conventional CMOS packages, such as flip-chip packages, CuP packages, or QFN packages, without additional bonding), fewer parasitic effects (e.g., less Q-factor degradation), and lower manufacturing costs.

[0138] Figure 11 A mobile device 1100 according to various aspects of this disclosure is illustrated. In some aspects, the mobile device 1100 may be implemented by including one or more ICs, which include semiconductor structures manufactured based on the examples described in this disclosure.

[0139] In some aspects, mobile device 1100 can be configured as a wireless communication device. As shown, mobile device 1100 includes a processor 1101. Processor 1101 is communicatively coupled to memory 1132 via a link, which may be a die-to-die or chip-to-chip link. Mobile device 1100 also includes a display 1128 and a display controller 1126, wherein display controller 1126 is coupled to processor 1101 and display 1128. Mobile device 1100 may include an input device 1130 (e.g., a physical or virtual keyboard), a power supply 1144 (e.g., a battery), a speaker 1136, a microphone 1138, and a wireless antenna 1142. In some aspects, power supply 1144 may directly or indirectly provide power supply voltage for some or all of the components of mobile device 1100.

[0140] In some respects, Figure 11 It may include a decoder / decoder (codec) 1134 (e.g., an audio and / or voice codec) coupled to processor 1101; a speaker 1136 and a microphone 1138 coupled to codec 1134; and a wireless circuit 1140 (which may include a modem, RF circuitry, filters, etc.) coupled to wireless antenna 1142 and processor 1101.

[0141] In some aspects, one or more of the processor 1101, display controller 1126, memory 1132, codec 1134, and wireless circuit 1140 may include one or more ICs, which include semiconductor structures manufactured according to the examples described in this disclosure.

[0142] It should be noted that, although Figure 11 Mobile device 1100 is described, but similar architectures can be used to implement devices including set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed location data units, computers, laptops, tablets, communication devices, mobile phones, or other similar devices.

[0143] Figure 12 Various electronic devices 1210, 1220, and 1230 that can be integrated with ICs 1212, 1222, and 1232 according to aspects of this disclosure are illustrated. For example, mobile phone device 1210, laptop computer device 1220, and fixed-location terminal device 1230 can each generally be considered user equipment (UE) and may include one or more ICs such as ICs 1212, 1222, and 1232, as well as a power supply for providing a supply voltage to power the ICs. ICs 1212, 1222, and 1232 may, for example, correspond to components based on the above references. Figures 3 to 8E The example described is an IC with a semiconductor structure.

[0144] Figure 12 The devices 1210, 1220, and 1230 illustrated herein are merely non-limiting examples. Other electronic devices may also feature ICs including semiconductor structures as described in this disclosure, including, but not limited to, a group of devices (e.g., electronic devices): mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units (such as instrument reading devices), communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, laptop computers, access points, base stations, or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0145] It should be understood that the various aspects disclosed herein can be described as functional equivalents of structures, materials, and / or devices as described and / or understood by those skilled in the art. For example, in one aspect, the apparatus may include components for performing the various functions discussed above. It should be understood that the foregoing aspects are provided by way of example only, and the claimed aspects are not limited to the specific references and / or illustrations cited as examples.

[0146] Figure 1 to Figure 12 One or more of the illustrated components, processes, features, and / or functions may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may be added without departing from this disclosure. In some specific embodiments, Figures 1 to... Figure 12 The corresponding descriptions can be used to manufacture, create, provide, and / or produce integrated devices. In some specific implementations, devices may include dies, integrated devices, die packages, ICs, device packages, IC packages, wafers, semiconductor devices, system-in-package (SiP), system-on-a-chip (SoC), and PoP devices, etc.

[0147] As used herein, the terms “user equipment” (or “UE”), “user terminal”, “client equipment”, “communication equipment”, “wireless equipment”, “wireless communication equipment”, “handheld device”, “mobile device”, “mobile terminal”, “mobile station”, “mobile phone”, “access terminal”, “subscriber equipment”, “subscriber terminal”, “subscriber station”, “terminal”, and variations thereof may interchangeably refer to any suitable mobile or stationary device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, onboard equipment in motor vehicles, and / or other types of portable electronic devices that are typically carried by an individual and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices that communicate with another device capable of receiving wireless communication and / or navigation signals (such as via short-range wireless, infrared, wired, or other connections), regardless of whether satellite signal reception, auxiliary data reception, and / or positioning-related processing occur at that device or at the other device. The UE can be implemented using any of several types of devices, including but not limited to printed circuit (PC) cards, compact flash memory devices, external or internal modems, wireless or wired phones, smartphones, tablet devices, consumer tracking devices, asset tags, etc.

[0148] Wireless communication between electronic devices can be based on various technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee / Thread), or other protocols that can be used in wireless communication networks or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart)

[0149] Nothing described or illustrated in this application is intended to offer any component, action, feature, benefit, advantage, or equivalent to the public, whether or not such component, action, feature, benefit, advantage, or equivalent is stated in the claims.

[0150] Furthermore, those skilled in the art will appreciate that the various exemplary logic blocks, modules, circuits, and algorithmic actions described in conjunction with the examples disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this hardware-software interchangeability, the various exemplary components, blocks, modules, circuits, and actions described above are generalized in their functional form. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0151] Although some aspects have been described in conjunction with the device, these aspects undoubtedly also constitute a description of the corresponding method, and therefore, blocks or components of the device should also be understood as corresponding method actions or features of method actions. Similarly, aspects described in conjunction with or as method actions also constitute a description of the corresponding blocks, details, or features of the corresponding device. Some or all of the method actions can be performed by (or using) hardware devices, such as, for example, microprocessors, programmable computers, or electronic circuits. In some examples, some or more of the most important method actions can be performed by such devices.

[0152] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features than those explicitly mentioned in each clause. Rather, the various aspects of this disclosure may include fewer features than those in the individual example clauses disclosed. Therefore, the following clauses should be regarded accordingly as incorporated into the description, where each clause can be considered a separate example on its own. Although each dependent clause may refer in the clause to a specific combination with one of the other clauses, the aspect of that dependent clause is not limited to that specific combination. It should be understood that other example clauses may also include combinations of aspects of a dependent clause with the subject matter of any other dependent or independent clause, or any feature combined with other dependent and independent clauses. The various aspects disclosed herein explicitly include these combinations unless explicitly stated or can be readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of a clause may be included in any other independent clause, even if that clause does not directly depend on the independent clause.

[0153] Specific implementation examples are described in the following numbered clauses:

[0154] Clause 1. An integrated circuit (IC) comprising: one or more transistors on a substrate; and an interconnect structure on the one or more transistors, the interconnect structure including a plurality of interconnect layers, a plurality of interlayer dielectric layers, and a semiconductor structure embedded in the interconnect structure, wherein the semiconductor structure includes: a cavity structure including: a bottom portion of a first etch stop layer; a top portion of a second etch stop layer above the first etch stop layer; one or more sidewalls connecting the bottom and the top of the cavity structure; and a cavity between the top and the bottom of the cavity structure and surrounded by the one or more sidewalls; a piezoelectric layer above the cavity structure; an upper conductive structure on the piezoelectric layer; and a first contact structure on the upper conductive structure.

[0155] Clause 2. The IC according to Clause 1, the IC further includes: a lower conductive structure between the piezoelectric layer and the top of the cavity structure.

[0156] Clause 3. The IC according to Clause 2, wherein: the lower conductive structure includes: a lower patterned portion above the cavity; and a lower anchoring portion coupled to the lower patterned portion, the upper conductive structure includes: an upper patterned portion above the cavity and at least partially overlapping the lower patterned portion; and an upper anchoring portion coupled to the upper patterned portion, the lower patterned portion having a lower patch pattern or a lower finger pattern, the upper patterned portion having an upper patch pattern or an upper finger pattern, a first contact structure coupled to the upper anchoring portion, and the semiconductor structure further includes a second contact structure coupled to the lower anchoring portion.

[0157] Clause 4. The IC according to Clause 2, wherein: the lower conductive structure includes: a lower finger-like portion above the cavity; and a lower anchoring portion coupled to the lower finger-like portion; the upper conductive structure includes: an upper finger-like portion above the cavity without overlapping the lower finger-like portion; and an upper anchoring portion coupled to the upper finger-like portion; a first contact structure coupled to the upper anchoring portion; and the semiconductor structure further includes a second contact structure coupled to the lower anchoring portion.

[0158] Clause 5. The IC according to any one of Clauses 1 to 4, wherein: the upper conductive structure comprises: an upper patterned portion above the cavity; and an upper anchoring portion coupled to the upper patterned portion, the upper patterned portion having an upper patch pattern or an upper finger pattern, and the first contact structure coupled to the upper anchoring portion.

[0159] Clause 6. The IC according to Clause 1, wherein: the upper conductive structure includes: a first upper patterned portion above the cavity; a first upper anchoring portion coupled to the first upper patterned portion; a second upper patterned portion above the cavity without overlapping the first upper patterned portion; and a second upper anchoring portion coupled to the second upper patterned portion, the first contact structure being coupled to the first upper anchoring portion, and the semiconductor structure further includes a second contact structure coupled to the second upper anchoring portion.

[0160] Clause 7. The IC according to Clause 1, wherein: the upper conductive structure includes: a vibration pattern above the cavity; and a plurality of input / output terminals capacitively coupled to the vibration pattern, the semiconductor structure including a plurality of contact structures, the plurality of contact structures including the first contact structure, and the plurality of contact structures being respectively coupled to the plurality of input / output terminals.

[0161] Clause 8. The IC according to any one of Clauses 1 to 7, the IC further includes: an acoustic reflection structure above the upper conductive structure.

[0162] Clause 9. The IC as described in Clause 8, wherein the acoustic reflection structure comprises a refractory material layer, and the refractory material comprises tungsten, titanium, tantalum oxide, or any combination thereof.

[0163] Clause 10. The IC according to any one of Clauses 1 to 9, wherein the piezoelectric layer comprises aluminum nitride, scandium aluminum nitride, or any combination thereof.

[0164] Clause 11. The IC according to any one of Clauses 1 to 10, wherein the top, the bottom, and the one or more sidewalls of the cavity structure comprise silicon nitride.

[0165] Clause 12. The IC according to any one of Clauses 1 to 11, wherein the cavity structure further comprises: an intermediate etch stop layer; and a dielectric layer between the top of the cavity structure and the intermediate etch stop layer, wherein the cavity is between the intermediate etch stop layer and the bottom of the cavity structure.

[0166] Clause 13. The IC according to any one of Clauses 1 to 12, wherein the interconnect structure further comprises a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor in one of the plurality of interlayer dielectric layers, wherein the one of the plurality of interlayer dielectric layers is on the second etch stop layer.

[0167] Clause 14. A method of manufacturing an integrated circuit (IC), the method comprising: forming one or more transistors on a substrate; and forming an interconnect structure on the one or more transistors, the interconnect structure including a plurality of interconnect layers, a plurality of interlayer dielectric layers, and a semiconductor structure embedded in the interconnect structure, the interconnect structure comprising: forming a piezoelectric layer over a first etch stop layer and a second etch stop layer, the first etch stop layer being over the substrate, and the second etch stop layer being over the first etch stop layer; forming an upper conductive structure on the piezoelectric layer; forming a cavity structure after forming the upper conductive structure, the cavity structure including: a bottom part of the first etch stop layer; a top part of the second etch stop layer; one or more sidewalls connecting the bottom and the top of the cavity structure; and a cavity between the top and the bottom of the cavity structure and surrounded by the one or more sidewalls; and forming a first contact structure on the upper conductive structure.

[0168] Clause 15. The method according to Clause 14, wherein the piezoelectric layer comprises aluminum nitride, scandium aluminum nitride, or any combination thereof.

[0169] Clause 16. The method according to any one of Clauses 14 to 15, wherein forming the interconnect structure further comprises: forming an acoustic reflection structure above the upper conductive structure.

[0170] Clause 17. The method according to Clause 16, wherein the acoustic reflection structure comprises a refractory material layer, and the refractory material comprises tungsten, titanium, tantalum oxide, or any combination thereof.

[0171] Clause 18. The method according to any one of Clauses 14 to 17, wherein forming the interconnect structure further comprises forming a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor in one of the plurality of interlayer dielectric layers, wherein the one of the plurality of interlayer dielectric layers is on the second etch stop layer.

[0172] Clause 19. The method according to any one of Clauses 14 to 18, wherein forming the cavity structure comprises: forming one or more first openings through the second etch stop layer and an interlayer dielectric layer between the first etch stop layer and the second etch stop layer, the one or more first openings exposing a portion of the first etch stop layer; forming a third etch stop layer over the upper conductive structure; filling the one or more first openings at least partially with an etch stop material to form the one or more sidewalls; forming one or more second openings through the second etch stop layer in an internal region defined by the one or more sidewalls; and performing an etching process based on moving an etchant through the one or more second openings to remove a portion of the interlayer dielectric layer in the region defined by the bottom, the top, and the one or more sidewalls.

[0173] Clause 20. The method according to Clause 19, wherein forming the cavity structure further comprises: sealing the one or more second openings with the etch-stop material.

[0174] Clause 21. The method according to any one of Clauses 19 to 20, wherein the formation of the third etch stop layer and the filling of at least partially the one or more first openings are based on the same deposition process.

[0175] Clause 22. The method according to any one of Clauses 19 to 21, wherein the formation of the one or more second openings is based on an anisotropic etching process.

[0176] Clause 23. The method according to any one of Clauses 14 to 22, the method further comprising: forming a lower conductive structure between the piezoelectric layer and the top of the cavity structure.

[0177] Clause 24. The method according to Clause 23, wherein: forming the lower conductive structure includes patterning a lower conductive layer to become the lower conductive structure, the lower conductive structure including: a lower patterned portion above the cavity; and a lower anchoring portion coupled to the lower patterned portion; forming the upper conductive structure includes patterning an upper conductive layer to become the upper conductive structure, the upper conductive structure including: an upper patterned portion above the cavity and at least partially overlapping the lower patterned portion; and an upper anchoring portion coupled to the upper patterned portion, the lower patterned portion having a lower patch pattern or a lower finger pattern, the upper patterned portion having an upper patch pattern or an upper finger pattern, a first contact structure coupled to the upper anchoring portion, and the method further includes forming a second contact structure coupled to the lower anchoring portion.

[0178] Clause 25. The method according to Clause 23, wherein: forming the lower conductive structure includes patterning a lower conductive layer to become the lower conductive structure, the lower conductive structure including: a lower finger-like portion above the cavity; and a lower anchoring portion coupled to the lower finger-like portion; forming the upper conductive structure includes patterning an upper conductive layer to become the upper conductive structure, the upper conductive structure including: an upper finger-like portion above the cavity without overlapping the lower finger-like portion; and an upper anchoring portion coupled to the upper finger-like portion, the first contact structure being coupled to the upper anchoring portion, and the method further includes forming a second contact structure coupled to the lower anchoring portion.

[0179] Clause 26. The method according to any one of Clauses 14 to 25, wherein: forming the upper conductive structure includes patterning an upper conductive layer to become the upper conductive structure, the upper conductive structure including: an upper patterned portion above the cavity; and an upper anchoring portion coupled to the upper patterned portion, the upper patterned portion having an upper patch pattern or an upper finger pattern, and the first contact structure being coupled to the upper anchoring portion.

[0180] Clause 27. The method according to any one of Clauses 14 to 22, wherein: forming the upper conductive structure includes patterning an upper conductive layer to become the upper conductive structure, the upper conductive structure including: a first upper patterned portion above the cavity; a first upper anchoring portion coupled to the first upper patterned portion; a second upper patterned portion above the cavity without overlapping the first upper patterned portion; and a second upper anchoring portion coupled to the second upper patterned portion, the first contact structure being coupled to the first upper anchoring portion, and the method further includes forming a second contact structure coupled to the second upper anchoring portion.

[0181] Clause 28. The method according to any one of Clauses 14 to 22, wherein: forming the upper conductive structure includes patterning an upper conductive layer to become the upper conductive structure, the upper conductive structure including: a vibration pattern above the cavity; and a plurality of input / output terminals capacitively coupled to the vibration pattern, the method further comprising forming a plurality of contact structures including the first contact structure, and the plurality of contact structures being respectively coupled to the plurality of input / output terminals.

[0182] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0183] Furthermore, those skilled in the art will understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been broadly described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application; however, such implementation decisions should not be construed as departing from the scope of this disclosure.

[0184] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using general-purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic units, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0185] The methods, sequences, and / or algorithms described in conjunction with the aspects disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or a combination of both. The software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. Example storage media are coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integral with the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a user terminal (e.g., a UE). Alternatively, the processor and storage medium can reside as discrete components in the user terminal.

[0186] In one or more examples, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium that is accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that may be used to carry or store the desired program code in the form of instructions or data structures and that is accessible to a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of a medium. As used herein, disks and optical discs include: compact optical discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0187] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Furthermore, although elements of this disclosure may be described or claimed in the singular, the plural form may also be considered unless explicitly stated as limited to the singular.

Claims

1. An integrated circuit (IC), said integrated circuit (IC) comprising: One or more transistors on a substrate; as well as The interconnect structure on the one or more transistors, the interconnect structure comprising multiple interconnect layers, multiple interlayer dielectric layers, and a semiconductor structure embedded in the interconnect structure. The semiconductor structure includes: Cavity structure, the cavity structure comprising: The bottom layer is part of the first etch stop layer; The top, which is part of the second etch stop layer above the first etch stop layer; One or more sidewalls, the one or more sidewalls connecting the bottom and the top of the cavity structure; and A cavity, the cavity being located between the top and the bottom of the cavity structure and surrounded by the one or more sidewalls; The piezoelectric layer above the cavity structure; The upper conductive structure on the piezoelectric layer; and The first contact structure on the upper conductive structure.

2. The IC according to claim 1, further comprising: The lower conductive structure between the piezoelectric layer and the top of the cavity structure.

3. The IC according to claim 2, wherein: The lower conductive structure includes: The lower pattern portion above the cavity; and The lower anchor portion is coupled to the lower pattern portion. The upper conductive structure includes: The upper pattern portion above the cavity and at least partially overlapping the lower pattern portion; and The upper anchoring portion is coupled to the upper patterned portion. The lower pattern portion has a lower patch pattern or a lower finger pattern. The upper patterned portion has an upper patch pattern or an upper finger-shaped pattern. The first contact structure is coupled to the upper anchoring portion, and The semiconductor structure also includes a second contact structure coupled to the lower anchor portion.

4. The IC according to claim 2, wherein: The lower conductive structure includes: The lower finger-shaped portion above the cavity; and The lower anchoring portion is coupled to the lower finger-like portion. The upper conductive structure includes: The upper finger-like portion above the cavity that does not overlap with the lower finger-like portion; and The upper anchoring portion is coupled to the upper finger-like portion. The first contact structure is coupled to the upper anchoring portion, and The semiconductor structure also includes a second contact structure coupled to the lower anchor portion.

5. The IC according to claim 1, wherein: The upper conductive structure includes: The upper pattern portion above the cavity; and The upper anchoring portion is coupled to the upper patterned portion. The upper patterned portion has an upper patch pattern or an upper finger-shaped pattern, and The first contact structure is coupled to the upper anchoring portion.

6. The IC according to claim 1, wherein: The upper conductive structure includes: The first upper pattern portion above the cavity; The first upper anchoring portion is coupled to the first upper pattern portion; A second upper pattern portion above the cavity that does not overlap with the first upper pattern portion; and The second upper anchoring portion is coupled to the second upper pattern portion. The first contact structure is coupled to the first upper anchoring portion, and The semiconductor structure further includes a second contact structure coupled to the second upper anchor portion.

7. The IC according to claim 1, wherein: The upper conductive structure includes: The vibration pattern above the cavity; and Multiple input / output terminals are capacitively coupled to the vibration pattern. The semiconductor structure includes a plurality of contact structures, the plurality of contact structures including the first contact structure, and the plurality of contact structures are respectively coupled to the plurality of input / output terminals.

8. The IC according to claim 1, further comprising: The acoustic reflection structure above the upper conductive structure.

9. The IC of claim 8, wherein the acoustic reflection structure comprises a refractory material layer, and the refractory material comprises tungsten, titanium, tantalum oxide, or any combination thereof.

10. The IC of claim 1, wherein the piezoelectric layer comprises aluminum nitride, scandium aluminum nitride, or any combination thereof.

11. The IC of claim 1, wherein the top, the bottom, and the one or more sidewalls of the cavity structure comprise silicon nitride.

12. The IC according to claim 1, wherein the cavity structure further comprises: Intermediate etch stop layer; as well as The dielectric layer between the top of the cavity structure and the intermediate etch stop layer. The cavity is located between the intermediate etch stop layer and the bottom of the cavity structure.

13. The IC of claim 1, wherein the interconnect structure further comprises a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor in one of the plurality of interlayer dielectric layers, wherein the one of the plurality of interlayer dielectric layers is on the second etch stop layer.

14. A method for manufacturing an integrated circuit (IC), the method comprising: One or more transistors are formed on a substrate; as well as An interconnect structure is formed on one or more transistors, the interconnect structure including multiple interconnect layers, multiple interlayer dielectric layers, and a semiconductor structure embedded in the interconnect structure, wherein forming the interconnect structure includes: A piezoelectric layer is formed over a first etch stop layer and a second etch stop layer, wherein the first etch stop layer is over the substrate and the second etch stop layer is over the first etch stop layer; An upper conductive structure is formed on the piezoelectric layer; After forming the upper conductive structure, a cavity structure is formed, the cavity structure comprising: The bottom, which is part of the first etch stop layer; The top, which is part of the second etch stop layer; One or more sidewalls, the one or more sidewalls connecting the bottom and the top of the cavity structure; and A cavity, the cavity being located between the top and the bottom of the cavity structure and surrounded by the one or more sidewalls; and A first contact structure is formed on the upper conductive structure.

15. The method of claim 14, wherein the piezoelectric layer comprises aluminum nitride, scandium aluminum nitride, or any combination thereof.

16. The method of claim 14, wherein forming the interconnect structure further comprises: An acoustic reflection structure is formed above the upper conductive structure.

17. The method of claim 16, wherein the acoustic reflection structure comprises a refractory material layer, and the refractory material comprises tungsten, titanium, tantalum oxide, or any combination thereof.

18. The method of claim 14, wherein forming the interconnect structure further comprises forming a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor in one of the plurality of interlayer dielectric layers, wherein the one of the plurality of interlayer dielectric layers is on the second etch stop layer.

19. The method of claim 14, wherein forming the cavity structure comprises: One or more first openings are formed through the second etch stop layer and the interlayer dielectric layer between the first etch stop layer and the second etch stop layer, the one or more first openings exposing a portion of the first etch stop layer; A third etch stop layer is formed above the upper conductive structure; The one or more first openings are at least partially filled with an etching stop material to form the one or more sidewalls; One or more second openings are formed through the second etch stop layer, the one or more second openings being within an internal region defined by the one or more sidewalls; as well as An etching process is performed by moving etchant through the one or more second openings to remove portions of the interlayer dielectric layer within the area defined by the bottom, the top, and the one or more sidewalls.

20. The method of claim 19, wherein forming the cavity structure further comprises: The one or more second openings are sealed with the etching-stopping material.

21. The method of claim 19, wherein the formation of the third etch stop layer and the at least partially filling of the one or more first openings are based on the same deposition process.

22. The method of claim 19, wherein the formation of the one or more second openings is based on an anisotropic etching process.

23. The method according to claim 14, further comprising: A lower conductive structure is formed between the piezoelectric layer and the top of the cavity structure.

24. The method according to claim 23, wherein: The formation of the lower conductive structure includes patterning a lower conductive layer to form the lower conductive structure, the lower conductive structure comprising: The lower pattern portion above the cavity; and The lower anchor portion is coupled to the lower pattern portion. The formation of the upper conductive structure includes patterning an upper conductive layer to form the upper conductive structure, the upper conductive structure comprising: The upper pattern portion above the cavity and at least partially overlapping the lower pattern portion; and The upper anchoring portion is coupled to the upper patterned portion. The lower pattern portion has a lower patch pattern or a lower finger pattern. The upper patterned portion has an upper patch pattern or an upper finger-shaped pattern. The first contact structure is coupled to the upper anchoring portion, and The method further includes forming a second contact structure coupled to the lower anchoring portion.

25. The method according to claim 23, wherein: The formation of the lower conductive structure includes patterning a lower conductive layer to form the lower conductive structure, the lower conductive structure comprising: The lower finger-shaped portion above the cavity; and The lower anchoring portion is coupled to the lower finger-like portion. The formation of the upper conductive structure includes patterning an upper conductive layer to form the upper conductive structure, the upper conductive structure comprising: The upper finger-like portion above the cavity that does not overlap with the lower finger-like portion; and The upper anchoring portion is coupled to the upper finger-like portion. The first contact structure is coupled to the upper anchoring portion, and The method further includes forming a second contact structure coupled to the lower anchoring portion.

26. The method of claim 14, wherein: The formation of the upper conductive structure includes patterning an upper conductive layer to form the upper conductive structure, the upper conductive structure comprising: The upper pattern portion above the cavity; and The upper anchoring portion is coupled to the upper patterned portion. The upper patterned portion has an upper patch pattern or an upper finger-shaped pattern, and The first contact structure is coupled to the upper anchoring portion.

27. The method of claim 14, wherein: The formation of the upper conductive structure includes patterning an upper conductive layer to form the upper conductive structure, the upper conductive structure comprising: The first upper pattern portion above the cavity; The first upper anchoring portion is coupled to the first upper pattern portion; A second upper pattern portion above the cavity that does not overlap with the first upper pattern portion; and The second upper anchoring portion is coupled to the second upper pattern portion. The first contact structure is coupled to the first upper anchoring portion, and The method further includes forming a second contact structure coupled to the second upper anchoring portion.

28. The method of claim 14, wherein: The formation of the upper conductive structure includes patterning an upper conductive layer to form the upper conductive structure, the upper conductive structure comprising: The vibration pattern above the cavity; and Multiple input / output terminals are capacitively coupled to the vibration pattern. The method further includes forming a plurality of contact structures including the first contact structure, and The plurality of contact structures are respectively coupled to the plurality of input / output terminals.

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