Aligned cyclic low density parity check (QC-LDPC) codes for two-step lifting of WI-FI

Abstract

The present disclosure provides methods, components, devices, and systems for low density parity check (LDPC) coding. Some aspects are more particularly directed to expanding an LDPC codeword to produce a longer codeword. In some examples, a first wireless device may generate a baseline LDPC code by performing a first boost on a basis matrix, which may produce an LDPC code for a current Wi-Fi implementation. The first wireless device may then perform a second boost or re-boost (such as a cyclic boost, a product boost, an exchange boost, or a combination thereof) to generate an extended boosted code. The extended lifted code may be an extension of the first LDPC code such that the first LDPC code may be held as part of the extended code. The first wireless device may then transmit the expanded LDPC code as an expanded or boosted codeword.

Description

[0001] Cross-references

[0002] This patent application claims priority to US Patent Application No. 18 / 189,865, filed March 24, 2023, entitled “EXTENDING LOW-DENSITY PARITY CHECK (LDPC) CODES FOR WI-FI”, which has been assigned to the assignee of this application and is expressly incorporated herein by reference. Technical Field

[0003] In summary, this disclosure relates to wireless communications, and more specifically, to extended low-density parity-check (LDPC) codes for Wi-Fi. Background Technology

[0004] A Wireless Local Area Network (WLAN) can be formed by one or more wireless access points (APs) that provide a shared wireless communication medium for use by multiple client devices (also known as wireless stations (STAs)). The basic building block of a WLAN conforming to the IEEE 802.11 family of standards is the Basic Service Set (BSS), which is managed by the AP. Each BSS is identified by a Basic Service Set Identifier (BSSID) advertised by the AP. The AP periodically broadcasts beacon frames so that any STA within the AP's wireless range can establish or maintain a communication link with the WLAN. Summary of the Invention

[0005] The systems, methods, and apparatuses disclosed herein each have multiple innovative aspects, wherein no single aspect is solely responsible for the desired properties disclosed herein. The techniques described herein can support efficient extensions of low-density parity-check (LDPC) codes, and more specifically, can support techniques for extending existing LDPC codes to longer codes, while the original code can still be recovered from the longer code. For example, a first wireless device can perform a first boosting to generate a first LDPC matrix and a first LDPC code by performing a first boosting on a basis matrix that can generate the original code. The first wireless device can then generate an extended LDPC matrix and an extended LDPC code by performing a second boosting on the first LDPC matrix. The first wireless device can then encode a first plurality of bits according to the extended LDPC matrix and the extended LDPC code to generate a boosted codeword, and can transmit the boosted codeword to a second wireless device.

[0006] One innovative aspect of the subject matter described in this disclosure can be implemented in a first wireless communication device. The first wireless communication device includes means that may include a processor, a memory coupled to the processor, and instructions stored in the memory. The instructions are executable by the processor to cause the means to generate a first low-density parity-check matrix and a first low-density parity-check code by performing a first lifting on a base matrix; to generate an extended low-density parity-check matrix and an extended low-density parity-check code by performing a second lifting on the first low-density parity-check matrix, wherein one or more lifting permutation matrices associated with the base edges of the first low-density parity-check matrix can be recovered as block-by-block submatrices of one or more lifting permutation matrices associated with the corresponding base edges of the extended low-density parity-check matrix, the extended low-density parity-check code being an extension of the first low-density parity-check code; to encode a first multi-bit set according to the extended low-density parity-check matrix and the extended low-density parity-check code to produce a lifted codeword; and to perform transmission of the lifted codeword from the first wireless device to a second wireless device.

[0007] Another innovative aspect of the subject matter described in this disclosure can be implemented in a method for wireless communication. The method includes: generating a first low-density parity-check matrix and a first low-density parity-check code by performing a first lifting on a base matrix; generating an extended low-density parity-check matrix and an extended low-density parity-check code by performing a second lifting on the first low-density parity-check matrix, wherein one or more lifting permutation matrices associated with the base edges of the first low-density parity-check matrix can be recovered as block-wise submatrices of one or more lifting permutation matrices associated with the corresponding base edges of the extended low-density parity-check matrix, the extended low-density parity-check code being an extension of the first low-density parity-check code; encoding a first multi-bit set according to the extended low-density parity-check matrix and the extended low-density parity-check code to produce a lifted codeword; and performing transmission of the lifted codeword from a first wireless device to a second wireless device.

[0008] Another innovative aspect of the subject matter described in this disclosure can be implemented in a first wireless communication device. The first wireless communication device may include means for generating a first low-density parity-check matrix and a first low-density parity-check code by performing a first lifting on a base matrix; means for generating an extended low-density parity-check matrix and an extended low-density parity-check code by performing a second lifting on the first low-density parity-check matrix, wherein one or more lifting permutation matrices associated with the base edges of the first low-density parity-check matrix can be recovered as block-by-block submatrices of one or more lifting permutation matrices associated with the corresponding base edges of the extended low-density parity-check matrix, the extended low-density parity-check code being an extension of the first low-density parity-check code; means for encoding a first multi-bit set according to the extended low-density parity-check matrix and the extended low-density parity-check code to generate a lifted codeword; and means for performing transmission of the lifted codeword from the first wireless device to a second wireless device.

[0009] Another innovative aspect of the subject matter described in this disclosure can be implemented in a non-transitory computer-readable medium storing code for wireless communication. The code may include processor-executable instructions to: generate a first low-density parity-check matrix and a first low-density parity-check code by performing a first lifting on a base matrix; generate an extended low-density parity-check matrix and an extended low-density parity-check code by performing a second lifting on the first low-density parity-check matrix, wherein one or more lifting permutation matrices associated with the base edges of the first low-density parity-check matrix can be recovered as block-by-block submatrices of one or more lifting permutation matrices associated with the corresponding base edges of the extended low-density parity-check matrix, the extended low-density parity-check code being an extension of the first low-density parity-check code; encode a first multi-bit set according to the extended low-density parity-check matrix and the extended low-density parity-check code to produce a lifted codeword; and perform transmission of the lifted codeword from a first wireless device to a second wireless device.

[0010] In some examples, the extended low-density parity matrix includes a two-step boosting process, comprising a first boosting step and a second boosting step. The method and wireless communication device can generate integer pairs to identify one or more images of a first low-density parity boosted bit vector within a corresponding extended and boosted parity bit vector. The first integer of the integer pair corresponds to the first boosting step, and the second integer of the integer pair corresponds to the second boosting step. The method further includes: first enumerating bits of the extended low-density parity boosted bit vector based on the first integer of the integer pair used to identify bits within the first low-density parity boosted bit vector; and second enumerating bits of the extended low-density parity boosted bit vector based on the second integer of the integer pair used to identify images of the first low-density parity boosted bit vector within the extended low-density parity boosted bit vector. The method and wireless communication device can also perform the first and second boosting steps based on either an internal or external expansion of the first boosting process to generate the extended low-density parity code.

[0011] In some examples of the method and wireless communication device, the second boosting step includes the internal expansion, which can be recovered from the second boost based on the application of the first boost via a bitmask or a modulo operation, to preserve the first low-density parity boost as a subcomponent of the expanded low-density parity boost.

[0012] In some examples of the method and wireless communication device, the internal expansion can recover a block-by-block submatrix as the expanded low-density parity check matrix from the expanded lifting permutation according to the first lifting permutation, thereby preserving the lifted edge permutation of the first low-density parity check code as a subcomponent of the edge permutation of the expanded low-density parity check code.

[0013] In some examples, the method and wireless communication device may exchange at least two images of the one or more images of the first low-density parity check code during the first boosting step or the second boosting step.

[0014] In some examples of the method and wireless communication device, the extended low-density parity code includes one or more boosted low-density parity codes, the boosted low-density parity code including at least the first low-density parity code, which can be recovered from the extended low-density parity code.

[0015] Another innovative aspect of the subject matter described in this disclosure can be implemented in a first wireless communication device. The first wireless communication device includes means that may include a processor, a memory coupled to the processor, and instructions stored in the memory. The instructions are executable by the processor to cause the means to generate a first low-density parity-check matrix and a first low-density parity-check code by performing a first lifting on a base matrix; to generate an extended low-density parity-check matrix and an extended low-density parity-check code by performing a second lifting on the first low-density parity-check matrix, wherein one or more lifting permutation matrices associated with the base edges of the first low-density parity-check matrix can be recovered as block-by-block submatrices of one or more lifting permutation matrices associated with the corresponding base edges of the extended low-density parity-check matrix, the extended low-density parity-check code being an extension of the first low-density parity-check code; to receive a lifted codeword from the first wireless device according to the extended low-density parity-check matrix; and to decode the lifted codeword according to the extended low-density parity-check code.

[0016] Another innovative aspect of the subject matter described in this disclosure can be implemented in a method for wireless communication. The method includes: generating a first low-density parity-check matrix and a first low-density parity-check code by performing a first lifting on a base matrix; generating an extended low-density parity-check matrix and an extended low-density parity-check code by performing a second lifting on the first low-density parity-check matrix, wherein one or more lifting permutation matrices associated with the base edges of the first low-density parity-check matrix can be recovered as block-by-block submatrices of one or more lifting permutation matrices associated with the corresponding base edges of the extended low-density parity-check matrix, the extended low-density parity-check code being an extension of the first low-density parity-check code; receiving a lifted codeword from a first wireless device based on the extended low-density parity-check matrix; and decoding the lifted codeword based on the extended low-density parity-check code.

[0017] Another innovative aspect of the subject matter described in this disclosure can be implemented in a first wireless communication device. The first wireless communication device may include means comprising: units for generating a first low-density parity-check matrix and a first low-density parity-check code by performing a first lifting on a base matrix; units for generating an extended low-density parity-check matrix and an extended low-density parity-check code by performing a second lifting on the first low-density parity-check matrix, wherein one or more lifting permutation matrices associated with the base edges of the first low-density parity-check matrix can be recovered as block-by-block submatrices of one or more lifting permutation matrices associated with the corresponding base edges of the extended low-density parity-check matrix, the extended low-density parity-check code being an extension of the first low-density parity-check code; units for receiving a lifted codeword from the first wireless device based on the extended low-density parity-check matrix; and units for decoding the lifted codeword based on the extended low-density parity-check code.

[0018] Another innovative aspect of the subject matter described in this disclosure can be implemented in a non-transitory computer-readable medium storing code for wireless communication. The code may include processor-executable instructions to: generate a first low-density parity-check matrix and a first low-density parity-check code by performing a first lifting operation on a base matrix; generate an extended low-density parity-check matrix and an extended low-density parity-check code by performing a second lifting operation on the first low-density parity-check matrix, wherein one or more lifting permutation matrices associated with the base edges of the first low-density parity-check matrix can be recovered as block-by-block submatrices of one or more lifting permutation matrices associated with the corresponding base edges of the extended low-density parity-check matrix, the extended low-density parity-check code being an extension of the first low-density parity-check code; receive a lifted codeword from a first wireless device based on the extended low-density parity-check matrix; and decode the lifted codeword based on the extended low-density parity-check code.

[0019] In some examples of the method and wireless communication device, the extended low-density parity-check matrix includes a two-step boosting step, comprising a first boosting step and a second boosting step. The method and wireless communication device can generate integer pairs to identify one or more images of a first low-density parity-check boosted bit vector within a corresponding extended and boosted low-density parity-check bit vector. The first integer of the integer pair corresponds to the first boosting step, and the second integer of the integer pair corresponds to the second boosting step. The method can first enumerate the bits of the first low-density parity-check boosted bit vector based on the first integer of the integer pair used to identify the bits within the first low-density parity-check boosted bit vector, and secondly enumerate the bits of the first low-density parity-check boosted bit vector based on the second integer of the integer pair used to identify the images of the first low-density parity-check boosted bit vector within the extended and boosted bit vector. The boosted codeword is decoded according to the first boosting step and the second boosting step, depending on whether it is an internal or external boosting step.

[0020] In some examples, the method and wireless communication device may decode the boosted codeword according to the internal extension, which can be recovered from the boosted low-density parity boosting permutation identifier by the application of a first low-density parity boosting permutation identifier via a bitmask or modulo operation, so as to retain the first low-density parity boosting permutation identifier as a subcomponent of the boosted low-density parity boosting permutation identifier.

[0021] In some examples of the method and wireless communication device, the internal expansion can recover a block-by-block submatrix as the expanded low-density parity check matrix from the expanded lifting permutation according to the first lifting permutation, thereby preserving the lifted edge permutation of the first low-density parity check code as a subcomponent of the edge permutation of the expanded low-density parity check code.

[0022] In some examples, the method and wireless communication device may exchange at least two images of the one or more images of the first low-density parity check code during the first boosting step or the second boosting step.

[0023] In some examples of the method and wireless communication device, the extended low-density parity code includes one or more boosted low-density parity codes, the boosted low-density parity code including at least the first low-density parity code, which can be recovered from the extended low-density parity code.

[0024] Details of one or more implementations of the subject matter described in this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the specification, drawings, and claims. It should be noted that the relative dimensions in the following drawings may not be drawn to scale. Attached Figure Description

[0025] Figure 1 and Figure 2 A schematic diagram of an example wireless communication network supporting extended low-density parity-check (LDPC) codes for Wi-Fi is shown.

[0026] Figure 3 The example shows a base graph consisting of a set of variable nodes and check nodes, edges connecting the nodes, and a lifting process that introduces multiple copies of the base graph and replaces the lifted edges that support extended LDPC codes for Wi-Fi.

[0027] Figure 4 An example of the LDPC decoding process at a layered decoder that supports extended LDPC codes for Wi-Fi is shown.

[0028] Figure 5 An example of a cyclic boosting process is shown, performed on the first boosted code of an LDPC code that supports extensions for Wi-Fi.

[0029] Figure 6 An example of the product lifting process performed on the first lifted code of the LDPC code that supports extensions for Wi-Fi is shown.

[0030] Figure 7 An example cyclic permutation is shown, illustrating a cyclic shift operation that supports extended LDPC codes for Wi-Fi.

[0031] Figure 8 This demonstrates the first lift of the block matrix recovery that supports extended LDPC codes for Wi-Fi.

[0032] Figure 9 An example of the signaling process flow between wireless devices on a wireless link that supports extended LDPC codes for Wi-Fi is shown.

[0033] Figure 10 A flowchart illustrating an example process executable by a wireless device that supports LDPC codes extended for Wi-Fi is shown.

[0034] Figure 11 A flowchart illustrating an example process executable by a wireless device that supports LDPC codes extended for Wi-Fi is shown.

[0035] Figure 12 A block diagram of an example wireless communication device that supports extended LDPC codes for Wi-Fi is shown.

[0036] Figure 13 A block diagram of an example wireless communication device that supports extended LDPC codes for Wi-Fi is shown.

[0037] Similar reference numerals and naming conventions in the various figures indicate similar elements. Detailed Implementation

[0038] The following description refers to specific examples for the purpose of illustrating the innovative aspects of this disclosure. However, it will be readily recognized by those skilled in the art that the teachings herein can be applied in a variety of different ways. Some or all of the examples described can be implemented in any device, system, or network capable of transmitting and receiving radio frequency (RF) signals according to one or more of the following: the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard, the IEEE 802.15 standard, and as defined by the Bluetooth Special Interest Group (SIG). Standards, or Long Term Evolution (LTE), 3G, 4G, or 5G (New Radio (NR)) standards issued by the 3rd Generation Partnership Project (3GPP), and other examples. The described examples can be implemented in any device, system, or network capable of transmitting and receiving RF signals according to one or more of the following technologies or techniques: Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal FDMA (OFDMA), Single Carrier FDMA (SC-FDMA), Space Division Multiple Access (SDMA), Rate Split Multiple Access (RSMA), Multi-User Shared Access (MUSA), Single-User (SU) Multiple-Input Multiple-Output (MIMO), and Multi-User (MU) MIMO. The described implementations can also be implemented using other wireless communication protocols or RF signals suitable for use in one or more of the following networks: Wireless Personal Area Network (WPAN), Wireless Local Area Network (WLAN), Wireless Wide Area Network (WWAN), or Internet of Things (IoT) networks.

[0039] Wireless communication generally involves, in particular, low-density parity-check (LDPC) codes. Some aspects involve more specifically extending existing LDPC codes. In some examples, LDPC codes can support efficient and relatively low-error data transmission over wireless communication channels and can be implemented as forward error correction (FEC) codes in several communication standards, such as Wireless Local Area Networks (WLANs, IEEE 802.11). However, LDPC decoding can be associated with relatively large codes and different codeword lengths (at least including 648 bits, 1296 bits, and 1944 bits). These different codeword lengths may increase further with increasing bandwidth, introducing higher modulation orders and enabling more spatial streams. This increase in LDPC codeword length can improve channel and device performance, but device encoders and decoders supporting extended LDPC codes may be limited by various power consumption, area, latency, and cost constraints, posing challenges to implementing efficient hardware capable of LDPC encoding and decoding for extended LDPC codewords.

[0040] The various techniques described herein can support extended LDPC codewords using extended boosting of the boosted basemap (such as extended boosting of the 802.11 boosted basemap for Wi-Fi), thereby reducing the impact on device hardware. Extended boosting of the boosted basemap maintains the structure of the existing LDPC code in the extended code. To efficiently extend LDPC codes to improve performance without significantly increasing the device hardware burden, wireless devices can implement additional boosting to extend the existing boosting of the basemap (such as for Wi-Fi codewords). For example, a wireless device can perform a first boosting (such as cyclic boosting) on ​​the basemap to generate Wi-Fi codes and apply additional boosting or re-boosting (such as additional cyclic boosting, product boosting, exchange boosting, or combinations thereof) to extend the current boosting of the Wi-Fi length-1944 LDPC basemap to create codewords with a length several times the original code length (e.g., 2x, 4x, 8x, 16x, or more of the original code length). The same approach can be applied to smaller Wi-Fi codewords to obtain a relatively finer set of codeword lengths. The techniques described herein preserve the existing LDPC structure and minimize its impact on device hardware by generating extended LDPC codes composed of operations that combine smaller existing LDPC codes. Preserving the existing structure, as an alternative or supplement to implementing the combinatorial operations of the extended LDPC codes, allows for alternative operations for multiple instances of the existing LDPC codes.

[0041] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. With the development of wireless communication technologies, throughput has increased accordingly, and it has become commonplace to include multiple instances of LDPC encoders and decoders in wireless devices. Extending LDPC codes to allow the merging of potentially multiple decoders or encoders into a larger single decoder or encoder capable of decoding or encoding extended codewords can increase the performance gain associated with larger block sizes without substantially increasing the hardware burden on the device. If the merging also preserves the original structure of the smaller encoding and decoding blocks, such that the original operations used to encode and decode the smaller LDPC codes remain as sub-components of the larger decoding and encoding system, additional overhead for the larger blocks can be reduced. Alternatively or concurrently, the smaller merged encoding and decoding blocks can also be used as their original form as encoding and decoding blocks of the smaller LDPC codes. Traditional devices may not support larger block sizes, so communication may revert the merged smaller blocks to their independent state as separate blocks for smaller codewords. Another advantage of preserving the original LDPC code structure as a substructure of larger codes is that, from a data processing perspective, transmitting larger blocks is very similar to transmitting multiple smaller blocks. In such examples, larger codewords can be integrated almost seamlessly into existing systems. In some examples, by maintaining the original structure of existing LDPC codes, the described techniques can be used to reduce the decoding and encoding complexity for LDPC codes. The described techniques can further support reduced hardware costs by reusing existing hardware to support extended LDPC codes.

[0042] Figure 1 A block diagram of an example wireless communication network 100 is shown. According to some aspects, the wireless communication network 100 can be an example of a wireless local area network (WLAN) such as a Wi-Fi network (and will be referred to as WLAN 100 below). For example, WLAN 100 can be a network implementing at least one standard of the IEEE 802.11 wireless communication protocol standard family (such as standards defined by the IEEE 802.11-2020 specification or its revisions, including but not limited to 802.11ay, 802.11ax, 802.11az, 802.11ba, 802.11bd, 802.11be, 802.11bf, and 802.11 modifications associated with Wi-Fi 8). WLAN 100 can include multiple wireless communication devices, such as wireless AP 102 and multiple wireless STA 104. Although Figure 1 Only one AP 102 is shown, but the WLAN network 100 may also include multiple APs 102. Figure 1The AP 102 in the text can represent various types of APs, including but not limited to enterprise-grade APs, single-band APs, dual-band APs, stand-alone APs, software-implemented APs (soft APs), and multi-link APs. The coverage and capacity of cellular networks (such as LTE, 5G NR, etc.) can be further improved by small cells supported by APs acting as micro base stations. Furthermore, small cells can also be used to establish dedicated cellular networks through radio area networks.

[0043] Each of STA 104 may also be referred to as a mobile station (MS), mobile device, mobile phone, wireless phone, access terminal (AT), user equipment (UE), subscriber station (SS), or subscriber unit, and other examples. STA 104 can represent a variety of devices, such as mobile phones, personal digital assistants (PDAs), other handheld devices, netbooks, laptops, tablets, laptop computers, Chrome-enabled computers, extended reality (XR) headsets, wearable devices, display devices (such as TVs (including smart TVs), computer monitors, navigation systems, etc.), music or other audio or stereo devices, remote control devices (“remote controllers”), printers, kitchen appliances (including smart refrigerators) or other home appliances, key fobs (such as those used in passive keyless entry and start (PKES) systems), Internet of Things (IoT) devices, and vehicles, and other examples. The various STA 104s in the network can communicate with each other via AP 102.

[0044] A single AP 102 and its associated set of STA 104s can be referred to as a Basic Service Set (BSS), which is managed by the corresponding AP 102. Figure 1 Example coverage area 108 of AP 102 is also shown, which may represent the Basic Service Area (BSA) of WLAN 100. The BSA can identify or indicate users via a Service Set Identifier (SSID) and other devices via a Basic Service Set Identifier (BSSID), which may be the Media Access Control (MAC) address of AP 102. AP 102 may periodically broadcast beacon frames (“beacons”) including the BSSID to enable any STA 104 within the wireless range of AP 102 to “associate” or reassociate with AP 102 to establish or maintain a corresponding communication link 106 with AP 102 (also referred to hereinafter as a “Wi-Fi link”). For example, the beacon may include an identifier or indication of the primary channel used by the corresponding AP 102 and timing synchronization functions for establishing or maintaining timing synchronization with AP 102. AP 102 can provide access to external networks to each STA 104 in the WLAN via the corresponding communication link 106.

[0045] To establish a communication link 106 with AP 102, each STA 104 is configured to perform a passive or active scanning operation (“scan”) on frequency channels in one or more frequency bands (e.g., 2.4 GHz, 5 GHz, 6 GHz, or 60 GHz bands). To perform a passive scan, STA 104 listens for beacons transmitted by the corresponding AP 102 at periodic time intervals (measured in units of time, where one TU may be equal to 1024 microseconds (μs)) called Target Beacon Transmission Time (TBTT). To perform an active scan, STA 104 generates probe requests and sequentially sends probe requests on each channel to be scanned, and listens for probe responses from AP 102. Each STA 104 can be configured to identify, determine, ascertain, or select an AP 102 to associate with based on scan information obtained through the passive or active scan, and perform authentication and association operations to establish a communication link 106 with the selected AP 102. At the end of the association operation, AP 102 assigns AP 102 to STA 104 to track the association identifier (AID) of STA 104.

[0046] Due to the increasing prevalence of wireless networks, STA 104 may have the opportunity to select one of many BSSs within its range or to choose from multiple APs 102, which together form an Extended Service Set (ESS) comprising multiple connected BSSs. The extended network station associated with WLAN 100 can be connected to a wired or wireless distribution system that allows multiple APs 102 to be connected within such an ESS. Therefore, STA 104 can be covered by more than one AP 102 and can be associated with different APs 102 at different times for different transmissions. Furthermore, after associating with an AP 102, STA 104 can periodically scan its surroundings to find a more suitable AP 102 to associate with. For example, a STA 104 moving relative to its associated AP 102 can perform a "roaming" scan to find another AP 102 with more desirable network characteristics (such as a higher Received Signal Strength Indicator (RSSI) or reduced traffic load).

[0047] AP 102 and STA 104 can operate and communicate (via the corresponding communication link 106) according to one or more standards in the IEEE 802.11 wireless communication protocol family. These standards define WLAN radio and baseband protocols for the PHY and MAC layers. AP 102 and STA 104 send and receive wireless communications (hereinafter also referred to as “Wi-Fi communication” or “wireless packets”) to each other in the form of PHY Protocol Data Units (PPDUs). AP 102 and STA 104 in WLAN 100 can transmit PPDUs on unlicensed spectrum, which can be a portion of the spectrum including bands traditionally used by Wi-Fi technologies (such as the 2.4 GHz band, 5 GHz band, 60 GHz band, 3.6 GHz band, and 900 MHz band). Some examples of AP 102 and STA 104 described herein can also communicate in other bands, such as the 5.9 GHz and 6 GHz bands, which can support both licensed and unlicensed communication. AP 102 and STA 104 can also communicate on other frequency bands (such as shared licensed bands), where multiple operators may have licenses to operate on one or more of the same or overlapping frequency bands.

[0048] Each frequency band can include multiple sub-bands or multiple frequency channels. For example, PPDUs conforming to the IEEE 802.11n, 802.11ac, 802.11ax, and 802.11be standard revisions can be transmitted on 2.4 GHz, 5 GHz, or 6 GHz bands, with each band divided into multiple 20 MHz channels. Therefore, these PPDUs are transmitted on physical channels with a minimum bandwidth of 20 MHz, but larger channels can be formed through channel bonding. For example, PPDUs can be transmitted on physical channels with bandwidths of 40 MHz, 80 MHz, 160 MHz, or 320 MHz by bonding multiple 20 MHz channels together.

[0049] Each PPDU is a composite structure comprising a PHY preamble and a payload in the form of a PHY Service Data Unit (PSDU). The receiving device can use the information provided in the preamble to decode subsequent data in the PSDU. When the PPDU is transmitted over a bonded channel, the preamble field can be copied and transmitted in each of the multiple component channels. The PHY preamble can include a traditional portion (or "traditional preamble") and a non-traditional portion (or "non-traditional preamble"). The traditional preamble can be used for packet detection, automatic gain control, channel estimation, and other purposes. The traditional preamble is also typically used to maintain compatibility with legacy equipment. The format of the non-traditional portion of the preamble, the encoding of the non-traditional portion, and the information provided in the non-traditional portion are associated with the specific IEEE 802.11 protocol to be used to transmit the payload.

[0050] In some wireless communication environments, Extremely High Throughput (EHT) systems or other systems compliant with the IEEE 802.11 wireless communication protocol family may offer additional capabilities than previous systems (e.g., High Efficiency (HE) systems or other legacy systems). EHT and newer wireless communication protocols can support flexible operating bandwidth enhancements at both the AP and STA (such as extended operating bandwidth or finer-grained operation relative to legacy operation). For example, EHT systems can allow communication across operating bandwidths of 20 MHz, 40 MHz, 80 MHz, 160 MHz, 240 MHz, and 320 MHz. EHT systems can support various bandwidth modes, such as a continuous 240 MHz bandwidth mode, a continuous 320 MHz bandwidth mode, a non-contiguous 160+160 MHz bandwidth mode, or a non-contiguous 80+80+80+80 (or "4x80") MHz bandwidth mode.

[0051] This operating bandwidth can also accommodate concurrent operation on other unlicensed frequency bands (such as the 6 GHz band) and portions of the spectrum including bands traditionally used by Wi-Fi technologies. In discontinuous examples, the operating bandwidth can span one or more completely different sub-channel sets. For example, a 320 MHz bandwidth could be continuous within the same 6 GHz band, or discontinuous across different frequency bands (such as partially within the 5 GHz band and partially within the 6 GHz band).

[0052] In some examples, operational enhancements, and particularly bandwidth-increasing operations, associated with the EHT and the newer generation of the IEEE 802.11 wireless communication protocol family may include improvements to carrier sensing and signal reporting mechanisms. These techniques may include modifications to existing rules, structures, or signals implemented for legacy systems.

[0053] In the wireless communication network 100, LDPC codes can be used as forward error correction codes to support accurate data transmission. Some LDPC encoding transmission schemes can be associated with relatively large and varying codeword lengths (including at least 648 bits, 1296 bits, and 1944 bits), and the codeword length may further increase with increasing bandwidth, the introduction of higher modulation orders, and the availability of more spatial streams. The various techniques described herein can support extended LDPC codewords with reduced impact on device hardware, and can also take full advantage of backward compatibility with the original LDPC codeword size by using extended enhancements of existing basemaps (such as extended enhancements of the 802.11 basemap for Wi-Fi), thereby maintaining the structure of the existing LDPC code in the extended code. To effectively extend LDPC codewords to improve performance without significantly increasing the burden on device hardware, wireless devices such as AP 102 can implement additional enhancements to extend existing enhancements of Wi-Fi codewords. For example, AP 102 can perform a first lift (such as cyclic lift) on the base graph to generate a Wi-Fi code, and apply additional lifts or re-lifts (such as additional cyclic lifts, product lifts, exchange lifts, or combinations thereof) to extend the current lift of the Wi-Fi LDPC base graph of size Z=81 (which generates a codeword length of 81x24=1944) to create a codeword with a length that is several times the length of the original code (e.g., 2x, 4x, 8x, 16x or more of the original code length).

[0054] Figure 2 An example of a wireless communication network 200 supporting extended LDPC codes for Wi-Fi is shown. For example, the wireless communication network 200 can show communication between AP 202 and STA 204.

[0055] LDPC codes are linear error-correcting codes constructed using sparse Tanner graphs (a subclass of bipartite graphs) and can be used to transmit data over relatively noisy channels. LDPC codes can be implemented to transmit data accurately and efficiently over channels with a code rate relatively close to the theoretical maximum value of the channel (e.g., the Shannon limit), thus effectively reducing the probability of information loss. In several communication standards such as Wireless Local Area Networks (WLAN, IEEE 802.11n), Wireless Radio Access Networks (WRAN, IEEE 802.22), Digital Video Broadcasting (DVB), and the Advanced Television Systems Committee (ATSC), LDPC codes can be implemented as forward error-correcting (FEC) codes. Alternatively or concurrently, LDPC coding can be used to support cellular wireless communications, such as fifth-generation (5G) communications, to enhance mobile broadband (eMBB) data channels.

[0056] In some implementations, such as in Wi-Fi, an OFDM symbol or frame can be constructed to contain multiple codewords of length -1944. Combining multiple codewords into a longer, extended codeword can improve channel and device performance. However, in some cases, the device encoders and decoders supporting extended LDPC codes (such as the decoders and encoders present at AP 202 and STA 204) may be limited by various power, area, latency, and cost constraints, which can pose challenges to implementing efficient hardware capable of LDPC encoding and decoding for extended LDPC codewords.

[0057] The various techniques described herein can support extended LDPC codewords using extended boosting of existing basegraphs (such as extended 802.11 basegraphs for Wi-Fi), thereby reducing the impact on device hardware. Extended boosting of existing basegraphs preserves the structure of the existing LDPC code in the extended code. In some examples, LDPC codes can be based on or generated from a small graph called a basegraph or “prototype graph,” which captures the macroscopic (e.g., node degree) structure of the code so that a larger graph with this structure can be constructed by boosting the basegraph. The boosted graph can be obtained by taking Z copies of the basegraph and permuting Z copies of the base edges between the Z copies. For example, some LDPC codewords of length 1944 bits can be constructed using a basegraph with 24 variable nodes and 81 Z values. In some examples, this requires connecting 81 copies of the base variable nodes to 81 copies of the base edges of 81 copies of the base check nodes. The 81 connections corresponding to the edges can be permuted to wrap around these 81 copies to form a larger connected graph. Permutations (e.g., permutations of Z copies of the base edges between the base variables and the Z copies of the check nodes) can be described via different promotion methods (e.g., cyclic promotion, product promotion, exchange promotion, or any combination thereof). Permutations are typically (at least in some implementations) represented as integers indexed to a particular permutation. Alternatively or additionally, extended permutations can be represented using extended internal or external representations, where existing permutation indices can be extended to low- or high-order numbers, and in some examples, to binary numbers.

[0058] To effectively extend LDPC codewords for performance improvement without significantly increasing hardware overhead, devices such as the AP 202 or STA 204 can implement additional enhancements to extend existing enhancements to Wi-Fi codewords. For example, the AP 202 can apply additional enhancements to extend the current enhancements of the Wi-Fi length-1944-bit LDPC codeword basemap to create codewords with a length several times that of the original 1944-bit codeword (e.g., 2x, 4x, 8x, 16x, or more of the original codeword length).

[0059] For example, at 206, AP 202 can generate a baseline or "raw" code by performing a first lift on the base matrix. For example, the first lift can produce an LDPC code used in current 802.11 Wi-Fi implementations. Then, at 208, AP 202 can perform a second lift or re-lift (e.g., cyclic lift, product lift, exchange lift, or a combination thereof) to generate an extended lift code. In some implementations, the extended lift code can be an extension of an existing Wi-Fi code so that the Wi-Fi code generated at 206 can be retained as part of the extended code. For example, one or more lift permutation matrices associated with the base edges of the first low-density parity check matrix used to perform the first lift can recover as block-by-block submatrices of the lift permutation matrices associated with the corresponding base edges of the extended low-density parity check matrix used to generate the extended code. AP 202 can then transmit the extended LDPC code as an extended or lifted codeword 210.

[0060] The techniques described in this paper can preserve existing code structures and minimize their impact on device hardware by generating extended LDPC codes composed of enhanced hybrids of smaller existing LDPC code structures. For example, certain aspects of the original LDPC code known to STA 204 can be preserved as sub-elements of the new extended LDPC code to reduce encoding and decoding complexity. In some examples, implementations supporting extended LDPC codes can revert to parallel implementations of the original LDPC code.

[0061] Figure 3 The example shows a base graph consisting of a set of variable nodes and check nodes, edges connecting the nodes, and a lifting process that introduces multiple copies of the base graph and replaces the lifted base edges. Figure 3 It can support a graphical representation of the lifting process, where a larger Tanner graph is constructed from the lifting of the base Tanner graph and an algebraic representation of the parity check matrix, where the entries of the base parity check matrix are replaced with square matrices whose size corresponds to the size of the lifting. Figure 3 The example shown here can be performed on or by various devices as described here.

[0062] The parity check matrix of an LDPC code can be represented by a Tanner graph or a bipartite graph, corresponding to the parity check matrix representation. In this representation, the rows of the parity check matrix correspond to the check nodes in the Tanner graph, and the columns correspond to the variable nodes. If the corresponding row and column have a "1" in the matrix, the check node and variable node can be connected by an edge; otherwise, no edge is represented by a "0" in the matrix.

[0063] Figure 3 Tanner graph 300 for an example LDPC code is shown. For example, Tanner graph 300 includes seven variable nodes V1 to V7, represented by seven circles, and four parity nodes C1 to C4, represented by four squares. Each variable node represents a code bit, which can be transmitted or punched (not transmitted). The seven code bits for variable nodes V1 to V7 constitute a codeword. Variable nodes are connected to parity nodes via edges. The basis parity matrix H corresponding to Tanner graph 300 may include seven columns for the seven variable nodes V1 to V7 and four rows for the four parity nodes C1 to C4. Each column of H includes a one-1 element for each edge connected to the variable node corresponding to that column. For example, column 1 includes three ones in rows 1, 2, and 3 for the three edges a, b, and c in Tanner graph 300 that connect the corresponding variable node V1 to parity nodes C1, C2, and C3. Each remaining column of H includes two or three ones for two or three edges that connect the corresponding variable node to two or three parity nodes. In some cases (such as certain generalized versions), a basis Tanner graph can have multiple edges, where variable nodes and parity nodes are connected by more than one edge. In such examples, the basis parity matrix does not have to be binary and can have integer terms greater than one to reflect the multiple edges.

[0064] Small base LDPC codes can be boosted to obtain larger boosted LDPC codes. The boosting can be described from a Tanner graph or algebraically. In an algebraic description, boosting is achieved by replacing each "1" element in the base parity matrix for the base LDPC code with a Z×Z permutation matrix, and replacing the "0" elements with a Z×Z "0" matrix, thus obtaining a boosted parity matrix for the boosted LDPC code, which can be Z times larger than the base code. From a graphical perspective, Z copies of the base graph for the base LDPC code can be generated. The Z×Z permutation matrix in the boosted parity matrix corresponds to the permutation of the boosted edges connecting the variable nodes in each graph copy to the parity nodes in the Z graph copies. For example, each non-zero element of H (corresponding to an edge in the Tanner graph) is replaced with a Z×Z permutation matrix to obtain the expanded graph 302 and the boosted parity matrix H. Specifically, the small graph corresponds to the constructed basis H, and in the lifting, each element of the basis parity matrix H is replaced with a ZxZ matrix (e.g., an edge (“1”) can be replaced with a cyclic permutation matrix (σ)).

[0065] In the compressed visual representation 304, items in the grid can represent edges in the lifted graph, where columns correspond to base edges and the number of rows corresponds to the lift size Z. Base edges are associated with both base variable nodes and base check nodes. In the lifted representation, the corresponding columns are connected by permutations. Z copies of each edge can be cyclically shifted by an amount determined by the cyclic permutation matrix for that edge. The grid can show Z parallel nodes and edges, and can illustrate efficient parallel encoding as a Z-parallel implementation of the base decoder and encoder.

[0066] Given a parity check matrix, any permutation row may not change the code, while a permutation column is equivalent to the elements (bits) of the permuted codeword. When lifting is performed, the order of the bits in the lifted code corresponds to the base order, and each bit in the base code is replaced with a vector of Z bits, where Z is the lifting size.

[0067] In some examples, extended lifting can be performed according to the techniques and structures described herein to preserve the existing lifting structure. For example, performing extended lifting on Tanner graph 300 can produce extended LDPC codes consisting of smaller existing LDPC structures corresponding to smaller liftings. For example, one or more lifted permutation matrices associated with a first matrix derived from a first lifting can recover block-by-block submatrices of the extended lifted permutation matrices associated with the base edges of the base graphs associated with the two liftings.

[0068] Figure 4 Examples of LDPC decoding processes 400-a and 400-b performed via a layered decoding process supporting extended (e.g., for Wi-Fi) LDPC codes are shown. In some examples, LDPC decoding processes 400-a and 400-b may be performed at or by one or more wireless devices described herein.

[0069] Figure 4 The LDPC decoder stream can be shown, including the stream for the Zx24 memory grid (V). memThe LDPC decoding process 400-a is shown. Columns represent Z images of the base variable nodes, where a value is stored as part of the decoding process. In some examples, the LDPC code can be decoded via a message-passing algorithm that iteratively exchanges messages along the edges between the variable nodes and the check nodes. In some examples, such as decoding aligned cyclic LDPC codes (using cyclic permutation for lifting), the decoder can read column 404 from memory 402 and permutate column 404 to align the lifted variable node values ​​with the lifted check node values. The decoder can then obtain the updated message 406 by subtracting the obtained previous check node message vector d from the stored compressed check output to obtain the vector input for parallel check node processing. The decoder can then perform parallel processing (such as Z parallel check node processing) to obtain the vector message 408(d') emitted from the parallel check node processors along the lifted edges.

[0070] Alternatively, at LDPC decoding process 400-b, the device can bundle multiple such grids together for LDPC decoding of the expanded code. For example, the decoder can expand Z to 2Z to perform decoding on a boost that is expanded by a factor of 2. The decoder can take one column 412 from each of two Zx24 memories 410 and permutate the merged concatenated columns to align with the corresponding 2Z parity nodes, which can be considered as two copies of Z parity nodes. The decoder can then subtract the obtained message d from the stored compressed parity output to obtain the updated parity node input message 414. The decoder can then perform parallel processing (e.g., 2Z parallel parity node processing) to obtain the decoded message 416(d'). Decoding the expanded code described herein can reduce the decoder complexity at least in part due to the reuse of the Z parallel structure. If the permutation of the 2Z concatenated elements is a cyclic permutation, then the implementation of the 2Z cyclic permutation cannot be significantly improved by existing permutation operations of size Z. The technique described herein can achieve improved hardware reuse by decomposing the 2Z vector in another way.

[0071] Figure 5 An example of an effective extended cyclic boost 500 is shown, illustrated in this example as a 4x increase, which is performed as a two-step process involving a block cyclic shift of the Z vector followed by an intra-vector cyclic shift. For example, if the first boosted code with cyclic permutation R is associated with a boosted edge, then in some examples the extended cyclic boost reuses the cyclic shift of R on the smaller Z vector, but a cyclic shift of R+1 can also be achieved. In this extension, four copies of a column of size Z can be interleaved to form a 4Z bit vector and cannot be concatenated. In some examples, the cyclic boost 500 can be performed by one or more wireless devices described herein.

[0072] LDPC codes for different implementations (such as Wi-Fi) can be designed using base graph lifting. For example, some LDPC codes for Wi-Fi implementations can utilize cyclic groups for lifting (e.g., a length 1944 code can use a lifting size Z = 81). To support extended LDPC codes by re-lifting existing codes, different groups (such as cyclic lifting, product lifting, swap-based lifting, other liftings in the design of LDPC codes) can be used. For example, an extended length Lx1944 codeword can have a combined lifting size Z’ = LxZ, and the lifting for the length Lx1944 codeword can be cyclic lifting. In some implementations, a device can use a second cyclic lifting step to perform re-lifting and extension of Wi-Fi codes.

[0073] The extension of the permutation associated with lifting described herein can be defined using an internal representation or an external representation. Depending on the group structure associated with the extension, an internal representation can be used to maintain the hardware structure for the current code to support efficient hardware implementations. Specifically, the current code (supported by hardware) can be recovered from the extended code such that the extended code is supported by the hardware that supports the first lifting. In one example, re-lifting a base graph by L = 4 to obtain Z’ = 4x81 = 324 for a Wi-Fi code (copying the base graph 81 times) and copying it more than 4 times may be required. If the original lifting of an edge is R, the cyclic permutation is R<Z, and the extended lifting is also cyclic, then for the extended permutation, the cyclic permutation uses an internal extension to obtain a cyclic permutation value of 4R+z, where z is 0, 1, 2, or 3, which can maintain the original permutation of size R on the Z vector, as Figure 5 shown.

[0074] In some examples, each promoted node corresponding to the base node can be indexed by an integer x between 0 and 323 (e.g., Z' = 324). Each node can be equivalently identified by an integer pair (a, b), where a is between 0 and 80, and b is between 0 and 3. These integer pairs allow the extended promoted bit vector to be interpreted in a bit order different from the bit order typically associated with cyclic promotion. Integer pair indexing facilitates the decomposition of the extended promotion, thus preserving the structure of the original promotion. In some examples, a node can be identified by a (a, b) pair, where “a” may correspond to the node selected from the Z = 81 replicas associated with the first promotion, and “b” may correspond to the selection from the L = 4 replicas out of the Z = 81 replicas of the first promotion. To convert between the two node representations x and (a, b), the device can use an internal representation and an external representation. The internal representation can be used to convert between x, a, and b using the formula x = 4a + b. In the case of this internal representation, a = x / 4 (where a can be rounded down to the nearest integer). The external representation can be converted between x, a, and b using the formula x = 81b + a, where a = (x mod 81).

[0075] In some examples, the extended LDPC code can use cyclic lifting. For the implementation of cyclic lifting, the index of the lifted variable node can be represented as v. n And the verification node can be represented as c n .v n , where v n and c n For integers between 0 and 323. When performing loop promotion on the y-value, the variable node v... n Connect to verification node c n =(v n +y)mod324.

[0076] The extended promotion index and associated cyclic permutation can be represented using integer pairs to indicate the first and second promotion factors. An example using (a, b) representation and outer extension for cyclic promotion can be shown below:

[0077] v n =81b+a, y=81b′+a′ and c n =81b″+a″,

[0078] In this form, "b" is 0, 1, 2, or 3, and "a" is 0, ..., 80. In this form, "a" represents the first hoisting and "b" represents the second hoisting. The second hoisting value is in the higher-order digit, and the first hoisting value is in the lower-order digit.

[0079] Another example of using (a, b) to represent the cyclic lifting of the outer extension can be seen as follows:

[0080] v n =4a+b, y=4a′+b′ and c n =4a″+b″,

[0081] Where "b" is 0, 1, 2, or 3 and "a" is 0…80. Here, "a" represents the first lifting and "b" represents the second lifting. The second lifting value is in the lower-order number, and the first lifting value is in the higher-lower-order number.

[0082] For internal extensions, use C. n =(v n Calculating (b+b') mod 324 will yield a″ = (a+a'+(b+b') / 4) mod 81, b″ = (b+b') mod 4, where (b+b') / 4 divided by (b+b') equals 4 and is rounded down to the nearest integer. In such examples, b″ can be independent of either a or a'.

[0083] The loop group representing loop lifting "almost" treats a and b as independent operations because for both representations, only one coordinate is independent of the other. In some implementations, all variable nodes v with the same b" value in the (a, b) representation... n All are mapped to check nodes c that have the same b” in the (a”, b”) representation. n In this case, the representation of b” can be independent of a and a', and the internal representation satisfies this, b″=(b+b′)mod 4.

[0084] In another example, a second lift can be applied to the first lift to extend the LDPC code. The first lift can be a cyclic lift of size Z, where each permutation matrix replacing a "1" in the base parity matrix is ​​a power of the shift matrix. Then, for the second lift, the first cyclic shift becomes larger, Z' = LZ (e.g., using L = 2, 4, 8, or 16, a larger Z' = 2x, 4x, 8x, or 16x). If the first cyclic shift is a, then the extended shift can be written as a + Z * b, where b is 0, 1, ..., L-1. The original cyclic shift can then be recovered from the extended shift by taking the value of the modulus Z. When using inner cyclic extension, the cyclic shift value can be written as La + b, and when L is a power of 2, the original first cyclic shift can be recovered by removing the least significant bit of L from the binary representation.

[0085] like Figure 5As shown, multiple grids Z can be bundled together for cyclic lifting and for LDPC decoding. For example, the decoder can extend Z to 4Z and perform a cyclic shift over the entire 4Z vector. The decoder can take one column from each of the four Z memories and permutate the columns to align with the corresponding parity nodes. If the 4Z vector order is given by (a, b) notation, where “a” is selected in the Z vector and “b” equals 0, 1, 2, or 3 and is selected in the copy, and for some b’, the overall cyclic permutation is 4R+b’, then the decoder can perform the cyclic shift as follows: first perform a cyclic shift of size b’ in the 4Z vector, and then perform a cyclic shift of value R or R+1 in the Z vector. At least one Z vector can use the cyclic shift R. If R is the value of the first lift, then in this implementation, the cyclic shift of the 4Z vector is largely maintained as an operation on the Z vector. In some examples, the device can perform additional pervading vector identity shifts for bundling, where the pass-through setup implementing identity permutations restores the structure to four independent decoders. If b' = 0, then at least in some examples, there are no permutations between them, and each Z vector is permuted by a cyclic permutation R. In such examples, the structure can be used to decode four first lifts in parallel. By relaxing the synchronization of parallel operations and allowing different permutations in the four copies, four independent decoders of the first lift can be recovered.

[0086] Figure 6 An example of product lifting performed on a first lifted code of an LDPC code supporting extensions for Wi-Fi is shown. In some examples, product lifting 600 can be performed by one or more wireless devices as described herein. In product lifting, the lifting extension can be achieved by performing independent permutations on the Z vectors so that the permutations within each Z vector are identical. In this implementation, each permutation on the Z vector can be equal to the first lifting value, while larger lifting structures are achieved via permutations between Z vectors.

[0087] Besides cyclic lifting, some LDPC codes used in Wi-Fi implementations can be extended using product lifting or exchange lifting (which can be the type of product lifting). This is achieved by re-lifting and extending the Wi-Fi code using a second separate cyclic lifting or exchange lifting step, which can be a cyclic shift of size 2, or more generally, a cyclic shift of size 2 consisting of k-dimensional cyclic shifts (each of size 2). kThe shift can be described using either an internal or external representation. For example, an internal representation can preserve the hardware structure used for the current code to support efficient hardware implementations. Specifically, the current code (hardware-backed) can be recovered from the extended code, so that the extended code can also be hardware-backed. In implementations of product lifting, the first and second liftings can be independent. In such examples, the first lifting structure can be preserved regardless of whether the extended representation is internal or external. Furthermore, the enumeration of bits in the extended bit vector can be aligned accordingly with the internal or external extension to support the recovery of the first lifting as a component of the extended lifting.

[0088] In transmissions using first-lifted LDPC codewords, such as in Wi-Fi, bits in the LDPC codeword are mapped to symbols, such as QAM constellations. LDPC codewords can be enumerated for such mappings, and the structure utilizing the lifted codewords can also be enumerated. LDPC codewords consist of Z*V bits, where V is the number of basic variable nodes; for example, V = 24 for some Wi-Fi implementations. Z*V bits can also be arranged in a ZxV two-dimensional array. The selection of bits used for mapping to transmission symbols (e.g., constellation mapping) can occur with row-wise or column-wise priority. For extended LDPC codes, this enumeration can include a first enumeration in the Z dimension followed by the V dimension, regardless of the mapping performed. This corresponds to column-wise enumeration of the two-dimensional array. The bits of an extended LDPC codeword can be viewed as multiple two-dimensional arrays (e.g., multiple L-fold arrays), and the order within the Z dimension can be maintained to facilitate reuse of pre-existing transmission structures. The mapping of extended codewords to transmission resources can simulate the mapping that can occur for corresponding multiple first-lifted codewords.

[0089] In some examples, the size of the allowed set of edge permutations and the size of the lift can be the same, for example, equal to Z. The Z vector resulting from the lift (whether it is a lifted base variable node, check node, or edge) can be indexed by integers 0, 1, ..., Z-1, and the permutations associated with the lifted base edges can also be represented by such integers. For an extended lift that includes a first lift and a second lift, the extended lift can be identified by a pair of integers, where one element of the pair represents the first lift step and the other element represents the second lift step. Two integers can be combined into a single integer to represent the extended lift, and the method of merging is related to the interpretation of the extended lift.

[0090] There can be one or more ways to merge two integers that correspond to the inner and outer lifts, respectively. In the inner lift, the value of the second lift can be placed in the lower-order part of the merged value, and in the outer lift, the value of the second lift can be placed in the higher-order part of the merged value. The choice of inner to outer lift reflects the bit order in the codeword transmission and the architectural decomposition of the expanded lift. In some examples, each of the expanded lifted nodes, edges, or permutations can correspond to an integer x between 0 and 323 (e.g., Z' = 324), and each of the vector elements can also be identified by the integer pair (a, b), where "a" is between 0 and 80 and "b" is between 0 and 3. When an element is identified by the pair (a, b), "a" can correspond to the selection within the first lift of Z = 81, and "b" can correspond to the selection within the second lift of size 4. To convert between the two representations of x and (a, b), the device can use both the inner and outer representations. The inner representation can be converted between x, a, and b using the formula x = 4a + b. In this internal representation, a = x / 4 (where a can be rounded down to the nearest integer). The external representation can be converted between x, a, and b using the formula x = 81b + a, where a = (x mod 81). The permutation associated with the extended lifted edge can also be represented by a pair (a', b'), thus representing the permutation on such a pair. In some examples, product lifting can be used to extend the LDPC code, where the two elements representing the permutation act independently on their respective elements (e.g., node pairs) to determine the extended permutation. In this example, the extended lifting factor enters into the first and second lifting. In other examples, the second lifting can be a swap lifting, which is in the form of product lifting, where the second lifting performs pairwise swaps of vectors. In other examples, the extended lifting is a cyclic lifting that is not product lifting. In such examples, the two elements represented by the lifting pair may not act independently.

[0091] Product lifting can be defined using operations directly on a and b. For example, the permutation (a, b) can be applied to (a', b') to produce (a", b") via: a″ = (a + a') mod 81, and b″ = (b + b') mod 4. In this example, both the first and second liftings are cyclic liftings, and the extended lifting is the product of these two cyclic liftings. For LDPC codes designed using product lifting, a and b can be combined using either an external or internal representation, where the permutations used in the lifting are defined on a and b, respectively. In this example, the two representations can be equivalent because they define the same lifting operation. However, it should be noted that, for the sake of hardware reuse through extended lifting, the codeword bit order can be considered as being in the internal extension. If an external extension is used to represent the lifting, the preferred bit order for the codeword bits will still be in the internal extension order when the first and second permutations are represented independently. For this purpose, an internal extension representation of the lifting value can be used.

[0092] The integer index of a promoted variable node can be represented as v n And the integer index of the verification node can be represented as c n In some examples, v n and c n It can be an integer between 0 and 323. In some examples, the internal representation used for promotion can allow the value v. n and c n Described in binary form, where the value of b can be determined by the least significant bit (LSB) v. n =4a+b can be obtained directly, and the value of a can be converted from the most significant bit (MSB).

[0093] In some other examples, the device can implement swap lift to extend the LDPC code. In such an example, x can be represented by an integer triplet of (a, b, c), where the second lift consists of two consecutive lifts of size 2, or equivalently, the second lift itself is a product lift with two factors, where "a" is an integer between 0 and 80 representing the first lift (e.g., an existing Wi-Fi lift), and b and c are both 0 or 1, and for the internal representation, x = 4a + 2b + c. The swap lift operation corresponding to the permutation (a, b, c) of node indices (a', b', c') to (a", b", c") can be defined as:

[0094] a″=(a+a′)mod 81

[0095] b″=(b+b′)mod 2

[0096] c″=(c+c′)mod 2.

[0097] After defining the boost for the case Z' = 4x81 using swap boosting, a boost for Z = 2x81 can be obtained by discarding c, and a boost for the original Z = 81 can be obtained by discarding both b and c and keeping only a. Alternatively, for other cases (e.g., Z = 2x4x81 = 8x81), an additional bit "d" can be introduced and defined as d" = (d + d') mod 2, similar to the definition of b and c.

[0098] like Figure 6 As shown, multiple grids representing the height Z of the memory storage for, for example, the first raised LPDC code can be bundled together to perform extended raised LDPC operations involving product and swapping of the extended raised. For example, the decoder can extend Z to 4Z and can perform swapping of the entire Z or 2Z vector. The decoder can take one column from each of the four Z-memories and permutate the column to align with the corresponding check node. The decoder can perform shifts (such as R) within the Z vector, where R is the permutation value associated with the first raised. In some examples, the device can perform additional shifts across the vector for bundling, where the configuration restores the structure to four independent decoders.

[0099] Figure 7 Example cyclic permutations 700-a, 700-b, 700-c, and 700-d are shown, illustrating cyclic shift operations supporting LDPC codes extended for Wi-Fi. In some examples, the cyclic permutation may be associated with cyclic lifting as described herein, and may be performed at or by one or more wireless devices described herein.

[0100] LDPC codes for different implementations (such as Wi-Fi) can be designed using boosting and re-boosting; for example, some codes can be boosted using cyclic groups. To support extended LDPC codes via re-boosting of existing codes, different groups (e.g., cyclic groups) can be used. In some implementations, the device can use a second cyclic boosting step to perform re-boosting and extension of the Wi-Fi code.

[0101] Cyclic permutation example 700-a can show an approximate factorization of a cyclic group where Z = 13. For example, matrix 702-a can undergo column-to-row permutation and cyclic shift 704 (which can be a cyclic shift of 1) to produce the shifted matrix 702-b. In this case, the columns can be cyclically shifted, and the rows can be cyclically shifted while wrapping around.

[0102] Cyclic permutation example 700-b can illustrate the interleaved case, where, during cyclic shift 706, each row of matrix 702-c undergoes a cyclic shift of b = (K / 4), where (K / 4) represents the integer obtained by rounding down $K / 4.$, and each column of matrix 702-c undergoes a cyclic shift of a = (K / 4) or a = (K / 4) + 1 to produce matrix 702-d. In such an interleaved case, K can be equal to 4*(K / 4) + (K / 4).

[0103] Example 700-c of cyclic permutations illustrates an example of a cyclic product that demonstrates a true factorization product of cyclic shifts. For instance, each column of matrix 702-e can undergo the same rotation to produce a shifted matrix 702-f. Alternatively, each row of matrix 702-e can undergo the same rotation to produce a shifted matrix 702-f. In such an example, the shifted matrix 702-f can be a product of cyclic lifting. Furthermore, the column permutations of matrix 702-f can be the same as the current 802.11 value.

[0104] Cyclic permutation example 700-d can illustrate example exchange cases (e.g., 3D product cyclic cases) that show alternative or alternative cyclic product cases. For example, each column of matrix 702-g can undergo the same rotation to produce a shifted matrix 702-h. Alternatively, each row of matrix 702-g can undergo the same rotation to produce a shifted matrix 702-h. The product cyclic example of 700-d can support multiple product cyclic promotions, where column permutations can be the same as the current 802.11 values. Additionally, the product cyclic example of 700-d can implement exchange-switching structures instead of fully cyclic structures (such as structures equivalent to 2D product cyclic structures).

[0105] Figure 8 Examples 800-a, 800-b, and 800-c are shown illustrating the first lift of the LDPC code for Wi-Fi.

[0106] In the first example 800-a, a cyclic shift of the base can be implemented. For the shift matrix 802-a (matrix S), the first lift can be a cyclic lift of size Z (e.g., Z can be an integer, such as Z = 7 in example 800-a). In such an example, each permutation matrix replacing the "1" terms in the base parity check matrix can be a power of the shift matrix 802-a. For example, if the cyclic shift 804 is a cyclic shift of 3, then the shifted matrix 802-b (matrix S) 3 It can be shifted cyclically as shown in the figure.

[0107] Additionally, in Example 800-b, the cyclic shift can be made larger (e.g., a factor of one or more, such as a factor of four or any other integer multiple of a factor ... 3 It is obtained by using each 0 and each 1 in the formula.

[0108] Example 800-b can illustrate the inner cyclic extension 806, where the cyclic shift value is equal to 4a+b. For example, if b=2, the codewords are reordered, and the new permutation matrix is ​​where each submatrix is ​​ZxZ, and S a It is a block-by-block submatrix that can be recovered from the permutation matrix.

[0109] Example 800-c can illustrate an inner representation product expansion where the expanded permutation matrix is ​​a Kronecker product of two permutation matrices, each derived from two lifting steps. For example, a second lifting factor can be on the left side of the product. In this case, the permutation matrix is ​​expanded by 4 with a cyclic shift of 2 to produce the permutation matrix associated with the inner product expansion 808. Here, S a This can be a block-by-block submatrix that can be recovered from the permutation matrix. Alternatively or concurrently, the matrix structure associated with the exchange permutation 810 can be obtained by performing an exchange permutation for the second step (of size 4). In either example, the second lift (e.g., product, cyclic, or exchange lift) can support the block-by-block submatrix recovery (S) of the first lift. a ).

[0110] Figure 9 An example of a process flow 900 illustrating signaling between wireless devices on a wireless link supporting Extended LDPC codes for Wi-Fi is shown. Process flow 900 can be implemented or may be implemented to implement or facilitate aspects of wireless communication network 100. For example, process flow 900 illustrates communication between a first wireless device 902 and a second wireless device 904, which could be an example of the corresponding wireless devices described herein. (As shown by...) Figure 9 The first wireless device 902 and the second wireless device 904 shown and described herein may be examples of the corresponding devices shown and described herein, including references. Figure 1 .

[0111] In the following description of process flow 900, operations may be performed (e.g., reporting or providing) in a different order than those shown, or the operations performed by the example device may be performed in a different order or at different times. Some operations may also be omitted from process flow 900, or other operations may be added to process flow 900. Furthermore, although some operations or signaling may be shown to occur at different times for discussion purposes, these operations may actually occur simultaneously.

[0112] At 906, the first wireless device 902 can generate a first low-density parity check matrix and a first low-density parity check code by performing a first lift on the basis matrix.

[0113] At 908, the first wireless device 902 can generate an extended low-density parity check (LDPC) code corresponding to the extended LPC matrix by performing a second lifting on the first LPC matrix. For example, performing the second lifting can allow the lifted permutation matrix associated with the base edges of the first LPC matrix to be recovered as a block-by-block submatrix of one or more lifted permutation matrices associated with the corresponding base edges of the extended LPC matrix. For example, the second lifting permutation for the base edges of the first LPC matrix can be associated with, for example, Z, lifted variable nodes, and one or more parity nodes from the first lifting. In such an example, the extended LPC code can be an extension of the first LPC code (i.e., the extended LPC code can be longer than the first LPC code based on the second lifting).

[0114] In some examples, the expanded low-density parity matrix may be associated with a two-step lifting process, including a first lifting step and a second lifting step, wherein the second lifting step is applied to the result of the first lifting step to produce the expanded lifting. The two-step lifting may include a process of generating integer pairs (e.g., (a, b) integer pairs) to identify one or more images of the first low-density parity boosted bit vector within the corresponding expanded and boosted low-density parity bit vector. In some examples, the first integer of the integer pair may correspond to the first lifting step, and the second integer of the integer pair may correspond to the second lifting step, and the bits of the first low-density parity boosted bit vector of the expanded low-density parity boosted bit vector are first enumerated based on the first integer of the integer pair used to identify the bits within the first low-density parity boosted bit vector, and the bits of the first low-density parity boosted bit vector of the expanded low-density parity boosted bit vector are second enumerated based on the second integer of the integer pair used to identify the images of the first low-density parity boosted bit vector within the expanded low-density parity boosted bit vector.

[0115] LDPC codewords can be enumerated for such a mapping, and the enumeration utilizes the enhanced structure of the codewords. For an extended LDPC codeword, this enumeration can include a first enumeration in the Z dimension followed by the V dimension, regardless of the mapping performed. This corresponds to column-wise enumeration of a two-dimensional array, which can include codeword bits. The bits of an extended LDPC codeword can be viewed as multiple two-dimensional arrays, and the order within the Z dimension can be maintained to facilitate reuse of pre-existing transmission structures.

[0116] The first wireless device 902 can perform a first boosting step and a second boosting step based on either an internal or external expansion of the first boosting to generate an expanded low-density parity check (LDPC) code. In some examples of performing the second boosting step based on an internal expansion, the second boosting step can retain the first LPC boosting as a subcomponent of the expanded LPC boosting. For example, the second boosting can be recovered from the first boosting by applying a bitmask, modulo operation, or both. In some other examples of performing the second boosting step based on an external expansion, the second boosting step can retain the first LPC boosting as a subcomponent of the expanded LPC boosting based on the first boosting being recoverable from the second boosting by applying a modulo operation. In some examples, the first boosting step can be associated with the second boosting step via a boosting factor and a modulo operation.

[0117] In some implementations, according to product lifting, the first lifting (corresponding to the first integer of the integer pair) is independent of the second lifting (corresponding to the second integer of the integer pair). Additionally or alternatively, the block-by-block submatrix corresponding to the permutation of the image of the first lifting is the same submatrix. In some other implementations, the first wireless device 902 may perform swap lifting, wherein the first wireless device 902 swaps at least two images of one or more images of the first low-density parity-check code during the first lifting step or the second lifting step.

[0118] In some examples, the extended low-density parity code includes one or more images of an enhanced low-density parity code, which at least includes a first low-density parity code recoverable from the extended low-density parity code. In this case, the structure of the first low-density parity code can be preserved in the extended low-density parity code.

[0119] At 910, the first wireless device 902 can encode the first set of bits according to the extended low-density parity-check matrix and the extended low-density parity-check code, which can produce an enhanced codeword for transmission.

[0120] At 912, the first wireless device 902 can perform the transmission of the enhanced codeword to the second wireless device 904.

[0121] Figure 10 A flowchart illustrating an example process 1000 that can be performed at a wireless device supporting LDPC codes extended for Wi-Fi, according to some aspects of this disclosure, is shown. The operation of process 1000 can be implemented by a wireless device such as the wireless receiving device described herein (e.g., a wireless AP or non-AP STA) or its components. For example, process 1000 can be implemented by a wireless communication device (such as referenced...) Figure 1 and 2 The described wireless communication device performs the operation either as a wireless access point (AP) or within a wireless AP. In some implementations, process 1000 may be performed by a wireless AP (such as those described in the reference). Figure 1 The AP described in AP 102 is used to perform this action.

[0122] In some examples, at box 1002, the wireless device can generate a first low-density parity-check matrix and a first low-density parity-check code by performing a first lifting operation on the basis matrix. The operation of 1002 can be performed according to examples disclosed herein. In some examples, aspects of the operation of 1002 can be derived from references... Figure 12 The first lifting component 1202 is described and executed.

[0123] In some examples, at block 1004, the wireless device can generate an expanded low-density parity-check (LDPC) matrix and an expanded LPC code by performing a second lifting operation on the first LPC matrix. One or more lifted permutation matrices associated with the base edges of the first LPC matrix can be recovered as block-by-block submatrices of one or more lifted permutation matrices associated with the corresponding base edges of the expanded LPC matrix. The expanded LPC code is an extension of the first LPC code. The operation of 1004 can be performed according to the examples disclosed herein. In some examples, aspects of the operation of 1004 can be derived from, as referenced... Figure 12 The second lifting component 1204 is described and executed.

[0124] In some examples, at block 1006, the wireless device may encode the first multi-bit set according to an extended low-density parity-check matrix and an extended low-density parity-check code to produce an elevated codeword. The operation of 1006 can be performed according to examples disclosed herein. In some examples, aspects of the operation of 1006 may be performed by an LDPC encoding component 1206 as described with reference to 12.

[0125] In some examples, at box 1008, the wireless device can perform the transmission of the raised codeword to a second wireless device. The operation of 1008 can be performed according to the examples disclosed herein. In some examples, aspects of the operation of 1008 can be performed by the LDPC encoding component 1206 as described with reference to 12.

[0126] Figure 11 A flowchart illustrating an example process 1100 that can be performed at a wireless device supporting LDPC codes extended for Wi-Fi, according to some aspects of this disclosure, is shown. The operation of method 1100 can be implemented by a network device (such as a wireless STA) or its components as described herein. For example, process 1100 can be implemented by a wireless communication device (such as a reference STA). Figure 1 and 2 The described operation is performed by a wireless device or a wireless communication device operating within a wireless device. In some examples, process 1100 may be performed by a wireless device (such as reference 1100). Figure 1 The STA described in STA 104 is used to perform this action.

[0127] In some examples, at block 1102, the wireless device can generate a first low-density parity-check matrix and a first low-density parity-check code by performing a first lifting operation on the basis matrix. The operation of 1102 can be performed according to examples disclosed herein. In some examples, aspects of the operation of 1102 can be derived from, as referenced... Figure 13 The first lifting component 1302 is described and executed.

[0128] In some examples, at block 1104, the wireless device can generate an expanded low-density parity-check (LDPC) matrix and an expanded LPC code by performing a second lifting operation on the first LPC matrix. One or more lifted permutation matrices associated with the base edges of the first LPC matrix can be recovered as block-by-block submatrices of one or more lifted permutation matrices associated with the corresponding base edges of the expanded LPC matrix. The expanded LPC code is an extension of the first LPC code. The operation of 1104 can be performed according to the examples disclosed herein. In some examples, aspects of the operation of 1104 can be derived from, as referenced... Figure 13 The second lifting component 1304 is described and executed.

[0129] In some examples, at box 1106, the wireless device can receive, from a first wireless device such as an AP, an elevated codeword encoded based on an extended low-density parity-check matrix. The operation of 1106 can be performed according to examples disclosed herein. In some examples, aspects of the operation of 1106 can be derived from, as referenced... Figure 13 The decoding component 1306 described is used to perform this.

[0130] In some examples, at box 1108, the wireless device can decode the raised codeword based on an extended low-density parity-check code. The operation of 1108 can be performed according to examples disclosed herein. In some examples, aspects of the operation of 1108 can be derived from, as referenced... Figure 13 The decoding component 1306 described is used for execution.

[0131] Figure 12 A block diagram of an example wireless communication device 1200 supporting extended LDPC codes for Wi-Fi according to some aspects of this disclosure is shown. In some examples, the wireless communication device 1200 is configured or operable to perform reference... Figure 10 The process 1000 is described. In various examples, the wireless communication device 1200 may be a chip, SoC, chipset, package, or device, which may include: one or more modems (such as Wi-Fi, Wi-Fi (IEEE 802.11) modems, or cellular modems such as 3GPP 4G LTE or 5G compatible modems); one or more processors, processing blocks, or processing elements (collectively, “processors”); one or more radio units (collectively, “radio units”); and one or more memories or memory blocks (collectively, “memory”).

[0132] In some examples, the wireless communication device 1200 may be used for use in an AP (such as reference). Figure 1 The device used in the described AP 102). In some other examples, the wireless communication device 1200 may be an AP including such a chip, SoC, chipset, package, or device, and multiple antennas. The wireless communication device 1200 is capable of transmitting and receiving wireless communications, for example, in the form of wireless packets. For example, the wireless communication device may be configured or operated to transmit and receive packets in the form of physical layer PPDUs conforming to one or more standards in the IEEE 802.11 wireless communication protocol family. In some examples, the wireless communication device 1200 also includes or may be coupled to an application processor, which may be further coupled to another memory. In some examples, the wireless communication device 1200 also includes at least one external network interface that enables communication with the core network or backhaul network to obtain access to external networks, including the Internet.

[0133] Wireless communication device 1200 includes a first boosting component 1202, a second boosting component 1204, an LDPC encoding component 1206, an integer pair generation component 1208, an extended application component 1210, and a switching boosting component 1212. A portion of one or more of components 1202, 1204, 1206, 1208, 1210, and 1212 may be implemented at least partially using hardware or firmware. For example, the first boosting component 1202 or the second boosting component 1204 may be implemented at least partially by a modem. In some examples, at least some of components 1202, 1204, 1206, 1208, 1210, and 1212 are implemented at least partially by a processor and software stored in memory. For example, portions of one or more of components 1202, 1204, 1206, 1208, 1210, or 1212 may be implemented as non-transitory instructions (or "code") executable by a processor to perform the function or operation of the corresponding module.

[0134] In some implementations, the processor may be a component of a processing system. A processing system generally refers to a system or a series of machines or components that receive and process inputs to produce outputs (the set of outputs may be passed to other systems or, for example, components of device 1200). For example, the processing system of device 1200 may refer to a system that includes various other components or sub-components of device 1200, such as a processor, transceiver, communication manager, or other components or combinations of components of device 1200. The processing system of device 1200 may interface with other components of device 1200 and may process information received from other components (such as inputs or signals) or output information to other components. For example, the chip or modem of device 1200 may include a processing system, a first interface for outputting information, and a second interface for acquiring information. In some implementations, the first interface may refer to the interface between the processing system of the chip or modem and the transmitter, enabling device 1200 to send information output from the chip or modem. In some implementations, the second interface may refer to the interface between the processing system of the chip or modem and the receiver, enabling device 1200 to receive information or signal input, and the information can be transmitted to the processing system. Those skilled in the art will readily recognize that the first interface can also receive information or signal input, and the second interface can also output information or signal.

[0135] The first lifting component 1202 can be configured or operable to generate a first low-density parity check matrix and a first low-density parity check code by performing a first lifting on the base matrix.

[0136] The second lifting component 1204 can be configured or operable to generate an expanded low-density parity check matrix and an expanded low-density parity check code by performing a second lifting on the first low-density parity check matrix, wherein one or more lifted permutation matrices associated with the base edges of the first low-density parity check matrix can be recovered as block-by-block submatrices of one or more lifted permutation matrices associated with the corresponding base edges of the expanded low-density parity check matrix, and the expanded low-density parity check code is an extension of the first low-density parity check code.

[0137] The LDPC encoding component 1206 can be configured or operable to encode a first multi-bit set according to an extended low-density parity-check matrix and an extended low-density parity-check code to produce an extended boost. The LDPC encoding component 1206 can also be configured or operable to perform the transmission of the boosted codeword from a first wireless device to a second wireless device.

[0138] The integer pair generation component 1208 can be configured or operable to generate integer pairs to identify one or more images of a first low-density parity boosted bit vector within a corresponding extended boosted low-density parity bit vector, wherein the first integer of the integer pair corresponds to a first boosting step and the second integer of the integer pair corresponds to a second boosting step, and to first enumerate the bits of the first low-density parity boosted bit vector of the extended low-density parity boosted bit vector based on the first integer of the integer pair used to identify the bits within the first low-density parity boosted bit vector, and to second enumerate the bits of the first low-density parity boosted bit vector of the extended low-density parity boosted bit vector based on the second integer of the integer pair used to identify the image of the first low-density parity boosted bit vector within the extended low-density parity boosted bit vector.

[0139] In some examples, the second lifting step includes an internal expansion that preserves the first low-density parity lift as a subcomponent of the expanded low-density parity lift, based on the fact that the first lift can be recovered from the second lift via a bitmask application. In some examples, the second lifting step includes an external expansion that preserves the first low-density parity lift as a subcomponent of the expanded low-density parity lift, based on the fact that the first lift can be recovered from the second lift via a modulo operation.

[0140] In some examples, the first lifting step is associated with the second lifting step via a lifting factor and a modulo operation.

[0141] In some examples, the internal expansion can recover a block-by-block submatrix as an expanded low-density parity check matrix from the expanded lifting permutation based on the first lifting permutation, to preserve the lifted edge permutation of the first low-density parity check code as a subcomponent of the edge permutation of the expanded low-density parity check code.

[0142] In some examples, the first lift corresponding to the first integer pair according to the internal extension is independent of the second lift corresponding to the second integer pair, and the block-by-block submatrix of the permutation of the image corresponding to the first lift is the same.

[0143] The extended application component 1210 can be configured or operable to perform a first promotion step and a second promotion step based on an internal or external promotion, wherein the first promotion step and the second promotion step are performed based on an internal or external promotion.

[0144] The exchange boosting component 1212 can be configured or operable to exchange at least two images of one or more images of the first low-density parity check code during a first boosting step or a second boosting step.

[0145] Figure 13 A block diagram of an example wireless communication device 1300 supporting extended LDPC codes for Wi-Fi according to some aspects of this disclosure is shown. In some examples, the wireless communication device 1300 is configured or operable to perform reference... Figure 11 The process 1100 is described. In various examples, the wireless communication device 1300 may be a chip, SoC, chipset, package, or device, which may include: one or more modems (such as Wi-Fi, Wi-Fi (IEEE 802.11) modems, or cellular modems such as 3GPP 4G LTE or 5G compatible modems); one or more processors, processing blocks, or processing elements (collectively, “processors”); one or more radio units (collectively, “radio units”); and one or more memories or memory blocks (collectively, “memory”).

[0146] In some examples, the wireless communication device 1300 may be used for use in STA (such as reference) Figure 1The device used in the described STA104). In some other examples, the wireless communication device 1300 may be an STA including such a chip, SoC, chipset, package, or device, and multiple antennas. The wireless communication device 1300 is capable of transmitting and receiving wireless communications, for example, in the form of wireless packets. For example, the wireless communication device may be configured or operated to transmit and receive packets in the form of physical layer PPDUs conforming to one or more standards in the IEEE 802.11 wireless communication protocol family of standards. In some examples, the wireless communication device 1300 also includes or may be coupled to an application processor, which may be further coupled to another memory. In some examples, the wireless communication device 1300 also includes a user interface (UI) (such as a touchscreen or keypad) and a display, which may be integrated with the UI to form a touchscreen display. In some examples, the wireless communication device 1300 may also include one or more sensors, such as one or more inertial sensors, accelerometers, temperature sensors, pressure sensors, or altitude sensors.

[0147] Wireless communication device 1300 includes a first boosting component 1302, a second boosting component 1304, a decoding component 1306, an integer pair generation component 1308, an extended application component 1310, and a switching boosting component 1312. A portion of one or more of components 1302, 1304, 1306, 1308, 1310, and 1312 may be implemented at least partially using hardware or firmware. For example, the first boosting component 1302 and the second boosting component 1304 may be implemented at least partially by a modem. In some examples, at least some of components 1302, 1304, 1306, 1308, 1310, and 1312 are implemented at least partially by a processor and software stored in memory. For example, portions of one or more of components 1302, 1304, 1306, 1308, 1310, or 1312 may be implemented as non-transitory instructions (or "code") executable by a processor to perform the function or operation of the corresponding module.

[0148] In some implementations, the processor may be a component of a processing system. A processing system generally refers to a system or a series of machines or components that receive and process inputs to produce outputs (the set of outputs may be passed to other systems or, for example, components of device 1300). For example, the processing system of device 1300 may refer to a system that includes various other components or sub-components of device 1300, such as a processor, transceiver, communication manager, or other components or combinations of components of device 1300. The processing system of device 1300 may interface with other components of device 1300 and may process information received from other components (such as inputs or signals) or output information to other components. For example, the chip or modem of device 1300 may include a processing system, a first interface for outputting information, and a second interface for acquiring information. In some implementations, the first interface may refer to the interface between the processing system of the chip or modem and a transmitter, enabling device 1300 to send information output from the chip or modem. In some implementations, the second interface may refer to the interface between the processing system of the chip or modem and the receiver, enabling device 1300 to receive information or signal input, and the information can be transmitted to the processing system. Those skilled in the art will readily recognize that the first interface can also receive information or signal input, and the second interface can also output information or signal.

[0149] The first lifting component 1302 can be configured or operable to generate a first low-density parity check matrix and a first low-density parity check code by performing a first lifting on the base matrix.

[0150] The second lifting component 1304 can be configured or operable to generate an extended low-density parity check matrix and an extended low-density parity check code by performing a second lifting on the first low-density parity check matrix, wherein one or more lifted permutation matrices associated with the base edges of the first low-density parity check matrix can be recovered as block-by-block submatrices of one or more lifted permutation matrices associated with the corresponding base edges of the extended low-density parity check matrix, and the extended low-density parity check code is an extension of the first low-density parity check code.

[0151] Decoding component 1306 can be configured or operable to receive, from a first wireless device, a boosted codeword encoded based on an extended low-density parity-check matrix. In some examples, decoding component 1306 can be configured or otherwise supported to include units for decoding the boosted codeword according to the extended low-density parity-check code. In some examples, the second boosting includes a two-step boosting step, comprising a first boosting step and a second boosting step, and decoding component 1306 can be configured or otherwise supported to include units for decoding the boosted codeword according to the first boosting step and the second boosting step, based on an internal or external extension.

[0152] The integer pair generation component 1308 can be configured or operable to generate integer pairs to identify one or more images of a first low-density parity boosted bit vector within a corresponding extended boosted low-density parity bit vector, wherein the first integer of the integer pair corresponds to a first boosting step and the second integer of the integer pair corresponds to a second boosting step, and to first enumerate the bits of the first low-density parity boosted bit vector of the extended low-density parity boosted bit vector based on the first integer of the integer pair used to identify the bits within the first low-density parity boosted bit vector, and to second enumerate the bits of the first low-density parity boosted bit vector of the extended low-density parity boosted bit vector based on the second integer of the integer pair used to identify the image of the first low-density parity boosted bit vector within the extended low-density parity boosted bit vector.

[0153] In some examples, the decoding component 1306 may be configured or otherwise supported as a unit for performing the following operations: decoding a boosted codeword according to an internal extension, the internal extension being recoverable from the boosted low-density parity boosting permutation identifier via a bitmask, to preserve the first low-density parity boosting permutation identifier as a subcomponent of the boosted low-density parity boosting permutation identifier. In some examples, the decoding component 1306 may be configured or otherwise supported as a unit for performing the following operations: decoding a boosted codeword according to an external extension, the external extension being recoverable from the boosted low-density parity boosting permutation identifier via a modulo operation, to preserve the first low-density parity boosting permutation identifier as a subcomponent of the boosted low-density parity boosting permutation identifier.

[0154] In some examples, the decoding component 1306 may be configured or otherwise supported for the unit to perform the following operations: decoding the boosted codeword according to an internal extension that can be recovered from the boosted low-density parity boosted permutation identifier via the application of a bitmask, thereby preserving the first low-density parity boosted permutation identifier as a subcomponent of the boosted low-density parity boosted permutation identifier.

[0155] In some examples, the second lifting step includes an external expansion that can be recovered from the second lifting based on the application of the first lifting via modulo operation, to preserve the first low-density parity lifting as a subcomponent of the expanded low-density parity lifting. In some examples, the decoding component 1306 can decode the lifted codeword based on the external expansion, which can be recovered from the expanded low-density parity lifting permutation identifier based on the application of the first low-density parity lifting permutation identifier via modulo operation, to preserve the first low-density parity lifting permutation identifier as a subcomponent of the expanded low-density parity lifting permutation identifier.

[0156] In some examples, the first lifting step is associated with the second lifting step via a lifting factor and a modulo operation.

[0157] In some examples, the internal expansion can recover a block-by-block submatrix as an expanded low-density parity check matrix from the expanded lifting permutation based on the first lifting permutation, to preserve the lifted edge permutation of the first low-density parity check code as a subcomponent of the edge permutation of the expanded low-density parity check code.

[0158] In some examples, the first lift corresponding to the first integer pair according to the internal extension is independent of the second lift corresponding to the second integer pair, and the block-by-block submatrix of the permutation of the image corresponding to the first lift is the same.

[0159] The control application component 1310 can be configured or operable to perform a first lifting step and a second lifting step based on internal or external extensions.

[0160] In some examples, the extended low-density parity code includes one or more boosted low-density parity codes, which at least include a first low-density parity code recoverable from the extended low-density parity code.

[0161] The swapping boosting component 1312 can be configured or operable to swap at least two of one or more images of the first low-density parity check code during a first boosting step or a second boosting step.

[0162] Examples of implementation methods are described in the following numbered clauses:

[0163] Clause 1: A method for wireless communication includes: generating a first low-density parity-check matrix and a first low-density parity-check code by performing a first lifting on a base matrix; generating an extended low-density parity-check matrix and an extended low-density parity-check code by performing a second lifting on the first low-density parity-check matrix, wherein one or more lifting permutation matrices associated with the base edges of the first low-density parity-check matrix can be recovered as block-wise submatrices of one or more lifting permutation matrices associated with corresponding base edges of the extended low-density parity-check matrix, the extended low-density parity-check code being an extension of the first low-density parity-check code; encoding a first plurality of bits according to the extended low-density parity-check matrix and the extended low-density parity-check code to generate a lifted codeword; and performing transmission of the lifted codeword from a first wireless device to a second wireless device.

[0164] Clause 2: The method according to Clause 1, wherein the expanded low-density parity-check matrix includes a two-step lifting step, the two-step lifting step including a first lifting step and a second lifting step, the second lifting step being applied to the result of the first lifting step to produce an expanded lifting, the method further comprising: generating integer pairs to identify one or more images of a first low-density parity-check boosted bit vector within a corresponding expanded and boosted parity-check bit vector, the first integer of the integer pair corresponding to the first lifting step and the second integer of the integer pair corresponding to the second lifting step, and according to the method for identifying the first low-density parity-check boosted bit vector within the first low-density parity-check boosted bit vector The first integer of the integer pair of bits can first enumerate the bits of the first low-density parity boosted bit vector of the extended first low-density parity boosted bit vector, and second enumerate the bits of the first low-density parity boosted bit vector of the extended first low-density parity boosted bit vector according to the second integer of the integer pair of the image of the first low-density parity boosted bit vector within the extended low-density parity boosted bit vector; and perform the first boosting step and the second boosting step according to the inner or outer expansion of the first boosting to generate the extended low-density parity code.

[0165] Clause 3: The method according to Clause 2, wherein the second boosting step includes the internal expansion, which can be recovered from the second boost via the application of a bitmask, to preserve the first low-density parity boost as a subcomponent of the expanded low-density parity boost.

[0166] Clause 4: The method according to any of Clauses 2 to 3, wherein the second boosting step includes the external extension, which can be recovered from the second boost via modulo operation based on the application of the first boost, to preserve the first low-density parity boost as a subcomponent of the extended low-density parity boost.

[0167] Clause 5: The method described in any of Clauses 2 to 4, wherein the first boosting step is associated with the second boosting step via a boosting factor and a modulo operation.

[0168] Clause 6: The method according to any of Clauses 2 to 5, wherein the inner expansion can recover a block-by-block submatrix as an expanded low-density parity-check matrix from the expanded lifting permutation according to the first lifting permutation, to preserve the lifted edge permutation of the first low-density parity-check code as a subcomponent of the edge permutation of the expanded low-density parity-check code.

[0169] Clause 7: The method described in any of Clauses 2 to 6, wherein, according to the internal extension, the first lift of the first integer corresponding to the first integer pair is independent of the second lift of the second integer corresponding to the second integer pair, and the block-by-block submatrix of the permutation of the image corresponding to the first lift is identical.

[0170] Clause 8: The method described under any of Clauses 2 to 7 further comprises: exchanging at least two of the one or more images of the first low-density parity check code during the first boosting step or the second boosting step.

[0171] Clause 9: The method according to any of Clauses 1 to 8, wherein the extended low-density parity code comprises one or more boosted low-density parity codes, the one or more boosted low-density parity codes comprising at least a first low-density parity code recoverable from the extended low-density parity code.

[0172] Clause 10: A method for wireless communication, comprising: generating a first low-density parity-check matrix and a first low-density parity-check code by performing a first lifting on a base matrix; generating an extended low-density parity-check matrix and an extended low-density parity-check code by performing a second lifting on the first low-density parity-check matrix, wherein one or more lifting permutation matrices associated with the base edges of the first low-density parity-check matrix can be recovered as block-wise submatrices of the one or more lifting permutation matrices associated with corresponding base edges of the extended low-density parity-check matrix, the extended low-density parity-check code being an extension of the first low-density parity-check code; receiving a lifted codeword from a first wireless device based on the extended low-density parity-check matrix; and decoding the lifted codeword based on the extended low-density parity-check code.

[0173] Clause 11: The method according to Clause 10, wherein the expanded low-density parity check matrix includes a two-step lifting step, the two-step lifting step including a first lifting step and a second lifting step, the second lifting step being applied to the result of the first lifting step to produce an expanded lifting, the method further comprising: generating integer pairs to identify one or more images of a first low-density parity check boosted bit vector within a corresponding expanded and boosted low-density parity check bit vector, the first integer of the integer pair corresponding to the first lifting step and the second integer of the integer pair corresponding to the second lifting step, and according to the method for identifying the first low-density parity check bit vector... The first integer of the integer pair of bits within the checked boosted bit vector can first enumerate the bits of the first low-density parity boosted bit vector of the extended first low-density parity boosted bit vector, and second enumerate the bits of the first low-density parity boosted bit vector of the extended low-density parity boosted bit vector according to the second integer of the integer pair of the image of the first low-density parity boosted bit vector within the extended low-density parity boosted bit vector; and decode the boosted codeword according to the first boosting step and the second boosting step according to internal or external boosting.

[0174] Clause 12: The method according to Clause 11 further comprises: decoding the boosted codeword according to the internal extension, wherein the internal extension can be recovered from the boosted low-density parity boosting permutation identifier via the application of a bitmask, thereby preserving the first low-density parity boosting permutation identifier as a subcomponent of the boosted low-density parity boosting permutation identifier.

[0175] Clause 13: The method described under any of Clauses 11 to 12 further comprises: decoding the enhanced codeword according to the external extension, wherein the external extension is recoverable from the enhanced low-density parity enhancement permutation identifier via modulo operation, thereby preserving the first low-density parity enhancement permutation identifier as a subcomponent of the enhanced low-density parity enhancement permutation identifier.

[0176] Clause 14: The method described in any of Clauses 11 to 13, wherein the first boosting step is associated with the second boosting step via a boosting factor and a modulo operation.

[0177] Clause 15: The method according to any of Clauses 11 to 14, wherein the inner expansion can recover a block-by-block submatrix as an expanded low-density parity-check matrix from the expanded lifting permutation according to the first lifting permutation, to preserve the lifted edge permutation of the first low-density parity-check code as a subcomponent of the edge permutation of the expanded low-density parity-check code.

[0178] Clause 16: The method according to any of Clauses 11 to 15, wherein, according to the internal extension, the first lift of the first integer corresponding to the first integer pair is independent of the second lift of the second integer corresponding to the second integer pair, and the block-by-block submatrix of the permutation of the image corresponding to the first lift is the same.

[0179] Clause 17: The method described under any of Clauses 11 to 16 further comprises: exchanging at least two of the one or more images of the first low-density parity check code during the first boosting step or the second boosting step.

[0180] Clause 18: The method according to any of Clauses 11 to 17, wherein the extended low-density parity code comprises one or more boosted low-density parity codes, the one or more boosted low-density parity codes comprising at least a first low-density parity code recoverable from the extended low-density parity code.

[0181] Clause 19: An apparatus for wireless communication, comprising: a processor; a memory coupled to the processor; and instructions stored in the memory and executable by the processor to cause the apparatus to perform the method described in any of Clauses 1 to 9.

[0182] Clause 20: An apparatus for wireless communication, comprising at least one unit for performing the method described in accordance with any one of Clauses 1 to 9.

[0183] Clause 21: A non-transitory computer-readable medium storing code for wireless communication, said code including instructions executable by a processor to perform methods of any of Clauses 1 to 9.

[0184] Clause 22: An apparatus for wireless communication, comprising: a processor; a memory coupled to the processor; and instructions stored in the memory and executable by the processor to cause the apparatus to perform the method described in any of Clauses 10 to 18.

[0185] Clause 23: An apparatus for wireless communication, comprising at least one unit for performing the method described pursuant to any one of Clauses 10 to 18.

[0186] Clause 24: A non-transitory computer-readable medium storing code for wireless communication, said code including instructions executable by a processor to perform methods of any of Clauses 10 to 18.

[0187] As used herein, the term "determine" or "determining" encompasses a wide variety of operations; therefore, "determining" can include calculating, computation, processing, derivation, investigation, searching (e.g., via searching in a table, database, or other data structure), reasoning, assertion, measurement, etc. Furthermore, "determining" can include receiving (such as receiving information), accessing (such as accessing data stored in memory), sending (such as sending information), etc. Additionally, "determining" can also include solving, selecting, obtaining, choosing, establishing, and other similar actions.

[0188] As used herein, the phrase “at least one of the items” refers to any combination of those items, including a single member. For example, “at least one of a, b, or c” is intended to cover: a, b, c, ab, ac, bc, and abc. As used herein, “or” is intended to indicate inclusion unless otherwise expressly indicated. For example, “a or b” could include only a, only b, or a combination of a and b.

[0189] As used herein, unless otherwise expressly indicated, “based on” is intended to be interpreted in an inclusive sense. For example, unless otherwise expressly indicated, “based on” may be used interchangeably with “at least partially based on,” “associated with,” or “according to.” Specifically, unless the phrase refers to “based solely on 'a'” or its equivalent in the context, both “based on 'a'” and “at least partially based on 'a'” may be based solely on “a” or on a combination of “a” and one or more other factors, conditions, or information. In other words, as used herein, unless otherwise expressly indicated, the phrase “based on” should be interpreted in the same way as the phrases “at least partially based on,” “associated with,” or “according to.” Specifically, unless the phrase refers to “based solely on 'a'” or its equivalent in the context, both “based on 'a'” and “at least partially based on 'a'” may be based solely on “a” or on a combination of “a” and one or more other factors, conditions, or information.

[0190] As used herein, the term "determine" or "determining" encompasses a wide variety of operations; therefore, "determining" can include calculating, computation, processing, derivation, investigation, searching (e.g., via searching in a table, database, or other data structure), reasoning, assertion, measurement, etc. Furthermore, "determining" can include receiving (such as receiving information), accessing (such as accessing data stored in memory), sending (such as sending information), etc. Additionally, "determining" can also include solving, selecting, obtaining, choosing, establishing, and other similar actions.

[0191] The various illustrative components, logic, logic blocks, modules, circuits, operations, and algorithmic processes described in conjunction with the examples disclosed herein can be implemented as electronic hardware, firmware, software, or a combination of hardware, firmware, or software, including the structures disclosed in this specification and their structural equivalents. The interchangeability of hardware, firmware, and software has been generally described around functionality and illustrated in the various illustrative components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware, firmware, or software depends on the specific application and the design constraints imposed on the system as a whole.

[0192] Various modifications to the examples described in this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other examples without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the examples shown herein, but are given the broadest scope consistent with this disclosure, the principles disclosed herein, and the novel features.

[0193] Furthermore, the various features described in this specification in the context of separate examples can also be implemented in combination in a single implementation. Conversely, the various features described in the context of a single implementation can also be implemented individually or in any suitable sub-combination in multiple examples. Accordingly, although features may be described above as taking action in a particular combination, and even initially claimed in this manner, in some cases, one or more features from the claimed combination may be removed from that combination, and the claimed combination may be for sub-combinations or variations thereof.

[0194] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring such operations to be performed in the specific order shown or in sequential order, or to perform all shown operations to achieve the desired result. Furthermore, the drawings may schematically illustrate one or more example processes in the form of flowcharts or block diagrams. However, other operations not depicted may be incorporated into the schematically shown example processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any of the shown operations. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the examples described above should not be construed as requiring such separation in all examples, and it should be understood that the described program components and systems can generally be integrated together in a single software product or encapsulated in multiple software products.

Claims

1. An apparatus for wireless communication, comprising: processor; A memory coupled to the processor; as well as Instructions, stored in the memory and executable by the processor, to cause the device to perform the following operations: The first low-density parity check matrix and the first low-density parity check code are generated by performing a first lifting on the basis matrix. An extended low-density parity check matrix and an extended low-density parity check code are generated by performing a second lifting operation on the first low-density parity check matrix. One or more lifted permutation matrices associated with the base edges of the first low-density parity check matrix can be recovered as block-wise submatrices of the one or more lifted permutation matrices associated with the corresponding base edges of the extended low-density parity check matrix. The extended low-density parity check code is an extension of the first low-density parity check code. The first plurality of bits are encoded according to the extended low-density parity-check matrix and the extended low-density parity-check code to generate an enhanced codeword. as well as The enhanced codeword is transmitted from the first wireless device to the second wireless device.

2. The apparatus according to claim 1, wherein, The expanded low-density parity-check matrix includes a two-step boosting process, comprising a first boosting step and a second boosting step, wherein the second boosting step is applied to the result of the first boosting step to produce the expanded boosting, and the instructions can also be executed by the processor to cause the device to perform the following operations: Integer pairs are generated to identify one or more images of a first low-density parity boosted bit vector within a corresponding extended boosted low-density parity bit vector, wherein a first integer of the integer pair corresponds to the first boosting step and a second integer of the integer pair corresponds to the second boosting step; and bits of the first low-density parity boosted bit vector of the extended low-density parity boosted bit vector are first enumerated based on the first integer of the integer pair used to identify bits within the first low-density parity boosted bit vector, and bits of the first low-density parity boosted bit vector of the extended low-density parity boosted bit vector are second enumerated based on the second integer of the integer pair used to identify images of the first low-density parity boosted bit vector within the extended low-density parity boosted bit vector. as well as The first boosting step and the second boosting step are performed according to the internal or external expansion of the first boosting to generate the expanded low-density parity check code.

3. The apparatus according to claim 2, wherein, The second boosting step includes the internal expansion, which can be recovered from the second boost via the application of a bitmask, to preserve the first low-density parity boost as a subcomponent of the expanded low-density parity boost.

4. The apparatus according to claim 2, wherein, The second boosting step includes the external extension, which can be recovered from the second boost based on the application of the first boost via modulo operation, to retain the first low-density parity boost as a sub-component of the extended low-density parity boost.

5. The apparatus according to claim 2, wherein, The first boosting step is related to the second boosting step via boosting factor and modulo operation.

6. The apparatus according to claim 2, wherein, The internal expansion can recover a block-by-block submatrix as the expanded low-density parity check matrix from the expanded lifting permutation according to the first lifting permutation, so as to preserve the lifted edge permutation of the first low-density parity check code as a subcomponent of the edge permutation of the expanded low-density parity check code.

7. The apparatus according to claim 2, wherein, According to the internal extension, the first lift corresponding to the first integer of the integer pair is independent of the second lift corresponding to the second integer of the integer pair, and the block-by-block submatrix of the permutation of the image corresponding to the first lift is the same.

8. The apparatus according to claim 2, wherein, The instructions can further be executed by the processor to cause the device to perform the following operations: During the first or second boosting step, at least two of the one or more images of the first low-density parity check code are swapped.

9. The apparatus according to claim 1, wherein, The extended low-density parity check code includes one or more boosted low-density parity check codes, the one or more boosted low-density parity check codes including at least the first low-density parity check code recoverable from the extended low-density parity check code.

10. A method for wireless communication, comprising: The first low-density parity check matrix and the first low-density parity check code are generated by performing a first lifting on the basis matrix. An extended low-density parity check matrix and an extended low-density parity check code are generated by performing a second lifting operation on the first low-density parity check matrix. One or more lifted permutation matrices associated with the base edges of the first low-density parity check matrix can be recovered as block-wise submatrices of the one or more lifted permutation matrices associated with the corresponding base edges of the extended low-density parity check matrix. The extended low-density parity check code is an extension of the first low-density parity check code. The first plurality of bits are encoded according to the extended low-density parity-check matrix and the extended low-density parity-check code to generate an enhanced codeword. as well as The enhanced codeword is transmitted from the first wireless device to the second wireless device.

11. The method according to claim 10, wherein, The expanded low-density parity-check matrix includes a two-step lifting process, comprising a first lifting step and a second lifting step, wherein the second lifting step is applied to the result of the first lifting step to produce the expanded lifting. The method further includes: Generate integer pairs to identify one or more images of a first low-density parity boosted bit vector within a corresponding extended boosted parity bit vector, wherein a first integer of the integer pair corresponds to the first boosting step and a second integer of the integer pair corresponds to the second boosting step; and first enumerate the bits of the first low-density parity boosted bit vector of the extended first low-density parity boosted bit vector based on the first integer of the integer pair used to identify bits within the first low-density parity boosted bit vector; and second enumerate the bits of the first low-density parity boosted bit vector of the extended first low-density parity boosted bit vector based on the second integer of the integer pair used to identify images of the first low-density parity boosted bit vector within the extended low-density parity boosted bit vector; and The first boosting step and the second boosting step are performed according to the internal or external expansion of the first boosting to generate the expanded low-density parity check code.

12. The method according to claim 11, wherein, The second boosting step includes the internal expansion, which can be recovered from the second boost via the application of a bitmask, to preserve the first low-density parity boost as a subcomponent of the expanded low-density parity boost.

13. The method according to claim 11, wherein, The second boosting step includes the external extension, which can be recovered from the second boost based on the application of the first boost via modulo operation, to retain the first low-density parity boost as a sub-component of the extended low-density parity boost.

14. The method according to claim 11, wherein, The first boosting step is related to the second boosting step via boosting factor and modulo operation.

15. The method according to claim 11, wherein, The internal expansion can recover a block-by-block submatrix as the expanded low-density parity check matrix from the expanded lifting permutation according to the first lifting permutation, so as to preserve the lifted edge permutation of the first low-density parity check code as a subcomponent of the edge permutation of the expanded low-density parity check code.

16. The method according to claim 11, wherein, According to the internal extension, the first lift corresponding to the first integer of the integer pair is independent of the second lift corresponding to the second integer of the integer pair, and the block-by-block submatrix of the permutation of the image corresponding to the first lift is the same.

17. The method of claim 11, further comprising: During the first or second boosting step, at least two of the one or more images of the first low-density parity check code are swapped.

18. The method according to claim 10, wherein, The extended low-density parity check code includes one or more boosted low-density parity check codes, the one or more boosted low-density parity check codes including at least the first low-density parity check code recoverable from the extended low-density parity check code.

19. An apparatus for wireless communication, comprising: processor; A memory coupled to the processor; as well as Instructions, stored in the memory and executable by the processor, to cause the device to perform the following operations: The first low-density parity check matrix and the first low-density parity check code are generated by performing a first lifting on the basis matrix. An extended low-density parity check matrix and an extended low-density parity check code are generated by performing a second lifting operation on the first low-density parity check matrix. One or more lifted permutation matrices associated with the base edges of the first low-density parity check matrix can be recovered as block-wise submatrices of the one or more lifted permutation matrices associated with the corresponding base edges of the extended low-density parity check matrix. The extended low-density parity check code is an extension of the first low-density parity check code. Receive from the first wireless device an enhanced codeword encoded according to the extended low-density parity check matrix; as well as The enhanced codeword is decoded according to the extended low-density parity-check code.

20. The apparatus according to claim 19, wherein, The expanded low-density parity-check matrix includes a two-step boosting process, comprising a first boosting step and a second boosting step, wherein the second boosting step is applied to the result of the first boosting step to produce the expanded boosting, and the instructions can also be executed by the processor to cause the device to perform the following operations: Generate integer pairs to identify one or more images of a first low-density parity-boosted bit vector within a corresponding extended and boosted low-density parity bit vector, wherein a first integer of the integer pair corresponds to the first boosting step and a second integer of the integer pair corresponds to the second boosting step; and first enumerate the bits of the first low-density parity-boosted bit vector of the extended low-density parity-boosted bit vector based on the first integer of the integer pair used to identify bits within the first low-density parity-boosted bit vector, and second enumerate the bits of the first low-density parity-boosted bit vector of the extended low-density parity-boosted bit vector based on the second integer of the integer pair used to identify images of the first low-density parity-boosted bit vector within the extended low-density parity-boosted bit vector; and Based on internal or external expansion, the boosted codeword is decoded according to the first boosting step and the second boosting step.

21. The apparatus according to claim 20, wherein, The instructions can further be executed by the processor to cause the device to perform the following operations: The enhanced codeword is decoded according to the internal extension, which can be recovered from the enhanced low-density parity enhancement permutation identifier by the application of a bit mask, thereby preserving the first low-density parity enhancement permutation identifier as a sub-component of the enhanced low-density parity enhancement permutation identifier.

22. The apparatus according to claim 20, wherein, The instructions can further be executed by the processor to cause the device to perform the following operations: The enhanced codeword is decoded according to the external extension, which can be recovered from the enhanced low-density parity enhancement permutation identifier by the application of modulo operation based on the first low-density parity enhancement permutation identifier, so as to retain the first low-density parity enhancement permutation identifier as a sub-component of the enhanced low-density parity enhancement permutation identifier.

23. The apparatus according to claim 20, wherein, The first boosting step is related to the second boosting step via boosting factor and modulo operation.

24. The apparatus according to claim 20, wherein, The internal expansion can recover a block-by-block submatrix as the expanded low-density parity check matrix from the expanded lifting permutation according to the first lifting permutation, so as to preserve the lifted edge permutation of the first low-density parity check code as a subcomponent of the edge permutation of the expanded low-density parity check code.

25. The apparatus according to claim 20, wherein, According to the internal extension, the first lift corresponding to the first integer of the integer pair is independent of the second lift corresponding to the second integer of the integer pair, and the block-by-block submatrix of the permutation of the image corresponding to the first lift is the same.

26. The apparatus according to claim 20, wherein, The instructions can further be executed by the processor to cause the device to perform the following operations: During the first or second boosting step, at least two of the one or more images of the first low-density parity check code are swapped.

27. The apparatus according to claim 20, wherein, The extended low-density parity check code includes one or more boosted low-density parity check codes, the one or more boosted low-density parity check codes including at least the first low-density parity check code recoverable from the extended low-density parity check code.

28. A method for wireless communication, comprising: The first low-density parity check matrix and the first low-density parity check code are generated by performing a first lifting on the basis matrix. An extended low-density parity check matrix and an extended low-density parity check code are generated by performing a second lifting operation on the first low-density parity check matrix. One or more lifted permutation matrices associated with the base edges of the first low-density parity check matrix can be recovered as block-wise submatrices of the one or more lifted permutation matrices associated with the corresponding base edges of the extended low-density parity check matrix. The extended low-density parity check code is an extension of the first low-density parity check code. Receive from the first wireless device an enhanced codeword encoded via the extended low-density parity-check matrix; as well as The enhanced codeword is decoded according to the extended low-density parity-check code.

29. The method according to claim 28, wherein, The expanded low-density parity-check matrix includes a two-step lifting process, comprising a first lifting step and a second lifting step, wherein the second lifting step is applied to the result of the first lifting step to produce the expanded lifting. The method further includes: Generate integer pairs to identify one or more images of a first low-density parity-boosted bit vector within a corresponding extended and boosted low-density parity bit vector, wherein a first integer of the integer pair corresponds to the first boosting step and a second integer of the integer pair corresponds to the second boosting step; and first enumerate the bits of the first low-density parity-boosted bit vector of the extended low-density parity-boosted bit vector based on the first integer of the integer pair used to identify bits within the first low-density parity-boosted bit vector, and second enumerate the bits of the first low-density parity-boosted bit vector of the extended low-density parity-boosted bit vector based on the second integer of the integer pair used to identify images of the first low-density parity-boosted bit vector within the extended low-density parity-boosted bit vector; and The boosted codeword is decoded according to the first boosting step and the second boosting step, depending on whether it is an internal or external boosting step.

30. The method of claim 29, further comprising: The enhanced codeword is decoded according to the internal extension, which can be recovered from the enhanced low-density parity enhancement permutation identifier by the application of a bit mask, thereby preserving the first low-density parity enhancement permutation identifier as a sub-component of the enhanced low-density parity enhancement permutation identifier.

Images