Semiconductor device

Abstract

The semiconductor device includes first to fourth power supply lines formed below a substrate in which a through hole is formed, and a power switch circuit having a first transistor formed above the substrate. The power switch circuit overlaps the second power supply line in a plan view and is away from the fourth power supply line. The first transistor is disposed at a position overlapping the first power supply line in plan view, and a source thereof is connected to a via connected to the first power supply line. The second power supply line and the fourth power supply line are connected via a wiring extending in the second direction. As a result, a fourth power supply line disposed away from the power switch circuit can be connected to the power switch circuit formed at a position overlapping the first power supply line in plan view.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Techniques are known for providing power switching circuits in semiconductor devices, such as standard cells, for switching the supply and disconnection of power to transistors. BS-PDN (Backside Power Delivery Network) technology is known, which places power lines on the back side of a semiconductor substrate and supplies power to transistors disposed on the surface of the semiconductor substrate via TSVs (Through Silicon Vias). Techniques are also known for directly connecting vias from the back side of the semiconductor substrate to the source and drain of transistors disposed on the surface of the semiconductor substrate.

[0003] Patent Document 1: U.S. Patent Application Publication No. 2022 / 0344263

[0004] Patent Document 2: U.S. Patent Application Publication No. 2022 / 0208757

[0005] Patent Document 3: U.S. Patent Application Publication No. 2021 / 0272903

[0006] Patent Document 4: U.S. Patent Application Publication No. 2019 / 0305773

[0007] Patent Document 5: International Publication No. 2020 / 065916

[0008] Patent Document 6: International Publication No. 2022 / 066797

[0009] Patent Document 7: US Patent No. 11,552,069 Summary of the Invention

[0010] <Problem to be solved by this invention>

[0011] There has been no specific research on how wiring and vias should be configured and connected when power lines formed below the semiconductor substrate are directly connected to the source and drain of a power switch circuit formed above the semiconductor substrate using vias formed on the semiconductor substrate. For example, there has been no research on how to connect virtual power lines that are not adjacent to the power lines, which are generated due to suppressing the frequency of power line configuration below the semiconductor substrate, to power switch circuits formed in the plan view at positions overlapping with the power lines.

[0012] The present invention was made in view of the above circumstances, and its object is to connect a fourth power line, which is located away from the power switch circuit due to suppressing the configuration frequency of the first power line under the substrate, to a power switch circuit formed in the plan view at a position overlapping with the first power line.

[0013] <Methods for solving problems>

[0014] According to one aspect of the present invention, a semiconductor device includes: a substrate having a first through-hole formed thereon; a first power line, a second power line, a third power line, and a fourth power line formed below the substrate, the first power line being supplied with a first potential, the second power line being supplied with a second potential, the third power line being supplied with a third potential, and the fourth power line being supplied with a second potential; and a power switch circuit having a first transistor formed above the substrate and electrically connected between the first power line and the second power line, wherein the first power line, the second power line, the third power line, and the fourth power line extend continuously in a first direction in a plan view, the first transistor has a first source and a first drain, the first transistor is disposed at a position overlapping the first power line in the plan view, the first source is connected to the first through-hole connected to the first power line, the first power line, the second power line, the third power line, and the fourth power line are arranged in a second direction different from the first direction in the plan view, the second power line and the fourth power line are electrically connected via wiring extending in the second direction, and the power switch circuit is disposed at a position overlapping the second power line and away from the fourth power line in the plan view.

[0015] <Effects of the Invention>

[0016] According to the disclosed technology, a fourth power line, which is positioned away from the power switch circuit due to suppressing the configuration frequency of the first power line under the substrate, can be connected to a power switch circuit formed in a plan view at a position overlapping with the first power line. Attached Figure Description

[0017] Figure 1 This is a plan view illustrating an example of the layout of a semiconductor device in one embodiment.

[0018] Figure 2 It is shown Figure 1 A cross-sectional view of an example of the cross-sectional structure of a semiconductor device.

[0019] Figure 3 It shows the configuration in Figure 1 A circuit diagram of an example of a circuit in a standard unit block.

[0020] Figure 4 This is shown in the plan view as a configuration on the back side of a semiconductor substrate. Figure 3 A plan view illustrating the positional relationship between power lines, virtual power lines, ground lines, and vias at the overlapping locations of standard unit blocks and the power switch circuit.

[0021] Figure 5 It is shown Figure 3 and Figure 4 A plan view of an example of the layout of a power switch circuit.

[0022] Figure 6 It shows a ratio Figure 5 A floor plan illustrating an example of a layout covering a wider area.

[0023] Figure 7 It shows along Figure 5 A cross-sectional view of an example of the cross section along line X1-X2.

[0024] Figure 8 It shows along Figure 5 Another example of a cross-sectional view of the X1-X2 line.

[0025] Figure 9 It shows along Figure 5 Another example of a cross-sectional view of the X1-X2 line.

[0026] Figure 10 It is shown Figure 3 A plan view of a first variation of the layout of a power switch circuit.

[0027] Figure 11 It is shown Figure 3 A plan view of a second variation of the layout of the power switch circuit.

[0028] Figure 12 It is shown Figure 3 A plan view of the third variation of the power switch circuit layout.

[0029] Figure 13 It is shown Figure 4 A plan view of a variation of the layout.

[0030] Figure 14 It is shown Figure 13 A plan view of an example layout of the power switch circuit and control circuit. Detailed Implementation

[0031] Hereinafter, embodiments will be described using the accompanying drawings. The symbols representing signals will also be used to represent signal lines or signal terminals. The symbols representing power supply potential will also be used to represent power lines or power terminals to which power supply potential is supplied.

[0032] Figure 1 An example of the layout of a semiconductor device in one embodiment is shown. For example, Figure 1 The semiconductor device 100 shown may be a SoC (System on Chip), a single FPGA (Field-Programmable Gate Array), etc.

[0033] Semiconductor device 100 includes multiple I / O units IOC, IOCP, and internal circuit region INTR. I / O units IOC are interface circuits for signals such as input signals, output signals, or input / output signals (SIG). I / O units IOCP are interface circuits for power supply potentials or ground potentials.

[0034] Each I / O unit (IOC) and IOCP is connected to the internal circuit region (INTR). For example, the internal circuit region (INTR) has one or more standard cell blocks (SCBs) containing standard cells. Note that logic circuits other than standard cells, and memory, can be mounted in the internal circuit region (INTR). Memory can be installed within the standard cell blocks (SCBs). For example, the transistors mounted in the semiconductor device 100 can be fin FETs (Field Effect Transistors), nanosheet FETs, or CFETs (Complementary Field Effect Transistors).

[0035] Figure 2 Show Figure 1 This is an example of the cross-sectional structure of a semiconductor device 100. The semiconductor device 100 includes a substrate SUB, a wiring layer WL1 formed on the surface FS side of the substrate SUB, and a wiring layer WL2 formed on the back side BS side of the substrate SUB. The surface FS of the substrate SUB is an example of the upper surface of the substrate SUB, and the back side BS of the substrate SUB is an example of the lower surface of the substrate SUB. A fin FIN, which is part of a transistor, is formed on the surface of the substrate SUB. The fin FIN has a source, a drain, and a channel. On the side (back side) of the wiring layer WL2 opposite to the substrate SUB, a pad PAD, which serves as an external connection terminal, is formed.

[0036] The wiring layer WL2 has multiple wiring layers BSM1, BSM2 ( Figure 2 The structure consists of two layers (BSM stands for Backside Metal). For example, wiring layers BSM1 and BSM2 have wirings W1 and W2 respectively, supplying power and ground potentials. Wirings W1 and W2 are interconnected via via VIA1. Wiring W2 is interconnected with pads via via VIA2.

[0037] Wiring W1 is connected to the source of the fin FIN via a TSV formed on the substrate SUB. The TSV is an example of a first or second via. Wiring W1 can be connected via the TSV to a buried power rail (BPR) embedded in the surface of the substrate SUB.

[0038] Note that the transistor formed on the substrate SUB is not limited to a finned FET; it can also be a planar MOSFET, a nanosheet FET, or a CFET (Complementary Field-Effect Transistor). Similarly, in planar MOSFETs and nanosheet FETs, the via TSV supplying power or ground potential is connected to the source of the transistor. Furthermore, in the case of a CFET, the via TSV supplying power or ground potential can be connected to the source closest to the substrate SUB.

[0039] Figure 3 The configuration is shown in Figure 1 An example of a circuit in a standard cell block SCB. The standard cell block SCB has a power switch circuit PSW and a standard cell SC. The standard cell SC is connected to the virtual power line VVDD and the ground line VSS, and operates by receiving the virtual power potential VVDD from the virtual power line VVDD.

[0040] The power switch circuit PSW has a control circuit CNTL and a switching transistor SWT. The control circuit CNTL is a buffer circuit with inverters IV1 and IV2 connected in series between the input signal line IN and the output signal line OUT. Each inverter IV1 and IV2 operates by connecting to the power supply line TVDD and the ground line VSS. Inverter IV1 inverts the logic of the input signal IN and outputs it as the output signal OUT0. Inverter IV2 inverts the logic of the output signal OUT0 from inverter IV1 and outputs it as the output signal OUT.

[0041] The power line TVDD is an example of a first power line, and the power potential TVDD is an example of a first potential. The virtual power line VVDD is an example of a second power line, and the virtual power potential VVDD is an example of a second potential. The ground line VSS is an example of a third power line, and the ground potential VSS is an example of a third potential.

[0042] The switching transistor SWT is a PMOS transistor with its source connected to the power supply line TVDD and its drain connected to the dummy power supply line VVDD. It operates by receiving the voltage from the output signal OUT0 of the control circuit CNTL as its gate potential. During the conduction period of the switching transistor SWT, the power supply line TVDD is electrically connected to the dummy power supply line VVDD, and the power supply potential TVDD is supplied to the standard cell SC via the dummy power supply line VVDD. During the de-conduction period of the switching transistor SWT, the electrical connection between the power supply line TVDD and the dummy power supply line VVDD is broken, and the dummy power supply line VVDD is set to a floating state. Note that instead of the output of inverter IV1, the input IN of inverter IV1 or the output OUT of inverter IV2 can also be connected to the gate of the switching transistor SWT. This also applies to other implementations.

[0043] Note that the control circuit CNTL can also be configured in a different area than the configuration area of ​​the power switch circuit PSW. Additionally, the output signal OUT can also be supplied to the input terminal IN of another power switch circuit PSW. The switching transistor SWT is an example of a first transistor formed on the substrate SUB and electrically connected between the power line TVDD and the virtual power line VVDD.

[0044] Figure 4 The semiconductor substrate SUB is shown in the plan view with the back side (BS side) arranged in the plan view. Figure 3 An example of the positional relationship between the power line TVDD, virtual power line VVDD, ground line VSS, and via VIA1 at the overlapping location of the standard unit block SCB and the power switch circuit PSW. The traces in wiring layer BSM1 extend continuously and uninterruptedly along the X direction, while the traces in wiring layer BSM2 extend along the Y direction, a second direction different from the X direction. The X direction is an example of a first direction. Figure 4 The symbol ROW indicates the width of the standard cell SC in the Y direction of the wiring layer BSM1.

[0045] In wiring layer BSM1, ground line VSS, power line TVDD, dummy power line VVDD1, ground line VSS, and dummy power line VVDD2 are arranged along the Y direction. Dummy power line VVDD1 overlaps with the power switch circuit PSW in the plan view, while dummy power line VVDD2 does not overlap with the power switch circuit PSW in the plan view. Dummy power line VVDD1 is an example of a second power line, and dummy power line VVDD2 is an example of a fourth power line. When describing dummy power lines VVDD1 and VVDD2 without distinction, they are also referred to as dummy power line VVDD.

[0046] In cabling layer BSM1, the configuration frequency of the power line TVDD is lower than that of the virtual power line VVDD and the ground line VSS. By reducing the configuration frequency of the power line TVDD, the configuration frequency of the virtual power line VVDD and the ground line VSS can be relatively increased, thereby relatively reducing the cabling resistance of the virtual power line VVDD and the ground line VSS.

[0047] In cabling layer BSM2, the power line TVDD, dummy power line VVDD, and ground line VSS are arranged repeatedly in this order. The power switch circuits PSW, indicated by the thick dashed box, are arranged along the X direction with the location of the power line TVDD in cabling layer BSM1 as the center in the Y direction. Standard cells SC are arranged in areas where no power switch circuits PSW are configured. By centrally configuring the power switch circuits PSW along the cabling area of ​​the power line TVDD in cabling layer BSM1, the frequency of configuring the power line TVDD in cabling layer BSM1 can be reduced.

[0048] The virtual power lines VVDD of cabling layers BSM1 and BSM2 are interconnected via vias VIA1 located at the crossover points. The power lines TVDD of cabling layers BSM1 and BSM2 are interconnected via vias VIA1 located at the crossover points. The ground lines VSS of cabling layers BSM1 and BSM2 are interconnected via vias VIA1 located at the crossover points.

[0049] Note that, although not specifically limited, the configuration frequency (configuration interval in the X direction) of the power switching circuit PSW can be set to be higher than... Figure 4 Low.

[0050] Figure 5 Show Figure 3 and Figure 4 An example of the layout of a power switch circuit (PSW). Figure 5 In the accompanying diagrams, the symbol Mint represents a wiring formed on the metal wiring layer Mint, which is closest to the substrate SUB among multiple metal wiring layers. The symbol LI represents a local wiring formed on a wiring layer closer to the substrate SUB than the Mint layer. The wiring LI can be directly connected to the source and drain of the transistor. The symbol GT represents the gate of the transistor. The symbol VIA represents a via connecting the Mint wiring and the local wiring LI, or a via connecting the Mint wiring and the gate wiring GT.

[0051] The symbol TR (PMOS) represents the transistor region (source, drain, and channel) of a PMOS transistor. The symbol TR (NMOS) represents the transistor region (source, drain, and channel) of an NMOS transistor. For example, in a finned FET, fins are formed in region TR. In a nanosheet FET, semiconductor layers serving as the source and drain are formed in region TR, and a nanosheet serving as the channel is formed between the source and drain.

[0052] A power switch circuit (PSW) includes switching transistors (SWTs) arranged along the X-direction in the plan view and control circuitry (CNTL, buffer circuit). For example, the power switch circuit (PSW) is designed as a single unit. The switching transistors (SWTs) are positioned in the plan view to overlap with the ground line (VSS), power line (TVDD), and dummy power line (VVDD) of wiring layer BSM1.

[0053] In a SWT (Switching Transistor Welded) transistor, the source of a PMOS transistor that overlaps with the power line TVDD of wiring layer BSM1 in the plan view is directly connected to a TSV (Through Via) connected to the power line TVDD of wiring layer BSM1. This TSV directly connected to the source of a PMOS transistor that overlaps with the power line TVDD of wiring layer BSM1 in the plan view is an example of a first via. In a SWT transistor, the source of a PMOS transistor that does not overlap with the power line TVDD of wiring layer BSM1 in the plan view is connected to the source of a PMOS transistor connected to the TSV of power line TVDD via local wiring LI. Note that direct connection means that the electrical conductors included in the TSV are in contact with the semiconductor layer containing the source, drain, etc., of each transistor. For example, this includes cases where, when the TSV has multiple layers of electrical conductors, a portion of those multiple layers of conductors is in contact with the semiconductor layer containing the source and drain of the transistors.

[0054] In the SWT switching transistor, the drain of the PMOS transistor that overlaps with the virtual power line VVDD1 of the wiring layer BSM1 in the planar diagram is directly connected to the virtual power line VVDD1 of the wiring layer BSM1 via TSV. In the SWT switching transistor, the drain of the PMOS transistor that does not overlap with the virtual power line VVDD1 of the wiring layer BSM1 in the planar diagram is connected to the drain of the PMOS transistor connected to the TSV of the virtual power line VVDD1 via local wiring LI.

[0055] Furthermore, in the switching transistor SWT, the dummy transistor DMY (NMOS) is positioned in the area overlapping with the ground line VSS of the wiring layer BSM1 in the planar diagram. Note that the dummy transistor DMY can also be omitted.

[0056] The control circuit CNTL is positioned in the plan view, overlapping with the ground line VSS and power line TVDD of the wiring layer BSM1. The source of the PMOS transistor in the control circuit CNTL is directly connected to the power line TVDD of the wiring layer BSM1 via TSV. The source of the NMOS transistor in the control circuit CNTL is directly connected to the ground line VSS of the wiring layer BSM1 via TSV.

[0057] The source of the PMOS transistor in inverter IV, configured in standard cell SC, is directly connected to the virtual power line VVDD1 of wiring layer BSM1 via TSV. The source of the NMOS transistor in inverter IV, configured in standard cell SC, is directly connected to the ground line VSS of wiring layer BSM1 via TSV.

[0058] Note that although the control circuit CNTL (inverters IV1, IV2) is included in the power switch circuit PSW, it can also be configured separately from the power switch circuit PSW. In this case, the power switch circuit PSW and the control circuit CNTL can be designed as different units. Alternatively, multiple power switch circuits PSW can be controlled by one control circuit CNTL.

[0059] The virtual power line VVDD1 of wiring layer BSM1 is connected to the virtual power line VVDD of wiring layer BSM2 via via VIA1. That is, the drain of the PMOS transistor connected to the virtual power line VVDD1 of wiring layer BSM1 via TSV is electrically connected to the virtual power line VVDD2 of wiring layer BSM2, which does not overlap with the power switch circuit PSW in the plan view. Figure 4 Although not shown, the power line TVDD and ground line VSS of wiring layer BSM1 are each as shown. Figure 4 Connect them to the corresponding power line TVDD and ground line VSS in the wiring layer BSM2 as shown.

[0060] Figure 6 It shows a ratio Figure 5 An example of a layout with a wider geographical reach. Figure 6 The power switch circuit PSW shown corresponds to Figure 5 The power switch circuit PSW. In the plan view, on both sides of the virtual power line VVDD2 of the wiring layer BSM1, which is opposite to the standard cell SC (inverter IV), ground lines VSS are arranged. That is, the virtual power line VVDD2 is not formed in the plan view at a position overlapping with the power switch circuit PSW; therefore, the virtual power potential VVDD generated by the power switch circuit PSW cannot be supplied to the standard cell SC solely through the wiring of the wiring layer BSM1.

[0061] Therefore, in Figure 6In the diagram, the virtual power line VVDD1 of the wiring layer BSM1, which overlaps with the power switch circuit PSW, is connected to the virtual power line VVDD2 via via VIA1 and the virtual power line VVDD of the wiring layer BSM2. This allows the virtual power potential VVDD generated by the power switch circuit PSW to be supplied to the standard cell SC.

[0062] At this point, since it is not necessary to place the power line TVDD of the routing layer BSM1 at a position overlapping with the standard cell SC in the plan view, the placement frequency (number of placements) of the power line TVDD of the routing layer BSM1 can be suppressed. In other words, in a layout that suppresses the placement frequency of the power line TVDD of the routing layer BSM1, a virtual power potential VVDD can be supplied from the power switch circuit PSW to the virtual power line VVDD2, which is not formed at a position overlapping with the power switch circuit PSW in the plan view.

[0063] Figure 7 Show along Figure 5 An example of the cross-section of line X1-X2. The virtual power line VVDD formed on the wiring layer BSM1 on the back side BS is connected to the P-type impurity region (drain D of the PMOS transistor) of the fin FIN formed on the surface FS via TSV formed on the substrate SUB.

[0064] In each fin (FIN), the channel C is configured between the source (S) and drain (D). The gate GT is configured on the channel C via a gate insulating film (not shown). Note that although in Figure 7 In the middle, two cabling layers BSM1 and BSM2 are configured on the BS side of the back, but more than three cabling layers BSM can also be configured.

[0065] Figure 8 It shows along Figure 5 Another example of the cross-section of the X1-X2 line. Besides the fact that a wiring layer BSM1 is formed on the back side (BS side) of the substrate SUB, Figure 8 and Figure 6 Their cross-sectional structures are the same. Note that... Figure 7 The wiring layer BSM1 shown is different from the buried wiring BPR which is buried on the surface FS side of the substrate SUB. Figure 2 ).

[0066] Figure 9 It shows along Figure 5 Another example of the cross-section along line X1-X2. Besides the fact that the transistors formed on the substrate SUB are nanosheet FETs, Figure 9 and Figure 7The cross-sectional structure is the same. A nanosheet FET includes a semiconductor layer having a source (S) and a drain (D), a nanosheet NS having a semiconductor material formed between the source (S) and the drain (D), and a gate GT formed via a gate insulating film (not shown) disposed on the surface of the nanosheet NS. Note that a nanosheet FET can also be used instead of... Figure 8 The finned FET shown.

[0067] Figure 10 express Figure 3 The first variation of the layout of the power switching circuit PSW. Figure 10 In the diagram, the switching transistor SWT and the control circuit CNTL are arranged along the Y-axis in the plan view. Figure 5 Similarly, the switching transistor SWT is positioned in the plan view where it overlaps with the power line TVDD and the dummy power line VVDD1 of the routing layer BSM1. The control circuit CNTL is positioned in the plan view where it overlaps with the dummy power line VVDD2 and the ground line VSS of the routing layer BSM1. That is, the control circuit CNTL is not positioned in the plan view where it overlaps with the power line TVDD of the routing layer BSM1.

[0068] Therefore, the source of the PMOS transistor in the control circuit CNTL is electrically connected to the source of the PMOS transistor in the switching transistor SWT via local wiring LI and mint wiring. Thus, the source of the PMOS transistor in the control circuit CNTL can be electrically connected to the power line TVDD of the wiring layer BSM1. In other words, the sources of the PMOS transistors in the inverters IV1 and IV2 of the control circuit CNTL can be electrically connected to the power line TVDD of the wiring layer BSM1, regardless of the layout of the power line TVDD formed on the wiring layer BSM1. As a result, the layout freedom of the control circuit CNTL can be increased.

[0069] Note that the connection between the source of the PMOS transistor in the control circuit CNTL and the source of the PMOS transistor in the power switch circuit PSW can also be made using a wiring layer higher than the Mint layer. Furthermore, although the inverters IV1 and IV2 in the control circuit CNTL are... Figure 10 The control circuit CNTL is included within the power switching circuit (PSW), but it can also be configured separately from the PSW. In this case, the PSW and the control circuit CNTL can be designed as different units. Furthermore, one control circuit CNTL can control multiple PSWs.

[0070] Figure 11 Show Figure 3 A second variation of the layout of the power switch circuit PSW. Note that it is shown... Figure 11 The patterns of each element and Figure 5 and Figure 10 The patterns are the same. Figure 11 In the power switch circuit PSW shown, except that the N-type well tap region NWTP and the P-type well tap region PWTP are arranged along the Y direction between the switching transistor SWT and the control circuit CNTL, the circuit is otherwise identical to the PSW circuit. Figure 5 The power switching circuit (PSW) is the same. That is, the switching transistor (SWT) and the control circuit (CNTL) are arranged along the X direction in the plan view.

[0071] The well-tapped region NWTP is formed by an NMOS transistor whose gate is set to the ON (on) state. The well-tapped region NWTP is configured at the position overlapping with the power line TVDD of the wiring layer BSM1 in the plan view, and at the position overlapping with the virtual power line VVDD2 of the wiring layer BSM1 in the plan view.

[0072] In the plan view, the source and drain of the well tap region NWTP, which overlaps with the power line TVDD, are connected to the power line TVDD of the wiring layer BSM1 via a TSV. This allows the supply potential TVDD to be supplied to the N-type well region NW, which is the substrate region (shaded area) of the PMOS transistor. The TSV directly connected to the source and drain of the well tap region NWTP is an example of a second via.

[0073] In the well tap region NWTP that overlaps with the virtual power line VVDD2 in the plan view, for example, its source and drain are connected to the source and drain of the well tap region NWTP that overlaps with the power line TVDD using LI wiring, Mint wiring, and wiring UW1 of a wiring layer higher than the Mint layer. Thus, it is also possible to supply the power potential TVDD to the well tap region NWTP that is not overlapping with the power line TVDD in the plan view, as well as the shaded well region NW. Note that the source or drain of the well tap region NWTP that overlaps with the virtual power line VVDD2 can be electrically connected to the source of the switching transistor SWT.

[0074] The well-tapped region PWTP is formed by a PMOS transistor with its gate set to the ON state. In the plan view, the well-tapped region PWTP is positioned to overlap with the ground line VSS of the wiring layer BSM1. The source and drain of the well-tapped region PWTP are connected to the ground line VSS of the wiring layer BSM1 via TSV. This allows the ground potential VSS to be supplied to the P-type well region PW, which is the plate region (the region outside the mesh) of the NMOS transistor.

[0075] Note that the well region NW is an N-type impurity region formed in the substrate SUB and electrically connected to the channel of the fin FET (PMOS). The well region PW is a P-type substrate SUB or a P-type impurity region formed in the substrate SUB and electrically connected to the channel of the fin FET (NMOS). Furthermore, in Figure 11In this configuration, the control circuit CNTL can also be configured as a separate unit from the power switch circuit PSW, located away from the power switch circuit PSW.

[0076] Figure 12 Show Figure 3 The third variation of the layout of the power switch circuit PSW. Figure 12 In the diagram, the switching transistor SWT and the control circuit CNTL are arranged along the Y direction.

[0077] exist Figure 12 In the plan view, the switching transistor SWT is positioned to overlap with the power line TVDD and the dummy power line VVDD1 of the routing layer BSM1. The power switch circuit PSW is positioned to overlap with the ground line VSS adjacent to the power line TVDD in the plan view. The control circuit CNTL is positioned to overlap with the ground line VSS and the power line TVDD of the routing layer BSM1 in the plan view. That is, the control circuit CNTL is not positioned to overlap with the power line TVDD of the routing layer BSM1 in the plan view. Note that, as Figure 5 As shown, the control circuit CNTL can be arranged with the switching transistor SWT along the X direction.

[0078] For the switching transistor SWT, it is sufficient to form a PMOS transistor that connects the power line TVDD to the dummy power line VVDD1. Therefore, in the switching transistor SWT, a dummy transistor DMY is formed at the location where the wiring layer BSM1 overlaps with the ground line VSS. Note that the switching transistor SWT can be configured at the location overlapping with the ground line VSS instead of the dummy transistor DMY. In this case, the switching transistor SWT at the location overlapping with the ground line VSS is configured as a PMOS. In addition, the source and drain of the switching transistor SWT at the location overlapping with the ground line VSS are connected to the common ground of the source and drain of the switching transistor SWT at the location overlapping with the power line TVDD and the dummy power line VVDD, respectively.

[0079] Furthermore, since the PMOS transistors formed on both sides of the dummy transistor DMY in the Y direction span the dummy transistor DMY, they cannot be connected via LI wiring. Therefore, for example, the source and drain of the PMOS transistor that overlaps with the virtual power line VVDD1 of the wiring layer BSM1 in the planar diagram are connected via wiring UW2 of the wiring layer above the Mint layer to the source and drain of the PMOS transistor that overlaps with the power line TVDD of the wiring layer BSM1 in the planar diagram.

[0080] Figure 13 Show Figure 4 A variation of the layout. In Figure 13In the example shown, the control circuit CNTL and the power switch circuit PSW are configured separately. Then, using the signal line UW3 located on the surface FS side of the substrate SUB, the output signal OUT0 (from the control circuit CNTL) is transmitted. Figure 3 (Publicly supplied to multiple power switching circuits PSW.) Figure 13 The layout shown reduces the circuit area compared to the case where a control circuit CNTL is set for each power switch circuit PSW.

[0081] Figure 14 Show Figure 13 An example of the layout of a power switching circuit and control circuit. Figure 14 In this circuit, the control circuit CNTL is positioned in the Y direction of the switching transistor SWT. The output signal OUT0 from the inverter IV1 of the control circuit CNTL is supplied to the gates of the PMOS transistors of the multiple power switching circuits PSW via local wiring LI and Mint wiring. Note that the steps for supplying the output signal OUT0 to the gates of the PMOS transistors of the multiple power switching circuits PSW are omitted. Figure 14 The diagram shows the wiring of the switching transistor SWT (not shown) away from the control circuit CNTL in the Y direction.

[0082] Note that wiring from a higher wiring layer than the Mint layer can be used instead of the local wiring LI formed between the inverter IV1 and the power switch circuit PSW for the output signal OUT0. Furthermore, with... Figure 11 Similarly, well tap regions NWTP and PWTP can be set in each power switch circuit PSW. In this case, the well tap regions NWTP and the switching transistors SWT can be arranged in a specific configuration.

[0083] In this embodiment, by suppressing the configuration frequency of the power line TVDD, a virtual power line VVDD2, formed in a position in the plan view that does not overlap with the power switch circuit PSW, can be connected to the source of the PMOS transistor in the power switch circuit PSW. In other words, in a layout where the configuration frequency of the power line TVDD in the wiring layer BSM1 is suppressed, a virtual power potential VVDD can be supplied from the power switch circuit PSW to the virtual power line VVDD2, which is not formed in a position in the plan view that overlaps with the power switch circuit PSW.

[0084] By reducing the configuration frequency of the power line TVDD, the configuration frequency of the virtual power line VVDD and the ground line VSS can be relatively increased, thereby relatively reducing the wiring resistance of the virtual power line VVDD and the ground line VSS.

[0085] By supplying a common output signal OUT0 from the control circuit CNTL to multiple power switch circuits PSW, the circuit area can be reduced compared to, for example, setting a control circuit CNTL for each power switch circuit PSW.

[0086] By using the wiring on the surface FS side of the substrate SUB, the well tap region NWTP that overlaps with the power line TVDD in the plan view is connected to the well tap region NWTP that overlaps with the virtual power line VVDD2 in the plan view, and the power potential TVDD can be supplied to the well region NW that is not in a position that overlaps with the power line TVDD in the plan view.

[0087] The present invention has been described above based on various embodiments, but the present invention is not limited to the elements shown in the above embodiments. These points can be modified without prejudice to the spirit of the invention and can be appropriately determined according to their application.

[0088] Symbol Explanation

[0089] 100 Semiconductor Devices

[0090] BPR Embedded Cabling

[0091] BS back

[0092] BSM1 and BSM2 cabling layers

[0093] C-channel

[0094] CNTL control circuit

[0095] D drain

[0096] DMY pseudo transistor

[0097] FIN fins

[0098] FS surface

[0099] GT gate

[0100] INTR internal circuit area

[0101] IOC, IOCPI / O unit

[0102] IV, IV1, IV2 inverters

[0103] LI local cabling

[0104] Mint Metal Wiring

[0105] NW well region

[0106] NWTP trap tap area

[0107] OUT, OUT0 output signals

[0108] PAD pads

[0109] PSW power switch circuit

[0110] PW well region

[0111] PWTP well tap area

[0112] ROW interval

[0113] S source

[0114] SC Standard Unit

[0115] SCB Standard Unit Block

[0116] SIG signal

[0117] SUB substrate

[0118] SWT switching transistor

[0119] TR transistor region

[0120] TVDD power cord

[0121] VIA, VIA1, VIA2 through holes

[0122] VSS grounding wire

[0123] VVDD, VVDD1, VVDD2 virtual power lines

[0124] W1, W2 wiring

[0125] WL1 and WL2 wiring layers

Claims

1. A semiconductor device, comprising: A substrate having a first through-hole formed thereon; A first power line, a second power line, a third power line, and a fourth power line are formed below the substrate. The first power line is supplied with a first potential, the second power line is supplied with a second potential, the third power line is supplied with a third potential, and the fourth power line is supplied with the second potential. as well as A power switch circuit having a first transistor formed above the substrate and electrically connected between a first power line and a second power line. The first power line, the second power line, the third power line, and the fourth power line extend continuously along a first direction in the plan view. The first transistor has a first source and a first drain. The first transistor is positioned in the plan view at a location overlapping with the first power line. The first source electrode is connected to the first through-hole that is connected to the first power line. The first power line, the second power line, the third power line, and the fourth power line are arranged in a second direction different from the first direction in the plan view. The second power line and the fourth power line are electrically connected via wiring extending along the second direction. The power switch circuit is positioned in the plan view at a location that overlaps with the second power line and is away from the fourth power line.

2. The semiconductor device according to claim 1, wherein, The power switch circuit is provided in multiple ways, and the multiple power switch circuits are arranged along the first direction.

3. The semiconductor device according to claim 2, wherein, The first drains of the first transistors of the plurality of power switch circuits are electrically connected via wiring extending along the second direction to the fourth power line that does not overlap with the power switch circuit in the plan view.

4. The semiconductor device according to any one of claims 1 to 3, wherein, The power switch circuit also includes a control circuit for controlling the gate potential of the first transistor. The first transistor and the control circuit are arranged along the second direction.

5. The semiconductor device according to claim 4, wherein, The control circuit controls the gate potential of the first transistor in the plurality of power switching circuits.

6. The semiconductor device according to any one of claims 1 to 3, comprising: A well tap region, which is disposed above the substrate at a position overlapping the first power line in the plan view, is connected to a second via formed on the substrate and supplies the first potential to the first well of the first transistor; as well as The wiring electrically connects the first well of the first transistor to the second well of the transistor, which is located in a position in the plan view that does not overlap with the first power line.

7. The semiconductor device according to any one of claims 1 to 3, wherein, The power switch circuit is configured in the plan view at a position overlapping with the third power line adjacent to the first power line.

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