3D stacked high-speed visible light avalanche photodiode / single photon avalanche diode

Abstract

A backside illuminated (BSI) photodiode device includes a backside coupled with a plurality of microlenses, including a first microlens and a second microlens. The device includes a first doped region of p-type material within a first thickness of the backside, and a first sidewall having a first deep trench isolation (DTI) region; the front surface comprises a first sub-pixel region aligned with the first micro-lens and a second sub-pixel region aligned with the second micro-lens, and each sub-pixel region comprises a shaped p-type layer and a shaped n-type layer; the interconnect layer includes an electrode coupled with the molding layer. The device may also include an application specific integrated circuit (ASIC) coupled to the electrodes, and may act as an avalanche photodiode or a single photon avalanche diode having a thickness between the front and back surfaces of less than 3 [mu] m. Other embodiments are also provided.

Description

[0001] Cross-references to related applications

[0002] This section is not required if priority data is included in the Application Data Sheet (ADS). However, add this section to include other references. If you add text to this section, remove "Not Applicable".

[0003] This application claims priority to U.S. Provisional Application No. 63 / 533,039, filed February 13, 2024, entitled “3D Stacked High-Speed ​​Visible Avalanche Photodiode / Single Photon Avalanche Diode,” which is owned by the same applicant and whose entire contents are incorporated herein by reference. Technical Field

[0004] This invention relates to photodetector devices, and more specifically, to a high-speed back-illuminated avalanche photodiode or single-photon avalanche diode with a 3D stacked architecture. Background Technology

[0005] In recent years, the exponential growth of artificial intelligence (AI) and machine learning (ML) technologies has dramatically increased the demand for high-speed data processing and real-time communication within data centers. AI-driven applications, such as deep learning, natural language processing, and autonomous systems, require the parallel processing of massive amounts of data in distributed computing networks. This surge in data volume and complexity has pushed the electrical interconnects used in traditional data centers to their limits, leading to the widespread adoption of optical communication technologies to meet the demands for higher bandwidth, lower latency, and more energy-efficient data transmission.

[0006] In AI data centers, optical transceivers form the backbone of high-speed data exchange between servers, storage units, and computing nodes. These transceivers rely on photodiodes, such as avalanche photodiodes (APDs) and single-photon avalanche diodes (SPADs), to detect optical signals and convert them into electrical signals that can be processed by digital systems. However, as AI models become increasingly large and complex, the speed at which these photodiodes read and process incoming optical signals becomes a critical performance factor.

[0007] Therefore, new and improved photodiode devices are needed. Summary of the Invention

[0008] This overview is intended to introduce, in a simplified form, several concepts further elaborated in the detailed description below. This overview is not intended to identify key or necessary characteristics of the requested subject matter, nor is it intended as an aid in determining the scope of the requested subject matter.

[0009] In one embodiment, the present invention provides a back-illuminated photodiode device having a plurality of microlenses connected to its back side, including a first microlens and a second microlens. The device includes a first doped region of p-type material within a first thickness on the back side, and a first sidewall having a first deep trench isolation region. The front side includes a first sub-pixel region aligned with the first microlens and a second sub-pixel region aligned with the second microlens, each sub-pixel region comprising shaped p-type and n-type layers. An interconnect layer includes electrodes connected to the shaped layers. The device may further include an application-specific integrated circuit (ASIC) connected to the electrodes, and may be an avalanche photodiode or a single-photon avalanche photodiode with a thickness of less than 3 micrometers. Other embodiments are also available.

[0010] According to one aspect of the present invention, a back-illuminated (BSI) photodiode device is provided. The device includes a back surface and a plurality of microlenses connected to the back surface, the microlenses including a first microlens and a second microlens. The device includes a first doped region disposed within a first thickness of the back surface, the first doped region comprising a p-type material. The device includes a first sidewall and a second sidewall, the first sidewall comprising a first deep trench isolation (DTI) region. The device includes a front surface. The device includes a first sub-pixel region located at a second thickness of the front surface and aligned with the first microlens, the first sub-pixel region comprising a shaped p-type layer and a shaped n-type layer. The device includes a second sub-pixel region located at a second thickness of the front surface and aligned with a second microlens, the second sub-pixel region comprising a shaped p-type layer and a shaped n-type layer. The device includes an interconnect layer comprising a first electrode group and a second electrode group, the first electrode group being connected to the first-shaped p-type layer and the second-shaped p-type layer, and the second electrode group being connected to the first-shaped n-type layer and the second-shaped n-type layer.

[0011] According to other aspects of the invention, the device may further include one or more of the following features: The device may include an n-type layer of a third shape located between a first sub-pixel region and a second sub-pixel region. The device may include an application-specific integrated circuit (ASIC) connected to a first electrode group and a second electrode group. The first electrode group may include multiple anodes, and the second electrode group may include multiple cathodes. The BSI photodiode device may be an avalanche photodiode or a single-photon avalanche photodiode. The first sub-pixel region and the second sub-pixel region may be separated by a shallow trench isolation region. The device may include an epitaxial layer located between a back side and a front side. The device may include a first side layer disposed along a first sidewall, the first side layer comprising a p-type material. The device may include a second side layer disposed along the first side layer, the second side layer comprising a p-type material and having a doping gradient, wherein the doping concentration of the first side of the second side layer in contact with the first side layer is higher than the doping concentration of the second side layer away from the first side layer. The thickness between the front and back sides may be less than 3 micrometers.

[0012] According to another aspect of the present invention, a back-illuminated (BSI) photodiode device is provided. The device includes a back surface and a plurality of microlenses connected to the back surface. The device includes a first doped region of p-type material located within a first thickness of the back surface. The device includes a front surface opposite the back surface. The device includes a first sub-pixel region and a second sub-pixel region located on the front surface, each sub-pixel region comprising a shaped p-type layer and a shaped n-type layer, the first sub-pixel region being aligned with a first microlens. The device includes an interconnect layer comprising a plurality of electrodes connected to the shaped p-type layer and the shaped n-type layer. The device includes an application-specific integrated circuit (ASIC) connected to the plurality of electrodes, the ASIC being configured to process electrical signals generated by the sub-pixel regions to achieve high-speed readout.

[0013] According to other aspects of the invention, the device may further include one or more of the following features: The shaped p-type layer and the shaped n-type layer in each sub-pixel region may be separated by a shallow trench isolation (STI) region. The device may include a deep trench isolation (DTI) region for separating adjacent sub-pixel regions. A first doped region may extend along the sidewall of the device to form a continuous p-type layer surrounding the sub-pixel region. The device may include a gradient-doped p-type layer adjacent to the first doped region, the gradient-doped p-type layer having a higher doping concentration near the first doped region and a lower doping concentration away from the first doped region. The shaped n-type layer in each sub-pixel region may include multiple finger electrodes to reduce lateral transport time.

[0014] According to one aspect of the invention, an optical receiving system is provided. The system includes a plurality of photodiodes configured according to a first arrangement based on a second arrangement associated with an optical communication link bundle. Each photodiode may include a back side and a front side, with a p-type doped region disposed within a first thickness of the back side. The photodiode may have sidewalls, wherein at least one sidewall includes a deep trench isolation (DTI) region. The front side may include a plurality of sub-pixel regions, each sub-pixel region including a shaped p-type layer and an n-type layer. An interconnect layer includes electrodes connected to these shaped layers.

[0015] In some aspects, the system may include a microlens aligned with the sub-pixel region of the photodiode. The interconnect layer may include an anode connected to the p-type layer and a cathode connected to the n-type layer. In some implementations, the photodiode in the system may have a width ranging from 40 μm to 60 μm.

[0016] An optical receiving system can be configured to receive and process optical signals from multiple communication links, with its photodiode array corresponding to the arrangement of these links. This configuration allows for efficient detection and processing of optical signals in high-speed communication applications.

[0017] These and other benefits are achieved by the present invention within the context of known technologies. However, the nature and advantages of the invention can be further understood by referring to the latter part of the specification and the accompanying drawings. Attached Figure Description

[0018] Examples of non-restrictiveness and non-exhaustiveness are illustrated in the following figures.

[0019] Figure 1A A cross-sectional view of a BSI photodiode according to various aspects of the present invention is shown.

[0020] Figure 1B A top view of a BSI photodiode with a 2×2 subpixel array configuration according to one embodiment is shown.

[0021] Figure 2 A cross-sectional view of a BSI photodiode with a gradient doped layer according to various aspects of the present invention is shown.

[0022] Figure 3 A top orthogonal view of a subpixel array according to one embodiment is shown.

[0023] Figure 4 A top orthogonal view of a pixel array according to various aspects of the present invention is shown.

[0024] Figure 5A A cross-sectional view of a photodiode according to an embodiment of the present invention is shown.

[0025] Figure 5B Various aspects of the invention are shown. Figure 5A A top view of a photodiode. Detailed Implementation

[0026] In one embodiment, the present invention provides a back-illuminated photodiode device, including a back side coupled with a plurality of microlenses, including a first microlens and a second microlens. The device includes a first doped region of p-type material located within a first thickness of the back side, and a first sidewall having a first deep trench isolation region. The front side includes a first sub-pixel region aligned with the first microlens and a second sub-pixel region aligned with the second microlens, each sub-pixel region comprising shaped p-type and n-type layers. An interconnect layer includes electrodes coupled to the shaped layers. The device may further include an application-specific integrated circuit coupled to the electrodes and may serve as an avalanche photodiode or a single-photon avalanche photodiode with a thickness of less than 3 μm between the front and back sides. Other embodiments are also available.

[0027] As mentioned above, existing photodiode devices are insufficient to meet the demands of optical communication applications. For example, existing front-illuminated (FSI) photodiode architectures have limitations that hinder their performance in high-speed applications. In FSI structures, incident photons must pass through multiple dielectric layers and metal interconnects before reaching the active region of the photodiode, resulting in optical loss and prolonged carrier transport time. This not only reduces the device's sensitivity but also introduces delay, limiting the achievable data rates.

[0028] To address these issues, back-illuminated (BSI) architectures have been developed, in which photons enter the active region of the photodiode directly from the back of the device. This configuration minimizes optical losses and achieves more efficient photon absorption. However, even with BSI designs, optimizing readout speed and signal integrity remains challenging, especially when scaling photodiode arrays for high-bandwidth applications.

[0029] One challenge in achieving high-speed readout is carrier transport time—the time required for photogenerated carriers (electrons and holes) to reach the collecting electrode. In traditional photodiodes, carrier transport time is typically dominated by the diffusion process, which is inherently slow and introduces variability in signal timing. This becomes a bottleneck for applications requiring precise timing resolution, such as time-of-flight (ToF) sensors and photon counting communication systems.

[0030] To overcome these limitations, APDs and SPADs are employed in various embodiments because they are capable of operating in avalanche mode, where a single photon can trigger a cascade reaction of current carriers through shock ionization. This process significantly amplifies the signal, even detecting extremely weak optical signals. However, the readout circuitry must be able to process these fast signal events with minimal delay and noise, which is typically challenging in traditional integrated circuit (IC) technology.

[0031] Various embodiments of the present invention utilize 3D stacking technology to open new possibilities for integrating high-speed application-specific integrated circuits (ASICs) directly with photodiode arrays. By stacking the ASIC on a different wafer than the photodiode sensor, designers can leverage advanced semiconductor process nodes (e.g., 20nm for ASICs and 40nm+ for photodiodes) to optimize speed and sensitivity. This approach allows for parallel processing of signals from multiple photodiode elements, significantly reducing latency and power consumption while increasing data throughput.

[0032] In various embodiments, this invention provides innovations such as multiple pn junction regions, gradient doping profiles, and deep trench isolation (DTI) techniques to enhance the performance of APDs and SPADs. These features shorten lateral carrier transport time, minimize crosstalk between adjacent pixels, and improve the overall signal-to-noise ratio (SNR). Combined with a back-side microlens array that precisely focuses light onto the active region of the photodiode, these techniques enable faster and more accurate detection and readout of optical signals.

[0033] It should be understood that the photodiode architecture according to embodiments of the present invention can provide ultrafast readout speeds while maintaining high sensitivity and low noise characteristics. Such devices are crucial for next-generation high-speed communication systems, where the ability to transmit and process large amounts of data with minimal latency and high fidelity is essential.

[0034] The following description is provided to enable those skilled in the art to make and use the invention, and to place it in the context of a particular application. Various modifications and uses in different applications will be apparent to those skilled in the art, and the general principles defined herein can be applied to a wide range of embodiments. Therefore, the invention is not limited to the proposed embodiments, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

[0035] Numerous specific details are set forth in the following detailed description in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced and is not limited to these specific details. In other instances, well-known structures and apparatuses are shown in block diagram form rather than in detail to avoid obscuring the invention.

[0036] Readers should note that all papers and documents submitted concurrently with this specification are publicly available, and the contents of all such papers and documents are incorporated herein by reference. Unless otherwise expressly stated, all functions disclosed in this specification (including any appended claims, abstracts, and drawings) may be replaced by alternative functions for the same, equivalent, or similar purposes. Therefore, unless otherwise expressly stated, each disclosed feature is merely one example of a general series of equivalent or similar features.

[0037] Furthermore, no element not expressly stated in the claims, unless it expressly refers to "means" or "steps" for performing a particular function, shall be construed as a "means" or "step" as provided in Section 112, paragraph 6 of 35 U.S.C. In particular, the use of "steps" or "actions" in this claim is not intended to invoke paragraph 6 of 35 U.S.C.

[0038] Please note that if used, the labels left, right, front, back, up, down, front, reverse, clockwise, and counterclockwise are for convenience only and do not imply any particular fixed direction. Rather, they are used to reflect the relative position and / or orientation between different parts of an object.

[0039] Figure 1A A cross-sectional view of a BSI photodiode 100 is shown. The BSI photodiode 100 may include a back side and a front side. This figure is merely illustrative and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art. In some cases, multiple microlenses may be attached to the back side of the BSI photodiode 100. The multiple microlenses may include microlens 101 and microlens 102. These microlenses can be configured to focus incident light onto an effective area of ​​the device.

[0040] The BSI photodiode 100 may include an epitaxial layer 103 located between a back side and a front side. Within the epitaxial layer 103, a first sub-pixel region and a second sub-pixel region may be located at the thickness of the front side. The first sub-pixel region may be aligned with a microlens 101 and may contain a shaped n-type layer 104. The second sub-pixel region may be aligned with a microlens 102 and may contain a shaped n-type layer 105.

[0041] In some cases, the BSI photodiode 100 may include a first doped region disposed within the back thickness. This first doped region may include a p-type material and may include a p-type top layer 115. The device may also include p-type side layers 114, 116, and 124 positioned along the side of the structure.

[0042] The BSI photodiode 100 may include a first sidewall and a second sidewall. In some embodiments, the first sidewall may include a DTI 106 and the second sidewall may include a DTI 107. These deep trench isolation regions can provide electrical isolation between adjacent pixels or subpixels.

[0043] Within the sub-pixel region, shallow trench isolation (STI) structures may exist. These may include STI 108, STI 109, STI 110, and STI 111. STI structures can provide isolation between different doped regions within each sub-pixel.

[0044] Interconnect layer 112 may be included in BSI photodiode 100. Interconnect layer 112 may include a first electrode group and a second electrode group. In some cases, the first electrode group may include anodes 119, 121, and 123, while the second electrode group may include cathodes 120 and 122. The first electrode group may be coupled to a shaped p-type layer, and the second electrode group may be coupled to a shaped n-type layer.

[0045] The BSI photodiode 100 can be configured as a 3D stacked structure. In this configuration, the ASIC substrate 117 can be located below the interconnect layer 112. The ASIC 118 can be fabricated on the ASIC substrate 117. The ASIC 118 can be coupled to a first electrode group and a second electrode group through the interconnect layer 112.

[0046] In some implementations, the thickness between the front and back sides of the BSI photodiode 100 may be less than 3 μm. This thin structure may facilitate high-speed operation of the device.

[0047] The BSI photodiode 100 can be configured as an avalanche photodiode or a single-photon avalanche photodiode. These configurations can achieve high sensitivity under low light conditions and may enable single-photon detection in certain situations.

[0048] exist Figure 1A In some embodiments of the BSI photodiode 100 shown, large pixels (e.g., pixels with a size exceeding 15 μm) can be divided into smaller sub-pixel regions to improve device performance. For example, large pixels can be divided into 2×2, 3×3, or 4×4 sub-pixel arrays. This sub-pixel division, as shown in the figure, where the first sub-pixel region includes a shaped n-type layer 104 and the second sub-pixel region includes a shaped n-type layer 105, can help reduce the lateral transport time of charge carriers, thereby potentially improving the overall speed of the device.

[0049] Subpixel regions within larger pixels can be designed to have uniform or non-uniform size and shape. This flexibility in subpixel configuration can allow for device optimization for specific applications or light detection requirements. In some cases, non-uniform subpixel arrangements can be used to improve the sensitivity of specific regions of a pixel or to match a desired light distribution pattern.

[0050] To further improve light collection efficiency, the BSI photodiode 100 can use multiple microlenses for each pixel. For example, 2×2, 3×3, or 4×4 microlens arrays, such as microlenses 101 and 102, can be used to focus incident light onto a high-field region within the sub-pixel. This microlens array configuration may help concentrate light into the most sensitive region of each sub-pixel, potentially improving overall quantum efficiency and signal-to-noise ratio.

[0051] The BSI photodiode 100 can also integrate back-side deep trench isolation (DTI) structures, such as DTI 106 and DTI 107, between pixels to reduce crosstalk. These DTI structures may extend from the back of the device to the front, creating physical and electrical barriers between adjacent pixels. By minimizing the propagation of charge carriers between adjacent pixels, DTI structures help maintain signal integrity and improve overall image quality, especially in high-contrast scenes or when detecting details.

[0052] Figure 1B A top view of a BSI photodiode 100 with a 2×2 subpixel array configuration is shown. This figure is merely an example and should not be overly limiting of the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art. The BSI photodiode 100 includes four subpixels arranged in a square, each subpixel having a similar internal structure.

[0053] The structure includes microlenses 101 and 102, and microlenses 127 and 128 located at each corner of the array. These microlenses can be configured to focus incident light onto their respective sub-pixels.

[0054] Deep trench isolation (DTI) structures 106 and 107 form the outer boundary of the array, providing electrical isolation between adjacent pixels. Within each sub-pixel, shallow trench isolation (STI) structures 108, 109, 110, and 111 are arranged in parallel stripes. These STI structures separate the different doped regions within each sub-pixel.

[0055] The array includes a p-type region with p-type side layers 114 and 116, and a p-type top layer 115. Shaped p-type layers 125 and 126 are incorporated into the structure. Epitaxial layer 103, together with shaped n-type layers 104 and 105, forms part of the device structure.

[0056] In some cases, the BSI photodiode 100 may include a third-shaped n-type layer located between the first and second sub-pixel regions. The third-shaped n-type layer can provide additional control over the electrical characteristics of the device.

[0057] The arrangement of components creates four distinct subpixels, each containing multiple parallel structures separated by STI regions. In some cases, the first and second subpixel regions may be separated by shallow trench isolation regions. This separation can help reduce electrical crosstalk between adjacent subpixels.

[0058] exist Figure 1AIn some embodiments of the BSI photodiode 100 shown, the device can be optimized for visible light detection in the approximately 380-700 nanometer range. The epitaxial layer 103 can be designed to be relatively thin because silicon has a high absorption coefficient in this wavelength range. This thin epitaxial structure allows for efficient absorption of visible light photons within a compact device architecture. The back-illuminated configuration of the BSI photodiode 100 can offer several advantages compared to conventional front-illuminated structures. In front-illuminated devices, incident light typically must pass through a thick dielectric layer to reach the active region, which can lead to unwanted absorption and reduced sensitivity. However, in the BSI photodiode 100, light enters directly from the back side, which lacks a thick dielectric layer. This design choice can significantly improve the device's sensitivity to incident light.

[0059] The 3D stacked structure of the BSI photodiode 100, where the ASIC 118 is located on a separate substrate 117, allows for a larger absorption area in the sensor section without affecting the area of ​​the ASIC 118. This separation of the sensor and ASIC components allows for more efficient use of the overall device footprint. Furthermore, the stacked configuration may help reduce sensor congestion that can occur when the ASIC is placed in the optical path. By placing the ASIC 118 below the sensor section, the BSI photodiode 100 achieves higher light collection efficiency and overall performance.

[0060] It is important to note that, in Figure 1A In the BSI photodiode 100, the absence of a thick silicon substrate may help reduce thermal noise. The thin epitaxial layer 103 can minimize the volume of silicon that can generate thermally generated charge carriers. The reduction in thermally generated charge carriers may improve the signal-to-noise ratio (SNR), especially under low-light conditions where thermal noise can be a significant factor.

[0061] When configured as a single-photon avalanche diode (SPAD), the BSI photodiode 100 may suffer from thermal noise in the form of dark counts. These are false detection events caused by avalanche events triggered by thermally generated charge carriers. The thin structure of the BSI photodiode 100 helps to minimize the dark count rate by reducing the volume of heat-generating carriers, thereby improving the device's SNR and detection accuracy. The BSI photodiode 100 does not have the thick substrate typically found in front-illuminated sensors. This absence may allow for a shorter carrier transport distance from the back side to the collection area near the front side. The shorter transport distance reduces the probability of carrier recombination or trapping, thereby improving quantum efficiency and SNR, especially for longer wavelengths of light that penetrate deeper into silicon. Compared to conventional thick sensors, the thin structure of the BSI photodiode 100 reduces the depletion region. This smaller depletion region can result in lower capacitance, potentially leading to faster response times and lower electronic noise. The combination of lower capacitance and reduced noise contributes to improved SNR, especially in high-speed applications where rapid signal readout is crucial.

[0062] In various implementations, the BSI photodiode 100 features an optimized structure for back illumination. The arrangement of the p-type top layer 115 and the shaped n-type layers 104 and 105 generates an electric field distribution that effectively guides photogenerated carriers to the collection region. This optimized structure improves charge collection efficiency and reduces lateral carrier diffusion, thereby enhancing the device's SNR by minimizing crosstalk between adjacent sub-pixels and improving the overall quantum efficiency of the sensor.

[0063] Although Figure 1B The 2×2 subpixel array configuration has been described, but in some cases, the subpixel array can be arranged in other configurations, such as 3×3 or 4×4. These different configurations provide flexibility in designing the BSI photodiode 100 to meet various application and performance requirements.

[0064] Figure 2 A cross-sectional view of a BSI photodiode 200 is shown. This figure is merely an example and should not be overly limiting of the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art. The BSI photodiode 200 may include multiple p-type layers arranged in a configuration forming a gradient doping profile.

[0065] In some cases, the BSI photodiode 200 may include a p-type gradient side layer 201 positioned along the side of the structure. A p-type side layer 202 may be adjacent to the p-type gradient side layer 201. The p-type side layer 202 may include a p-type material and may be arranged along the first sidewall of the BSI photodiode 200.

[0066] The top of the structure may include a p-type top layer 203 and a p-type gradient top layer 204. The p-type gradient side layer 201 and the p-type gradient top layer 204 can be implemented to generate an electric field that can accelerate charge carriers within the device.

[0067] In some implementations, the p-type gradient side layer 201 can be characterized by a doping gradient. The first side adjacent to the p-type gradient side layer 202 can have a higher doping concentration compared to the second side of the p-type gradient side layer 201 that is farther from the p-type side layer 202. This gradient doping profile may help improve carrier acceleration and device performance.

[0068] The arrangement of these p-type layers with different doping concentrations may generate a built-in electric field within the BSI photodiode 200. This electric field may help accelerate the movement of photogenerated carriers to the collection region, potentially improving the device's speed and efficiency.

[0069] In some cases, the gradient doping profile may extend from the side regions to the top region of the BSI photodiode 200, creating a continuous gradient effect. This configuration may help optimize carrier collection in different regions of the device.

[0070] exist Figure 2 In some embodiments of the BSI photodiode 200 shown, multiple injection regions can be combined to create a doping gradient distribution within the device structure. This gradient doping distribution is represented by a p-type gradient side layer 201 and a p-type gradient top layer 204, which are adjacent to p-type side layers 202 and 203, respectively. The doping gradients generated by these multiple injection regions can produce electric fields within the device. This electric field can help accelerate charge carriers (electrons and holes) as they move through the structure. For example, the gradient between p-type gradient side layers 201 and 202 can generate an electric field that laterally guides the charge carriers, while the gradient between the p-type gradient top layer 204 and other regions can generate a vertical electric field component. Due to the acceleration of charge carriers caused by these electric fields, the transport time of photogenerated charge moving to the collection region may be faster. The reduced transport time may result in faster readout of the optical signal, potentially enabling the BSI photodiode 200 to operate at higher speeds.

[0071] In some cases, specific doping profiles and gradients can be customized to optimize carrier acceleration for specific wavelengths of light or applications. The ability to fine-tune these doping gradients provides a means of balancing factors such as sensitivity, speed, and noise performance in the BSI photodiode 200.

[0072] The cross-sectional view shows the internal arrangement of these p-type layers, which form part of the photodiode structure. The bottom of the figure may show other structural elements, including isolation regions and interconnect features, which may resemble the descriptions associated with other figures.

[0073] Figure 3 A top orthographic view of the subpixel array 300 is shown. The subpixel array 300 can be arranged in a 3×3 grid pattern, where each cell in the grid represents a single subpixel. In some cases, subpixels may be separated by shaded boundary regions that define the boundaries of adjacent subpixels.

[0074] The array structure of subpixel array 300 can display nine equally sized square subpixels arranged in a uniform pattern. The shaded areas surrounding and separating the subpixels may represent isolation structures between the individual subpixels. These isolation structures may resemble deep trench isolation (DTI) or shallow trench isolation (STI) structures associated with other images.

[0075] In some implementations, the subpixel array 300 may be part of a larger BSI photodiode structure. Each subpixel in the array may include components such as a shaped n-type layer, a shaped p-type layer, and other elements related to the previous figure.

[0076] The 3×3 grid pattern of the subpixel array 300 can offer several advantages for device performance and functionality. In some cases, this arrangement may allow for improved spatial resolution in light detection. By dividing larger pixels into multiple subpixels, the device may be able to capture more detailed information about the distribution of incident light.

[0077] Isolation structures between sub-pixels (as shown in the shaded area) help reduce electrical crosstalk between adjacent sub-pixels. This reduction in crosstalk helps improve signal integrity and enables more accurate light detection and measurement.

[0078] In some implementations, the 3×3 grid pattern can also facilitate parallel readout of multiple subpixels. This parallel readout capability can help accelerate the overall device operation, enabling high-speed applications such as time-of-flight measurements or high frame rate imaging.

[0079] The uniform size and arrangement of subpixels in the 300-pixel array allow for consistent performance across the entire array. In some cases, this consistency can simplify signal processing and calibration procedures throughout the device.

[0080] In some specific implementations, Figure 3The subpixel array 300 shown may be part of a stacked structure that allows for highly flexible pixel arrangement. This flexibility in the pixel array pattern may enable the sensor detection area to better match the optical contours of various objects or phenomena being detected, potentially improving sensitivity.

[0081] Figure 3 The 3×3 grid pattern shown is just one possible configuration. In other implementations, the subpixel array can be arranged in a non-uniform pattern or other shapes to suit specific detection requirements. For example, the array can be configured as circular, hexagonal, or irregular shapes depending on the application needs. This adaptability of the pixel arrangement makes the device suitable for a wide range of applications. In some cases, the pixel layout can be optimized to match the expected light distribution of a specific scene or object, potentially improving overall detection efficiency. The ability to customize the pixel array distribution may allow for customized solutions in various fields such as machine vision, automotive sensing, or scientific imaging. The flexibility provided by the stacked structure also allows for the integration of pixels with different sizes or sensitivities into the same array. In some implementations, this heterogeneous pixel arrangement allows for the simultaneous capture of high-resolution details and high-sensitivity low-light information, further expanding the potential applications of the device.

[0082] Figure 4 A top orthographic view of pixel array 400 is shown. Pixel array 400 may include multiple square pixels arranged in a non-uniform pattern. In some cases, pixels in pixel array 400 may be represented by shaded squares located in an asymmetrical configuration.

[0083] The arrangement of the pixel array 400 can display different spacings between the individual pixels, thus producing an irregular grid pattern. In some specific implementations, the pixels in the pixel array 400 can be distributed in the array in a way that allows for flexible positioning while maintaining connectivity between elements.

[0084] This non-uniform arrangement of pixels in pixel array 400 offers several potential advantages for various applications. In some cases, the flexible configuration allows for custom pixel layouts to meet specific light detection requirements. For example, certain areas of pixel array 400 can have higher pixel density to provide higher resolution in the region of interest.

[0085] In some cases, the pixel array 400 may be part of a larger BSI photodiode structure. Each pixel in the array may include components such as shaped n-type layers, shaped p-type layers, and other elements related to the previous figure.

[0086] The pixel array 400 may also offer advantages in signal processing and readout. In some cases, the non-uniform arrangement may allow for selective reading of specific regions of interest within the array, potentially providing faster processing speeds for certain applications.

[0087] Although Figure 4 A specific non-uniform arrangement is shown, but in some implementations, the pixel array 400 can be configured with different patterns or distributions of pixels. A specific configuration can be selected based on factors such as required spatial resolution, readout speed, or specific application requirements.

[0088] As an example, pixel array 400 includes a plurality of circular pixels arranged in a hexagonal pattern. Pixel array 400 includes a pixel 401 and an optical link 402 aligned with the first pixel 401. For example, the space between pixels is represented by a shading pattern, indicating isolation structures or boundaries between the individual pixels, which may include deep trench isolation (DTI) regions. According to embodiments, the pixel array may include hundreds or more pixels arranged to align with a set of optical links (e.g., optical fibers), wherein one or more pixels may be configured to detect light from the optical links.

[0089] It is important to note that the 2D array structure facilitates easy expansion to accommodate additional channels. This allows for increased optical communication capacity within a compact size, making it suitable for high-density optical receiver applications. The array can be easily expanded to match the arrangement of optical communication link bundles.

[0090] In some embodiments, some sub-pixels in the array can be used as matched dummy capacitors in the differential circuit. This enhances circuit balance and symmetry, thereby improving overall performance. This configuration optimizes the power supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR) of the differential circuit. By providing closely matched capacitive elements in the same array structure, this design reduces sensitivity to power supply fluctuations and common-mode noise. In various embodiments, the pixel arrangement contributes to improved noise performance through the balanced distribution of sub-pixels and the ability to implement differential sensing techniques.

[0091] The pixel layout allows next-generation devices to reduce fiber spacing from the current 50μm to 25μm. This 2D array sensor can be easily scaled up to achieve four times the bandwidth in future implementations, demonstrating its adaptability to evolving optical communication standards.

[0092] The system may include microlenses aligned with the sub-pixel regions to improve light collection efficiency and signal-to-noise ratio. Photodiodes in the array can be designed with specific dimensions, such as widths of 40 μm to 60 μm, to meet the requirements of various optical communication systems and fiber optic spacing. The interconnect layer includes multiple anodes connected to the p-type layer and multiple cathodes connected to the n-type layer, facilitating efficient collection and transmission of electrical signals.

[0093] Figure 5A A cross-sectional view of a photodiode 500 is shown. The photodiode 500 may include a first sidewall 501 and a second sidewall 502 defining the lateral boundaries of the device. In some cases, the photodiode 500 may be configured as a BSI photodiode.

[0094] The photodiode 500 may include multiple p-type layers arranged within its structure. These may include p-type layers 503, 504, 505, 506, and 507. The p-type layers may be located at different positions across the device width, contributing to the overall electrical characteristics of the photodiode 500. Depending on the implementation, the p-type layers may have different doping concentrations.

[0095] In some implementations, the photodiode 500 may include n-type layers 508 and 509. These n-type layers may be located within the device and may have a grid-like pattern. In some cases, the n-type layers 508 and 509 may include multiple finger electrodes. The finger electrode configuration can help reduce the lateral transport time of charge carriers, thereby potentially increasing the speed of the device.

[0096] Interconnect layer 510 may be located at the bottom of photodiode 500. Interconnect layer 510 may be connected to various components, including anode 511 and cathode 512. These electrodes may facilitate the collection and transmission of electrical signals generated within photodiode 500.

[0097] The bottom of the photodiode 500 may include a substrate 520. In some cases, an ASIC 521 may be fabricated on the substrate 520. The ASIC 521 can be connected to the anode 511 and the cathode 512 via an interconnect layer 510. This configuration allows the ASIC 521 to process the electrical signals generated by the photodiode 500 for high-speed readout.

[0098] In some implementations, the ASIC 521 can be manufactured using a more advanced technology node compared to the photodiode 500. For example, the ASIC 521 can be manufactured using a 20nm process, while the photodiode 500 can be manufactured using a 40nm or larger process. This difference in manufacturing process allows for the optimization of both the sensing capability of the photodiode 500 and the processing speed of the ASIC 521.

[0099] P-type and n-type layers can be arranged alternately to create different regions within the photodiode 500 structure. This arrangement facilitates the formation of sub-pixel regions within the device. In some cases, the shaped n-type layer in each sub-pixel region can contain multiple finger electrodes to reduce the lateral transport time of charge carriers.

[0100] exist Figure 5B In some embodiments of the photodiode device 500 shown, the concentric p-type layers can be spaced apart by a specific distance to optimize device performance. For example, the distance between adjacent concentric p-type layers, such as between p-type layers 503 and 504, or between p-type layers 504 and 505, can range from 2 micrometers (μm) to 5 μm. This spacing helps balance various factors, such as charge collection efficiency, reduction of crosstalk between adjacent regions, and overall device sensitivity. The spacing between adjacent p-type layers can be selected based on a variety of factors, including the intended application of the photodiode, the required spectral response, and the specific manufacturing process used. In some cases, a spacing in the range of 2 μm to 5 μm may allow for efficient charge carrier collection while maintaining a compact overall device structure. This spacing can also help create depletion regions between adjacent p-type layers, which can help improve photodetection performance. It should be noted that although a range of 2 μm to 5 μm has been described, the actual spacing may vary depending on specific design requirements and may be adjusted within or even outside this range in some implementations. The ability to fine-tune these spacings can provide flexibility for optimizing photodiode devices for a variety of applications, such as high-speed imaging, low-light detection, or specific wavelength sensitivity.

[0101] The cross-sectional view shows the vertical arrangement of these components, with interconnect layer 510 providing electrical connections between the photodiode 500 structure and the ASIC 521. This configuration enables efficient signal processing and high-speed readout of electrical signals generated in the sub-pixel regions of the photodiode 500.

[0102] Figure 5B A top orthographic view of a photodiode 500 is shown. This figure is merely an example and should not be overly limiting of the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art. The photodiode 500 may include a first sidewall 501 and a second sidewall 502 defining the outer boundary of the device. In some cases, the structure may contain multiple concentric regions with different doping characteristics.

[0103] The photodiode 500 may include several p-type layers arranged in a concentric pattern. P-type layer 503 may be located near the first sidewall 501, while p-type layer 504 may form the inner region. Additional p-type layers, including p-type layers 505, 506, and 507, may be arranged in a pattern that moves outward from the center.

[0104] In some implementations, the structure may also include n-type regions. An n-type layer 508 may be located near a p-type layer 506, and an n-type layer 509 may be located near a second sidewall 502. The arrangement of these doped regions may create a series of alternating p-type and n-type regions within the device.

[0105] The concentric patterns of the doped regions can be represented by different shading patterns in the diagram. In some cases, diagonals may represent certain areas, while darker shading may represent other areas. This arrangement of doped layers may enable the photodiode 500 to be used as a photosensor.

[0106] In some implementations, the concentric arrangement of p-type and n-type layers may contribute to the overall light sensing capability of the photodiode 500. Alternating patterns of different doped regions may create multiple pn junctions within the device. These junctions may facilitate the separation and collection of photogenerated charge carriers.

[0107] Concentric configuration allows for efficient light absorption across the entire area of ​​the photodiode 500. In some cases, this arrangement helps minimize edge effects and ensure consistent sensitivity throughout the device. Multiple concentric regions may also contribute to improved charge collection efficiency because charge carriers generated in different regions of the device may have a shorter distance to reach the collection region.

[0108] In some implementations, n-type layers 508 and 509 can be used as cathode regions, while p-type layers can be used as anode regions. The alternating arrangement of these layers may generate a radial electric field within the photodiode 500. This radial field may help guide photogenerated carriers to the collection region, potentially improving the device's speed and efficiency.

[0109] Concentric configurations can also offer advantages in terms of device scalability. In some cases, the number and width of the concentric regions can be adjusted to optimize the photodiode 500 for a specific application or performance requirement. This flexibility may allow for customization of device characteristics such as sensitivity, speed, or spectral response.

[0110] This figure is merely an example and should not be used to unduly limit the scope of the claims. Many variations, alternatives, and modifications will be apparent to those skilled in the art.

[0111] While the foregoing is a complete description of specific embodiments, various modifications, alternative structures, and equivalents may be used. Therefore, the foregoing description and illustrations should not be construed as limiting the scope of the invention as defined by the appended claims.

Claims

1. A back-illuminated (BSI) photodiode device, characterized in that, include: back; Multiple microlenses are connected to the back side, the multiple microlenses including a first microlens and a second microlens; A first doped region is disposed within a first thickness on the back side, the first doped region comprising p-type material; First sidewall and second sidewall, the first sidewall including a first deep trench isolation (DTI) area; front; A first sub-pixel region located at the second thickness on the front side and aligned with the first microlens, the first sub-pixel region comprising a p-type layer of a first shape and an n-type layer of a first shape; The second sub-pixel region is located at the second thickness on the front side and aligned with the second microlens. The second sub-pixel region contains a p-type layer of a second shape and an n-type layer of a second shape. An interconnect layer comprising a first electrode group and a second electrode group, the first electrode group being connected to a first-shaped p-type layer and a second-shaped p-type layer, and the second electrode group being connected to a first-shaped n-type layer and a second-shaped n-type layer.

2. The device according to claim 1, characterized in that, It also includes an n-type layer of a third shape located between the first and second sub-pixel regions.

3. The device according to claim 1, characterized in that, It also includes application-specific integrated circuits (ASICs) connected to the first electrode group and the second electrode group.

4. The device according to claim 1, characterized in that, The first electrode group includes multiple anodes, and the second electrode group includes multiple cathodes.

5. The device according to claim 1, characterized in that, Back-illuminated photodiode devices are avalanche photodiodes or single-photon avalanche diodes.

6. The device according to claim 1, characterized in that, The first sub-pixel region and the second sub-pixel region are separated by a shallow trench isolation region.

7. The device according to claim 1, characterized in that, It also includes an epitaxial layer located between the back and front sides.

8. The device according to claim 1, characterized in that, It also includes a first side layer disposed along the first sidewall, the first side layer comprising a p-type material.

9. The device according to claim 8, characterized in that, It also includes a second side layer disposed along the first side layer, the second side layer containing a p-type material and having a doping gradient, wherein the doping concentration of the first side of the second side layer in contact with the first side layer is higher than that of the second side layer away from the first side layer.

10. The device according to claim 1, characterized in that, The thickness between the front and back sides is less than 3μm.

11. A back-illuminated (BSI) photodiode device, comprising: back; Multiple microlenses connected to the back; A first doped region containing p-type material located within the first thickness on the back side; The front, opposite to the back; The first and second sub-pixel regions are located on the front side, and each sub-pixel region contains a shaped p-type layer and a shaped n-type layer; An interconnect layer comprising a plurality of electrodes connected to a shaped p-type layer and a shaped n-type layer; Application-specific integrated circuits (ASICs) connected to multiple electrodes are configured to process electrical signals generated by sub-pixel regions to achieve high-speed readout.

12. The device according to claim 11, characterized in that, The shaped p-type layer and the shaped n-type layer in each sub-pixel region are separated by a shallow trench isolation (STI) region.

13. The device according to claim 11, characterized in that, The first doped region extends along the sidewall of the device, forming a continuous p-type layer surrounding the sub-pixel region.

14. The device according to claim 11, characterized in that, The shaped n-type layer in each sub-pixel region contains multiple finger electrodes to reduce lateral transport time.

15. The device according to claim 11, characterized in that, It also includes a gradient-doped p-type layer adjacent to the first doped region, wherein the gradient-doped p-type layer has a higher doping concentration near the first doped region and a lower doping concentration away from the first doped region.

16. An optical receiving system, characterized in that, include: A plurality of photodiodes are configured according to a first arrangement, the first arrangement being based on a second arrangement associated with an optical communication link bundle, the plurality of photodiodes including a first photodiode, the first photodiode comprising: back; A first doped region is disposed within a first thickness on the back side, the first doped region comprising p-type material; First sidewall and second sidewall, the first sidewall including a first deep trench isolation (DTI) area; front; The first sub-pixel region is located at the second thickness on the front side, and the first sub-pixel region includes a p-type layer of a first shape and an n-type layer of a first shape; A second sub-pixel region located at the second thickness on the front side, the second sub-pixel region comprising a p-type layer of a second shape and an n-type layer of a second shape; and An interconnect layer comprising a first electrode group and a second electrode group, the first electrode group being connected to a first-shaped p-type layer and a second-shaped p-type layer, and the second electrode group being connected to a first-shaped n-type layer and a second-shaped n-type layer.

17. The system according to claim 16, characterized in that, It also includes a first microlens aligned with the first sub-pixel.

18. The system according to claim 16, characterized in that, The interconnect layer includes a plurality of anodes connected to the p-type layer and a plurality of cathodes connected to the n-type layer.

19. The system according to claim 16, characterized in that, The width of the first photodiode is 40 μm to 60 μm.

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