Phase division and analysis method and device for symmetrical faults of inverter power supply based on voltage detection delay and phase-locked transient state

Abstract

The invention discloses a phase division and analysis method and device for symmetrical faults of an inverter power supply based on voltage detection delay and phase-locked transient, and relates to the technical field of relay protection of a new energy power system. The voltage detection module based on the phase-locked loop measures the drop amplitude of the voltage of the grid-connected point; in consideration of voltage amplitude drop and phase jump after a fault, low-voltage ride-through control cannot be immediately input and a transient response process exists in a phase-locked loop, a fault transient process is divided based on voltage drop amplitude detection delay, different transition time of a current inner loop and a phase-locked transient state and a control switching process; and establishing a fault current analysis model of the whole fault process. According to the method, based on the influence of inverter control system voltage detection link time delay and phase locking transient on fault current transient characteristics, the whole fault current process stage division is accurate, and the analytical calculation precision is higher.

Description

TECHNICAL FIELD

[0001] The application discloses a method and device for stage division and analysis of symmetrical faults of an inverter power supply based on voltage detection delay and phase-locked transient, and relates to the technical field of relay protection of new energy power systems. BACKGROUND

[0002] At present, new energy is the main body of a new power system, and the development of green and low-carbon energy is an inevitable trend in the energy and power industry. In the process of energy transformation, the large-scale access of high-proportion renewable energy and high-proportion power electronic equipment in the power system poses new challenges to the performance of relay protection. Due to the characteristics of limited fault short-circuit current amplitude of new energy power supply and rich low-order harmonic content, the performance of relay protection based on traditional synchronous machine power frequency quantity setting is reduced, and therefore accurately grasping the short-circuit current characteristics of IIREG (inverter interfaced renewable energy generator) is the key to solving the problem of relay protection under the background of grid connection of new energy power supply.

[0003] A large amount of research work has been carried out by domestic and foreign scholars for the fault transient analysis of IIREG single machine. In early research, only the control strategy of normal grid operation is used, the fault characteristics and dominant factors of inverter power supply are qualitatively analyzed based on fault simulation, the influence of low-voltage ride-through control is not considered, and the fault transient law cannot be quantitatively revealed from the theoretical level, which has great limitations. With the premise of disconnecting the voltage outer ring after the low-pass control is put into operation, some documents obtain the output current and current command value by analysis and establish a fault current model in the frequency domain based on the frequency domain transfer function expression, and research on fault transient and steady-state characteristics is carried out.

[0004] The traditional analysis of fault characteristics of inverter power supply does not consider the influence of phase jump, takes the example of instantaneous drop of amplitude after fault and no phase jump, carries out fault current analysis and calculation, and divides the whole fault process into three stages, namely, LVRT control non-response stage, fault transient step response stage and fault steady-state stage. Actually, after the LVRT is put into operation, the fault current reference value is not an ideal step response, but a transient change process affected by the voltage drop amplitude detection delay. On the other hand, there is still phase jump after fault, so the existing stage division and analysis calculation of the whole process of fault current of inverter power supply are deviated, and therefore the research on the transient characteristics of IIREG fault current still needs to be further improved. SUMMARY

[0005] The present application provides a kind of based on voltage detection delay and phase-locked transient inverter power symmetry fault stage division and analytical method and device, consider the influence of voltage detection delay, phase-locked transient and voltage current control loop on fault current transient characteristic in new energy grid-connected inverter control system, carry out fault current whole process stage division and analytical calculation, can determine the transition process of each transient stage of inverter power fault current, while being able to improve the analytical precision when carrying out fault current analytical calculation, realizes the accurate analysis of fault transient current.The technical scheme adopted is:

[0006] The first aspect is a kind of based on voltage detection delay and phase-locked transient inverter power symmetry fault stage division and analytical method, comprising:

[0007] S1, the original signal of power grid is acquired at the point of interconnection to obtain PCC voltage, the q-axis, d-axis component of the PCC voltage is obtained by Park transformation, the phase θ of the q-axis component is driven to output phase-locked loop pll As the position information of voltage phase tracking, the voltage amplitude is calculated by the d-axis component;

[0008] S2, according to the voltage amplitude and position information of the PCC voltage, the fault transient process of grid-connected inverter system is divided into normal operation transition stage, LVRT control switching stage, current inner loop regulation stage and phase-locked loop recovery stage by voltage drop detection timing, phase-locked loop dynamic response characteristics and current inner loop regulation time;

[0009] S3, in the normal operation transition stage LVRT control is not put into, according to the position information, the current analytical calculation model of first stage of fault transient is established by the control equation of voltage outer loop and power balance equation;

[0010] S4, in the LVRT control switching stage LVRT control is put into, according to the position information, the current analytical calculation model of second stage of fault transient is established by the transient change of q-axis, d-axis current reference value, current inner loop and phase-locked transient;

[0011] S5, in the voltage amplitude stabilizes after the current inner loop regulation stage, according to the position information, the current analytical calculation model of third stage of fault transient is established by the dynamic response of d-axis, q-axis current in the stable state of d-axis, q-axis current reference value, single interval current inner loop dynamic response and phase-locked transient;

[0012] S6, in the phase-locked loop recovery stage d-axis, q-axis current reaches stable value, according to the position information, the current analytical calculation model of fourth stage of fault transient is established by the dynamic response of phase-locked transient.

[0013] In some implementations, when the PCC voltage drops below 90% of the rated voltage, the outer voltage loop is disconnected. According to the LVRT control strategy, a reference value for the q-axis current is given. Under the condition that the inverter does not experience overcurrent, the reference value for the d-axis current generates the maximum active power. In the fault scenario, the reference value for the inner loop current under the LVRT control strategy is shown in equation (1):

[0014]

[0015] In equation (1), P0 represents the active power output of the new energy power source; I N Rated current; U pcc.f This represents the voltage amplitude at the grid connection point after the fault.

[0016] In some implementations, the normal operation transition phase, LVRT control switching phase, current inner loop regulation phase, and phase-locked loop recovery phase include:

[0017] S21, during the normal operation transition phase, if the voltage drop amplitude detection delay does not reach the controller switching threshold, the actual current output value is obtained through a dual-loop control strategy based on the current reference value and the influence of DC bus voltage fluctuation.

[0018] S22, during the LVRT control switching phase, when the voltage drop amplitude is detected and confirmed, the current of the transient transition process is output through the LVRT algorithm based on the current reference value and the effect of detection delay.

[0019] S23, during the current inner loop adjustment phase, when the voltage drop amplitude detection is stable, the current inner loop reference value is tracked and updated according to the transient changes of the d-axis and q-axis current reference values ​​through the LVRT control strategy;

[0020] S24, during the phase-locked loop recovery phase, when the voltage drop amplitude is detected, the d-axis and q-axis current values ​​are stable, and the phase-locked loop transient transition is slow, the phase-locked loop output of the three-phase current is transformed according to the transient changes of the d-axis and q-axis current reference values ​​through the LVRT control strategy.

[0021] In some implementations, based on the power balance relationship, the DC bus voltage equation is obtained as follows:

[0022]

[0023]

[0024] Ignoring the response time of the inner current loop, and combining equations (2) and (3), the second-order differential equation of the DC bus voltage fault component is obtained as follows:

[0025]

[0026] Substituting the fault component of the DC bus voltage obtained from equation (4) into equation (3), we can obtain the fault component of the active current as follows:

[0027]

[0028] In the formula

[0029] The expressions for the d-axis and q-axis fault currents in the first transient stage are:

[0030]

[0031] The expression for the three-phase fault current in the first stage of transient operation is:

[0032]

[0033] Secondly, embodiments of the present invention provide a device for stage division and analysis of symmetrical faults in inverter power supplies based on voltage detection delay and phase-locked transients, comprising:

[0034] The voltage detection module is used to acquire the PCC voltage by collecting the raw grid signal at the grid connection point, obtain the q-axis and d-axis components of the PCC voltage through Park transform, and drive the phase-locked loop to output phase θ using the q-axis component. pll As position information for voltage phase tracking, the voltage amplitude is calculated using the d-axis component;

[0035] The phase processing module is used to divide the fault transient process of the grid-connected inverter system into the normal operation transition phase, LVRT control switching phase, current inner loop adjustment phase and phase-locked loop recovery phase based on the voltage amplitude and position information of the PCC voltage, through voltage drop detection timing, phase-locked loop dynamic response characteristics and current inner loop adjustment time.

[0036] The first modeling module is used to establish an analytical calculation model of the current in the first stage of the fault transient state based on the location information, using the control equations of the voltage outer loop and the power balance equations when the LVRT control is not engaged during the normal operation transition phase.

[0037] The second modeling module is used to establish a current analytical calculation model for the second stage of the fault transient based on the location information when the LVRT control is engaged during the LVRT control switching phase, through transient changes in the q-axis and d-axis current reference values, the current inner loop, and the phase-locked transient.

[0038] The third modeling module is used to establish an analytical calculation model of the current in the third stage of the fault transient state after the voltage amplitude stabilizes during the current inner loop adjustment stage, based on the position information and through the dynamic response of the d-axis and q-axis currents under the stable state of the d-axis and q-axis current reference values, the dynamic response of the single-interval current inner loop, and the phase-locked transient state.

[0039] The fourth modeling module is used to establish an analytical calculation model of the current in the fourth stage of the fault transient state based on the position information and the dynamic response of the phase-locked loop after the d-axis and q-axis currents reach stable values ​​during the recovery phase of the phase-locked loop.

[0040] In some implementations, when the PCC voltage drops below 90% of the rated voltage, the outer voltage loop is disconnected. According to the LVRT control strategy, a reference value for the q-axis current is given. Under the condition that the inverter does not experience overcurrent, the reference value for the d-axis current generates the maximum active power. In the fault scenario, the reference value for the inner loop current under the LVRT control strategy is shown in equation (1):

[0041]

[0042] In equation (1), P0 represents the active power output of the new energy power source; I N Rated current; U pcc.f This represents the voltage amplitude at the grid connection point after the fault.

[0043] In some implementations, the stage processing module element includes:

[0044] The transition unit is used to obtain the actual current output value through a dual-loop control strategy when the voltage drop amplitude detection delay has not reached the controller switching threshold during the normal operation transition phase, based on the current reference value and the influence of DC bus voltage fluctuation.

[0045] The switching unit is used to output the current of the transient transition process through the LVRT algorithm when the voltage drop amplitude is detected and confirmed during the LVRT control switching phase, based on the current reference value and the effect of detection delay.

[0046] The adjustment unit is used to track and update the current inner loop reference value according to the transient changes of the d-axis and q-axis current reference values ​​through the LVRT control strategy when the voltage drop amplitude detection is stable during the current inner loop adjustment stage.

[0047] The recovery unit is used to perform coordinate transformation on the phase-locked loop output of the three-phase current through the LVRT control strategy when the voltage drop amplitude is detected, the d-axis and q-axis current values ​​are stable, and the phase-locked loop transient transition is slow during the phase-locked loop recovery phase.

[0048] In some implementations, the DC bus voltage equation is obtained in the first modeling module based on the power balance relationship as follows:

[0049]

[0050] Ignoring the response time of the inner current loop, and combining equations (2) and (3), the second-order differential equation of the DC bus voltage fault component is obtained as follows:

[0051]

[0052] Substituting the fault component of the DC bus voltage obtained from equation (4) into equation (3), we can obtain the fault component of the active current as follows:

[0053]

[0054] In the formula

[0055] The expressions for the d-axis and q-axis fault currents in the first transient stage are:

[0056]

[0057] The expression for the three-phase fault current in the first stage of transient operation is:

[0058]

[0059] Thirdly, embodiments of the present invention provide an electronic device, including a memory and a processor, wherein the memory is used to store one or more computer instructions, wherein when the one or more computer instructions are executed by the processor, they implement the method described in the first aspect above.

[0060] Fourthly, embodiments of the present invention provide a computer storage medium, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, it implements the method described in the first aspect.

[0061] One or more embodiments of the present invention can bring at least the following beneficial effects: The present invention uses a phase-locked loop (PLL) voltage detection module to measure the voltage drop amplitude at the grid connection point; considering the voltage drop amplitude and phase jump after a fault, which prevents the low-voltage ride-through control from being immediately activated and the PLL will have a transient response process, the fault transient process is divided based on the voltage drop amplitude detection delay, the different transition times of the current inner loop and the PLL transient, and the control switching process; a fault current analytical model of the entire fault process is established. The method of the present invention is based on the influence of the voltage detection link delay and the PLL transient on the transient characteristics of the fault current in the inverter control system, and the stage division of the entire fault current process is accurate, and the analytical calculation accuracy is higher. BRIEF DESCRIPTION OF DRAWINGS

[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 This is a grid-connected inverter control block diagram provided by an embodiment of the present invention for a stage division and analysis method of symmetrical faults in inverter power supplies based on voltage detection delay and phase-locked transients;

[0064] Figure 2 This is a schematic diagram of the voltage drop amplitude detection and phase-locked transient process provided in the embodiment of the present invention;

[0065] Figure 3 This is a schematic diagram of the phase-locked loop control structure provided in the embodiment of the present invention;

[0066] Figure 4 This is a schematic diagram comparing the analytical waveform and the simulated waveform of the phase current when the voltage drops to 0.7 puA, as provided in an embodiment of the present invention.

[0067] Figure 5 This is a schematic diagram comparing the analytical waveform and the simulated waveform of the phase current when the voltage drops to 0.3puA, as provided in an embodiment of the present invention. Detailed Implementation

[0068] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0069] Example 1:

[0070] Firstly, this embodiment provides a method for stage division and analysis of symmetrical faults in inverter power supplies based on voltage detection delay and phase-locked transients, including:

[0071] S1, acquire the PCC voltage by collecting the original grid signal at the grid connection point, obtain the q-axis and d-axis components of the PCC voltage through Parker transformation, and drive the phase-locked loop to output phase θ through the q-axis component. pll As position information for voltage phase tracking, the voltage amplitude is calculated using the d-axis component;

[0072] S2, based on the voltage amplitude and position information of the PCC voltage, the fault transient process of the grid-connected inverter system is divided into normal operation transition stage, LVRT control switching stage, current inner loop adjustment stage and phase-locked loop recovery stage by means of voltage drop detection timing, phase-locked loop dynamic response characteristics and current inner loop adjustment time.

[0073] S3, when the LVRT control is not engaged during the normal operation transition phase, a current analytical calculation model for the first stage of fault transient is established based on the location information through the control equation of the voltage outer loop and the power balance equation.

[0074] S4, when LVRT control is activated during the LVRT control switching phase, based on the position information, a current analytical calculation model for the second stage of fault transient is established through transient changes in q-axis and d-axis current reference values, current inner loop, and phase-locked transient.

[0075] S5, after the voltage amplitude stabilizes during the current inner loop adjustment phase, based on the position information, a current analytical calculation model for the third stage of the fault transient is established using the dynamic response of the d-axis and q-axis currents under stable d-axis and q-axis current reference values, the dynamic response of the single-interval current inner loop, and the phase-locked transient.

[0076] S6. After the d-axis and q-axis currents reach stable values ​​during the phase-locked loop recovery phase, a current analysis calculation model for the fourth stage of the fault transient is established based on the position information and the dynamic response of the phase-locked transient.

[0077] According to S1, based on the guidelines for new energy grid connection, when a grid fault occurs, the new energy grid connection system is required to provide a certain reactive current support during the fault period to maintain grid connection operation for a period of time after the fault. Therefore, the new energy grid connection system needs to have LVRT capability: after the fault, if the PCC voltage drops to below 90% of the rated voltage, the voltage outer loop is disconnected, the q-axis current reference value is given according to the requirements of the LVRT control strategy, and the d-axis current reference value generates the maximum active power under the condition that the inverter does not overcurrent. The inner loop current reference value under the LVRT control strategy in the fault scenario is shown in Equation (1).

[0078]

[0079] In equation (1), P0 represents the active power output of the new energy power source; I N Rated current; Upcc.f The voltage amplitude at the grid connection point after the fault. According to equation (1), after a grid fault occurs, the current reference value is related to the degree of voltage drop at the grid connection point. After the low voltage ride-through control is put into operation, it shows a transient change rather than an ideal step change. Figure 1 The grid-connected inverter system control block diagram shown indicates that the current reference value is determined by the voltage outer loop during steady-state operation; after a fault occurs, the three-phase voltage drop at the grid connection point needs to be adjusted. abc The voltage amplitude U is input to the control system for extraction and measurement. pcc.f The voltage amplitude is compared and judged. If the LVRT voltage drop condition is met, the outer voltage loop is disconnected and the control is switched to LVRT control. The current reference value is given according to the voltage drop degree. The phase-locked loop performs phase tracking on the PCC voltage to obtain the reference phase. The PCC voltage, terminal voltage and inverter output current are transformed by Parker transformation through the reference phase to obtain the voltage and current components in the two-phase rotating coordinate system.

[0080] As shown in S2, when a grid fault occurs, amplitude detection needs to determine whether the positive sequence voltage amplitude at the grid connection point has dropped below 0.9 pu. When the amplitude drop condition is met, the outer voltage loop is disconnected, and the low voltage ride-through control (LVRT) is activated. Therefore, there is a certain delay from the moment the fault occurs to the activation of the LVRT control, which further leads to a transient change in the fault output current after the LVRT control is activated. Simultaneously, the PCC voltage phase jump after the fault causes a transient response in the phase-locked loop (PLL) output phase. This process further affects the output fault current of the grid-connected inverter by influencing the coordinate transformation. The transient duration of voltage drop amplitude detection is approximately 20 ms, while the duration of the PLL transient is generally greater than 100 ms. That is, the impact time of the PLL transient is much longer than the impact time of the voltage drop amplitude detection delay.

[0081] After a fault occurs, the transient response process of the inverter-type new energy power supply can be divided into four stages based on the differences in the transient transition time of the controller switching and nonlinear links.

[0082] The first stage is when the voltage drop amplitude detection delay does not reach the controller switching threshold. During normal operation, the dual-loop control strategy is used, and the current reference value is affected by the DC bus voltage fluctuation, which in turn affects the actual output current.

[0083] The second stage switches to the LVRT control strategy. The current reference value is given by the LVRT control and exhibits a transient change process due to the voltage drop amplitude detection delay. At this time, the output current also exhibits a transient transition process.

[0084] When the voltage drop amplitude detection stage stabilizes in the third stage, the current reference value also reaches a stable value, but the dq axis current still undergoes transient changes.

[0085] In the fourth stage, the dq-axis current reaches a stable value, but due to the slow transition time of the phase-locked loop (PLL), the three-phase current is still affected by the fault current and exhibits a transient change process. A schematic diagram of the voltage drop amplitude detection delay and the PLL transient is shown below. Figure 2 As shown.

[0086] Next, following step S3, as can be seen from step S2, when the LVRT control is not engaged, the outer loop of the DC bus voltage is not disconnected, and the current reference value is given by the outer loop of the DC voltage. The grid-connected inverter uses dual closed-loop control, requiring quantitative analysis of the impact of the DC bus voltage on the current reference value. Considering the slow transient response time of the phase-locked loop, it can be assumed that the phase output of the phase-locked loop remains unchanged during the first stage of the fault.

[0087] According to the power balance relationship, the equation for the DC bus capacitor voltage is as follows:

[0088]

[0089] Ignoring the response time of the inner current loop, the outer voltage loop control equations shown in equations (2) and (3) are used.

[0090]

[0091] Furthermore, we obtain the second-order differential equation for the DC voltage fault component.

[0092]

[0093] Substituting the fault component of the DC bus voltage obtained from equation (4) into equation (3), we can obtain the fault component of the active current as follows:

[0094] Δi d(t) =M2e -αt sin(βt-ζ1)(5)

[0095] In the formula

[0096] Therefore, the expression for the transient first stage dq-axis fault current can be obtained as follows:

[0097]

[0098] Therefore, the expression for the three-phase fault current in the first stage of transient condition can be obtained, taking phase a as an example:

[0099]

[0100] Next, according to S4, since the LVRT control voltage detection circuit contains an integral filtering module, the step signal of the PCC voltage drop can be approximated as a ramp signal by the controller's detection output. Furthermore, through point-based experimental fitting, it can be represented by a linear function U. PCC.f(t) = At ​​+ B approximates the transient change process of voltage drop, which further leads to a transient change process of current reference value, as shown in equations (8) and (9):

[0101]

[0102] In the formula: U x The boundary voltage value at which the inverter reaches the inverter current limiting constraint condition, when I max =1.5I N At that time, U x =0.7 (per unit value). Further, an interval segmentation method is adopted, using step functions of several intervals to approximate the original functions of the d-axis and q-axis currents. By considering the scenario of step changes in the current reference value in each small interval, an analytical calculation model of the fault current during the voltage drop transient process in the second stage of the fault is obtained.

[0103] The transfer function of the inner current loop is usually designed according to the typical type I circuit. Since the response speed of the inner current loop is very fast, generally 1 to 2 ms, while the response speed of the phase-locked transient is relatively slow, the influence of the phase-locked transient on the coupling of the inner current loop can be approximately ignored. The main consideration is the influence of the phase-locked transient on the fault current through coordinate transformation.

[0104] Ignoring the effect of phase-locked transients on the coupling of the inner current loop, the expression for the d-axis fault current component considering a step change in the current reference value can be obtained as follows:

[0105]

[0106] In the formula: i * d0 with i * d1 These are the values ​​before and after the step change in the current reference value; ω c Let be the bandwidth of the inner current loop control. Taking the inverse Laplace transform of equation (10), we obtain the expression for the single-interval transient response current in the time domain:

[0107]

[0108] Because the phase-locked loop output phase exhibits a transient response process, θ PLL (t) will further affect the three-phase currents abc through the Parker inverse transformation, as shown in equation (12):

[0109]

[0110] Figure 3 The diagram shown is a phase-locked loop structure diagram, consisting of... Figure 3 It can be known that the output phase of the phase-locked loop is:

[0111]

[0112] When a symmetrical fault occurs on the AC side of the system, let the amplitude before the fault be E. m0 The phase is θ0, and the amplitude after the fault is E. m The phase is θ1. The PCC voltage after the fault is:

[0113]

[0114] e abc After phase-locked loop coordinate transformation, we can obtain e. dq The expression is shown in equation (8):

[0115]

[0116] When the phase jump angle is small, by using Taylor expansion of equation (15) and neglecting second-order quantities, we can obtain:

[0117] e dq =E m [1 Δθ PLL (16)

[0118] Combining equations (13) and (16), the expression for the detection of the phase and amplitude of the phase-locked loop output in the frequency domain is shown in equation (17):

[0119]

[0120] Assuming a fault occurs at time t0, performing an inverse Laplace transform on equation (17) yields the output phase of the phase-locked loop in the time domain as follows:

[0121]

[0122] In the formula

[0123]

[0124] with i a For example, the phase-locked transient, through the Parker inverse transformation, makes the phase a current exhibit significant nonlinear characteristics, as shown in equation (13):

[0125]

[0126] Further considering the impact of phase-locked transient on the analytical calculation of fault current through coordinate transformation, the fault current expression considering the effect of phase-locked transient in a single interval can be obtained:

[0127]

[0128] In the formula

[0129]

[0130] The fault transient current in each interval can be analytically calculated according to equation (22). By superimposing the currents in each interval, the current expression for the voltage drop transient process in the second stage of the fault, as shown in equation (23), can be obtained:

[0131]

[0132] Next, according to S5, after the voltage drop amplitude detection stage ends, the current reference value reaches a stable state, but the inner current loop still has a transient response process. At this time, the inverter is still in LVRT operation mode, the voltage drop detection amplitude has reached a stable value, but the output current of the IIREG has not yet fully tracked the current reference value, and is in the fault transient tracking stage. The transient analytical model of this stage satisfies the single-interval step condition of the current reference value. Considering only the transient response of the inner loop PI controller, its transient response current expression can be obtained as follows:

[0133] Further considering the phase-locked transient, the analytical expression for the fault current of phase A in the third stage of the fault can be obtained.

[0134]

[0135] In the formula

[0136]

[0137] Finally, according to S6, after the three sets of free components with the same decay time constant as the inner current loop in equation (25) have decayed completely, the three-phase current will still be affected by the phase-locked loop transient. At this time, it enters the stage where the phase-locked loop alone affects the transient change. In this stage, the fault transient current is jointly dominated by the final value of the third stage and the phase-locked loop transient. At this time, we have:

[0138]

[0139] In the formula

[0140]

[0141] Taking phase A as an example, Figure 4 , Figure 5 Taking voltage drops to 0.7 pu and 0.3 pu as examples, respectively, the analytical and simulated waveforms of the voltage detection delay and phase-locked transient proposed in this embodiment of the invention are compared. Due to the 20 ms voltage detection delay and 103.6 ms phase-locked transient transition process, it can be seen from the figures that the fault current stage division process and analytical accuracy are high, verifying the correctness of the fault current analytical expression proposed in this invention.

[0142] This invention fully considers the impact of voltage detection delay, phase-locked loop (PLL) transients, and voltage-current loop on the transient characteristics of fault current in the control system of a new energy grid-connected system. It accurately divides the entire process of inverter power supply fault transient current into stages, achieving high accuracy in fault current analysis. Simultaneously, it clarifies the transition process of the fault transient current, enabling precise analysis of the fault current. A PLL-based voltage detection module measures the voltage drop amplitude at the grid connection point. Considering the voltage amplitude drop and phase jump after a fault, which prevents immediate activation of low-voltage ride-through control and the transient response process of the PLL, the fault transient process is divided into four stages based on the voltage drop amplitude detection delay, the different transition times of the current inner loop and PLL transients, and the control switching process: In the first stage of the fault transient, LVRT control is not activated; considering the influence of physical system power fluctuations and PLL transients, a fault current analytical calculation model is solved; in the second stage of the fault transient, the current reference value transient changes... The voltage dip amplitude detection delay causes transient changes in the current reference value. Considering both the inner current loop equation and the effects of phase-locked loop transients, an analytical calculation model for the fault current is derived based on the "interval segmentation" approach. In the third stage of the fault transient process, the voltage dip amplitude detection transient response ends, and the current reference value stabilizes. Considering the dynamic response of the single-interval current inner loop and the effects of phase-locked loop transients, an analytical calculation model for the fault current is established. In the fourth stage, the inner current loop transient response ends, and considering the effects of phase-locked loop transients, an analytical calculation model for the fault current is established. Finally, an analytical model for the fault current throughout the entire fault process is established. This analytical method takes into account the effects of the voltage detection delay and phase-locked loop transients in the inverter control system on the transient characteristics of the fault current. The stage division of the fault current process is accurate, and the analytical calculation accuracy is good.

[0143] Example 2:

[0144] This invention provides a device for stage division and analysis of symmetrical faults in inverter power supplies based on voltage detection delay and phase-locked transients, comprising:

[0145] The voltage detection module is used to acquire the PCC voltage by collecting the raw grid signal at the grid connection point, obtain the q-axis and d-axis components of the PCC voltage through Park transform, and drive the phase-locked loop to output phase θ using the q-axis component. pll As position information for voltage phase tracking, the voltage amplitude is calculated using the d-axis component;

[0146] The phase processing module is used to divide the fault transient process of the grid-connected inverter system into the normal operation transition phase, LVRT control switching phase, current inner loop adjustment phase and phase-locked loop recovery phase based on the voltage amplitude and position information of the PCC voltage, through voltage drop detection timing, phase-locked loop dynamic response characteristics and current inner loop adjustment time.

[0147] The first modeling module is used to establish an analytical calculation model of the current in the first stage of the fault transient state based on the location information, using the control equations of the voltage outer loop and the power balance equations when the LVRT control is not engaged during the normal operation transition phase.

[0148] The second modeling module is used to establish a current analytical calculation model for the second stage of the fault transient based on the location information when the LVRT control is engaged during the LVRT control switching phase, through transient changes in the q-axis and d-axis current reference values, the current inner loop, and the phase-locked transient.

[0149] The third modeling module is used to establish an analytical calculation model of the current in the third stage of the fault transient state after the voltage amplitude stabilizes during the current inner loop adjustment stage, based on the position information and through the dynamic response of the d-axis and q-axis currents under the stable state of the d-axis and q-axis current reference values, the dynamic response of the single-interval current inner loop, and the phase-locked transient state.

[0150] The fourth modeling module is used to establish an analytical calculation model of the current in the fourth stage of the fault transient state based on the position information and the dynamic response of the phase-locked loop after the d-axis and q-axis currents reach stable values ​​during the recovery phase of the phase-locked loop.

[0151] In some implementations, when the PCC voltage drops below 90% of the rated voltage, the outer voltage loop is disconnected. According to the LVRT control strategy, a reference value for the q-axis current is given. Under the condition that the inverter does not experience overcurrent, the reference value for the d-axis current generates the maximum active power. In the fault scenario, the reference value for the inner loop current under the LVRT control strategy is shown in equation (1):

[0152]

[0153] In equation (1), P0 represents the active power output of the new energy power source; I N Rated current; U pcc.f This represents the voltage amplitude at the grid connection point after the fault.

[0154] In some implementations, the stage processing module element includes:

[0155] The transition unit is used to obtain the actual current output value through a dual-loop control strategy when the voltage drop amplitude detection delay has not reached the controller switching threshold during the normal operation transition phase, based on the current reference value and the influence of DC bus voltage fluctuation.

[0156] The switching unit is used to output the current of the transient transition process through the LVRT algorithm when the voltage drop amplitude is detected and confirmed during the LVRT control switching phase, based on the current reference value and the effect of detection delay.

[0157] The adjustment unit is used to track and update the current inner loop reference value according to the transient changes of the d-axis and q-axis current reference values ​​through the LVRT control strategy when the voltage drop amplitude detection is stable during the current inner loop adjustment stage.

[0158] The recovery unit is used to perform coordinate transformation on the phase-locked loop output of the three-phase current through the LVRT control strategy when the voltage drop amplitude is detected, the d-axis and q-axis current values ​​are stable, and the phase-locked loop transient transition is slow during the phase-locked loop recovery phase.

[0159] In some implementations, the DC bus voltage equation is obtained in the first modeling module based on the power balance relationship as follows:

[0160]

[0161] Ignoring the response time of the inner current loop, and combining equations (2) and (3), the second-order differential equation of the DC bus voltage fault component is obtained as follows:

[0162]

[0163] Substituting the fault component of the DC bus voltage obtained from equation (4) into equation (3), we can obtain the fault component of the active current as follows:

[0164] Δi d(t) =M2e -αt sin(βt-ζ1) (5)

[0165] In the formula

[0166] The expressions for the d-axis and q-axis fault currents in the first transient stage are:

[0167]

[0168] The expression for the three-phase fault current in the first stage of transient operation is:

[0169]

[0170] Example 3:

[0171] This embodiment also provides an electronic device, including a memory and a processor, wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method of Embodiment 1;

[0172] In practical applications, the processor can be implemented as an Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), controller, microcontroller unit (MCU), microprocessor, or other electronic components to execute the methods described in the above embodiments.

[0173] The method implemented in this embodiment is as shown in Embodiment 1.

[0174] Example 4:

[0175] This embodiment also provides a computer storage medium, in which a computer program is stored, and when the computer program is executed by one or more processors, it implements the method of embodiment one.

[0176] The computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0177] The method implemented in this embodiment is as shown in Embodiment 1.

[0178] In the several embodiments provided in this invention, it should be understood that the disclosed systems and methods can also be implemented in other ways. The system and method embodiments described above are merely illustrative.

[0179] It should be noted that, in this document, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. The terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0180] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and variations in form and detail of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection for this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A method for stage division and analysis of symmetrical faults in inverter power supplies based on voltage detection delay and phase-locked transients, characterized in that, include: S1, acquire the PCC voltage by collecting the original grid signal at the grid connection point, obtain the q-axis and d-axis components of the PCC voltage through Parker transformation, and drive the phase-locked loop to output phase θ through the q-axis component. pll As position information for voltage phase tracking, the voltage amplitude is calculated using the d-axis component; S2, based on the voltage amplitude and position information of the PCC voltage, the fault transient process of the grid-connected inverter system is divided into normal operation transition stage, LVRT control switching stage, current inner loop adjustment stage and phase-locked loop recovery stage by means of voltage drop detection timing, phase-locked loop dynamic response characteristics and current inner loop adjustment time. S3, when the LVRT control is not engaged during the normal operation transition phase, a current analytical calculation model for the first stage of fault transient is established based on the location information through the control equation of the voltage outer loop and the power balance equation. S4, when LVRT control is activated during the LVRT control switching phase, based on the position information, a current analytical calculation model for the second stage of fault transient is established through transient changes in q-axis and d-axis current reference values, current inner loop, and phase-locked transient. S5, after the voltage amplitude stabilizes during the current inner loop adjustment phase, based on the position information, a current analytical calculation model for the third stage of the fault transient is established using the dynamic response of the d-axis and q-axis currents under stable d-axis and q-axis current reference values, the dynamic response of the single-interval current inner loop, and the phase-locked transient. S6. After the d-axis and q-axis currents reach stable values ​​during the phase-locked loop recovery phase, a current analysis calculation model for the fourth stage of the fault transient is established based on the position information and the dynamic response of the phase-locked transient.

2. The method according to claim 1, characterized in that, When the PCC voltage drops below 90% of the rated voltage, the outer voltage loop is disconnected. According to the LVRT control strategy, the q-axis current reference value is given. Under the condition that the inverter does not overcurrent, the d-axis current reference value generates the maximum active power. In the fault scenario, the inner loop current reference value under the LVRT control strategy is as shown in equation (1): In equation (1), P0 represents the active power output of the new energy power source; I N U is the rated current; pcc.f This represents the voltage amplitude at the grid connection point after the fault.

3. The method according to claim 2, characterized in that, The normal operation transition phase, LVRT control switching phase, current inner loop adjustment phase, and phase-locked loop recovery phase include: S21, during the normal operation transition phase, if the voltage drop amplitude detection delay does not reach the controller switching threshold, the actual current output value is obtained through a dual-loop control strategy based on the current reference value and the influence of DC bus voltage fluctuation. S22, during the LVRT control switching phase, when the voltage drop amplitude is detected and confirmed, the current of the transient transition process is output through the LVRT algorithm based on the current reference value and the effect of detection delay. S23, during the current inner loop adjustment phase, when the voltage drop amplitude detection is stable, the current inner loop reference value is tracked and updated according to the transient changes of the d-axis and q-axis current reference values ​​through the LVRT control strategy; S24, during the phase-locked loop recovery phase, when the voltage drop amplitude is detected, the d-axis and q-axis current values ​​are stable, and the phase-locked loop transient transition is slow, the phase-locked loop output of the three-phase current is transformed according to the transient changes of the d-axis and q-axis current reference values ​​through the LVRT control strategy.

4. The method according to claim 3, characterized in that, Based on the power balance relationship, the DC bus voltage equation is obtained as follows: Ignoring the response time of the inner current loop, and combining equations (2) and (3), the second-order differential equation of the DC bus voltage fault component is obtained as follows: Substituting the fault component of the DC bus voltage obtained from equation (4) into equation (3), we can obtain the fault component of the active current as follows: Yes d(t) =M2e -αt sin(βt-ζ1) (5) In the formula The expressions for the d-axis and q-axis fault currents in the first transient stage are: The expression for the three-phase fault current in the first stage of transient operation is:

5. A device for stage division and analysis of symmetrical faults in inverter power supplies based on voltage detection delay and phase-locked transients, characterized in that, include: The voltage detection module is used to acquire the PCC voltage by collecting the raw grid signal at the grid connection point, obtain the q-axis and d-axis components of the PCC voltage through Park transform, and drive the phase-locked loop to output phase θ using the q-axis component. pll As position information for voltage phase tracking, the voltage amplitude is calculated using the d-axis component; The phase processing module is used to divide the fault transient process of the grid-connected inverter system into the normal operation transition phase, LVRT control switching phase, current inner loop adjustment phase and phase-locked loop recovery phase based on the voltage amplitude and position information of the PCC voltage, through voltage drop detection timing, phase-locked loop dynamic response characteristics and current inner loop adjustment time. The first modeling module is used to establish an analytical calculation model of the current in the first stage of the fault transient state based on the location information, using the control equations of the voltage outer loop and the power balance equations when the LVRT control is not engaged during the normal operation transition phase. The second modeling module is used to establish a current analytical calculation model for the second stage of the fault transient based on the location information when the LVRT control is engaged during the LVRT control switching phase, through transient changes in the q-axis and d-axis current reference values, the current inner loop, and the phase-locked transient. The third modeling module is used to establish an analytical calculation model of the current in the third stage of the fault transient state after the voltage amplitude stabilizes during the current inner loop adjustment stage, based on the position information and through the dynamic response of the d-axis and q-axis currents under the stable state of the d-axis and q-axis current reference values, the dynamic response of the single-interval current inner loop, and the phase-locked transient state. The fourth modeling module is used to establish an analytical calculation model of the current in the fourth stage of the fault transient state based on the position information and the dynamic response of the phase-locked loop after the d-axis and q-axis currents reach stable values ​​during the recovery phase of the phase-locked loop.

6. The apparatus according to claim 5, characterized in that, When the PCC voltage drops below 90% of the rated voltage, the outer voltage loop is disconnected. According to the LVRT control strategy, the q-axis current reference value is given. Under the condition that the inverter does not overcurrent, the d-axis current reference value generates the maximum active power. In the fault scenario, the inner loop current reference value under the LVRT control strategy is as shown in equation (1): In equation (1), P0 is the active power output of the new energy power source; I is the rated current; U pcc.f This represents the voltage amplitude at the grid connection point after the fault.

7. The apparatus according to claim 6, characterized in that, The stage processing module includes: The transition unit is used to obtain the actual current output value through a dual-loop control strategy when the voltage drop amplitude detection delay has not reached the controller switching threshold during the normal operation transition phase, based on the current reference value and the influence of DC bus voltage fluctuation. The switching unit is used to output the current of the transient transition process through the LVRT algorithm when the voltage drop amplitude is detected and confirmed during the LVRT control switching phase, based on the current reference value and the effect of detection delay. The adjustment unit is used to track and update the current inner loop reference value according to the transient changes of the d-axis and q-axis current reference values ​​through the LVRT control strategy when the voltage drop amplitude detection is stable during the current inner loop adjustment stage. The recovery unit is used to perform coordinate transformation on the phase-locked loop output of the three-phase current through the LVRT control strategy when the voltage drop amplitude is detected, the d-axis and q-axis current values ​​are stable, and the phase-locked loop transient transition is slow during the phase-locked loop recovery phase.

8. The apparatus according to claim 7, characterized in that, In the first modeling module, based on the power balance relationship, the DC bus voltage equation is obtained as follows: Ignoring the response time of the inner current loop, and combining equations (2) and (3), the second-order differential equation of the DC bus voltage fault component is obtained as follows: Substituting the fault component of the DC bus voltage obtained from equation (4) into equation (3), we can obtain the fault component of the active current as follows: Yes d(t) =M2e -αt sin(βt-ζ1) (5) In the formula The expressions for the d-axis and q-axis fault currents in the first transient stage are: The expression for the three-phase fault current in the first stage of transient operation is:

9. An electronic device, characterized in that, The system includes a memory and a processor, the memory being used to store one or more computer instructions, wherein the one or more computer instructions, when executed by the processor, implement the method as described in any one of claims 1-4.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains a computer program that, when executed by a processor, is used to implement the method described in any one of claims 1-4.

Images