Voltage-controlled current source electrical stimulation circuit based on standard 5V process

Abstract

The invention provides a voltage-controlled current source electrical stimulation circuit based on a standard 5V process, and the circuit is characterized in that the circuit comprises a voltage-controlled current conversion module, a stacked transistor output and control module, and a charge pump boost circuit module. The circuit works under external 5V power supply, adopts a standard 5V process, and can drive a wide-range load from 1k omega to 5k omega and output a wide-range adjustable current from 50mu A to 2mA. The circuit has the remarkable advantages that the circuit structure is simple, a special high-voltage process or an external high-voltage assembly is not needed, the manufacturing cost and the design complexity are reduced, and high integration and miniaturization are easy to realize. The wide load range characteristic of the circuit can stably drive common dynamic change tissue impedance in bioelectrical stimulation; the wide current output characteristic can adapt to various stimulation intensity schemes. Due to the characteristics, the device is highly matched with electrical stimulation application, and an effective technical approach is provided for developing low-cost and high-performance portable electrical stimulation medical equipment.

Description

Technical Field

[0001] This invention belongs to the field of signal processing technology and relates to a voltage-controlled current source circuit, and more particularly to a voltage-controlled current source electrical stimulation circuit with a wide load range and a wide current output range under standard 5V technology. Technical Background

[0002] Transcranial direct current stimulation (tDCS) is a non-invasive brain stimulation method that can be used to alter the membrane excitability of neurons by applying a weak current to the scalp. As a neuromodulation technique, tDCS has received widespread attention in clinical and research settings, providing new avenues for exploring brain function, treating neuropsychiatric disorders, and improving cognitive performance.

[0003] Current on-chip voltage-controlled current source electrostimulation circuits, due to the limitation of the current source's output voltage compliance, cannot simultaneously achieve a wide load range and a wide output current range. When adapting to dynamically changing tissue impedance, the output current of on-chip voltage-controlled current source electrostimulation circuits is only in the microamplitude range; some circuits rely on external high-voltage power supplies and utilize high-voltage MOSFET technology or off-chip voltage-rated buffer FETs to achieve milliamp-level output current. This is clearly detrimental to reducing manufacturing costs and achieving high integration and miniaturization.

[0004] Therefore, this invention proposes a voltage-controlled current source electrical stimulation circuit based on standard 5V technology. Its main advantage is that it can have both a wide load range and a wide output current range to adapt to tDCS applications. Moreover, the circuit adopts standard 5V technology, operates under external 5V power supply, has a simple structure, and is conducive to reducing manufacturing costs and integration. Summary of the Invention

[0005] To overcome the problem that existing on-chip voltage-controlled current source electrical stimulation circuits cannot simultaneously achieve a wide load range and a wide output current range under standard processes and high integration, and to adapt to the dynamically changing tissue impedance and various stimulation intensity schemes in tDCS, this invention proposes a voltage-controlled current source electrical stimulation circuit based on standard 5V process.

[0006] The technical solution adopted in this invention is as follows:

[0007] A voltage-controlled current source electrostimulation circuit based on standard 5V technology is characterized by comprising a voltage-controlled current conversion module, a stacked transistor output and control module, and a charge pump boost circuit module; including a control voltage input terminal VSINK, a bias voltage input terminal VBIAS, external capacitor terminals C_15, C_15_1, C_15_2, C_15_3, C_15_4, C_10, C_10_1, and C_10_2, an output current positive terminal OUT+, and an output current negative terminal OUT-, powered by positive power supplies VDD1, VDD2, and ground terminal GND;

[0008] The voltage-controlled current conversion module generates a controlled voltage V. SINK Controlled current I M4 It consists of resistors R1, R2, R3, R4, NMOS transistors M1, M2, M3, M4, M5 and operational amplifier A1, including voltage input terminal VSINK, bias input terminal VBIAS, voltage-controlled current generation terminal, and VDD2 power supply.

[0009] The stacked transistor output and control module is used to adapt to voltage changes. It consists of resistor R5, NMOS transistors M6, M7, M8, M9, M10, M11, M12, M15, and M16, PMOS transistors M13, M14, M17, and M18, and operational amplifier A2. It includes the gate voltage input terminals of M11 and M15, the bias input terminal VBIAS, the voltage input terminal VSINK, the 15V power supply input terminal, the 10V power supply input terminal, the voltage-controlled current input terminal, the positive output current terminal OUT+, and the negative output current terminal OUT-. The gate voltage input terminals of M11 and M15 are connected to VDD2, and the voltage-controlled current input terminal is connected to the voltage-controlled current generation terminal of the voltage-controlled current conversion module. VDD2 is the power supply.

[0010] The charge pump boost module provides the high voltage required by the circuit and consists of a first-order and a second-order cross-coupled charge pump. The first-order cross-coupled charge pump has capacitor ports C_10, C_10_1, C_10_2 and a 10V voltage output terminal. The second-order cross-coupled charge pump has capacitor ports C_15, C_15_1, C_15_2, C_15_3, C_15_4 and a 15V voltage output terminal. The 15V voltage output terminal is connected to the 15V power supply input terminal of the stacked transistor output and control module, and the 10V voltage output terminal is connected to the 10V power supply input terminal of the stacked transistor output and control module. VDD1 provides the power supply.

[0011] Furthermore, the voltage-controlled current source electrostimulation circuit based on standard 5V technology is characterized in that, in the voltage-controlled current conversion module, R1, R2, R3, and R4 are connected in series; one end of R1 is connected to the gate of M4 to form the voltage input terminal VSINK, with a voltage of V. SINK The voltage at the other end of R1 is V.SINK1 The voltage across one end of R2 is V. SINK1 The voltage at the other end is V. SINK2 The voltage at one end of R3 is V. SINK2 The voltage at the other end is V. SINK3 The voltage at one end of R4 is V. SINK3 The other end is connected to GND; operational amplifier A1 is powered by VDD2 and GND, and the non-inverting input of A1 serves as the bias input VBIAS, with a voltage of V. BIAS The inverting input terminal is connected to the drains of M1, M2, M3, and M4 and the source of M5; the output terminal of A1 is connected to the gate of M5; the gate voltages of M1, M2, and M3 are V respectively. SINK3 V SINK2 and V SINK1 The sources of M1, M2, M3, M4 and M5 are all connected to GND; the drain of M5 forms the voltage-controlled current generation terminal; the substrates of M1, M2, M3, M4 and M5 are all connected to GND.

[0012] M4 acts as a voltage-controlled resistor, operating in the deep linear region; M5 and A1 together form feedback, clamping the drain voltage of M4 at V. BIAS Nearby, it also provides a large output impedance; V BIAS It is a relatively small fixed voltage. The process transconductance parameter of NMOS is K. N The threshold voltage is V THN The aspect ratio of the M4 is The current I flowing through M4 and M5 M4 for

[0013]

[0014] M3, M2, and M1 follow V SINK As the voltage increases, it is sequentially activated to compensate for the high V. gs Output current I due to velocity saturation and other second-order effects OUT Decrease. The DC gain of the operational amplifier is A1, and the transconductance of M5 is g. m5 The drain-source resistance of M5 is r o5 The equivalent voltage-controlled resistor of M4 is R. M4 The output resistance R of the voltage-controlled current conversion module OUT1 for

[0015] R OUT1 =A 1gm5 r o5 R M4 (2)

[0016] Among them, R M4 Given by the following formula

[0017]

[0018] When the DC gain A1 of the operational amplifier is sufficiently large, the output resistance R of the voltage-controlled current conversion module... OUT1 It will also be large enough. The circuit only requires a DC gain for A1.

[0019] Furthermore, the voltage-controlled current source electrostimulation circuit based on standard 5V technology is characterized in that, in the stacked transistor output and control module, the source of M11 serves as the voltage-controlled current input terminal and is connected to the voltage-controlled current generation terminal; the gates of M11 and M15 serve as the gate voltage input terminals of M11 and M15 and are connected to VDD2; the drain of M11 is connected to the source of M12; the drain of M15, the source of M16, and the gate of M12 are connected; the drain of M12 constitutes the output negative terminal OUT-; and the gate of M16 constitutes the 10V power supply input terminal; the drain of M16, M1... The gate of M7 is connected to the drain of M17. The source of M17 and the gate of M18 are connected to one end of R5. The other end of R5 is connected to the source of M18 and M14, forming a 15V power supply input. The drain of M18, the gate of M13, and the drain of M13 form the positive output terminal OUT+. The source of M13, the gate of M14, and the drain of M14 are connected. The drain of M10 is connected to the source of M15. The source of M10 and the drains of M6, M7, M8, and M9 are connected to the inverting input of A2. The non-inverting input of A2 serves as the bias input VBIAS, with a voltage of V. BIAS The output of A2 is connected to the gate of M10; the gate of M9 forms the voltage input terminal VSINK, with a voltage of V. SINK The gate voltages of M6, M7, and M8 are respectively V SINK3 V SINK2 and V SINK1 The sources of all M6, M7, M8, M9, and M10 are connected to GND; the substrates of M11, M12, M13, M14, M15, M16, M17, and M18 are connected to their own sources; the current I between the OUT+ and OUT- terminals... OUT This is the output current.

[0020] Furthermore, the voltage-controlled current source electrical stimulation circuit based on standard 5V technology is characterized in that M1, M2, M3, M4, M5, and A1 are structurally symmetrical with M6, M7, M8, M9, M10, and A2, and operational amplifiers A1 and A2 are identical. The current flowing through M10 is I. CTRL That is, the circuit controlling the branch, M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10 have a width-to-length ratio of... The aspect ratio of a transistor satisfies the following formula:

[0021]

[0022] Where k is a certain constant, I CTRL and I M4 The proportional relationship is as follows:

[0023]

[0024] k represents I M4 With control branch current I CTRL The proportional relationship, that is, according to I M4 The magnitude of the current I in the control branch determines the current I. CTRL The size, thereby enabling different I M4 The operating state of the stacked transistor output stage is adjusted to achieve dynamic control. The value of k needs to take into account power consumption, control accuracy, and transistor width-to-length ratio limitations.

[0025] Furthermore, the voltage-controlled current source electrical stimulation circuit based on standard 5V technology is characterized in that the transconductance of M11 is g. m11 The drain-source resistance is r o11 The transconductance of M12 is g m12 The drain-source resistance is r o12 The output resistance R of the voltage-controlled current source electrical stimulation circuit OUT as follows

[0026] R OUT =(1+g m12 r o12 )[(1+g m11 r o11 )R OUT1 +r o11 ]+r o12 (6)

[0027] R OUT1 Substituting the values, we obtain the output resistance R. OUT as follows

[0028] R OUT ≈A1g m5 g m11 g m12 r o5 r o11 r o12 R M4 (7)

[0029] Output resistance R oUT It is a very large value, meaning the internal resistance of the voltage-controlled current source is large enough. Therefore, the current I flowing through the M4 transistor can be considered to be... M4 That is, the output current I OUT

[0030] I OUT=I M4 (8)

[0031] Substituting (1) into (8), we obtain the output current I. OUT as follows

[0032]

[0033] From (9), it can be seen that the large output resistance R OUT This ensures that the output current I remains constant even with changes in load impedance. OUT Subject only to control voltage V SINK Influence.

[0034] Similarly, from (8), we can obtain the output current I. OUT and I CTRL The proportional relationship is as follows:

[0035]

[0036] That is, according to I OUT The magnitude of the current I in the control branch determines the current I. CTRL The size, thereby enabling different I OUT The operating state of the stacked transistor output stage is adjusted to achieve dynamic control.

[0037] Furthermore, the voltage-controlled current source electrical stimulation circuit based on standard 5V technology is characterized in that when the output current I... OUT When the voltage is large, there is a significant voltage drop between the positive output terminal OUT+ and the negative output terminal OUT-, and simultaneously, the current I in the control branch... CTRL The current flows through R5, forming a relatively large voltage drop, which serves as the gate-source voltage |V of M18. GS18 When transistor M18 is turned on, it maintains the voltage between the 15V power supply input terminal and OUT+ at a relatively small value, which is the drain-source voltage V of M11 and M12. DS11 and V DS12 Provide sufficient voltage margin. When I OUT When the voltage is small, the voltage drop between OUT+ and OUT- is small, while I CTRL The pressure drop formed by flowing through R5 is relatively small, |V GS18 With a relatively small voltage, transistor M18 is cut off. The voltage between the 15V power supply input and OUT+ is mainly contributed by M13 and M14, consuming enough voltage to ensure the drain-source voltage V of M11 and M12. DS11 and V DS12 The voltage will not exceed the 5V limit to maintain transistor reliability. The gate voltages of M11 and M15 are provided by VDD2, the gate voltage of M16 is provided by a first-order cross-coupled charge pump, and the gate voltage of M12 is provided by the node voltage of the control branch, achieving dynamic control. The current I of the control branch is controlled by stacking transistors.CTRL The voltage between the OUT+ terminal and the 15V power supply input terminal in the stacked transistor output module is dynamically adjusted, while M11 and M12 consume excess voltage, so as to ensure the reliability of the electrical stimulation circuit under a wide load range and a wide output current range.

[0038] As shown in (9), adjusting the aspect ratio of M4 Or bias voltage V BIAS Under the same control voltage V SINK Within the range, I OUT The value range of I can be adjusted, but considering the reliability of the transistors in the stacked transistor output module, when I OUT When the maximum output value is exceeded, the voltage drop between the OUT+ and OUT- terminals becomes too large, and the source voltages of M11 and M12 become too low, causing V to... GS11 and V GS12 The range exceeds 5V; when I OUT When the output value is less than the minimum output value, the voltage drop between the OUT+ and OUT- terminals is too small, and the voltage between the source of M11 and the drain of M12 is too high, causing V to... DS11 and V DS12 A voltage range exceeding 5V will affect the reliability of the transistor's gate oxide layer.

[0039] Furthermore, the voltage-controlled current source electrostimulation circuit based on standard 5V technology is characterized in that the charge pump boost circuit module includes a first-order cross-coupled charge pump and a second-order cross-coupled charge pump. The first-order cross-coupled charge pump provides a voltage of 10V, and the second-order cross-coupled charge pump provides a voltage of 15V. To accommodate a wide output current range and reduce power supply ripple, the pump capacitor and load capacitor of the cross-coupled charge pump are placed off-chip to obtain a larger capacitance value. In the cross-coupled charge pump structure, the voltage across a single transistor will not exceed the standard voltage of 5V.

[0040] Furthermore, the voltage-controlled current source electrical stimulation circuit based on standard 5V technology is characterized in that the external capacitor terminals C_15, C_15_1, C_15_2, C_15_3, C_15_4, C_10, C_10_1, and C_10_2 are respectively connected to external capacitors C1, C2, C3, C4, C5, C6, C7, and C8. The other ends of capacitors C1 and C6 are grounded, the other ends of capacitors C2, C5, and C7 are connected to the clock signal CLK, and the other ends of capacitors C3, C4, and C8 are connected to the clock signal CLKB. The clock signals CLK and CLKB are timing-aligned inverted clock signals. The capacitance value of C1 is 10nF or higher, the capacitance values ​​of C2, C3, C4, C5, and C6 are 1nF or higher, and the capacitance values ​​of C7 and C8 are 40pF or higher.

[0041] Furthermore, the voltage-controlled current source electrical stimulation circuit based on standard 5V technology is characterized in that it is powered by VDD1 and VDD2, both of which are standard 5V voltages. VDD1 is used for the charge pump boost circuit module, and VDD2 is used for other circuit modules. The charge pump boost circuit module requires a certain power-on time to reach stability.

[0042] Furthermore, the load impedance of the OUT+ and OUT- terminals can range from 1kΩ to 5kΩ, and the output current can range from 50μA to 2mA. The magnitude of the output current is determined by the VSINK terminal voltage V. SINK adjust.

[0043] Compared with the prior art, the present invention has the following advantages:

[0044] 1. The circuit structure proposed in this invention has both wide load range characteristics and wide current output characteristics.

[0045] 2. The circuit proposed in this invention operates under an external 5V power supply and adopts a standard 5V process, eliminating the need for high-voltage processes or external high-voltage components, thus reducing manufacturing costs and complexity.

[0046] 3. The circuit structure proposed in this invention is simple and easy to achieve high integration and miniaturization. Attached Figure Description

[0047] Figure 1 This is the circuit diagram of the present invention.

[0048] Figure 2 The circuit diagram is shown for the first-order cross-coupled charge pump.

[0049] Figure 3 The circuit diagram is shown below for the second-order cross-coupled charge pump.

[0050] Figure 4 In a specific implementation, with a load resistance of 1kΩ to 5kΩ, the output current I... OUT With control voltage V SINK The relationship. Detailed Implementation

[0051] To better illustrate the performance and advantages of the present invention, the following embodiments are proposed and described in conjunction with the accompanying drawings, which further facilitates the explanation of the advantages of the present invention. The described embodiments are merely some embodiments of the present invention, and not all embodiments of the present invention. It should be understood that the present invention is not limited to the exemplary embodiments described herein.

[0052] The technical solution adopted in this invention is as follows:

[0053] A voltage-controlled current source electrical stimulation circuit based on standard 5V technology, the circuit diagram of which is shown below. Figure 1 As shown, the feature is that it includes a voltage-controlled current conversion module, a stacked transistor output and control module, and a charge pump boost circuit module; it includes a control voltage input terminal VSINK, a bias voltage input terminal VBIAS, external capacitor terminals C_15, C_15_1, C_15_2, C_15_3, C_15_4, C_10, C_10_1 and C_10_2, an output current positive terminal OUT+ and an output current negative terminal OUT-, and is powered by positive power supplies VDD1, VDD2 and ground terminal GND.

[0054] The voltage-controlled current conversion module generates a controlled voltage V. SINK Controlled current I M4 It consists of resistors R1, R2, R3, and R4, NMOS transistors M1, M2, M3, M4, and M5, and operational amplifier A1. It includes a voltage input terminal VSINK, a bias input terminal VBIAS, and a voltage-controlled current generator, and is powered by VDD2. R1, R2, R3, and R4 are connected in series; one end of R1 is connected to the gate of M4 to form the voltage input terminal VSINK, with a voltage of V. SINK The voltage at the other end of R1 is V. SINK1 The voltage across one end of R2 is V. SINK1 The voltage at the other end is V. SINK2 The voltage at one end of R3 is V. SINK2 The voltage at the other end is V. SINK3 The voltage at one end of R4 is V. SINK3 The other end is connected to GND; operational amplifier A1 is powered by VDD2 and GND, and the non-inverting input of A1 serves as the bias input VBIAS, with a voltage of V. BIAS The inverting input terminal is connected to the drains of M1, M2, M3, and M4 and the source of M5; the output terminal of A1 is connected to the gate of M5; the gate voltages of M1, M2, and M3 are V respectively. SINK3 V SINK2 and V SINK1 The sources of M1, M2, M3, M4 and M5 are all connected to GND; the drain of M5 forms the voltage-controlled current generation terminal; the substrates of M1, M2, M3, M4 and M5 are all connected to GND.

[0055] The stacked transistor output and control module is used to adapt to voltage changes. It consists of resistor R5, NMOS transistors M6, M7, M8, M9, M10, M11, M12, M15, and M16, PMOS transistors M13, M14, M17, and M18, and operational amplifier A2. It includes the gate voltage input terminals of M11 and M15, the bias input terminal VBIAS, the voltage input terminal VSINK, the 15V power supply input terminal, the 10V power supply input terminal, the voltage-controlled current input terminal, the positive output current terminal OUT+, and the negative output current terminal OUT-. The gate voltage input terminals of M11 and M15 are connected to VDD2, and the voltage-controlled current input terminal is connected to the voltage-controlled current generation terminal of the voltage-controlled current conversion module. VDD2 is the power supply. In this configuration, the source of M11 serves as the voltage-controlled current input terminal and is connected to the voltage-controlled current generation terminal; the gates of M11 and M15 serve as the gate voltage input terminals of M11 and M15, respectively, and are connected to VDD2; the drain of M11 is connected to the source of M12; the drain of M15, the source of M16, and the gate of M12 are connected; the drain of M12 forms the output negative terminal OUT-; the gate of M16 forms the 10V power supply input terminal; the drain of M16, the gate of M17, and the drain of M17 are connected; the source of M17 and the gate of M18... The gate of M18 is connected to one end of R5, and the other end of R5 is connected to the source of M18 and M14 to form a 15V power supply input. The drain of M18, the gate of M13, and the drain of M13 form the positive output terminal OUT+. The source of M13, the gate of M14, and the drain of M14 are connected. The drain of M10 is connected to the source of M15. The source of M10 and the drains of M6, M7, M8, and M9 are connected to the inverting input of A2. The non-inverting input of A2 serves as the bias input VBIAS, with a voltage of V. BIAS The output of A2 is connected to the gate of M10; the gate of M9 forms the voltage input terminal VSINK, with a voltage of V. SINK The gate voltages of M6, M7, and M8 are respectively V SINK3 V SINK2 and V SINK1 The sources of all M6, M7, M8, M9, and M10 are connected to GND; the substrates of M11, M12, M13, M14, M15, M16, M17, and M18 are connected to their own sources; the current I between the OUT+ and OUT- terminals... OUT This is the output current.

[0056] Among them, M1, M2, M3, M4, M5, and A1 are structurally symmetrical with M6, M7, M8, M9, M10, and A2, and operational amplifiers A1 and A2 are identical. The current flowing through M10 is I. CTRL That is, the circuit controlling the branch, M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10 have a width-to-length ratio of... The aspect ratio of a transistor satisfies the following formula:

[0057]

[0058] k is a constant; in this embodiment, k = 25, i.e., I CTRL and I OUT The proportional relationship is as follows:

[0059]

[0060] By properly setting the value of k, and adjusting the transistor's aspect ratio, the resistance value of resistor R5, and the bias voltage V... BIAS The size is adjusted to dynamically regulate the voltage between the OUT+ terminal and the 15V power supply input in the stacked transistor output module, ensuring the gate-source voltage V of all transistors is maintained. GS and drain-source voltage V DS It will not exceed the 5V limit.

[0061] The charge pump boost circuit module is used to provide the high voltage required by the overall circuit, and consists of a first-order cross-coupled charge pump and a second-order cross-coupled charge pump. The circuit diagram of the first-order cross-coupled charge pump is shown below. Figure 2 As shown, the circuit diagram of the second-order cross-coupled charge pump includes capacitor ports C_10, C_10_1, C_10_2, and a 10V voltage output terminal. Figure 3As shown, there are capacitor ports C_15, C_15_1, C_15_2, C_153, C_15_4 and a 15V voltage output terminal. The 15V voltage output terminal is connected to the 15V power supply input terminal of the stacked transistor output and control module, and the 10V voltage output terminal is connected to the 10V power supply input terminal of the stacked transistor output and control module. They are all powered by VDD1. In the first-order cross-coupled charge pump circuit, the drains of M19 and M20 together form the power supply terminal VDD1. The source of M19, the drain of M21, the gate of M20, and the gate of M22 are connected and also serve as capacitor port C_10_1. The source of M20, the drain of M22, the gate of M19, and the gate of M21 are connected and also serve as capacitor port C_10_2. The source of M21 and the source of M22 are connected and together form the 10V voltage output terminal. In the second-order cross-coupled charge pump circuit, the drains of M23 and M24 together form the power supply terminal VDD1. The source of M23, the drain of M25, the gate of M24, and the gate of M26 are connected and also serve as capacitor port C_15_1. The source of M24, the drain of M26, the gate of M23, and the gate of M25 are connected and also serve as capacitor port C_15_3. The source of M25 is connected to the drain of M27, and the source of M26 is connected to the drain of M28. The source of M27, the drain of M29, the gate of M28, and the gate of M30 are connected and also serve as capacitor port C_15_2. The source of M28, the drain of M30, the gate of M27, and the gate of M29 are connected and also serve as capacitor port C_15_4. The source of M29 and the source of M30 are connected, together forming the 15V voltage output terminal. The first-order cross-coupled charge pump provides 10V, and the second-order cross-coupled charge pump provides 15V. To accommodate a wide output current range and reduce power supply ripple, the pump capacitor and load capacitor of the cross-coupled charge pump are placed off-chip to obtain a larger capacitance value. In the cross-coupled charge pump structure, the voltage that a single transistor can withstand will not exceed the standard voltage of 5V.

[0062] External capacitors C_15, C_15_1, C_15_2, C_15_3, C_15_4, C_10, C_10_1, and C_10_2 are connected to external capacitors C1, C2, C3, C4, C5, C6, C7, and C8, respectively. The other ends of capacitors C1 and C6 are grounded, the other ends of capacitors C2, C5, and C7 are connected to the clock signal CLK, and the other ends of capacitors C3, C4, and C8 are connected to the clock signal CLKB. Clock signals CLK and CLKB are timing-aligned inverted clock signals. By appropriately selecting the values ​​of the external capacitors, the power supply ripple at the 10V and 15V voltage output terminals in the charge pump boost circuit module is reduced, and sufficient current is provided.

[0063] This case study is based on a 180nm process, and the relevant parameters of this invention are given below.

[0064] Appendix Figure 1 In the middle, the bias voltage V BI45 The frequency f of clock signals CLK and CLKB and the capacitance values ​​of capacitors C1 to C8 are as follows:

[0065] V BIAS =80mV

[0066] f = 5MHz

[0067] C1 = 10nF

[0068] C2=1nF

[0069] C3=1nF

[0070] C4=1nF

[0071] C5=1nF

[0072] C6=1nF

[0073] C7 = 40pF

[0074] C8 = 40pF

[0075] Appendix Figure 1 The parameters of each MOSFET and resistor are as follows:

[0076]

[0077]

[0078] R1 = 330kg

[0079] R2 = 119kΩ

[0080] R3 = 75kg

[0081] R4 = 140kΩ

[0082] R5 = 58kΩ

[0083] Operational amplifiers A1 and A2 are identical, and a folded cascode structure is used in this embodiment. M11, M12, M15, and M16 are DNW transistors, while the other transistors are ordinary transistors.

[0084] Appendix Figure 2 The parameters of each MOSFET are as follows:

[0085]

[0086] Appendix Figure 3 The parameters of each MOSFET are as follows:

[0087]

[0088] Based on the parameters above, this embodiment theoretically possesses the following performance characteristics.

[0089] Operational amplifiers A1 and A2 have a DC gain of 66.5 dB. The first-order cross-coupled charge pump has a stabilizing voltage of 9.83 V, and the second-order cross-coupled charge pump has a stabilizing voltage ranging from 14.3 V to 14.7 V. Their actual values ​​are related to the output current I. OUT The magnitude of the output current I is related to its value. OUT With control voltage V SINK Satisfy the following formula

[0090]

[0091] When the load resistance varies from 1kΩ to 5kΩ, the output current I of the voltage-controlled current source electrical stimulation circuit is... OUT With control voltage V SINK Relationship such as Figure 4 As shown, when V SINK When I changes from 950mV to 4.75V, OUT The linearity was good when the voltage changed from 49.2 μA to 2.05 mA. Figure 4 As can be seen from the enlarged sub-graph, for a fixed V SINK As the load resistance increases, I OUT It gradually decreases, but the difference is on the order of nanoamperes; with V SINK Taking a voltage of 3.95V as an example, when the load resistance is 1kΩ, I OUT = 1.61214mA, when the load resistance is 5kΩ, I OUT = 1.61211mA, the difference is 30nA. The output impedance R of the voltage-controlled current source electrical stimulation circuit. OUT The output current I is very large, and the circuit has a good load regulation rate. It can be considered that within a certain range, the output current I... OUT Subject only to control voltage V SINK It is controlled, and is independent of the load resistance.

[0092] The results shown are consistent with the theory. The voltage-controlled current source electrical stimulation circuit based on standard 5V technology has a wide load range and wide current output characteristics, and can drive loads from 1kΩ to 5kΩ and output an adjustable current from 50μA to 2mA.

[0093] The above description is only one embodiment of the present invention and is not intended to limit the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the technology of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A voltage-controlled current source electrical stimulation circuit based on standard 5V technology, characterized in that, It includes a voltage-controlled current conversion module, a stacked transistor output and control module, and a charge pump boost circuit module; it includes a control voltage input terminal VSINK, a bias voltage input terminal VBIAS, external capacitors C_15, C_15_1, C_15_2, C_15_3, C_15_4, C_10, C_10_1 and C_10_2, an output current positive terminal OUT+ and an output current negative terminal OUT-, and is powered by positive power supplies VDD1, VDD2 and ground terminal GND; The voltage-controlled current conversion module generates a controlled voltage V. SINK Controlled current I M4 It consists of resistors R1, R2, R3, R4, NMOS transistors M1, M2, M3, M4, M5 and operational amplifier A1, including voltage input terminal VSINK, bias input terminal VBIAS, voltage-controlled current generation terminal, and VDD2 power supply. The stacked transistor output and control module is used to adapt to voltage changes. It consists of resistor R5, NMOS transistors M6, M7, M8, M9, M10, M11, M12, M15, and M16, PMOS transistors M13, M14, M17, and M18, and operational amplifier A2. It includes the gate voltage input terminals of M11 and M15, the bias input terminal VBIAS, the voltage input terminal VSINK, the 15V power supply input terminal, the 10V power supply input terminal, the voltage-controlled current input terminal, the positive output current terminal OUT+, and the negative output current terminal OUT-. The gate voltage input terminals of M11 and M15 are connected to VDD2, and the voltage-controlled current input terminal is connected to the voltage-controlled current generation terminal of the voltage-controlled current conversion module. VDD2 is the power supply. The charge pump boost module provides the high voltage required by the circuit and consists of a first-order and a second-order cross-coupled charge pump. The first-order cross-coupled charge pump has capacitor ports C_10, C_10_1, C_10_2 and a 10V voltage output terminal. The second-order cross-coupled charge pump has capacitor ports C_15, C_15_1, C_15_2, C_15_3, C_15_4 and a 15V voltage output terminal. The 15V voltage output terminal is connected to the 15V power supply input terminal of the stacked transistor output and control module, and the 10V voltage output terminal is connected to the 10V power supply input terminal of the stacked transistor output and control module. VDD1 provides the power supply. The voltages of VDD1 and VDD2 are 5V, meaning that the circuit achieves a wide load range and wide current output under standard 5V process and external 5V power supply.

2. The voltage-controlled current source electrical stimulation circuit based on standard 5V technology according to claim 1, characterized in that, In the voltage-controlled current conversion module, R1, R2, R3, and R4 are connected in series; one end of R1 is connected to the gate of M4 to form the voltage input terminal VSINK, with a voltage of V. SINK The voltage at the other end of R1 is V. SINK1 The voltage across one end of R2 is V. SINK1 The voltage at the other end is V. SINK2 The voltage at one end of R3 is V. SINK2 The voltage at the other end is V. SINK3 The voltage at one end of R4 is V. SINK3 The other end is connected to GND; operational amplifier A1 is powered by VDD2 and GND, and the non-inverting input of A1 serves as the bias input VBIAS, with a voltage of V. BIAS The inverting input terminal is connected to the drains of M1, M2, M3, and M4 and the source of M5; the output terminal of A1 is connected to the gate of M5; the gate voltages of M1, M2, and M3 are V respectively. SINK3 V SINK2 and V SINK1 The sources of M1, M2, M3, M4 and M5 are all connected to GND; the drain of M5 forms the voltage-controlled current generation terminal; the substrates of M1, M2, M3, M4 and M5 are all connected to GND.

3. The voltage-controlled current source electrical stimulation circuit based on standard 5V technology according to claim 1, characterized in that, In the stacked transistor output and control module, the source of M11 serves as the voltage-controlled current input terminal and is connected to the voltage-controlled current generation terminal; the gates of M11 and M15 serve as the gate voltage input terminals of M11 and M15, respectively, and are connected to VDD2; the drain of M11 is connected to the source of M12; the drain of M15, the source of M16, and the gate of M12 are connected; the drain of M12 forms the output negative terminal OUT-; the gate of M16 forms the 10V power supply input terminal; the drain of M16, the gate of M17, and the drain of M17 are connected; and the drain of M17... The source of M18 and the gate of M18 are connected to one end of R5, and the other end of R5 is connected to the sources of M18 and M14 to form a 15V power supply input. The drain of M18, the gate of M13, and the drain of M13 form the positive output terminal OUT+. The source of M13, the gate of M14, and the drain of M14 are connected. The drain of M10 is connected to the source of M15. The source of M10 and the drains of M6, M7, M8, and M9 are connected to the inverting input of A2. The non-inverting input of A2 serves as the bias input VBIAS, with a voltage of V. BIAS The output of A2 is connected to the gate of M10; the gate of M9 forms the voltage input terminal VSINK, with a voltage of V. SINK The gate voltages of M6, M7, and M8 are respectively V SINK3 V SINK2 and V SINK1 The sources of all M6, M7, M8, M9, and M10 are connected to GND; the substrates of M11, M12, M13, M14, M15, M16, M17, and M18 are connected to their own sources; the current I between the OUT+ and OUT- terminals... OUT This is the output current.

4. The voltage-controlled current source electrical stimulation circuit based on standard 5V technology according to claim 1, characterized in that, Operational amplifiers A1 and A2 are identical, and the width-to-length ratios of NMOS transistors M5 and M10, M4 and M9, M3 and M8, M2 and M7, and M1 and M6 are the same.

5. The voltage-controlled current source electrical stimulation circuit based on standard 5V technology according to claim 1, characterized in that, The charge pump boost circuit module includes a first-order cross-coupled charge pump and a second-order cross-coupled charge pump. The first-order cross-coupled charge pump provides a voltage of 10V, and the second-order cross-coupled charge pump provides a voltage of 15V. In order to accommodate a wide output current range and reduce power supply ripple, the pump capacitor and load capacitor of the cross-coupled charge pump are placed off-chip to obtain a larger capacitance value. In the cross-coupled charge pump structure, the voltage that a single transistor can withstand will not exceed the standard voltage of 5V.

6. The voltage-controlled current source electrical stimulation circuit based on standard 5V technology according to claim 1, characterized in that, External capacitors C_15, C_15_1, C_15_2, C_15_3, C_15_4, C_10, C_10_1, and C_10_2 are connected to external capacitors C1, C2, C3, C4, C5, C6, C7, and C8, respectively. The other end of capacitors C1 and C6 is grounded, the other end of capacitors C2, C5, and C7 is connected to the clock signal CLK, and the other end of capacitors C3, C4, and C8 is connected to the clock signal CLKB. Clock signals CLK and CLKB are timing-aligned inverted clock signals. The capacitance value of C1 should be 10nF or higher, the capacitance values ​​of C2, C3, C4, C5, and C6 should be 1nF or higher, and the capacitance values ​​of C7 and C8 should be 40pF or higher.

7. The voltage-controlled current source electrical stimulation circuit based on standard 5V technology according to claim 1, characterized in that, The load impedance of the OUT+ and OUT- terminals can range from 1kΩ to 5kΩ, and the output current can range from 50μA to 2mA. The magnitude of the output current is determined by the voltage V at the VSINK terminal. SINK adjust.

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