Clock management unit, system on chip, and electronic device
By combining the clock controller, low-power distributor, and interface selector in the clock management unit, the problem of high design cost and low flexibility of low-power control of bus IP in SoC is solved, achieving flexible clock management and reducing design cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- THIS CORE WANREN INTELLIGENT TECH (JIANGSU) CO LTD
- Filing Date
- 2025-09-03
- Publication Date
- 2026-07-07
AI Technical Summary
In existing technologies, the low-power control design of bus IP in SoC is costly and inflexible, making it difficult to meet complex low-power requirements.
A clock management unit, including a clock controller, a low-power distributor, and an interface selector, is adopted. By using different top-level interface conduction methods of the interface selector, flexible clock management of the on-chip network system can be achieved, reducing design costs and improving flexibility.
Without changing the low-power distributor wiring and code design, it can flexibly respond to the addition or reduction of processor modules, reduce the overall design cost and improve the flexibility of clock management.
Smart Images
Figure CN120973180B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chips, and more specifically, to a clock management unit, a system-on-a-chip, and an electronic device. Background Technology
[0002] In System-on-Chip (SoC) design, the ultra-high power density of chip cores and the demand for low power in mobile applications have made low-power control increasingly important. Low-power control not only extends product lifespan but also reduces chip costs. Therefore, appropriate low-power design techniques are employed at every stage of system development, including system architecture, front-end design, back-end implementation, manufacturing, process technology, and mass production.
[0003] In the front-end design phase, commonly used low-power control techniques include clock gating and power gating. To meet the complex requirements of low-power control, Advanced Risc Machine (ARM) provides standard low-power interfaces for Q-channel and P-channel to satisfy such application scenarios. Each semiconductor intellectual property module (IP module) in a SoC defines different Q-channel and P-channel implementations according to its own needs. The SoC uses these standard interfaces to perform low-power control of the IP modules.
[0004] Low-power control of bus IP (also known as on-chip network system) is a continuous focus for those skilled in the art, but problems such as high design cost and low flexibility still exist. Summary of the Invention
[0005] The purpose of this invention is to provide a clock management unit, a system-on-a-chip, and an electronic device to improve the above-mentioned problems.
[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:
[0007] In a first aspect, embodiments of the present invention provide a clock management unit, the clock management unit including a clock controller, a low-power distributor, and an interface selector;
[0008] The low-power master control interface of the low-power distributor is connected to the low-power master control interface of the clock controller, and the N low-power distribution interfaces of the low-power distributor are connected one-to-one with the N low-power underlying interfaces of the interface selector. The clock controller is used to connect to the on-chip network system.
[0009] The interface selector is also provided with N sets of low-power top-level interfaces, which are used to connect to the processor module deployed at the top level of the system on chip.
[0010] The i-th low-power top-level interface of the interface selector is a first type of top-level interface. The interface selector is used to connect its internal i-th low-power top-level interface with the i-th low-power bottom-level interface, so as to connect the i-th low-power distribution interface of the low-power distributor with the target module. The first type of top-level interface is a low-power top-level interface connected to a processor module in normal working state, and the processor module connected to the first type of top-level interface is the target module.
[0011] The i-th group of low-power top-level interfaces of the interface selector is a second type of top-level interface, and the interface selector is used to connect the analog processor module deployed therein with the i-th group of low-power distribution interfaces of the low-power distributor.
[0012] The simulated processor module is used to simulate a processor module deployed at the top level of the on-chip system and in an inactive state. The second type of top-level interface is a low-power top-level interface other than the first type of top-level interface.
[0013] The clock controller is used to manage the clock of the on-chip network system based on the monitoring results of the low-power distributor, the target module, and the analog processor module.
[0014] Optionally, if the i-th low-power top-level interface is a first type of top-level interface, the interface selector is used to send a first type of data signal to the low-power distributor through the i-th low-power transmission line;
[0015] Wherein, the i-th low-power transmission line is the low-power transmission line between the i-th low-power distribution interface of the low-power distributor and the i-th low-power bottom interface of the interface selector, and the first type of data signal is the data signal transmitted between the target module corresponding to the i-th low-power top interface and the on-chip network system.
[0016] If the i-th low-power top-level interface is a second type of top-level interface, the interface selector is used to send a second type of data signal to the low-power distributor through the i-th low-power transmission line;
[0017] The second type of data signal is a data signal generated by the analog processor module that does not include an active state identifier;
[0018] When the clock of the on-chip network system is in the on state, the low-power distributor is used to identify whether the received first type of data signal and second type of data signal include an active state identifier in order to obtain a state analysis report, and send the analysis report to the clock controller;
[0019] The status analysis report includes the analysis results of whether the upstream module is in an active state. The upstream module is the processor module and the analog processor module corresponding to the N groups of low-power distribution interfaces of the low-power distributor.
[0020] The clock controller is used to initiate a clock shutdown process when the status analysis report indicates that all upstream modules are inactive.
[0021] Optionally, after initiating the clock shutdown process, the clock controller is used to send a clock shutdown request to the low-power distributor;
[0022] The low-power distributor is used to send a clock shutdown request to the interface selector through N sets of low-power transmission lines when it receives a clock shutdown request sent by the clock controller.
[0023] If the i-th low-power top-level interface is a first-type top-level interface, the interface selector is used to forward the clock shutdown request received by the i-th low-power top-level interface to its corresponding target module, and transmit the clock shutdown feedback information transmitted by the target module to the low-power distributor through the i-th low-power transmission line.
[0024] If the i-th low-power top-level interface is a second type of top-level interface, the interface selector is used to transmit the clock shutdown feedback information generated by the analog processor module to the low-power distributor through the i-th low-power transmission line.
[0025] The clock shutdown feedback information generated by the analog processor module all indicate agreement to shut down the clock.
[0026] The low-power distributor is used to send a clock shutdown command to the clock controller when all received clock shutdown feedback messages agree to perform clock shutdown.
[0027] The clock controller is used to turn off the clock of the on-chip network system when it receives a clock shutdown command.
[0028] Optionally, the second type of data signal does not include on-chip network system access requests;
[0029] When the clock of the on-chip network system is in the off state, the low-power distributor is used to send the on-chip network system access request to the clock controller when it recognizes that either the first type of data signal or the second type of data signal it received includes an on-chip network system access request.
[0030] The clock controller is used to initiate the clock start process when an access request from the on-chip network system is received.
[0031] Optionally, after initiating the clock enable process, the clock controller is used to send a clock enable request to the low-power distributor;
[0032] The low-power distributor is used to send a clock-on request to the interface selector through N sets of low-power transmission lines when it receives a clock-on request sent by the clock controller.
[0033] If the i-th low-power top-level interface is a first-type top-level interface, the interface selector is used to forward the clock enable request received by the i-th low-power top-level interface to its corresponding target module, and transmit the clock enable feedback information transmitted by the target module to the low-power distributor through the i-th low-power transmission line.
[0034] If the i-th low-power top-level interface is a second type of top-level interface, the interface selector is used to transmit the clock enable feedback information generated by the analog processor module to the low-power distributor through the i-th low-power transmission line.
[0035] The clock-on feedback information generated by the analog processor module all indicate agreement to enable the clock.
[0036] The low-power distributor is used to send a clock-on command to the clock controller when all received clock-on feedback messages agree to enable the clock.
[0037] The clock controller is used to turn on the clock of the on-chip network system when it receives a clock-on command.
[0038] Optionally, the i-th group of low-power transmission lines includes a data signal acquisition line and a handshake signal transmission line.
[0039] Optionally, the interface selector is provided with N status registers. When the i-th group of low-power top-level interfaces is connected to a processor module in normal working state, the value of the i-th status register matches the identifier of the first type of top-level interface.
[0040] When the i-th low-power top-level interface is not connected to a processor module in normal working condition, the value of the i-th status register matches the identifier of the second type of top-level interface.
[0041] Secondly, embodiments of the present invention provide a system-on-a-chip, the system-on-a-chip including the clock management unit described above.
[0042] Thirdly, embodiments of the present invention provide an electronic device including the above-described system-on-a-chip.
[0043] Compared to existing technologies, the clock management unit, system-on-chip, and electronic device provided in this embodiment of the invention include an interface selector whose i-th low-power top-level interface is a first type of top-level interface. The interface selector is used to connect its internal i-th low-power top-level interface with the i-th low-power bottom-level interface, thereby connecting the i-th low-power distribution interface of the low-power distributor with the target module. The interface selector's i-th low-power top-level interface is a second type of top-level interface, and the interface selector is used to connect the deployed analog processor module therein with the i-th low-power distribution interface of the low-power distributor. The clock controller is used to perform clock management on the on-chip network system based on the monitoring results of the low-power distributor, the target module, and the analog processor module. This means that under any circumstances, all N low-power uplink ports of the low-power distributor are connected to the processor module. When adding or removing processor modules deployed at the top level of the system-on-a-chip, only the interface selector needs to be configured in software to change its internal conduction relationship and whether to start the corresponding simulation function. There is no need to change the wiring of the low-power distributor, redesign the low-power distributor code, or redivide the chip layout, thereby reducing the overall design cost and improving the flexibility of clock management.
[0044] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0045] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0046] Figure 1 This is one of the structural schematic diagrams of the clock management unit provided in an embodiment of the present invention.
[0047] Figure 2 This is a second schematic diagram of the structure of the clock management unit provided in an embodiment of the present invention. Detailed Implementation
[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0049] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0050] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0051] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0052] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.
[0053] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0054] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0055] Please refer to Figure 1 , Figure 1 This is one of the structural schematic diagrams of a clock management unit provided in an embodiment of the present invention. The clock management unit includes a clock controller, a low-power distributor (LPD), and a low-power interface selector (LPI selector).
[0056] The low-power master control interface of the low-power distributor is connected to the low-power master control interface of the clock controller. The N low-power distribution interfaces of the low-power distributor are connected one-to-one with the N low-power underlying interfaces of the interface selector (that is, the nth low-power distribution interface of the low-power distributor is connected to the nth low-power underlying interface of the interface selector, 1≤n≤N). The clock controller is used to connect to the on-chip network system.
[0057] The interface selector also has N sets of low-power top-level interfaces, which are used to connect to the processor module deployed at the top level of the system on the chip.
[0058] In the diagram, LPI TOP n represents the transmission line between the nth low-power top-level interface and the processing module, LPI In represents the nth low-power transmission line, which is the low-power transmission line between the nth low-power distribution interface of the low-power distributor and the nth low-power bottom interface of the interface selector, and LPI 0 represents the low-power transmission line between the low-power master control interface of the low-power distributor and the low-power master control interface of the clock controller.
[0059] Optionally, the low-power top-level interface has at least two sub-ports. One sub-port is used to connect to the processor module's low-power handshake port for clock-off and clock-on handshakes. The other sub-port is used to connect to the processor module's data signal port, which is used to connect to the on-chip network system to transmit data signals, such as the first type of data signal described below.
[0060] The processor module deployed at the top level of the system-on-a-chip can be, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), or a data processing unit (DPU).
[0061] The i-th low-power top-level interface (1≤i≤N) of the interface selector is a first-type top-level interface. The interface selector is used to connect its internal i-th low-power top-level interface with the i-th low-power bottom-level interface, so as to connect the i-th low-power distribution interface of the low-power distributor with the target module. This enables data monitoring and handshake interaction between the two.
[0062] Among them, the first type of top-level interface is a low-power top-level interface connected to a processor module that is in normal working condition. The processor module connected to the first type of top-level interface is the target module. The processor module in normal working condition refers to a processor module that has not experienced a fault and has not been powered down.
[0063] The i-th group of low-power top-level interfaces of the interface selector is a second type of top-level interface. The interface selector is used to connect the analog processor module deployed therein with the i-th group of low-power distribution interfaces of the low-power distributor.
[0064] Among them, the simulated processor module is used to simulate a processor module deployed at the top level of the on-chip system and in an inactive state. The second type of top-level interface is (in the interface selector) a low-power top-level interface other than the first type of top-level interface, that is, a low-power top-level interface that is not connected to a processor module, or a low-power top-level interface that is connected to a processor module in an abnormal working state (fault or power-down).
[0065] Please refer to Figure 2 , Figure 2 This is a second schematic diagram of the structure of the clock management unit provided in an embodiment of the present invention. Figure 2 In the Nth low-power top-level interface, no processor module is connected. The Nth low-power top-level interface is the second type of top-level interface.
[0066] The clock controller is used to manage the clock of the on-chip network system based on the monitoring results of the low-power distributor, target module, and analog processor module.
[0067] In this embodiment of the invention, it is equivalent to all N groups of low-power uplink ports of the low-power distributor being connected to the processor module under any circumstances. When adding or removing processor modules deployed at the top level of the system-on-a-chip, only the interface selector needs to be configured in software to change its internal conduction relationship and whether to start the corresponding simulation function. There is no need to change the wiring of the low-power distributor, redesign the low-power distributor code, or redivide the chip layout, thereby reducing the overall design cost and improving the flexibility of clock management.
[0068] When the upstream processor module fails to work properly or is powered off, and cannot drive the LPI normally, the clock management unit can still perform the function of dynamically switching the clock normally due to the simulation function of the analog processor module.
[0069] Building upon the preceding text, this invention also provides an optional implementation method for disabling the clock of the on-chip network system, as detailed below.
[0070] If the i-th low-power top-level interface is a first-type top-level interface, the interface selector is used to send first-type data signals to the low-power distributor through the i-th low-power transmission line.
[0071] Among them, the i-th low-power transmission line is the low-power transmission line between the i-th low-power distribution interface of the low-power distributor and the i-th low-power bottom interface of the interface selector, and the first type of data signal is the data signal transmitted between the target module corresponding to the i-th low-power top interface and the on-chip network system.
[0072] If the i-th low-power top-level interface is a second type of top-level interface, the interface selector is used to send the second type of data signal to the low-power distributor through the i-th low-power transmission line;
[0073] The second type of data signal is the data signal generated by the analog processor module that does not include an active status identifier;
[0074] When the clock of the on-chip network system is on, the low-power distributor is used to identify whether the received first type of data signal and second type of data signal include an active status identifier in order to obtain a status analysis report and send the analysis report to the clock controller.
[0075] The status analysis report includes the analysis results of whether the upstream modules are in an active state. The upstream modules are the processor modules and analog processor modules corresponding to the N groups of low-power distribution interfaces of the low-power distributor.
[0076] When the active status indicator is present in the first type of data signal corresponding to the processor module, it indicates that the processor module is in an active state; otherwise, it indicates that the processor module is in an inactive state. All analog processor modules are in an inactive state.
[0077] The clock controller is used to initiate the clock shutdown process when the status analysis report indicates that all upstream modules are inactive.
[0078] Regarding how to ensure that the upstream processor module is not affected during the clock shutdown process, this embodiment of the invention also provides an optional implementation method, please refer to the following.
[0079] After initiating the clock shutdown process, the clock controller is used to send a clock shutdown request to the low-power distributor.
[0080] The low-power distributor is used to send clock shutdown requests to the interface selector through N sets of low-power transmission lines when it receives a clock shutdown request from the clock controller.
[0081] If the i-th low-power top-level interface is a first-type top-level interface, the interface selector is used to forward the clock shutdown request received by the i-th low-power top-level interface to its corresponding target module, and transmit the clock shutdown feedback information transmitted by the target module to the low-power distributor through the i-th low-power transmission line.
[0082] If the i-th low-power top-level interface is a second type of top-level interface, the interface selector is used to transmit the clock shutdown feedback information generated by the analog processor module to the low-power distributor through the i-th low-power transmission line.
[0083] The clock shutdown feedback information generated by the analog processor module all indicate agreement to shut down the clock.
[0084] The low-power distributor sends a clock shutdown command to the clock controller when all received clock shutdown feedback messages agree to perform clock shutdown (indicating that the clock shutdown handshake is complete).
[0085] The clock controller is used to turn off the clock of the on-chip network system when it receives a clock shutdown command.
[0086] In one alternative implementation, the second type of data signal does not include on-chip network system access requests. Based on this, the present invention also provides an alternative implementation regarding how to enable the clock of the on-chip network system, as described below.
[0087] When the clock of the on-chip network system is off, the low-power distributor is used to send the on-chip network system access request to the clock controller when it recognizes that either the first type of data signal or the second type of data signal it has received includes an on-chip network system access request.
[0088] The clock controller is used to initiate the clock start process when an access request from the on-chip network system is received.
[0089] Regarding how to ensure that the upstream processor module is not affected during the clock startup process, this embodiment of the invention also provides an optional implementation method, which is detailed below.
[0090] After initiating the clock-on process, the clock controller sends a clock-on request to the low-power distributor.
[0091] The low-power distributor is used to send the clock-on request to the interface selector through N sets of low-power transmission lines when it receives the clock-on request from the clock controller.
[0092] If the i-th low-power top-level interface is a first-type top-level interface, the interface selector is used to forward the clock enable request received by the i-th low-power top-level interface to its corresponding target module, and transmit the clock enable feedback information transmitted by the target module to the low-power distributor through the i-th low-power transmission line.
[0093] If the i-th low-power top-level interface is a second type of top-level interface, the interface selector is used to transmit the clock enable feedback information generated by the analog processor module to the low-power distributor through the i-th low-power transmission line.
[0094] The clock-on feedback information generated by the analog processor module all indicate agreement to enable the clock.
[0095] The low-power distributor sends a clock-on command to the clock controller when all received clock-on feedback messages agree to clock-on (indicating that the clock-on handshake is complete).
[0096] The clock controller is used to turn on the clock of the on-chip network system when it receives a clock-on command.
[0097] In one optional implementation, the i-th group of low-power transmission lines includes a data signal acquisition line and a handshake signal transmission line. The data signal acquisition line is used to transmit first-type data signals and second-type data signals; the handshake signal transmission line is used to transmit clock-off requests, clock-off feedback information, clock-on requests, and clock-on feedback information.
[0098] To facilitate the interface selector's understanding of the current connection status of each low-power top-level interface and avoid repeatedly querying whether a processor module in normal working condition is connected to the low-power top-level interface, this embodiment of the invention also provides an optional implementation method, please refer to the following.
[0099] The interface selector has N status registers. When the i-th low-power top-level interface is connected to a processor module that is in normal working condition, the value of the i-th status register matches the identifier of the first type of top-level interface.
[0100] When the i-th low-power top-level interface is not connected to a processor module in normal working condition, the value of the i-th status register matches the identifier of the second type of top-level interface.
[0101] This invention also provides a system-on-a-chip (SoC) including the aforementioned clock management unit.
[0102] This invention also provides an electronic device, including the system-on-a-chip described above.
[0103] In summary, the clock management unit, system-on-chip, and electronic device provided in this embodiment of the invention include an interface selector whose i-th group of low-power top-level interfaces is a first type of top-level interface. The interface selector is used to connect its internal i-th group of low-power top-level interfaces with its i-th group of low-power bottom-level interfaces, thereby connecting the i-th group of low-power distribution interfaces of the low-power distributor with the target module. The interface selector's i-th group of low-power top-level interfaces is a second type of top-level interface. The interface selector is used to connect the analog processor module deployed therein with the i-th group of low-power distribution interfaces of the low-power distributor. The clock controller is used to perform clock management on the on-chip network system based on the monitoring results of the low-power distributor, the target module, and the analog processor module. This means that under any circumstances, all N low-power uplink ports of the low-power distributor are connected to the processor module. When adding or removing processor modules deployed at the top level of the system-on-a-chip, only the interface selector needs to be configured in software to change its internal conduction relationship and whether to start the corresponding simulation function. There is no need to change the wiring of the low-power distributor, redesign the low-power distributor code, or redivide the chip layout, thereby reducing the overall design cost and improving the flexibility of clock management.
[0104] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
[0105] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
Claims
1. A clock management unit, characterized in that, The clock management unit includes a clock controller, a low-power distributor, and an interface selector; The low-power master control interface of the low-power distributor is connected to the low-power master control interface of the clock controller, and the N low-power distribution interfaces of the low-power distributor are connected one-to-one with the N low-power underlying interfaces of the interface selector. The clock controller is used to connect to the on-chip network system. The interface selector is also provided with N sets of low-power top-level interfaces, which are used to connect to the processor module deployed at the top level of the system on chip. The i-th low-power top-level interface of the interface selector is a first type of top-level interface. The interface selector is used to connect its internal i-th low-power top-level interface with the i-th low-power bottom-level interface, so as to connect the i-th low-power distribution interface of the low-power distributor with the target module. The first type of top-level interface is a low-power top-level interface connected to a processor module in normal working state, and the processor module connected to the first type of top-level interface is the target module. The i-th group of low-power top-level interfaces of the interface selector is a second type of top-level interface, and the interface selector is used to connect the analog processor module deployed therein with the i-th group of low-power distribution interfaces of the low-power distributor. The simulated processor module is used to simulate a processor module deployed at the top level of the on-chip system and in an inactive state. The second type of top-level interface is a low-power top-level interface other than the first type of top-level interface. The clock controller is used to manage the clock of the on-chip network system based on the monitoring results of the low-power distributor, the target module, and the analog processor module.
2. The clock management unit as described in claim 1, characterized in that, If the i-th low-power top-level interface is a first-type top-level interface, the interface selector is used to send a first-type data signal to the low-power distributor through the i-th low-power transmission line. Wherein, the i-th low-power transmission line is the low-power transmission line between the i-th low-power distribution interface of the low-power distributor and the i-th low-power bottom interface of the interface selector, and the first type of data signal is the data signal transmitted between the target module corresponding to the i-th low-power top interface and the on-chip network system. If the i-th low-power top-level interface is a second type of top-level interface, the interface selector is used to send a second type of data signal to the low-power distributor through the i-th low-power transmission line; The second type of data signal is the data signal generated by the analog processor module that does not include an active state identifier; When the clock of the on-chip network system is in the on state, the low-power distributor is used to identify whether the received first type of data signal and second type of data signal include an active state identifier in order to obtain a state analysis report, and send the analysis report to the clock controller; The status analysis report includes the analysis results of whether the upstream module is in an active state. The upstream module is the processor module and the analog processor module corresponding to the N groups of low-power distribution interfaces of the low-power distributor. The clock controller is used to initiate a clock shutdown process when the status analysis report indicates that all upstream modules are inactive.
3. The clock management unit as described in claim 2, characterized in that, After initiating the clock shutdown process, the clock controller is used to send a clock shutdown request to the low-power distributor; The low-power distributor is used to send a clock shutdown request to the interface selector through N sets of low-power transmission lines when it receives a clock shutdown request sent by the clock controller. If the i-th low-power top-level interface is a first-type top-level interface, the interface selector is used to forward the clock shutdown request received by the i-th low-power top-level interface to its corresponding target module, and transmit the clock shutdown feedback information transmitted by the target module to the low-power distributor through the i-th low-power transmission line. If the i-th low-power top-level interface is a second type of top-level interface, the interface selector is used to transmit the clock shutdown feedback information generated by the analog processor module to the low-power distributor through the i-th low-power transmission line. The clock shutdown feedback information generated by the analog processor module all indicate agreement to shut down the clock. The low-power distributor is used to send a clock shutdown command to the clock controller when all received clock shutdown feedback messages agree to perform clock shutdown. The clock controller is used to turn off the clock of the on-chip network system when it receives a clock shutdown command.
4. The clock management unit as described in claim 2, characterized in that, The second type of data signal does not include on-chip network system access requests; When the clock of the on-chip network system is in the off state, the low-power distributor is used to send the on-chip network system access request to the clock controller when it recognizes that either the first type of data signal or the second type of data signal it received includes an on-chip network system access request. The clock controller is used to initiate the clock start process when an access request for the on-chip network system is received.
5. The clock management unit as described in claim 4, characterized in that, After initiating the clock enable process, the clock controller is used to send a clock enable request to the low-power distributor; The low-power distributor is used to send a clock-on request to the interface selector through N sets of low-power transmission lines when it receives a clock-on request sent by the clock controller. If the i-th low-power top-level interface is a first-type top-level interface, the interface selector is used to forward the clock enable request received by the i-th low-power top-level interface to its corresponding target module, and transmit the clock enable feedback information transmitted by the target module to the low-power distributor through the i-th low-power transmission line. If the i-th low-power top-level interface is a second type of top-level interface, the interface selector is used to transmit the clock enable feedback information generated by the analog processor module to the low-power distributor through the i-th low-power transmission line. The clock-on feedback information generated by the analog processor module all indicate agreement to enable the clock. The low-power distributor is used to send a clock-on command to the clock controller when all received clock-on feedback messages agree to enable the clock. The clock controller is used to turn on the clock of the on-chip network system when it receives a clock-on command.
6. The clock management unit as described in claim 5, characterized in that, The i-th group of low-power transmission lines includes data signal acquisition lines and handshake signal transmission lines.
7. The clock management unit as claimed in claim 1, characterized in that, The interface selector is equipped with N status registers. When the i-th low-power top-level interface is connected to a processor module in normal working state, the value of the i-th status register matches the identifier of the first type of top-level interface. When the i-th low-power top-level interface is not connected to a processor module in normal working condition, the value of the i-th status register matches the identifier of the second type of top-level interface.
8. A system-on-a-chip, characterized in that, The system-on-chip includes the clock management unit as described in any one of claims 1-7.
9. An electronic device, characterized in that, Includes the system-on-a-chip as described in claim 8.