Solid state disk and electronic equipment

Abstract

The invention provides a solid state disk and electronic equipment. The solid state disk comprises a mainboard; the plurality of controllers are arranged on the main board; the plurality of flash memory particles are electrically connected with the plurality of controllers, the plurality of flash memory particles are used for storing data, and the plurality of controllers are used for controlling data operation of the plurality of flash memory particles. According to the scheme of the embodiment of the invention, the configuration of the plurality of controllers is adopted in the solid state disk, and the overall performance and reliability of the solid state disk are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, and in particular, to a solid state disk and an electronic device. BACKGROUND

[0002] A solid state disk (SSD) is a high-performance storage device with high reliability, low power consumption, and high performance. It is widely used in electronic devices. The solid state disk usually includes a storage chip for storing data and a master control chip for managing the storage chip. The master control chip and the storage chip are usually integrated in a direct connection manner on a circuit board.

[0003] With the increase of the capacity of the SSD, the number of flash memory chips on the SSD also increases, which makes the reliability and performance of the SSD face greater challenges. SUMMARY

[0004] The present application provides a solid state disk and an electronic device, which is beneficial to guarantee the reliability and performance of the SSD.

[0005] In a first aspect, a solid state disk is provided, comprising: a mainboard; a plurality of controllers disposed on the mainboard; a plurality of flash memory particles electrically connected with the plurality of controllers, the plurality of flash memory particles being configured to store data, and the plurality of controllers being configured to control data operations of the plurality of flash memory particles.

[0006] According to the scheme of the embodiments of the present application, the configuration of multiple controllers is adopted in the SSD, which is beneficial to improve the overall control performance and thus improve the overall performance of the SSD. At the same time, the configuration of multiple controllers is adopted in the SSD, and when a part of the controllers fails, the other controllers can still work normally, which is beneficial to avoid the failure of the entire SSD, thereby improving the reliability of the SSD and reducing the cost of fault repair.

[0007] Exemplarily, each controller can be electrically connected with all the flash memory particles in the plurality of flash memory particles.

[0008] Exemplarily, the plurality of controllers configured to control data operations of the plurality of flash memory particles can include: the plurality of controllers configured to write data to the plurality of flash memory particles, and / or read data from the plurality of flash memory particles.

[0009] In combination with the first aspect, in some implementations of the first aspect, a first group of flash memory particles in the plurality of flash memory particles is assigned to a first controller in the plurality of controllers, and a second group of flash memory particles in the plurality of flash memory particles is assigned to a second controller in the plurality of controllers.

[0010] The first controller can independently manage the first group of flash memory particles, and the second controller can independently manage the second group of flash memory particles.

[0011] In the scheme of the embodiments of the present application, the plurality of controllers can independently manage part of the flash memory particles, that is, one controller does not need to manage all the flash memory particles, avoiding the influence of the overall performance of the SSD due to the insufficient performance of a single controller, thereby facilitating the improvement of the overall performance of the SSD. Meanwhile, when part of the controllers fail, the other controllers can still normally manage part of the flash memory particles, which is beneficial to avoid the failure of the entire SSD, thereby facilitating the improvement of the reliability of the SSD and reducing the cost of fault repair.

[0012] With reference to the first aspect, in some implementations of the first aspect, the first controller or the second controller of the plurality of controllers is configured to manage all of the plurality of flash memory particles.

[0013] With reference to the first aspect, in some implementations of the first aspect, the first controller and the second controller of the plurality of controllers are configured to manage all of the plurality of flash memory particles.

[0014] In the scheme of the embodiments of the present application, the plurality of controllers can cooperatively manage the plurality of flash memory particles, which is beneficial to realize the efficient operation of the flash memory particles and improve the overall performance of the SSD. Meanwhile, the cooperative control of the plurality of controllers on the plurality of flash memory particles can support redundancy protection, thereby facilitating the improvement of the reliability of the SSD.

[0015] With reference to the first aspect, in some implementations of the first aspect, in the case where the first controller fails, the second controller is configured to take over the operation originally performed by the first controller.

[0016] In the scheme of the embodiments of the present application, when part of the controllers, for example, the first controller, in the plurality of controllers fails, the other controllers, for example, the second controller, can take over the work tasks thereof to maintain the normal work of the SSD, thereby facilitating the guarantee of the reliability of the SSD.

[0017] With reference to the first aspect, in some implementations of the first aspect, the plurality of controllers are distributed on one side of the area where the plurality of flash memory particles are located.

[0018] With reference to the first aspect, in some implementations of the first aspect, the plurality of controllers are distributed on at least two sides of the area where the plurality of flash memory particles are located.

[0019] In the scheme of the embodiments of the present application, the plurality of controllers are distributed on at least two sides of the area where the plurality of flash memory particles are located, which is beneficial to realize the close arrangement of the controllers and the flash memory particles and reduce the threads between the controllers and the flash memory particles, for example, in the case where the controllers independently control the flash memory particles, the scheme is beneficial to realize the close management of the controllers on the flash memory particles, thereby facilitating the improvement of the performance of the SSD.

[0020] With reference to the first aspect, in some implementations of the first aspect, the solid state disk further includes one or more storage bars, each storage bar including at least one flash memory chip of a plurality of flash memory chips, and at least one storage bar is detachably connected to the mainboard.

[0021] The detachable storage bar can be understood as a detachable independent unit including one or more flash memory chips arranged on the mainboard.

[0022] Further, the solid state disk further includes one or more storage interfaces arranged on the mainboard. The plurality of controllers are electrically connected to the one or more storage interfaces. The at least one storage bar is detachably connected to the one or more storage interfaces.

[0023] In the scheme of the embodiments of the present application, the storage bar is connected to the mainboard in a detachable manner, which is conducive to improving the reliability of the SSD. Specifically, when the flash memory chip fails, the storage bar can be detached and replaced as a basic unit, avoiding the failure of the SSD due to the failure of the flash memory chip, and reducing the fault repair cost. At the same time, the storage bar is connected to the mainboard in a detachable manner, which is conducive to flexibly adjusting the capacity of the SSD.

[0024] With reference to the first aspect, in some implementations of the first aspect, the solid state disk includes a plurality of storage bars, and the types of flash memory chips in different storage bars are different. The type of flash memory chip includes at least one of the following: single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC).

[0025] In the scheme of the embodiments of the present application, the mounting capability of multiple types of flash memory chips is enabled, which can realize the cooperative data storage of multiple types of flash memory chips, and is conducive to obtaining an SSD that meets different needs in terms of performance and / or capacity. The detachable connection manner allows more flexible configuration of flash memory chips. Users can select appropriate types of flash memory chips to obtain an SSD that meets their needs, which is conducive to improving user experience.

[0026] With reference to the first aspect, in some implementations of the first aspect, the solid state disk includes a plurality of storage bars, and the number of layers of flash memory chips in different storage bars is different.

[0027] In the scheme of the embodiments of the present application, the mounting capability of multiple generations of flash memory chips is enabled, which can realize the cooperative data storage of multiple generations of flash memory chips, and is conducive to obtaining an SSD that meets different needs in terms of performance and / or capacity. The detachable connection manner allows more flexible configuration of flash memory chips. Users can select appropriate generations of flash memory chips to obtain an SSD that meets their needs, which is conducive to improving user experience.

[0028] In a second aspect, an electronic device is provided, which includes the solid state disk in the first aspect or any implementation manner of the first aspect and a host. The host is configured to write data to the solid state disk and / or read data from the solid state disk.

[0029] The technical effects achieved by the second aspect can be described with reference to the technical effects achieved by the first aspect and any implementation manner of the first aspect, and the repeated parts will not be discussed. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a schematic block diagram of a structure of a solid state disk.

[0031] Figure 2 is a schematic block diagram of a structure of a solid state disk.

[0032] Figure 3 is a schematic structural diagram of a flash memory chip.

[0033] Figure 4 is a schematic block diagram of a structure of a solid state disk.

[0034] Figure 5 is a schematic block diagram of a structure of a solid state disk.

[0035] Figure 6 is a schematic block diagram of a structure of a solid state disk.

[0036] Figure 7 is a schematic block diagram of a structure of a solid state disk.

[0037] Figure 8 is a schematic block diagram of a structure of a solid state disk.

[0038] Figure 9 is a schematic block diagram of a structure of a solid state disk. DETAILED DESCRIPTION

[0039] The technical solutions in the present application will be described below with reference to the drawings.

[0040] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” and “the” are intended to include expressions such as “one or more,” unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, “at least one,” “at least one,” and “one or more” refer to one, two, or more than two. “At least one of the following” or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. “First,” “second,” and various numerical designations are merely distinctions for descriptive convenience and are not intended to limit the scope of the embodiments of this application, nor do they limit the position, order, priority, quantity, or content of the described objects. The term "and / or" describes the correspondence between corresponding objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously. A and B can be singular or plural. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. In various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. For example, in the embodiments of this application, the words "301," "401," and "501" are merely identifiers for descriptive convenience and do not limit the order of execution steps.

[0041] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. In this application, the words "exemplary" or "for example" are used to indicate that something is illustrative, exemplary, or descriptive. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. In the embodiments of this application, descriptions such as "when," "in the case of," "if," and "if" all refer to the fact that the device will perform a corresponding processing under certain objective circumstances, and are not a limitation on time, nor do they require the device to perform a judgment action during implementation, nor do they imply any other limitations.

[0042] In the present application, "for indicating" can include for directly indicating and for indirectly indicating. When describing that certain indication information is for indicating A, it can include that the indication information directly indicates A or indirectly indicates A, and does not mean that A must be carried in the indication information.

[0043] Figure 1 A structural block diagram of a solid state disk is shown. As shown in the figure, the solid state disk includes a master control chip and a plurality of flash memory chips. The master control chip and the plurality of flash memory chips are integrated in a direct connection manner on a mainboard. The master control chip can be used to control and manage the storage chips. The storage chips can be used to store data. The master control chip can communicate with an external host to receive input / output (IO) tasks of the external host. Figure 1

[0044] With the development of technology, the capacity of SSDs is increasing, and large-capacity SSDs (such as SSDs with a capacity greater than 64 TB) will gradually become mainstream storage media. The current structure of SSDs is difficult to meet the reliability and performance challenges brought by the increase in the capacity of SSDs, that is, the current structure of SSDs is difficult to meet the high reliability and high performance requirements faced by the development of the capacity of SSDs.

[0045] One of the main ways to increase the capacity of SSDs is to increase the number of flash memory chips on the SSD. That is, as the capacity of the SSD increases, the number of flash memory chips that the master control chip needs to control and manage at the same time also increases. The performance of the master control chip will become a technical bottleneck that limits the overall performance of the SSD. At the same time, a master control chip failure can cause the entire SSD to fail, and the entire SSD may need to be replaced, resulting in high cost for failure repair.

[0046] Therefore, the embodiments of the present application provide a solid state disk adopting a multi-master control configuration, which is beneficial to improve the performance and reliability of the solid state disk.

[0047] Figure 2 A structural block diagram of a solid state disk is shown.

[0048] As shown in the figure, the solid state disk 200 includes a mainboard 210 and a plurality of controllers 220 (such as a controller A and a controller B as shown in the figure). Figure 2 Figure 2 The plurality of controllers 220 are electrically connected with a plurality of flash memory particles 231.

[0049] The plurality of controllers 220 can be arranged on the mainboard 210.

[0050] The plurality of flash memory particles 231 can be arranged on the mainboard 210.

[0051] ​​The plurality of controllers 220 are electrically connected with the plurality of flash memory dies 231. It can be understood that the plurality of controllers 220 can communicate with the plurality of flash memory dies 231.

[0052] Specifically, each of the plurality of controllers 220 is electrically connected with at least one of the plurality of flash memory dies 231.

[0053] Optionally, each of the plurality of controllers 220 can be electrically connected with all of the plurality of flash memory dies 231.

[0054] The flash memory die 231 can be used to store data. The controller 220 can be used to control, manage and / or drive the flash memory die 231. That is, the controller 220 can be used to control, manage and / or drive the flash memory die 231 with which the controller 220 has an electrical connection relationship. For the convenience of description, in the embodiments of the present application, the description of the electrical connection relationship is omitted. The control, management and / or driving of the flash memory die 231 by the controller 220 is simply referred to as the management of the flash memory die 231 by the controller 220.

[0055] Optionally, the plurality of controllers 220 can be used to control the data operation of the plurality of flash memory dies 231.

[0056] Exemplarily, taking one controller 220 and one flash memory die 231 as an example, the controller 220 can be used to control the data operation of the flash memory die 231, which can include that the controller 220 can be used to read data from the flash memory die 231 and / or write data into the flash memory die 231. For example, the controller 220 can receive a data read / write request, i.e. an IO request, from an external device, and perform the data read / write of the flash memory die 231 according to the IO request.

[0057] The mainboard 210 can also be replaced by a master control board. The controller 220 can also be replaced by a master control chip.

[0058] The flash memory die 231 can be understood as a die.

[0059] Figure 3 A schematic block diagram of a flash memory chip (chip) of an embodiment of the present application is shown. One die can include one or more planes. One or more dies can be packaged as one chip, i.e. one package. That is, one flash memory chip can include one or more flash memory dies. For example, as shown in Figure 3 two planes (plane1 and plane2) are integrated into one die, and multiple dies (die1 and die2) are packaged as one chip.

[0060] One flash chip can include one or more flash dies, and thus, in some possible understandings, the flash die 231 in the embodiments of the present application can also be replaced by a flash chip.

[0061] In addition, as mentioned above, the plurality of controllers 220 can be used to control data operations of the plurality of flash dies 231. Illustratively, the management of the flash dies 231 by the controller 220 can be in a basic granularity of flash die. For example, the flash chip #1 includes the flash die #1 and the flash die #2. The controller A can be used to control writing data to the flash die #1, and / or, reading data from the flash die #1. Alternatively, the management of the flash dies 231 by the controller 220 can be in a basic granularity of flash chip. For example, the flash chip #1 includes the flash die #1 and the flash die #2. The controller A can be used to control writing data to the flash chip #1, and / or, reading data from the flash chip #1. That is, in this case, the controller A can be used to write data to the flash die #1 and the flash die #2, but cannot control to write data to a specific flash die; the controller A can be used to read data from the flash die #1 and the flash die #2, but cannot control to read data from a specific flash die.

[0062] The plurality of flash dies 231 can be the same flash dies, or different flash dies.

[0063] Optionally, the plurality of flash dies 231 can be the same type of flash dies.

[0064] Illustratively, the type of flash die can include single-level cell (SLC), multi-level cell (MLC), trinary-level cell (TLC), and quad-level cell (QLC), etc. TLC is 3 bits / cell, and QLC is 4 bits / cell, which is a multi-value storage mode of 3-dimensional (3D) NAND.

[0065] For example, the plurality of flash dies 231 can all be TLC flash dies.

[0066] For another example, the plurality of flash dies 231 can all be QLC flash dies.

[0067] Optionally, the plurality of flash dies 231 can include different types of flash dies.

[0068] For example, the plurality of flash dies 231 can include TLC flash dies and QLC flash dies.

[0069] Different types of flash memory chips differ in performance, capacity, and other aspects. Using multiple types of flash memory chips is beneficial for creating SSDs that meet different performance and / or capacity requirements, and enables collaborative data storage of multiple types of flash memory chips.

[0070] Optionally, the plurality of flash memory chips 231 can be flash memory chips of the same generation.

[0071] For example, the plurality of flash memory chips 231 may have the same number of layers. The number of layers of a flash memory chip refers to the number of storage cells of the 3D NAND flash memory chips stacked in the vertical direction.

[0072] For example, each of the plurality of flash memory chips 231 may have 128 layers.

[0073] Optionally, the plurality of flash memory chips 231 may include flash memory chips of different generations.

[0074] For example, the plurality of flash memory chips 231 may include flash memory chips with different numbers of layers.

[0075] For example, some of the flash memory chips 231 have 128 layers, and some have 232 layers.

[0076] Different generations of flash memory chips differ in performance, capacity, and other aspects. Using multiple generations of flash memory chips is beneficial for creating SSDs that meet different performance and / or capacity requirements, enabling collaborative data storage across multiple generations of flash memory chips. Optionally, the multiple controllers 220 can be the same controller.

[0077] Alternatively, the plurality of controllers 220 may include different controllers.

[0078] Different controllers may support different types of flash memory chips. For example, controller T1 can support MLC and QLC flash memory chips, while controller T2 can support TLC and QLC flash memory chips.

[0079] Different controllers can support more types of flash memory chips, allowing for more flexible selection of flash memory chips during SSD design to meet different needs and achieve collaborative data storage of multiple types of flash memory chips.

[0080] Furthermore, different controllers may vary in cost, performance, and generation. Combining different controllers can help meet different requirements for SSD cost or control performance, thus increasing the flexibility of SSD design.

[0081] The management of the storage medium by the plurality of controllers 220 can be implemented in various manners.

[0082] Optionally, a first group of flash memory chips in the plurality of flash memory chips 231 is assigned to a first controller in the plurality of controllers 220, and a second group of flash memory chips in the plurality of flash memory chips 231 is assigned to a second controller in the plurality of controllers 220.

[0083] That is, the first controller and the second controller manage part of the plurality of flash memory chips respectively.

[0084] The "first group of flash memory chips" and the "second group of flash memory chips" are different flash memory chips. For example, the two groups of flash memory chips do not include the same flash memory chip.

[0085] The "first" and "second" in the "first group of flash memory chips" and the "second group of flash memory chips" are only used to distinguish the two groups of flash memory chips, and have no other limiting effect. The first group of flash memory chips and the second group of flash memory chips can be any two groups of flash memory chips in the plurality of flash memory chips 231.

[0086] The "first" and "second" in the "first controller" and the "second controller" are only used to distinguish the two controllers, and have no other limiting effect. The first controller and the second controller can be any two controllers in the plurality of controllers 220.

[0087] For example, each controller 220 in the plurality of controllers 220 can manage part of the plurality of flash memory chips respectively.

[0088] Optionally, the first controller or the second controller in the plurality of controllers 220 is used to manage all of the plurality of flash memory chips.

[0089] For example, any controller 220 in the plurality of controllers 220 can manage all of the plurality of flash memory chips.

[0090] The following will be described by taking two management modes (mode 1 and mode 2) as examples.

[0091] Mode 1: independent management.

[0092] One controller 220 can independently manage the flash memory chips 231.

[0093] For example, one controller 220 can independently manage part of the plurality of flash memory chips 231.

[0094] "Independent management" can be understood in the following way. If a certain controller 220 independently manages a group of flash memory particles 231, other controllers 220 are irrelevant to the group of flash memory particles 231, or in other words, the other controllers 220 manage other flash memory particles 231 other than the group of flash memory particles 231.

[0095] Optionally, a first group of flash memory particles in the plurality of flash memory particles 231 is allocated to a first controller in the plurality of controllers 220, and a second group of flash memory particles in the plurality of flash memory particles 231 is allocated to a second controller in the plurality of controllers 220. The first controller can be used to independently manage the first group of flash memory particles, and the second controller can be used to independently manage the second group of flash memory particles.

[0096] The following exemplary describes the processing flow of IO requests of controllers in the independent management mode.

[0097] An external device, for example, a host, issues an IO request to a controller in the independent management mode, requesting to write data. The controller determines an idle flash memory particle from the flash memory particles managed by itself after receiving the IO request, and writes the data into the flash memory particle.

[0098] Further, the external device can establish a mapping table between the controllers and the data. The mapping table is used to indicate the correspondence between the controllers and the data. A certain data has a correspondence with a certain controller, which means that the data is stored in the flash memory particles managed by the controller. If the external device needs to read the data, it can determine the controller corresponding to the data according to the mapping table, and issue an IO request to the controller, requesting to read the data. The controller can read the data from the corresponding flash memory particle.

[0099] The following exemplary describes the processing flow of IO requests of controllers in the independent management mode. Figure 2 The following exemplary describes the processing flow of IO requests of controllers in the independent management mode.

[0100] An external device, such as a host, sends an I / O request to controller A, requesting to write data A to the SSD. Upon receiving the I / O request, controller A determines a free flash memory chip from the 24 flash memory chips managed by controller A (e.g., flash memory chip A), identifies an available address, and stores data A on flash memory chip A. An external device, such as a host, sends an I / O request to controller B, requesting to write data B to the SSD. Upon receiving the I / O request, controller B determines a free flash memory chip from the 24 flash memory chips managed by controller B (e.g., flash memory chip B), identifies an available address, and stores data B on flash memory chip B.

[0101] The host can establish a mapping table between the controller and the data. For example, data A corresponds to controller A, and data B corresponds to controller B. If the host needs to read data A, it can determine from the mapping table that data A corresponds to controller A, send an I / O request to controller A to read data A, and controller A can read data A from the corresponding flash memory chip. If the host needs to read data B, it can determine from the mapping table that data B corresponds to controller B, send an I / O request to controller B to read data B, and controller B can read data B from the corresponding flash memory chip.

[0102] As a possible example, the multiple controllers 220 can independently manage a portion of the multiple flash memory chips 231.

[0103] Specifically, the plurality of controllers 220 can be used to independently control the data operations of some of the plurality of flash memory chips 231.

[0104] Each of the plurality of controllers 220 can independently manage a portion of the plurality of flash memory chips 231.

[0105] For example, there are N controllers 220. N is an integer greater than 1. The multiple flash memory chips 231 are divided into N groups, each group containing at least one flash memory chip 231. The flash memory chips in each group are different. Each controller 220 manages one of the N groups.

[0106] In this case, the management of flash memory chips 231 by each controller 220 is independent of each other. The number of flash memory chips 231 independently managed by each controller 220 can be the same or different.

[0107] Furthermore, when the plurality of flash memory chips 231 include different types of flash memory chips, the flash memory chips 231 managed independently by the plurality of controllers 220 can be determined based on the type of the plurality of flash memory chips 231.

[0108] For example, if the number of the plurality of controllers 220 is greater than or equal to the number of types of the plurality of flash memory chips 231, each of the plurality of controllers 220 can independently manage one or more types of flash memory chips 231 among the plurality of flash memory chips 231.

[0109] by Figure 2 Taking controller A and controller B as examples, if the multiple flash memory chips 231 include TLC flash memory chips and QLC flash memory chips, controller A can independently manage TLC flash memory chips, and controller B can independently manage QLC flash memory chips.

[0110] It should be understood that the above are merely examples and do not constitute a limitation on the solutions of this application. When the plurality of flash memory chips 231 include different types of flash memory chips, the controller's management of the flash memory chips can also be based on other factors. For example, based on the principle of proximity control, the controller 220 can independently manage the flash memory chips located near itself.

[0111] Furthermore, when the plurality of flash memory chips 231 include flash memory chips of different generations, the flash memory chips 231 managed independently by the plurality of controllers 220 can be determined based on the generation of the plurality of flash memory chips 231.

[0112] For example, if the number of the plurality of controllers 220 is greater than or equal to the number of generations of the plurality of flash memory chips 231, each of the plurality of controllers 220 can independently manage one or more generations of flash memory chips 231.

[0113] by Figure 2 Taking controller A and controller B as examples, if the multiple flash memory chips 231 include TLC flash memory chips and QLC flash memory chips, controller A can independently manage flash memory chips 231 with 128 layers, and controller B can independently manage flash memory chips 231 with 232 layers.

[0114] It should be understood that the above are merely examples and do not constitute a limitation on the solutions of the embodiments of this application. When the plurality of flash memory chips 231 include flash memory chips of different generations, the management of the flash memory chips 231 by the controller 220 can also be based on other factors. For example, based on the principle of proximity control, the controller 220 can independently manage the flash memory chips 231 located near itself.

[0115] Mode 2: Collaborative Management.

[0116] One controller 220 can work with other controllers 220 to manage some or all of the multiple flash memory chips 231.

[0117] "Collaborative management" can be understood as follows: if two controllers 220 collaboratively manage a group of flash memory chips 231, then both controllers 220 can control the data operations of the group of flash memory chips 231.

[0118] Optionally, the first controller and the second controller in the plurality of controllers 220 are both used to manage all the flash memory chips in the plurality of flash memory chips.

[0119] by Figure 2 For example, controller A and controller B can be considered as the first and second controllers, respectively. Controller A and controller B work together to manage the 48 flash memory chips; that is, controller A can manage the 48 flash memory chips, and controller B can also manage the 48 flash memory chips.

[0120] Optionally, the first controller and the second controller in the plurality of controllers 220 are both used to manage the same portion of the flash memory chips in the plurality of flash memory chips.

[0121] by Figure 2 For example, controller A and controller B can be considered as the first controller and the second controller, respectively. If controller A and controller B work together to manage 24 flash memory chips, that is, controller A can manage the 24 flash memory chips, and controller B can also manage the 24 flash memory chips.

[0122] The following is an example of how a controller in collaborative management mode processes IO requests.

[0123] Example 1:

[0124] In Example 1, an external device can select the controller to perform the IO request from among multiple controllers in cooperative management mode, or in other words, the external device can determine which controller to send the IO request to.

[0125] For example, an external device can obtain the task queue information of multiple controllers in collaborative management mode and determine the controller to execute the I / O request based on the length of the task queue. For instance, the external device can send the I / O request to the controller with the shortest current task queue.

[0126] For example, after receiving an I / O request, if the I / O request indicates data storage, the controller can determine a free flash memory chip from its managed flash memory chips and write the data into that flash memory chip. As another example, after receiving an I / O request, if the I / O request indicates data reading, the controller can read the data from the corresponding flash memory chip.

[0127] It should be understood that the above is merely an example, and the selection of a controller by an external device can also be random. That is, the external device can randomly determine the controller used to perform I / O requests.

[0128] Example 2:

[0129] In Example 2, an interaction channel can be established between multiple controllers in cooperative management mode. The controllers in cooperative management mode independently determine which controller is used to execute I / O requests. In this case, from the perspective of an external device, the multiple controllers in cooperative management mode can logically be regarded as a single controller.

[0130] For example, multiple controllers in collaborative management mode can determine which controller will execute an I / O request based on the length of the task queue. For instance, the I / O request might be executed by the controller with the shortest current task queue.

[0131] For example, after receiving an I / O request, the controller can determine the controller to execute the I / O request based on the length of the task queue, and send the I / O request to that controller.

[0132] The following is based on Figure 2 Let's illustrate the I / O request processing flow with an example. Controller A and Controller B can be considered as the first and second controllers, respectively. Controller A and Controller B operate in a collaborative management mode. For instance, Controller A and Controller B collaboratively manage these 48 flash memory chips.

[0133] Taking Example 1 as an example, in a scenario requiring data writing, if the length of the task queue of controller A is less than or equal to the length of the task queue of controller B, the host can send an IO request to controller A to write data A to the SSD. Upon receiving the IO request, controller A determines a free flash memory chip from its 48 flash memory chips (e.g., flash memory chip A), identifies an available address, and stores data A on flash memory chip A. In a scenario requiring data reading, if the length of the task queue of controller B is less than or equal to the length of the task queue of controller A, the host can send an IO request to controller B to read data A from the SSD. Controller B can then read data A from the corresponding flash memory chip.

[0134] External devices can also randomly select a controller. That is, the external device can randomly determine the controller to execute the I / O request. For example, in a scenario where data needs to be written, the host can randomly send an I / O request to controller A or controller B, requesting to write data A to the SSD. The controller receiving the I / O request can determine a free flash memory chip from 48 flash memory chips, for example, flash memory chip A, determine the available address, and store data A on flash memory chip A. Similarly, in a scenario where data needs to be read, the host can randomly send an I / O request to controller A or controller B, requesting to read data A from the SSD. The controller receiving the I / O request can read data A from the corresponding flash memory chip.

[0135] Taking Example 2 as an example, in a scenario requiring data writing, the host can issue an IO request to the SSD to write data A. Controller A receives this IO request. If the current length of Controller A's task queue is less than or equal to the length of Controller B's task queue, Controller A can determine a free flash memory chip from the 48 flash memory chips, for example, flash memory chip A, identify an available address, and store data A on flash memory chip A. In a scenario requiring data reading, the host can issue an IO request to the SSD to read data A from the SSD. Controller A receives this IO request. If the current length of Controller B's task queue is less than or equal to the length of Controller A's task queue, Controller B can read data A from the corresponding flash memory chip.

[0136] As a possible example, the multiple controllers 220 employ a collaborative mechanism to manage all of the multiple flash memory chips 231, that is, the multiple controllers 220 collaboratively manage the multiple flash memory chips 231.

[0137] Specifically, the multiple controllers 220 can be used to coordinate the data operations of the multiple flash memory chips 231.

[0138] In Mode 2, multiple controllers work together to manage multiple flash memory chips, which is beneficial for achieving high-efficiency operation and high performance of the flash memory chips.

[0139] For example, Mode 1 and Mode 2 can also be used in combination.

[0140] For example, there are N controllers 220. There are M flash memory chips 231. Of the N controllers 220, n controllers 220 manage m flash memory chips 231 out of the M flash memory chips 231 using mode 1, and the remaining Nn controllers 220 manage Mm flash memory chips 231 out of the M flash memory chips using mode 2. N is an integer greater than 1. M is an integer greater than 1. n is a positive integer less than N. m is a positive integer less than M.

[0141] As one possible implementation, the multiple controllers 220 can manage the multiple flash memory chips 231 based on a "dual-active" mechanism.

[0142] The "dual-active" mechanism refers to the fact that the multiple controllers 220 are not simply stacked, but rather that there is a linkage management mechanism between these multiple controllers 220, which can deal with the problem of disk failure caused by controller failure. Even in extreme cases where only one controller is working normally, the availability of the entire disk can be maintained.

[0143] Optionally, in the event of a failure of the first controller, the second controller takes over the operations that were originally performed by the first controller.

[0144] In other words, if one of the multiple controllers 220 (such as the first controller) fails, the other controllers 220 (such as the second controller) can take over the flash memory chips 231 managed by the failed controller 220 before the failure, that is, take over the control, management and / or drive tasks of the failed controller 220 on the flash memory chips 231.

[0145] It should be understood that in some cases, multiple controllers may fail simultaneously, and all of these multiple controllers 220 that fail simultaneously can be regarded as the first controller.

[0146] It should be understood that in some cases, when a controller fails, multiple controllers may take over the flash memory chips managed by that controller. Any controller that takes over the flash memory chips managed by that controller can be regarded as a second controller.

[0147] The management mode of the flash memory chips by the taking over controller and the faulty controller can be the same or different.

[0148] The management modes of the flash memory chips by the taking over controller and the faulty controller can be related or unrelated.

[0149] For example, before the failure, the faulty controller could manage the flash memory chips in either Mode 1 or Mode 2. For example, after the failure, the taking over controller could manage the flash memory chips in either Mode 1 or Mode 2.

[0150] Taking the faulty controller as an example (e.g., controller #1), before the fault occurred, controller #1 could independently manage flash memory chip #1 and flash memory chip #2. After the fault occurred, controller #2 can independently manage flash memory chip #1 and flash memory chip #2. Alternatively, controller #3 and controller #4 can each independently manage flash memory chip #1 and flash memory chip #2. Alternatively, controller #5 and controller #6 can collaboratively manage flash memory chip #11 and flash memory chip #12.

[0151] Taking a faulty controller (e.g., controller #1) as an example, before the fault occurred, controller #1 could collaboratively manage flash memory chips #1 and #2 with controller #2. After the fault occurred, controller #3 could collaboratively manage flash memory chips #1 and #2 with controller #2. Alternatively, controller #4 could independently manage flash memory chips #1 and #2. Alternatively, controller #5 and controller #6 could collaboratively manage flash memory chips #1 and #2. Controller #7 and controller #8 could each independently manage flash memory chips #1 and #2.

[0152] Taking two controllers (e.g., controller #1 and controller #2) as an example, before the failure, controller #1 could independently manage flash memory chips #1 and #2. Before the failure, controller #2 could independently manage flash memory chips #3 and #4. After the failure, controller #3 can independently manage flash memory chips #21, #22, #23, and #24. Alternatively, controllers #4 and #5 can each independently manage a portion of flash memory chips #21, #22, #23, and #24. Alternatively, controllers #6 and #7 can collaboratively manage flash memory chips #21, #22, #23, and #24.

[0153] It should be understood that the above are merely examples and do not constitute a limitation on the solutions of the embodiments of this application. The management of the plurality of flash memory chips 231 by the plurality of controllers 220 can also be carried out in other ways. For example, one controller 220 can independently manage all the flash memory chips 231, i.e., the other controllers 220 are in an idle state. When the controller 220 fails, other controllers take over the operations originally performed by the controller 220.

[0154] In this way, if one of the multiple controllers fails, the other controllers can take over its tasks in a timely manner to maintain the normal operation of the SSD, thereby helping to ensure the reliability of the SSD.

[0155] Furthermore, the management mode of the multiple controllers 220 for the multiple flash memory chips 231 can be switched as needed.

[0156] Optionally, the plurality of controllers 220 can receive control instructions for instructing adjustment of the management mode. That is, the instructions are used to instruct the plurality of controllers 220 to adjust the mode in which they control the data operations of the plurality of flash memory chips 231.

[0157] For example, a mapping relationship exists between multiple control commands and multiple management modes. The user inputs the corresponding control command to select the desired management mode. After receiving the control command, the multiple controllers 220 adjust the management mode to the management mode indicated by the control command.

[0158] For example, the multiple controllers 220 can receive control commands from external devices. That is, the user can input control commands through external devices. For instance, the control command could instruct the first and second controllers to switch from an independent management mode to a collaborative management mode. Alternatively, the controller command could instruct the first and second controllers to switch from a collaborative management mode to an independent management mode.

[0159] Furthermore, this application embodiment also provides a user interface. This user interface can be used in conjunction with the switching operation of management mode.

[0160] Optionally, the user interface can be used to display multiple candidate management modes, i.e., multiple management modes to choose from.

[0161] For example, the user interface can display the current management mode and other available management modes for the user to choose from.

[0162] Users can select the desired management mode on the user interface. The multiple controllers 220 acquire the control command corresponding to the user's selection and adjust the management mode to the mode indicated by the control command.

[0163] For example, the user interface can be provided through the display unit of an external device. The external device can send control commands to the plurality of controllers 220 based on the user's selection. After receiving the control commands from the external device, the plurality of controllers 220 adjust their management mode to the management mode indicated by the control commands.

[0164] The distribution of the multiple controllers 220 is illustrated below.

[0165] In one possible implementation, the plurality of controllers 220 are distributed on one side of the region where the plurality of flash memory chips 231 are located.

[0166] Alternatively, the multiple flash memory chips 231 are distributed in storage area #1, and the multiple controllers 220 are distributed on one side of storage area #1.

[0167] like Figure 2 As shown, the area where the multiple flash memory chips 231 are located is storage area #1. Figure 4 The two controllers are located on the same side of storage area #1.

[0168] In one possible implementation, the plurality of controllers 220 are distributed at least on both sides of the region where the plurality of flash memory chips 231 are located.

[0169] Alternatively, some or all of the multiple flash memory chips 231 are distributed in storage area #2, and some or all of the multiple controllers 220 are distributed on both sides of storage area #2.

[0170] Figure 4 A schematic diagram of another SSD structure according to an embodiment of this application is shown.

[0171] For example, all of the plurality of flash memory chips 231 are distributed in storage area #2, and the plurality of controllers 220 are distributed on both sides of storage area #2.

[0172] For example, such as Figure 4 As shown in (a), the plurality of flash memory chips 231 are distributed in storage region A (an example of storage region #2). Figure 4 In (a), two controllers 220 are located on one side of storage area A, and two other controllers 220 are located on the opposite side of storage area A.

[0173] For example, such as Figure 4 As shown in (b), the plurality of flash memory chips 231 are distributed in storage region A and storage region B. Figure 4 In (b), the two controllers 220 are located on one side of storage area A, and the two controllers 220 are located on the opposite side of storage area A. In other words, Figure 5 In (b), the two controllers 220 are located on one side of storage region B, and the two controllers 220 are located on the opposite side of storage region B. Storage region A or storage region B can both be considered as an example of storage region #2.

[0174] In this way, compared to placing multiple controllers on the same side of the storage area, this solution is beneficial for arranging the controller and flash memory chips close together, reducing the number of threads between the controller and flash memory chips. For example, when the controller independently controls the flash memory chips, this solution is beneficial for the controller to manage the flash memory chips close together, thereby improving the performance of the SSD.

[0175] Meanwhile, compared to placing multiple controllers on the same side of the storage area, this solution increases the distribution of controllers, which is beneficial for making better use of space and increasing the number of controllers, thereby further improving the performance and reliability of SSDs.

[0176] According to the embodiments of this application, using a configuration of multiple controllers in an SSD is beneficial for improving overall control performance, thereby enhancing the overall performance of the SSD. For example, it improves the overall read and write performance of the SSD, enabling high-performance read and write operations. For instance, the multiple controllers can achieve coordinated control of multiple flash memory chips, thereby improving the overall performance of the SSD. Furthermore, the multiple controllers can independently control a portion of the flash memory chips, meaning that one controller does not need to manage all the flash memory chips, avoiding the impact of insufficient performance of a single controller on the overall performance of the SSD, thus contributing to improved overall SSD performance.

[0177] Meanwhile, employing multiple controllers in an SSD configuration allows other controllers to continue functioning normally even if some fail, helping to prevent complete SSD failure and thus improving SSD reliability. For example, a "dual-active" mechanism can be established among these controllers, ensuring continued SSD operation even if some fail. Furthermore, these controllers can coordinate the control of multiple flash memory chips, supporting redundancy protection and further enhancing SSD reliability. Alternatively, each controller can independently control a portion of the flash memory chips; if one controller fails, others can still manage those chips, preventing complete SSD failure and improving reliability while reducing repair costs.

[0178] Figure 5 A schematic block diagram illustrating the structure of another solid-state drive provided in an embodiment of this application is shown.

[0179] Furthermore, the solid-state drive 200 may include one or more storage modules 230. Each storage module 230 includes at least one flash memory chip from the plurality of flash memory chips 231. At least one storage module 230 is detachably connected to the motherboard 210.

[0180] Storage module 230, also known as flash memory module, is a storage medium with flash memory chips mounted on it.

[0181] The removable storage module 230 can be understood as a removable, independent unit on the motherboard that includes one or more flash memory chips.

[0182] The storage module 230 is detachably connected to the motherboard 210, meaning that the storage module 230 is detachably connected to the motherboard 210.

[0183] Furthermore, such as Figure 5 As shown, the solid-state drive 200 may further include one or more storage interfaces 240 disposed on the motherboard 210. The plurality of controllers 220 are electrically connected to the one or more storage interfaces 240. The at least one storage module 230 is detachably connected to the one or more storage interfaces 240.

[0184] The plurality of controllers 220 are electrically connected to the one or more storage interfaces 240, which may be that the plurality of controllers 220 are electrically connected to at least one of the one or more storage interfaces 240.

[0185] Optionally, each of the plurality of controllers 220 may be electrically connected to all of the one or more storage interfaces 240.

[0186] Storage interface 240, also known as flash memory interface or storage module interface, is used to connect storage modules.

[0187] For example, the number of storage interfaces 240 can be 2, 4, 6, or 8.

[0188] Each storage interface 240 can be used to connect one storage module 230. The number of storage interfaces 240 is greater than or equal to the number of removable storage modules 230.

[0189] For example, the storage module 230 and the storage interface 240 can be a pluggable connection. The storage module 230 can also be referred to as a pluggable storage module 230. The storage module 230 is installed on the motherboard 210 by inserting it into the storage interface 240, and correspondingly, the flash memory chip 231 on the storage module 230 is mounted on the motherboard 210 via the storage module 230. The storage module 230 is separated from the motherboard 210 by removing it from the storage interface 240.

[0190] For example, a connector adapted to the storage interface 240 can be provided on the storage module 230. The connector on the storage module 230 is electrically connected to the flash memory chip 231 on the storage module 230. The storage module can be inserted into the storage interface 240 via the connector on the storage module 230.

[0191] A controller 220 can be electrically connected to a removable storage strip 230 via a storage interface 240. This storage interface 240 is the storage interface electrically connected to the controller 220; for ease of description, it will not be repeated hereafter. The storage strip 230 is the storage strip 230 connected to the storage interface 240; for ease of description, it will not be repeated hereafter.

[0192] Alternatively, the controller 220 can communicate with the removable memory module 230 via the storage interface 240. Alternatively, the controller 220 can establish an electrical connection with the flash memory chips 231 within the memory module 230 via the storage interface 240. Alternatively, the controller 220 can communicate with the flash memory chips 231 within the memory module 230 via the storage interface 240.

[0193] The one or more storage interfaces 240 can be implemented based on various types of communication protocols.

[0194] For example, the one or more storage interfaces 240 may include at least one of the following: an open NAND flash interface (ONFI) or a Toggle storage interface.

[0195] It should be understood that the above are merely examples, and other storage interface standards applicable to the controller and flash memory chips are also applicable to the solutions in the embodiments of this application.

[0196] Optionally, the motherboard 210 may include one or more memory module mounting structures 211. The memory module mounting structure 211 is an interface connection structure. The one or more memory interfaces 240 are located on the one or more memory module mounting structures 211.

[0197] For example, multiple storage interfaces 240 based on ONFI or Toggle bus can be set on the storage strip mounting structure 211.

[0198] The storage module mounting structure 211 can also be called the flash memory module mounting structure.

[0199] Taking a motherboard 210 including a memory module mounting structure 211 as an example, the memory module mounting structure 211 can be located in the middle of the motherboard 210.

[0200] For example, such as Figure 6 As shown, the memory module mounting structure 211 is located in the middle of the motherboard 210, and multiple memory modules 230 are distributed on both sides of the memory module mounting structure 211.

[0201] Taking the motherboard 210 as an example, which includes two memory module mounting structures 211, the two memory module mounting structures 211 are respectively disposed at the top and bottom of the motherboard 210.

[0202] For example, such as Figure 5 As shown, two memory module mounting structures 211 are arranged in parallel at the top and bottom of the motherboard 210. The plurality of memory modules 230 are distributed between the two memory module mounting structures 211.

[0203] It should be understood that the above is only an example, and the storage strip mounting structure 211 can also be located in other locations. This application embodiment does not limit this.

[0204] The positional relationship between the multiple controllers 220 and the storage strip mounting structure 211 is illustrated below.

[0205] In one possible implementation, the plurality of controllers 220 can be distributed at one end of the one or more storage strip mounting structures 211, for example, as Figure 6 or Figure 7 As shown.

[0206] In one possible implementation, the plurality of controllers 220 may be distributed at both ends of the one or more storage strip mounting structures 211.

[0207] For example, such as Figure 5 As shown, the multiple controllers 220 are distributed at opposite ends of the storage strip mounting structure 211.

[0208] In this way, compared to setting multiple controllers on the same end of the storage module mounting structure, this solution is conducive to the close arrangement of controllers and flash memory chips, reducing the threads between controllers and flash memory chips. For example, in scenarios where the controller independently manages the flash memory chips, the controller can manage the flash memory chips nearby, which is beneficial to improving the performance of SSD.

[0209] Furthermore, compared to placing multiple controllers on the same end of the storage module mounting structure, this approach increases the distribution of controllers, which is beneficial for making better use of space and increasing the number of controllers, thereby further improving the performance and reliability of SSDs.

[0210] When the multiple flash memory chips 231 are disposed in multiple storage modules 230, the number of flash memory chips 231 on different storage modules 230 can be the same or different.

[0211] Optionally, when the multiple flash memory chips 231 are disposed in multiple storage modules 230, the types of flash memory chips 231 on different storage modules 230 can be different.

[0212] For example, the flash memory chip 231 on one storage module 230 is a TLC flash memory chip, and the flash memory chip 231 on the other storage module 230 is a QLC flash memory chip.

[0213] Alternatively, when the multiple flash memory chips 231 are disposed in multiple memory modules 230, the flash memory chips 231 on different memory modules 230 are of the same type.

[0214] When a storage module 230 includes multiple flash memory chips 231, the different flash memory chips 231 in the storage module 230 may be of the same type or different types.

[0215] In this embodiment, enabling the mounting capability of multiple types of flash memory chips allows for collaborative data storage across these types, facilitating the creation of SSDs that meet diverse performance and / or capacity requirements. The detachable connection method allows for more flexible flash memory chip configuration. Users can select the appropriate type of flash memory chip to obtain an SSD that meets their needs, thus improving the user experience.

[0216] When the multiple flash memory chips 231 are disposed in multiple memory modules 230, the generation of the flash memory chips 231 on different memory modules 230 can be the same or different.

[0217] Optionally, when the multiple flash memory chips 231 are disposed in multiple storage modules 230, the number of layers of flash memory chips 231 on different storage modules 230 may be different.

[0218] For example, the flash memory chip 231 on one storage module 230 is a 128-layer flash memory chip, and the flash memory chip 231 on another storage module 230 is a 232-layer flash memory chip.

[0219] Alternatively, when the multiple flash memory chips 231 are disposed in multiple storage modules 230, the number of layers of flash memory chips 231 on different storage modules 230 can be the same.

[0220] In the case where a storage module 230 includes multiple flash memory chips 231, the multiple flash memory chips 231 may be of the same generation or different generations.

[0221] For example, when a storage bar 230 includes multiple flash memory chips 231, the different flash memory chips 231 in the storage bar 230 may have the same or different number of layers.

[0222] In this embodiment, enabling the mounting capability of multiple generations of flash memory chips allows for collaborative data storage across these generations, facilitating the creation of SSDs that meet diverse performance and / or capacity requirements. The detachable connection method allows for more flexible flash memory chip configuration. Users can select the appropriate generation of flash memory chips to obtain an SSD that meets their needs, thus improving the user experience.

[0223] Furthermore, it can provide users with relevant information about the storage bar.

[0224] For example, the user interface can be used to display relevant information about the storage module. For instance, the relevant information about the storage module may include at least one of the following: the storage capacity of the storage module, the number of flash memory chips on the storage module, the model of the flash memory chips on the storage module, the storage capacity of the flash memory chips on the storage module, the performance of the flash memory chips on the storage module, the type of flash memory chips on the storage module, or the number of layers of flash memory chips on the storage module.

[0225] Optionally, the user interface can be used to display multiple candidate management modes, i.e., multiple management modes to choose from.

[0226] Furthermore, prompts can be provided to users to remind them to replace the storage module.

[0227] For example, when a memory module fails, at least one of the multiple controllers 220 can display a prompt message through the user interface to prompt the user to replace the memory module.

[0228] Furthermore, prompts can be provided to users to remind them to replace the controller.

[0229] For example, when a memory module malfunctions, at least one of the multiple controllers 220 can display a prompt message through the user interface to prompt the user to replace the controller.

[0230] As the number of flash memory chips on an SSD increases, the likelihood of flash memory chip failure also increases, and the probability of SSD failure due to flash memory chip failure also increases.

[0231] In the solution of this application embodiment, the storage module is connected to the motherboard in a detachable manner, which helps to improve the reliability of the SSD. Specifically, when the flash memory chip fails, it can be disassembled and replaced as a basic unit, avoiding the failure of the entire SSD due to flash memory chip failure and reducing the cost of fault repair.

[0232] Meanwhile, the storage module connects to the motherboard in a detachable manner, which allows for flexible adjustment of the SSD's capacity. For example, by replacing the current storage module with one having a larger or smaller capacity, the SSD's capacity can be expanded or reduced online. The capacity of a storage module can be understood as the total capacity of all the flash memory chips on that module.

[0233] Further, optionally, at least one of the plurality of controllers 220 is detachably mounted on the motherboard 210.

[0234] For example, the motherboard 210 may also include at least one controller slot, into which a control component containing the at least one controller 220 can be plugged and detached. That is, the controller is mounted on the motherboard by inserting the control component containing the controller into the controller slot, and the controller is detached from the motherboard by removing the control component containing the controller from the controller slot.

[0235] This helps reduce the difficulty of replacing the controller. For example, it makes it easier to replace the controller when it fails, thereby reducing the cost of troubleshooting.

[0236] The following is combined with Figure 5 The solutions of the embodiments of this application are described by way of example.

[0237] like Figure 5 As shown, the SSD includes a motherboard 210 and multiple controllers 220 mounted on the motherboard 210 (such as...). Figure 5 Controllers A and B) and a removable storage strip 230 based on the storage strip mounting structure 211 (e.g., controllers A and B) and a storage strip 230 based on the storage strip mounting structure 211. Figure 5 (8 memory modules). The memory module mounting structure 211 can be located in the middle of the motherboard 210. Multiple memory interfaces 240 based on ONFI or Toggle buses (such as...) can be configured on the memory module mounting structure 211. Figure 5 (The eight storage interfaces shown). The multiple controllers 220 can be distributed at one end of the storage strip mounting structure 211. Each controller 220 can be electrically connected to the multiple storage interfaces 240 respectively.

[0238] Each storage module 230 can be equipped with multiple flash memory chips 231 (e.g., ...). Figure 5 (Six flash memory chips are shown). The flash memory chips 231 on the storage module 230 can be connected to the motherboard through the storage interface 240 to realize communication between the flash memory chips 231 and the multiple controllers 220.

[0239] The following is about Figure 7 to Figure 9 The management modes of the multiple controllers 220 in the example are illustrated.

[0240] In Mode 1, controller A and controller B each independently manage a portion of the flash memory chips. For example, controller A independently manages 24 flash memory chips, and controller B independently manages the remaining 24 flash memory chips.

[0241] In Mode 2, Controller A and Controller B work together to manage all flash memory chips.

[0242] Controller A and Controller B can establish a "dual-active" mechanism. When one controller fails, the other controller can maintain the normal operation of the SSD.

[0243] Figure 7 Schematic diagrams of three other SSD examples according to embodiments of this application are shown.

[0244] Figure 5 and Figure 7 The main difference is that, Figure 7 In the solid-state drive 200 shown, the plurality of controllers 220 are four controllers 220, namely controller A, controller B, controller C and controller D, which are distributed at both ends of the storage strip mounting structure 211.

[0245] The following is about Figure 7 The management modes of the multiple controllers 220 in the example are illustrated.

[0246] In Mode 1, controllers A, B, C, and D each independently manage a portion of the flash memory chips. For example, controllers A, B, C, and D each independently manage 12 flash memory chips.

[0247] In Mode 2, controllers A, B, C, and D work together to manage all flash memory chips.

[0248] When one of the controllers (A, B, C, and D) fails, the other controllers can maintain the normal operation of the SSD. This ensures the SSD continues to function even if up to three controllers fail simultaneously.

[0249] Figure 5 Other descriptions can be found here. Figure 8 This will not be elaborated upon here.

[0250] Figure 5 and Figure 8 The main difference is that, Figure 8 The solid-state drives shown include different types of flash memory chips. For example... Figure 8 As shown, Figure 8 In the solid-state drive 200 shown, some flash memory chips are TLC flash memory chips, and some flash memory chips are QLC flash memory chips.

[0251] The following is about Figure 8 The management modes of the multiple controllers 220 in the example are illustrated.

[0252] In Mode 1, controller A and controller B each independently manage a portion of the flash memory chips. For example, controller A independently manages 24 flash memory chips, and controller B independently manages the remaining 24 flash memory chips.

[0253] Furthermore, controller A and controller B independently manage different types of flash memory chips. For example, controller A independently manages TLC flash memory chips, and controller B independently manages QLC flash memory chips.

[0254] In Mode 2, Controller A and Controller B work together to manage all flash memory chips.

[0255] Controller A and Controller B can establish a "dual-active" mechanism. When one controller fails, the other controller can maintain the normal operation of the SSD.

[0256] Figure 5 Other descriptions can be found here. Figure 9 This will not be elaborated upon here.

[0257] Figure 5 and Figure 9 The main difference is that, Figure 9 The solid-state drives shown include flash memory chips of different generations. For example... Figure 9 As shown, Figure 9 In the solid-state drive 200 shown, some flash memory chips are layer X flash memory chips, and some flash memory chips are layer Y flash memory chips. X and Y are positive integers, and X and Y are different. For example, X is 128 and Y is 232.

[0258] The following is about Figure 9 The management modes of the multiple controllers 220 in the example are illustrated.

[0259] In Mode 1, controller A and controller B each independently manage a portion of the flash memory chips. For example, controller A independently manages 24 flash memory chips, and controller B independently manages the remaining 24 flash memory chips.

[0260] Furthermore, controller A and controller B independently manage flash memory chips of different generations. For example, controller A independently manages flash memory chips of layer X, and controller B independently manages flash memory chips of layer Y.

[0261] In Mode 2, Controller A and Controller B work together to manage all flash memory chips.

[0262] Controller A and Controller B can establish a "dual-active" mechanism. When one controller fails, the other controller can maintain the normal operation of the SSD.

[0263] Figure 5 Other descriptions can be found here. Figure 5 to Figure 9 This will not be elaborated upon here.

[0264] also, Figure 7 Some of the solutions can also be used in combination.

[0265] For example,Figure 8 and Figure 7 These solutions can be used in combination. For example, multiple controllers 220 of the solid-state drive 200 are distributed at both ends of the storage module mounting structure 211. Some flash memory chips are TLC flash memory chips, and some flash memory chips are QLC flash memory chips.

[0266] For example, Figure 9 and Figure 8 The solutions can be used in combination. Multiple controllers 220 of the solid-state drive 200 are distributed at both ends of the storage module mounting structure 211. Some flash memory chips are X-layer flash memory chips, and some are Y-layer flash memory chips.

[0267] For example, Figure 9 and Figure 2 to Figure 9 The solutions can be used in combination. Some flash memory chips are TLC flash memory chips, and some are QLC flash memory chips. Some flash memory chips are X-layer flash memory chips, and some are Y-layer flash memory chips.

[0268] The above are just examples. Other combinations of the above schemes can also be used. For details, please refer to the previous text. They will not be repeated here.

[0269] It should be understood that Figure 8 The illustrated scheme is a schematic structural diagram. The number, type, and positional relationship of the various components in the diagram are merely examples and do not constitute a limitation on the scheme of this application embodiment. For example, in other possible implementations, the solid-state drive may also include other numbers of controllers, storage interfaces, storage modules, and / or flash memory chips, etc. Furthermore, in... Figure 9 In the illustrated scheme, the TLC flash memory chips are distributed on one side of the memory module mounting structure 211. In other possible implementations, the TLC flash memory chips can also be distributed on both sides of the memory module mounting structure 211. For example, in... ​ In the illustrated scheme, the flash memory chips of the Y layer are distributed on one side of the storage module mounting structure 211. In other possible implementations, the flash memory chips of the Y layer may also be distributed on both sides of the storage module mounting structure 211. Furthermore, in other possible implementations, the solid-state drive may also include other devices and / or components.

[0270] This application also provides an electronic device. The electronic device includes any of the aforementioned solid-state drives (SSDs) and a host computer. The host computer can be used to write data to the SSD and / or read data from the SSD.

[0271] For example, an electronic device may include a terminal device. For instance, an electronic device may include a computer, a mobile phone, or a tablet computer.

[0272] The above are just examples; electronic devices can also be other electronic devices that require storage devices.

[0273] Furthermore, optionally, the electronic device may also include a display unit.

[0274] Optionally, the display unit can be used to provide a user interface, which can be used to display multiple candidate management modes, i.e. multiple selectable management modes.

[0275] For example, the user interface can display the current management mode and other available management modes for the user to choose from. The user can select the desired management mode on the user interface. Multiple controllers 220 in the solid-state drive obtain the control command corresponding to the user's selection and switch the current management mode to the management mode indicated by the control command.

[0276] Optionally, the display unit can display relevant information about the storage module. For example, the relevant information about the storage module may include at least one of the following: the storage capacity of the storage module, the number of flash memory chips on the storage module, the model of the flash memory chips on the storage module, the storage capacity of the flash memory chips on the storage module, the performance of the flash memory chips on the storage module, the type of flash memory chips on the storage module, or the number of layers of flash memory chips on the storage module.

[0277] Optionally, the display unit can display a prompt message to remind the user to replace the memory stick.

[0278] For example, when a memory module malfunctions, at least one of the multiple controllers 220 can display a prompt message through the display unit to remind the user to replace the memory module.

[0279] Optionally, the display unit can display a prompt message to remind the user to replace the controller.

[0280] For example, when a controller malfunctions, at least one of the multiple controllers 220 can display a prompt message through the display unit to remind the user to replace the controller.

[0281] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0282] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0283] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0284] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0285] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0286] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the processing methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0287] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A solid-state drive, characterized in that, include: Motherboard; Multiple controllers are mounted on the motherboard; Multiple flash memory chips are electrically connected to multiple controllers. The multiple flash memory chips are used to store data, and the multiple controllers are used to control the data operations of the multiple flash memory chips.

2. The solid-state drive according to claim 1, characterized in that, The first group of flash memory chips in the plurality of flash memory chips is assigned to the first controller in the plurality of controllers, and the second group of flash memory chips in the plurality of flash memory chips is assigned to the second controller in the plurality of controllers.

3. The solid-state drive according to claim 1, characterized in that, The first controller or the second controller in the plurality of controllers is used to manage all the flash memory chips in the plurality of flash memory chips.

4. The solid-state drive according to claim 2 or 3, characterized in that, In the event of a failure of the first controller, the second controller is used to take over the operations that were originally performed by the first controller.

5. The solid-state drive according to any one of claims 1 to 4, characterized in that, The multiple controllers are distributed on one side of the area where the multiple flash memory chips are located.

6. The solid-state drive according to any one of claims 1 to 4, characterized in that, The plurality of controllers are distributed at least on both sides of the region where the plurality of flash memory chips are located.

7. The solid-state drive according to any one of claims 1 to 6, characterized in that, The solid-state drive also includes: One or more memory modules, each memory module including at least one flash memory chip from the plurality of flash memory chips, and at least one memory module being detachably connected to the motherboard.

8. The solid-state drive according to claim 7, characterized in that, The solid-state drive includes multiple storage modules, and the flash memory chips in the different storage modules are of different types. The types of flash memory chips include at least one of the following: single-cell SLC, multi-cell MLC, three-cell TLC, or four-cell QLC.

9. The solid-state drive according to claim 7 or 8, characterized in that, The solid-state drive includes multiple storage modules, and the number of layers of flash memory chips in different storage modules is different.

10. An electronic device, characterized in that, Includes a solid-state drive and a host as described in any one of claims 1 to 9, wherein the host is configured to write data to the solid-state drive and / or read data from the solid-state drive.

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