Memory controller, memory device including same, and method of operating same

Abstract

A storage device includes a storage controller that includes a training circuit and transmits a data signal including a command and user data, and a non-volatile memory device that receives the data signal from the storage controller. The training circuitry performs a read training operation based on at least a portion of the user data.

Description

TECHNICAL FIELD

[0001] Devices and apparatuses consistent with the present disclosure relate to a storage controller, a storage device including the same, and an operating method thereof, and more particularly, to a storage controller performing a read training operation based on at least a portion of user data, a storage device including the same, and an operating method thereof. BACKGROUND

[0002] Semiconductor memories are classified into volatile memory devices such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc., in which stored data is destroyed when power of the semiconductor memory is cut off, and non-volatile memory devices such as read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory device, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc., in which stored data is maintained even when power of the semiconductor memory is cut off.

[0003] Non-volatile memory devices such as flash memory devices are widely used as mass storage media in computing systems. The flash memory devices are configured to communicate with a memory controller based on electrical signals. The electrical signals can be distorted due to various factors occurring during operation of the flash memory devices, resulting in the flash memory devices not being able to properly transmit and receive data. SUMMARY

[0004] According to an aspect of one or more embodiments, there is provided a storage device including a storage controller including a training circuit and transmitting a data signal including a command and user data, and a non-volatile memory device receiving the data signal from the storage controller. The training circuit performs a read training operation based on at least a portion of the user data.

[0005] According to another aspect of one or more embodiments, there is provided a storage controller including a controller interface transmitting a data signal including a command and user data to a non-volatile memory device, a pattern generator generating a training pattern including at least a portion of the user data, a pattern buffer storing the training pattern, and a comparator receiving at least a portion of the user data from the non-volatile memory device and determining whether the training pattern stored in the pattern buffer and the at least a portion of the user data received from the non-volatile memory device correspond to each other.

[0006] According to yet another aspect of one or more embodiments, a method for operating a storage device is provided that includes sending, by a storage controller, a data signal including a command and user data to a non-volatile memory device, receiving, by the non-volatile memory device, the data signal from the storage controller, and performing, by a training circuit of the storage controller, a training operation based on at least a portion of the user data. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram illustrating a storage system according to some embodiments;

[0008] Figure 2 is a block diagram illustrating a storage device according to some embodiments;

[0009] Figure 3 is a block diagram illustrating a storage device according to some embodiments;

[0010] Figure 4 is a block diagram illustrating an example of a detailed configuration of a storage controller and a non-volatile memory device for performing a read training operation according to some embodiments;

[0011] Figure 5 is a flow diagram illustrating an example of performing a read training operation according to some embodiments;

[0012] Figure 6 is a flow diagram illustrating another example of performing a read training operation according to some embodiments;

[0013] Figures 7 to 9 is a diagram illustrating various examples of a data signal DQ sent and received in connection with a read training operation according to some embodiments;

[0014] Figure 10 is a block diagram illustrating an example of a configuration of a storage controller for performing a read training operation according to some embodiments in more detail;

[0015] Figures 11 to 13 is a diagram illustrating various examples of a storage controller and a non-volatile memory device performing a read training operation using Figure 10 according to some embodiments;

[0016] Figure 14 is a block diagram illustrating an example of a training circuit including a pattern generator according to some embodiments;

[0017] Figure 15 is a block diagram illustrating an example of generating a length-adjusted training pattern using a pattern generator according to some embodiments;

[0018] Figure 16is a block diagram illustrating an example of a pattern generator generating a plurality of training patterns using a mode according to some embodiments;

[0019] Figure 17 is a flowchart illustrating an example of a pattern generator performing a plurality of read training operations using Figure 16 a mode according to some embodiments;

[0020] Figure 18 is a block diagram illustrating a storage device including a frequency boost interface (FBI) chip according to some embodiments; and

[0021] Figure 19 is a flowchart illustrating a method of operating a storage device according to some embodiments. DETAILED DESCRIPTION

[0022] According to various aspects of the present disclosure, read training can be performed without a data input operation for which data is separately generated for a read training operation, thereby shortening the time required for read training. According to various aspects of the present disclosure, read training operations can even be performed during runtime of a non-volatile memory device.

[0023] According to various aspects of the present disclosure, a program data input command and a read training command can be transmitted to a non-volatile memory device as one command, so that the time of a read training operation can be further shortened compared to when a read training command and a program data input command are separately transmitted to a non-volatile memory device as separate commands.

[0024] The above-described advantages that can be obtained through various embodiments of the present disclosure are not limited to the above-described advantages, and various technical advantages not mentioned will be clearly understood by those skilled in the art from the following description.

[0025] As used in this specification, the phrase "at least one of A, B, or C" within the scope of a clause that includes "at least one of A, B, or C" includes "only A," "only B," "only C," "A and B," "A and C," "B and C," and "A, B, and C."

[0026] Hereinafter, various embodiments will be described with reference to the accompanying drawings. Figures 1 to 19 Throughout the specification, the same reference numerals can refer to the same components, and repetitive description thereof can be omitted for the sake of clarity.

[0027] Figure 1 is a block diagram illustrating a storage system 10 according to some embodiments. Referring to Figure 1The storage system 10 may include a host 20 and a storage device 100. In some embodiments, the storage device 100 may include a storage controller 200 and a plurality of non-volatile memory (NVM) devices 300_1 to 300_3. In some embodiments, in certain aspects, the host 20 may include a host controller 21 and a host memory 22. The host memory 22 may be used as a buffer memory for temporarily storing data to be sent to or received from the storage device 100. Although in Figure 1 The example shows three NVM devices 300_1 to 300_3, but this is only an example, and in some embodiments, the number of NVM devices 300 may be greater than or less than three.

[0028] Storage device 100 may include a storage medium for storing data in response to a request from host 20. For example, storage device 100 may be implemented as at least one of a solid-state drive (SSD), embedded memory, or removable external memory. If storage device 100 is an SSD, it may be a device compliant with the Non-Volatile Memory High Speed ​​(NVMe) standard. If storage device 100 is embedded memory or external memory, it may be a device compliant with the Universal Flash Memory (UFS) or Embedded Multimedia Card (eMMC) standard. Host 20 and storage device 100 may generate and transmit packets according to standard protocols adopted by host 20 and / or storage device 100.

[0029] In some embodiments, if the non-volatile memory devices 300_1 to 300_3 are implemented as flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical, or bond-vertical) NAND (VNAND) memory array. In some embodiments, the storage device 100 may include a variety of other types of non-volatile and / or volatile memory. For example, the storage device 100 may include at least one of volatile or non-volatile memory, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), magnetic RAM (MRAM), spin-torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), resistive RAM, etc.

[0030] In some embodiments, the host controller 21 and the host memory 22 can be implemented as separate semiconductor chips. In some embodiments, the host controller 21 and the host memory 22 can be integrated on the same semiconductor chip. For example, the host controller 21 can be any one of a plurality of modules provided in an application processor, and the application processor can be implemented as a system on chip (SoC). In some embodiments, the host memory 22 can be an embedded memory provided in the application processor, or can be a volatile memory or a memory module provided outside the application processor.

[0031] The host controller 21 can manage an operation of storing data (e.g., write data) from the host memory 22 to the non-volatile memory devices 300_1 to 300_3, or storing data (e.g., read data) from the non-volatile memory devices 300 to the host memory 22. For example, the host controller 21 can manage an operation of storing user data associated with execution of a specific program in the non-volatile memory devices 300_1 to 300_3.

[0032] The storage controller 200 can include a host interface (I / F) 211, a controller interface (I / F) 212, and a central processing unit (CPU) 213. In some embodiments, the storage controller 200 can further include an index read unit (IRU) 214, a flash translation layer (FTL) 215, a buffer memory 216, an error correction code (ECC) engine 217, and an internal non-volatile memory (NVM) 218. In some embodiments, the storage controller 200 can further include a working memory loaded with the flash translation layer 215, and a data write operation and / or a read operation with respect to the non-volatile memory can be controlled by the CPU 213 executing the flash translation layer 215. For example, an operation of writing user data for the non-volatile memory devices 300_1 to 300_3 can be controlled by the CPU 213 executing the flash translation layer 215.

[0033] The host interface (I / F) 211 can transmit and receive packets to and from the host 20. The packets transmitted from the host 20 to the host interface 211 can include a command and / or data (e.g., user data) to be written to the non-volatile memory devices 300_1 to 300_3, and the packets transmitted from the host interface 211 to the host 20 can include a response to the command, or data read from the non-volatile memory devices 300_1 to 300_3, etc. Figure 1 In the drawings, the host interface 211 is illustrated as being included in the storage controller 200, but embodiments are not limited thereto. For example, in some embodiments, the host interface 211 can be located outside the storage controller 200.

[0034] The controller interface (I / F) 212 can transmit data (e.g., user data) to be written to the non-volatile memory devices 300_1 to 300_3 to the non-volatile memory devices 300_1 to 300_3, or can receive read data (e.g., user data) from the non-volatile memory devices 300_1 to 300_3. The controller interface 212 can be implemented to comply with a standard protocol such as Toggle or Open NAND Flash Interface (ONFI).

[0035] The flash translation layer (FTL) 215 can perform several functions such as address mapping, wear leveling, and / or garbage collection. In some embodiments, the buffer memory 216 can temporarily store data to be written to the non-volatile memory devices 300 or data read from the non-volatile memory devices 300_1 to 300_3. The buffer memory 216 can be a component provided within the storage controller 200, but this is merely an example, and in some embodiments, the buffer memory 216 can be provided outside of the storage controller 200.

[0036] The error correction code (ECC) engine 217 can perform error detection and correction functions on read data read from the non-volatile memory devices 300_1 to 300_3. More specifically, the ECC engine 217 can generate parity bits for write data to be written to the non-volatile memory devices 300_1 to 300_3, and the generated parity bits can be stored in the non-volatile memory devices 300_1 to 300_3 along with the write data. When data is read from the non-volatile memory devices 300_1 to 300_3, the ECC engine 217 can use the parity bits read from the non-volatile memory devices 300_1 to 300_3 along with the read data to correct errors in the read data, and output the error-corrected read data. The index read unit (IRU) 214 can process and reorder indices for performing irregular memory accesses to improve memory merging.

[0037] Figure 2 is a block diagram illustrating a storage device 100 according to some embodiments.

[0038] Referring to Figure 2 , the non-volatile memory devices 300 and the storage controller 200 can be connected to each other through a plurality of channels CH1 to CHm.

[0039] The non-volatile memory devices 300 can include a plurality of non-volatile memory devices NVM11 to NVMmn. Here, m and n can each be an integer. The plurality of non-volatile memory devices NVM11 to NVMmn can correspond to Figure 1 the plurality of non-volatile memory devices 300_1 to 300_3 of FIG. 1.

[0040] Each of the non-volatile memory devices NVM11 to NVMmn can be connected to one of the plurality of channels CH1 to CHm through a respective channel. Each of the non-volatile memory devices NVM11 to NVMmn can be implemented in any unit of memory that can operate according to a separate command from the memory controller 200. For example, each of the non-volatile memory devices NVM11 to NVMmn can be implemented as a chip or a die, but embodiments are not limited thereto.

[0041] The memory controller 200 can transmit and receive data signals to and from the non-volatile memory devices 300 through the plurality of channels CH1 to CHm. For example, the memory controller 200 can transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the non-volatile memory devices 300 through the channels CH1 to CHm, or can receive data DATAa to DATAm from the non-volatile memory devices 300.

[0042] The memory controller 200 can select one of the non-volatile memory devices 300 connected to a respective channel through each channel and transmit and receive signals to and from the selected non-volatile memory device.

[0043] The memory controller 200 can transmit and receive signals to and from the non-volatile memory devices 300 through different channels in parallel. For example, the memory controller 200 can transmit a command CMDb to the memory device NVM21 through the second channel CH2 while transmitting a command CMDa to the memory device NVM11 through the first channel CH1. For example, the memory controller 200 can receive data DATAb from the memory device NVM21 through the second channel CH2 while receiving data DATAa from the memory device NVM11 through the first channel CH1.

[0044] Figure 2 It is shown that the non-volatile memory devices 300 communicate with the memory controller 200 through m channels and the non-volatile memory devices 300 include n non-volatile memory devices corresponding to each channel, but embodiments are not limited thereto, and in some embodiments, the number of channels and the number of non-volatile memory devices connected to one channel can vary differently.

[0045] Figure 3 is a block diagram illustrating a storage device 100 according to some embodiments.

[0046] Reference Figure 3The non-volatile memory device 300 can correspond to a non-volatile memory device based on Figure 2 one of a plurality of channels CH1 to CHm in communication with the memory controller 200. Figure 2 one of the non-volatile memory devices NVM11 to NVMmn in communication with the memory controller 200.

[0047] The non-volatile memory device 300 can include first to eighth pins P11 to P18, a memory interface (I / F) circuit 310, a control logic circuit 320, and a memory cell array 330.

[0048] The memory interface (I / F) circuit 310 can receive a chip enable signal nCE from the memory controller 200 through the first pin P11. The memory interface circuit 310 can transmit and receive signals to and from the memory controller 200 through the second to eighth pins P12 to P18 according to the chip enable signal nCE. For example, if the chip enable signal nCE is in an enabled state (e.g., high level), the memory interface circuit 310 can transmit and receive signals to and from the memory controller 200 through the second to eighth pins P12 to P18.

[0049] The memory interface (I / F) circuit 310 can receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 200 through the second to fourth pins P12 to P14. The memory interface circuit 310 can receive or transmit a data signal DQ to the memory controller 200 through the seventh pin P17. A command CMD, an address ADDR, and data DATA can be transmitted through the data signal DQ. For example, the data signal DQ can be transmitted through a plurality of data signal lines. In this case, the seventh pin P17 can include a plurality of pins corresponding to a plurality of data signals.

[0050] The memory interface (I / F) circuit 310 can acquire a command CMD from the data signal DQ received in an enable period (e.g., a period of a high level state) of the command latch enable signal CLE based on toggle timing of the write enable signal nWE. The memory interface circuit 310 can acquire an address ADDR from the data signal DQ received in an enable period (e.g., a period of a high level state) of the address latch enable signal ALE based on toggle timing of the write enable signal nWE.

[0051] The write enable signal nWE can remain static (e.g., high or low) and then toggle between high and low. For example, the write enable signal nWE can toggle in a period in which the command CMD and / or the address ADDR are transmitted. Accordingly, the memory interface circuit 310 can acquire the command CMD and / or the address ADDR based on the toggle timing of the write enable signal nWE.

[0052] The memory interface (I / F) circuit 310 can receive the read enable signal nRE from the memory controller 200 through the fifth pin P15. The memory interface circuit 310 can receive the data strobe signal DQS from the memory controller 200 or transmit the data strobe signal DQS to the memory controller 200 through the sixth pin P16.

[0053] In the data DATA output operation of the non-volatile memory device 300, the memory interface circuit 310 can receive the read enable signal nRE toggled through the fifth pin P15 before the data DATA is output. The memory interface circuit 310 can generate the data strobe signal DQS toggled based on the toggle of the read enable signal nRE. For example, the memory interface circuit 310 can generate the data strobe signal DQS that starts to toggle after a predetermined delay (e.g., tDQSRE) based on the toggle start time of the read enable signal nRE.

[0054] The memory interface (I / F) circuit 310 can transmit the data signal DQ containing the data DATA based on the toggle timing of the data strobe signal DQS. Accordingly, the data DATA can be aligned with the toggle timing of the data strobe signal DQS and transmitted to the memory controller 200.

[0055] In the data DATA input operation of the non-volatile memory device 300, if the data signal DQ including the data DATA is received from the memory controller 200, the memory interface circuit 310 can receive the data strobe signal DQS toggled with the data DATA from the memory controller 200. The memory interface circuit 310 can acquire the data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS. For example, the memory interface circuit 310 can acquire the data DATA by sampling the data signal DQ at the rising edge and the falling edge of the data strobe signal DQS.

[0056] The memory interface (I / F) circuit 310 can send a ready / busy output signal nR / B to the memory controller 200 through the eighth pin P18. The memory interface circuit 310 can send state information of the non-volatile memory device 300 to the memory controller 200 through the ready / busy output signal nR / B. If the non-volatile memory device 300 is in a busy state (i.e., if an internal operation of the non-volatile memory device 300 is being performed), the memory interface circuit 310 can send the ready / busy output signal nR / B indicating the busy state to the memory controller 200. If the non-volatile memory device 300 is in a ready state (i.e., if an internal operation of the non-volatile memory device 300 is not performed or completed), the memory interface circuit 310 can send the ready / busy output signal nR / B indicating the ready state to the memory controller 200. For example, the memory interface circuit 310 can send the ready / busy output signal (nR / B) indicating the busy state (e.g., a low level) to the memory controller 200 while the non-volatile memory device 300 is reading data DATA from the memory cell array 330 in response to a page read command. For example, the memory interface circuit 310 can send the ready / busy output signal nR / B indicating the busy state to the memory controller 200 while the non-volatile memory device 300 is programming data DATA in the memory cell array 330 in response to a program command.

[0057] The control logic circuit 320 can control various operations of the non-volatile memory device 300 as a whole. The control logic circuit 320 can receive the command / address CMD / ADDR acquired from the memory interface circuit 310. The control logic circuit 320 can generate control signals for controlling other components of the non-volatile memory device 300 according to the received command / address CMD / ADDR. For example, the control logic circuit 320 can generate various control signals for programming or reading data DATA in / from the memory cell array 330. In another example, the control logic circuit 320 can also generate control signals for adjusting channel potentials within the memory cell array.

[0058] The memory cell array 330 can store data DATA acquired from the memory interface circuit 310 under the control of the control logic circuit 320. The memory cell array 330 herein can output the stored data DATA to the memory interface circuit 310 under the control of the control logic circuit 320. In some embodiments, the memory cell array 330 can adjust channel potentials in the memory cell array 330 under the control of the control logic circuit 320. Data stored in the memory cell array 330 in response to a program command or the like can be referred to as "user data".

[0059] The memory cell array 330 can include a plurality of memory cells. For example, the plurality of memory cells can be flash memory cells. However, embodiments are not limited thereto, and in some embodiments, the memory cells can be resistive random access memory (RRAM) cells, ferroelectric random access memory (FRAM) cells, phase change random access memory (PRAM) cells, thyristor random access memory (TRAM) cells, and / or magnetic random access memory (MRAM) cells. The memory cells will be described below with reference to an example of NAND flash memory cells.

[0060] The storage controller 200 can include first through eighth pins P21 through P28 and a controller interface (I / F) 212. In some embodiments, the first through eighth pins P21 through P28 can correspond to the first through eighth pins P11 through P18 of the nonvolatile memory device 300, respectively.

[0061] The controller interface (I / F) 212 can transmit a chip enable signal nCE to the nonvolatile memory device 300 through the first pin P21. The controller interface 212 can transmit and receive signals to and from the nonvolatile memory device 300 selected by the chip enable signal (nCE) through the second through eighth pins P22 through P28.

[0062] The controller interface (I / F) 212 can transmit a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE to the nonvolatile memory device 300 through the second through fourth pins P22 through P24. The controller interface 212 can transmit or receive a data signal DQ to or from the nonvolatile memory device 300 through the seventh pin P27.

[0063] The controller interface (I / F) 212 can transmit a data signal DQ including a command CMD or an address ADDR to the nonvolatile memory device 300 together with a toggle write enable signal nWE. The controller interface 212 can transmit the data signal DQ including the command CMD to the nonvolatile memory device 300 in response to transmitting the command latch enable signal CLE having an enable state, and can transmit the data signal DQ including the address ADDR to the nonvolatile memory device 300 in response to transmitting the address latch enable signal ALE having an enable state.

[0064] The controller interface (I / F) 212 can transmit a read enable signal nRE to the nonvolatile memory device 300 through a fifth pin P25. The controller interface 212 can receive or transmit a data strobe signal DQS from or to the nonvolatile memory device 300 through a sixth pin P26.

[0065] In a data DATA output operation of the nonvolatile memory device 300, the controller interface 212 can generate and transmit a toggling read enable signal nRE to the nonvolatile memory device 300. For example, the controller interface 212 can generate the read enable signal nRE which changes from a fixed state (e.g., high level or low level) to a toggling state before outputting the data DATA. Accordingly, a data strobe signal DQS based on the toggling of the read enable signal nRE can be generated in the nonvolatile memory device 300. The controller interface 212 can receive a data signal DQ including the data DATA from the nonvolatile memory device 300 along with the toggling data strobe signal DQS. The controller interface 212 can acquire the data DATA from the data signal DQ based on the toggling timing of the data strobe signal DQS.

[0066] In a data input operation of the nonvolatile memory device 300, the controller interface 212 can generate a toggling data strobe signal DQS. For example, the controller interface 212 can generate the data strobe signal DQS which changes from a fixed state (e.g., high level or low level) to a toggling state before transmitting the data DATA. The controller interface 212 can transmit a data signal DQ including the data DATA to the nonvolatile memory device 300 based on the toggling timing of the data strobe signal DQS.

[0067] The controller interface (I / F) 212 can receive a ready / busy output signal nR / B from the nonvolatile memory device 300 through an eighth pin P28. The controller interface 212 can determine state information of the nonvolatile memory device 300 based on the ready / busy output signal nR / B.

[0068] Reference Figure 3 The controller interface (I / F) 212 and the memory interface (I / F) circuit 310 shown and described are examples, and embodiments are not limited thereto. For example, in some embodiments, the controller interface 212 and the memory interface circuit 310 can further include pins that transmit and receive signals related to the reference Figure 3The signals shown and described are different signals. In some embodiments, some of the plurality of pins P11 to P18 and P21 to P28 of the controller interface 212 and the memory interface circuit 310 can be omitted from the controller interface 212 and the memory interface circuit 310 or can be integrated with other pins.

[0069] Figure 4 is a block diagram showing detailed configurations of the memory controller 200 and the non-volatile memory device 300 for performing a read training operation according to some embodiments.

[0070] Referring to Figure 4 , the memory controller 200 can transmit a control signal CTRL to the non-volatile memory device 300. For example, the control signal CTRL can include Figure 3 a chip enable signal nCE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal nWE, and / or a read enable signal nRE.

[0071] The memory controller 200 can transmit a command CMD, an address ADDR, and / or data DATA to the non-volatile memory device 300 through a data signal DQ. In some embodiments, the memory controller 200 can transmit the command CMD and the address ADDR to the non-volatile memory device 300 through a separate command and address signal SCA, and transmit the data DATA to the non-volatile memory device 300 through the data signal DQ.

[0072] The non-volatile memory device 300 can identify (or capture) the data DATA provided through the data signal DQ based on a data strobe signal DQS. The non-volatile memory device 300 can store the identified data DATA based on the received command CMD and the address ADDR. The identified data DATA can include user data UD.

[0073] Hereinafter, for ease of description, it is assumed that "received data" in the non-volatile memory device 300 is data identified based on the data strobe signal DQS. These expressions are intended to facilitate the description of various embodiments of the present disclosure and do not limit the technical idea of the present disclosure.

[0074] The non-volatile memory device 300 can store the user data UD received from the memory controller 200 in the register 420 and / or the memory cell array 430 based on the data strobe signal DQS.

[0075] In some cases, the data strobe signal DQS can be distorted (e.g., delayed or advanced) due to various external factors (e.g., temperature changes, operating voltage changes, operating rate changes, etc.), resulting in the non-volatile memory device 300 not properly recognizing the user data UD. If the user data UD is not properly recognized, undesired data can be erroneously stored in the non-volatile memory device 300 by the user or program.

[0076] The storage controller 200 can include a training circuit 410. The training circuit 410 can be implemented in software, hardware, or a combination thereof. For example, in some embodiments, the training circuit 410 can be implemented using the CPU 213 and the buffer memory 216, etc., of the storage controller 200, where, for example, the buffer memory 216 stores program code for performing the training operations as discussed further herein, and the CPU 213 accesses the buffer memory 216 and executes the program code to cause the CPU 213 to perform the training operations as discussed below. In some embodiments, the training circuit 410 can be implemented as an application specific integrated circuit (ASIC) or other circuit that is hard-coded to implement the training operations as described below. Figure 1

[0077] The training circuit 410 can perform training operations. By performing the training operations through the training circuitry 410, the storage controller 200 can compensate for distortion of the data strobe signal DQS and improve the reliability of data exchange with the non-volatile memory device 300 described above.

[0078] The training circuit 410 can perform a read training operation. The read training operation can be performed during runtime of the storage device. The various aspects of performing the read training operation using the training circuit 410 will be described in detail below using the example of the storage controller 200 and the non-volatile memory device 300 described above. Figures 5 to 19 After receiving the read training request, and during runtime, the storage controller 200 can determine a point in time to perform the read training operation using the training circuit 410. In some embodiments, a host connected to the storage controller 200 can determine the point in time to perform the read training operation and send information related to the determined point in time to the storage controller 200.

[0079] Figure 5 is a flowchart illustrating an example of performing a read training operation according to some embodiments. The storage controller 200 can send a data signal including a command CMD, an address ADDR, and user data UD to the non-volatile memory device 300. Each operation performed in the Figure 5 below will be described in detail with reference to Figures 7 to 9 Various types of commands CMD will be described in detail below.

[0080] ​In operation 510, the non-volatile memory device 300 can store user data UD in a memory cell array (e.g., Figure 4 The user data UD was previously stored in a register (e.g., in the memory cell array 430) Figure 4 In register 420).

[0081] At least a portion of the user data UD stored in the registers of the non-volatile memory device 300 can be sent to the memory controller 200. If the data strobe signal DQS is not distorted, the user data UD sent to the memory controller 200 can be normal data.

[0082] On the other hand, if the data strobe signal DQS is distorted, the user data UD sent to the storage controller 200 may be abnormal data. That is, the data pattern indicating the arrangement or order of bits in the user data UD sent to the storage controller 200 may be a pattern that is deformed or distorted from the existing data pattern.

[0083] In operation 520, the storage controller 200 (or Figure 4 The training circuit 410 can determine whether the data patterns of at least a portion of the user data sent from the storage controller 200 and at least a portion of the user data received from the registers of the non-volatile memory device 300 match each other. For example, the user data sent from the storage controller 200 can be stored as a training pattern in the storage controller 200 (or the training circuit 410) and used when determining whether the data patterns of the sent and received user data match (or correspond) each other. In some embodiments, the size of the data sent from the registers to the storage controller can be the same as the size of the training pattern. That is, the storage controller 200 can compare normal user data before it is sent to the storage controller 200 with normal or abnormal user data (or various data patterns) received from the registers of the non-volatile memory device 300 to determine whether the data strobe signal DQS is normal (or distorted).

[0084] In response to determining that the transmitted and received user data do not match (520, No), the storage controller 200 may adjust the delay of the data signal DQ at 530. For example, in some embodiments, the storage controller 200 may adjust the delay when the data patterns do not match. After adjusting the delay of the data signal DQ, the previous processes 510 and 520 may be repeated for the same user data. For example, by repeatedly adjusting the delay of the data signal DQ, center alignment between the data strobe signal DQS and the data signal DQ can be achieved.

[0085] In response to determining that the transmitted and received user data match each other (520, yes), at 540, the user data UD can be stored in the memory cell array of the non-volatile memory device 300. For example, in some embodiments, the user data UD can be stored in the memory cell array of the non-volatile memory device when the data patterns match each other.

[0086] Figure 6 This is a flowchart illustrating another example of performing a read training operation according to some embodiments. Figure 5 The difference lies in Figure 6 In the process, after storing the user data UD in the register of the non-volatile memory device 300 at 610, the user data UD can be stored in the memory cell array of the non-volatile memory device 300 at 620.

[0087] At least a portion of the user data UD stored in the registers of the non-volatile memory device 300 can be sent to the memory controller 200. At 630, the memory controller 200 (or Figure 4 The training circuit 410 can determine whether at least a portion of the user data sent from the memory controller 200 and at least a portion of the user data received from the registers of the non-volatile memory device 300 match each other. For example, the memory controller (or Figure 4 The training circuit 410 can determine whether the data patterns match each other.

[0088] In response to determining that the data do not match each other (630, No), the storage controller 200 may adjust the delay of the data signal DQ at 640. After adjusting the delay of the data signal DQ, the previous operations 610 and 620 may be repeated for the same user data. In some embodiments, in response to determining that the data match each other (630, Yes), the read training operation performed by the storage controller 200 may be terminated.

[0089] Figures 7 to 9 This is a diagram illustrating various examples of data signals DQ transmitted and received in conjunction with read training operations according to some embodiments. Figures 7 to 9 The data signal DQ indicates that in the storage controller (e.g., Figures 1 to 6 The memory controller 200) and non-volatile memory devices (e.g., Figures 1 to 6 Signals sent and received between non-volatile memory devices (300) and may include commands (CMD) and user data. The ready / busy output signal nR / B indicates the status information of the non-volatile memory device and can be sent from the non-volatile memory device to the memory controller.

[0090] refer to Figure 7The storage controller can send a program data in command (Program Din CMD) 710 to the non-volatile memory device and can send at least a portion of user data associated with the program data in a data burst (Data Burst) 720. The at least a portion of user data can be stored in a register of the non-volatile memory device.

[0091] The storage controller can send a read training command (Read TRN CMD) 730 to the non-volatile memory device to initiate a read training operation. In some embodiments, the read training command 730 can be received from a host (e.g., host 20) connected to the storage controller and sent to the non-volatile memory device. Figure 1

[0092] In response to receiving the read training command 730 from the storage controller, the non-volatile memory device can send training data out 740 to the storage controller, the training data out 740 being the at least a portion of user data stored in the register.

[0093] In response to determining that the at least a portion of user data (e.g., the training pattern) and the data received from the non-volatile memory device (the training data) correspond or match each other, the storage controller can send a program confirm command (Program Confirm CMD) 750 to the non-volatile memory device.

[0094] In response to receiving the program confirm command 750 from the storage controller, the non-volatile memory device can store the user data stored in the register in the memory cell array. For example, during a program time tPROG 760, the user data stored in the register can be stored in the memory cell array of the non-volatile memory device, and the non-volatile memory device can send a ready / busy output signal nR / B to the storage controller indicating a busy state.

[0095] Referring to Figure 8 , Figure 7 The program data in command (Program Din CMD) 710 and the read training command 730 of FIG. 7 can be sent to the non-volatile memory device as one command 810. In response to the storage controller completing the burst transmission 820 of the at least a portion of user data, the non-volatile memory device can send training data out (830) to the storage controller.

[0096] In response to receiving the program confirm command 840 from the storage controller, the non-volatile memory device can store the user data stored in the register in the memory cell array of the non-volatile memory device during a program time tPROG 850. ​

[0097] Referring Figure 9 , the program data input command 910 and the burst transfer 920 can be sent from the storage controller to the non-volatile memory device. In response to the non-volatile memory device receiving the user data and the program confirmation command 930 from the storage controller, the user data can be stored in the memory cell array during the program time tPROG 940, and the read training command 950 can be sent to the non-volatile memory device.

[0098] Embodiments are not limited thereto, and the read training command 950 can be sent to the non-volatile memory device at any time after the storage controller completes the burst transfer 920 of at least a portion of the user data. In response to receiving the read training command 950, the non-volatile memory device can send the training data output to the storage controller at 960.

[0099] Figure 10 is a block diagram illustrating a configuration of a storage controller 200 for performing a read training operation in accordance with some embodiments in more detail. The storage controller 200 can include a volatile memory (VM) 1010 and a training circuit 410. The training circuit 410 can include a pattern buffer 1020 and a comparator 1030. Details of operations performed by each of the configurations illustrated in Figures 11 to 13 the detailed description uses Figure 10 to illustrate the details of the operations performed by each of the configurations.

[0100] Figures 11 to 13 is a block diagram illustrating a configuration of a storage controller 200 for performing a read training operation in accordance with some embodiments in more detail. The storage controller 200 can include a volatile memory (VM) 1010 and a training circuit 410. The training circuit 410 can include a pattern buffer 1020 and a comparator 1030. Details of operations performed by each of the configurations illustrated in Figure 10 to illustrate the details of the operations performed by each of the configurations.

[0101] Referring Figure 11 , the storage controller 200 can receive a read training command (READ TRN CMD) from the host. In some embodiments, the storage controller 200 can receive user data UD from the host. At 1110, the storage controller 200 can store the received user data UD in the volatile memory 1010.

[0102] The storage controller 200 can send a program data in command (Program Din CMD) and user data UD to the non-volatile memory device 300. In response to receiving the program data in command (Program Din CMD), at 1120, the non-volatile memory device 300 can store the received user data UD in the register 420.

[0103] At 1130, the storage controller 200 can store at least a portion of the user data UD in the pattern buffer 1020 as a training pattern. For example, in response to receiving a read training command (Read TRN CMD) from the host, the storage controller 200 can store the training pattern in the pattern buffer 1020. The storage controller 200 can store the training pattern in the pattern buffer 1020 before, after, or concurrently with storing the user data (UD) in the register 420.

[0104] The storage controller 200 can send the training pattern stored in the pattern buffer 1020 to the comparator 1030, and the non-volatile memory device 300 can send at least a portion of the user data stored in the register 420 to the comparator 1030. For example, in response to receiving the read training command (Read TRN CMD), the non-volatile memory device 300 can send at least a portion of the user data stored in the register 420 to the comparator 1030. The data sent from the register 420 to the comparator 1030 and the training pattern sent from the pattern buffer 1020 to the comparator 1030 can be corresponding data having the same size as each other.

[0105] At 1140, the comparator 1030 can compare (or determine) whether the training pattern received from the pattern buffer 1020 and the at least a portion of the user data received from the register 420 match (or correspond) to each other.

[0106] In response to determining that at least a portion of the training pattern and the user data received from the register 420 do not match each other (1140, No), the storage controller 200 can adjust the delay of the data signal at 1150. For example, as the delay of the data signal is repeatedly adjusted, center alignment between the data strobe signal and the data signal can be accomplished, and the read training operation can be completed.

[0107] In response to determining that at least a portion of the training pattern and the user data received from the register 420 match each other (1140, YES), the storage controller 200 can transmit a program confirm command (Program Confirm CMD) to the non-volatile memory device 300. In response to receiving the program confirm command, at 1160, the non-volatile memory device 300 can store the user data stored in the register 420 in the memory cell array (MCA) 430.

[0108] As shown and described above, according to various embodiments, at least a portion of the user data can be used to perform a read training operation of the storage device, instead of using separately generated data for the read training operation. With this configuration, according to various embodiments, the read training can be performed without a data input operation of the data separately generated for the read training operation, thereby shortening the time required for the read training. According to various embodiments, the read training operation can even be performed during a runtime of the non-volatile memory device 300.

[0109] Referring to Figure 12 , unlike Figure 11 , the program data input command (Program Din CMD) and the read training command (Read TRN CMD) can be transmitted to the non-volatile memory device 300 as one command.

[0110] In Figure 11 , in response to the non-volatile storage device 300 receiving the read training command (Read TRN CMD), at least a portion of the user data stored in the register 420 can be transmitted to the comparator 1030, whereas in Figure 12 , in response to completion of the user data storage operation 1120, at least a portion of the user data stored in the register 420 can be transmitted to the comparator 1030. With this configuration, the time for the read training operation can be further shortened compared to when the read training command (Read TRN CMD) is transmitted to the non-volatile memory device 300 as a separate command.

[0111] Referring to Figure 13 , unlike Figure 11 , the non-volatile storage device 300 can receive the read training command (Read TRN CMD) after receiving the program confirm command (Program Confirm CMD) from the storage controller 200. In response to receiving the program confirm command (Program Confirm CMD) from the storage controller 200, at 1340, the non-volatile memory device 300 can store the user data (UD) in the memory cell array (MCA) 430.

[0112] The read training command (Read TRN CMD) can be sent to the non-volatile memory device 300 at any time after the user data UD is sent from the volatile memory 1010 to the non-volatile memory device 300.

[0113] In response to receiving the read training command (Read TRN CMD) from the storage controller 200, the non-volatile memory device 300 can send at least a portion of the data stored in the register 420 to the comparator 1030.

[0114] At 1350, the comparator 1030 can compare (or determine) whether the training pattern and the pattern of the at least a portion of the user data match (or correspond) to each other. In response to the comparator 1030 determining that the training pattern and the at least a portion of the user data received from the register 420 do not match each other (1350, No), the storage controller 200 can adjust the delay of the data signal at 1360.

[0115] In some embodiments, in response to the comparator 1030 determining that the training pattern and the at least a portion of the user data match each other (1350, Yes), the training operation by the storage controller 200 can be terminated.

[0116] Figure 14 is a block diagram illustrating an example of the training circuit 410 including a pattern generator 1410, according to some embodiments. The pattern generator 1410 can generate a training pattern to be stored in the pattern buffer 1020 based on the user data. The pattern generator 1410 can adjust the length of the training pattern or generate multiple training patterns. Such configurations and operations will be described below with respect to Figure 15 and Figure 16 respectively.

[0117] Figure 15 is a block diagram illustrating an example of generating a length-adjusted training pattern using the pattern generator 1410, according to some embodiments. The pattern generator 1410 can receive a request to adjust the length of the training pattern. In some embodiments, the request to adjust the length of the training pattern can be received from a host. In some embodiments, the storage controller can generate the request to adjust the length of the training pattern.

[0118] In response to receiving the request to adjust the length of the training pattern, the pattern generator 1410 can adjust the size of the data (e.g., the training pattern) stored in the pattern buffer 1020.

[0119] In some embodiments, in response to receiving the request to adjust the length of the training pattern, the size of the data sent from the register 420 to the comparator 1030 can be adjusted. In some embodiments, in response to the control logic 320 receiving the request for length adjustment, the control logic 320 can adjust the size of the data sent from the register 420 to the comparator 1030 so that the data stored in the pattern buffer 1020 (e.g., the training pattern) and the data sent from the register 420 to the comparator 1030 have the same size.

[0120] The length-adjusted training pattern can be sent from the pattern buffer 1020 to the comparator 1030, and the data corresponding to the length-adjusted pattern in the data stored in the register 420 can be sent to the comparator 1030. The comparator 1030 can compare the length-adjusted training pattern with the data received from the register 420 to determine whether to adjust the delay of the data signal.

[0121] Figure 16 is a block diagram illustrating an example of generating a plurality of training patterns using the pattern generator 1410 according to some embodiments. The pattern generator 1410 can receive a request to generate a plurality of patterns. In some embodiments, the request to generate a plurality of patterns can be received from a host. In some embodiments, the storage controller can generate the request to generate a plurality of patterns.

[0122] In response to receiving the request to generate a plurality of patterns, the pattern generator 1410 can generate a plurality of training patterns to be stored in the pattern buffer 1020. For example, the pattern generator 1410 can divide the user data UD into divided user data UD_1 to UD_n, and generate a plurality of training patterns using the divided user data UD_1 to UD_n. At least some of the plurality of training patterns generated by the pattern generator 1410 can have different lengths from each other. In some embodiments, the plurality of training patterns can all have the same size and length. In some embodiments, the control logic 320 can receive the request to generate a plurality of patterns. In response to receiving the request to generate a plurality of patterns, the control logic 320 can control the register 420 so that the register 420 sends a plurality of patterns to the comparator 1030, and each of the plurality of patterns stored in the pattern buffer 1020 and each of the plurality of patterns sent from the register 420 to the comparator 1030 correspond to each other and have the same size.

[0123] The training circuit 410 can perform a plurality of read training operations using each of the plurality of training patterns. The operation and configuration will be described in detail below with reference to Figure 17

[0124] Figure 17 ​This illustrates the use according to some embodiments. Figure 16 The flowchart illustrates an example of the pattern generator 1410 performing multiple read training operations. The first user data UD_1 to the nth user data UD_n (where n is a natural number greater than 2) can be data generated by the storage controller 200 by partitioning the user data UD. The pattern generator of the storage controller 200 can generate multiple training patterns based on the first user data UD_1 to the nth user data UD_n and store the multiple training patterns in a pattern buffer.

[0125] The storage controller 200 can send the first user data UD_1 to the non-volatile memory device 300. In 1710_1, the non-volatile memory device 300 can store the first user data UD_1 in a register (e.g., Figure 16 In register 420).

[0126] The non-volatile storage device 300 can send at least a portion of the first user data UD_1 stored in the register to the storage controller 200 (or send to...). Figure 16 Comparator 1030).

[0127] The comparator of the storage controller 200 can retrieve the first training pattern stored in the pattern buffer at 1720_1, and determine at 1730_1 whether the first training pattern and at least a portion of the first user data UD_1 match each other.

[0128] In response to determining that the data patterns do not match (1730_1, No), the storage controller 200 may adjust the delay of the data signal at 1740_1. After adjusting the delay of the data signal, the previous processes 1710_1, 1720_1, and 1730_1 may be repeated for the same first user data UD_1. In response to determining that the data patterns match (1730_1, Yes), at 1750_1, the first user data UD_1 may be stored in the memory cell array of the non-volatile memory device 300.

[0129] The above process can be repeated a number of times corresponding to the number of training patterns generated based on user data.

[0130] For example, storage controller 200 can send the nth user data UD_n to non-volatile storage device 300 (where n is a natural number greater than or equal to 2). At 1710_n, non-volatile storage device 300 can store the nth user data UD_n in a register (e.g., Figure 16 In register 420).

[0131] At least a portion of the nth user data UD_n stored in the registers of the non-volatile memory device 300 can be sent to the storage controller 200 (or Figure 16 the comparator 1030).

[0132] The comparator of the storage controller 200 can acquire the nth training pattern stored in the pattern buffer at 1720_n, and determine whether the nth training pattern and at least a portion of the nth user data (UD_n) match each other at 1730_n.

[0133] In response to determining that the data patterns do not match each other (1730_n, No), the storage controller 200 can adjust the delay of the data signal at 1740_n. After adjusting the delay of the data signal, the previous processes (1710_n, 1720_n, 1730_n) can be repeatedly performed with respect to the same nth user data (UD_n). In response to determining that the data patterns match each other (1730_n, Yes), the nth user data UD_n can be stored in the memory cell array of the non-volatile memory device 300 at 1750_n.

[0134] Figure 18 is a block diagram illustrating a storage device including a frequency boost interface (FBI) chip 1800 according to some embodiments.

[0135] Referring to Figure 18 , the storage device can further include the FBI chip 1800. The FBI chip 1800 can be disposed between the storage controller 200 and the non-volatile memory device 300 to receive data from the storage controller 200 and transmit data to the non-volatile memory device 300, and can receive data from the non-volatile memory device 300 and transmit data to the storage controller 200. Although Figure 18 only one non-volatile memory device 300 is illustrated, in some embodiments, a plurality of non-volatile memory devices 300 that communicate data with the FBI chip 1800 can be implemented.

[0136] Unlike the embodiments illustrated in Figure 18 , in some embodiments, the training circuit 410 can be disposed in the FBI chip 1800. In this case, by using the pattern of the user data programmed in the non-volatile memory device 300, read training is preemptively performed in the training circuit 410 disposed in the FBI chip 1800, and errors can be quickly identified compared to when read training is performed in the storage controller 200.

[0137] Figure 19This is a flowchart illustrating a method 1900 for operating a storage device according to some embodiments. Method 1900 can be performed by a storage device including a storage controller and a non-volatile memory device, and the storage controller may include training circuitry.

[0138] At S1910, method 1900 can be initiated by the memory controller sending a data signal, including commands and user data, to the non-volatile memory device. At S1920, the non-volatile memory device can receive the data signal from the memory controller.

[0139] At S1930, the training circuitry of the memory controller can perform a training operation based on at least a portion of the user data. For example, the memory controller can send a Read TRN CMD command to the non-volatile memory device to initiate a read training operation.

[0140] At S1940, the storage controller (or comparator) can determine whether the training pattern, which is at least a part of the user data, and at least a part of the user data received from the storage controller by the non-volatile memory device match each other.

[0141] In response to the determination that the data patterns do not match each other (S1940, No), the storage controller can adjust the delay of the data signal at S1950.

[0142] In some embodiments, in response to determining that data patterns match each other (S1940, yes), the storage controller may perform programming operations on the user data at S1960.

[0143] Reference above Figure 19 The flowcharts and descriptions described are merely examples and may be implemented differently in some aspects. For example, in some examples, the order of the corresponding operations may be changed, some operations may be repeated, some operations may be omitted, or some operations may be added. For example, although the operations at S1940 to S1960 are shown as separate from S1930, in some embodiments, the operations at S1940 to S1960 may be included in S1930.

[0144] Although various embodiments have been described in conjunction with the accompanying drawings, it should be understood that this disclosure is not limited to the various embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: A storage controller, the storage controller including training circuitry and transmitting data signals including commands and user data; and A non-volatile memory device that receives the data signal from the memory controller, wherein the training circuit performs a read training operation based on at least a portion of the user data.

2. The storage device as claimed in claim 1, wherein: The non-volatile memory device includes a memory cell array, and The user data is data stored in the memory cell array during the operation of the storage device.

3. The storage device as claimed in claim 1, wherein: The training circuit includes a mode buffer, and The storage controller stores at least a portion of the user data as training patterns in the pattern buffer.

4. The storage device as claimed in claim 3, wherein: The training circuit also includes a comparator. The non-volatile memory device includes registers. The non-volatile memory device stores the user data received from the memory controller in the register. The non-volatile memory device sends at least a portion of the user data stored in the register to the comparator, and The comparator compares the training pattern stored in the pattern buffer with at least a portion of the user data received from the register.

5. The storage device as claimed in claim 4, wherein, Based on receiving a read training command from the storage controller, the non-volatile memory device sends at least a portion of the user data stored in the register to the comparator.

6. The storage device as claimed in claim 4, wherein, The size of at least a portion of the user data sent from the register to the comparator is the same as the size of the training pattern stored in the pattern buffer.

7. The storage device of claim 4, wherein: The non-volatile memory device further includes a memory cell array, and The non-volatile storage device stores the user data stored in the register in the memory cell array.

8. The storage device of claim 7, wherein: Based on the comparator determining that the training pattern stored in the pattern buffer matches at least a portion of the user data received from the register, the storage controller sends a programming confirmation command to the non-volatile memory device, and Based on the programming confirmation command received from the storage controller, the non-volatile storage device stores the user data stored in the register in the memory cell array.

9. The storage device of claim 4, wherein: The non-volatile memory device further includes a memory cell array, and After the non-volatile storage device stores the user data stored in the register into the memory cell array, the comparator determines whether the training mode and at least a portion of the user data received from the register correspond to each other.

10. The storage device of claim 4, wherein, Based on the comparator, if it is determined that the training mode and at least a portion of the user data received from the register do not correspond to each other, the storage controller adjusts the delay of the data signal.

11. The storage device of claim 4, wherein, Based on the received request to adjust the length of the training mode, the size of at least a portion of the user data stored in the mode buffer and the size of at least a portion of the user data sent from the register to the comparator are adjusted.

12. The storage device of claim 11, wherein, The request to adjust the length of the training mode is received from the host.

13. The storage device of claim 1, wherein, The training circuit performs the read training operation based on a read training request received from the host.

14. The storage device of claim 13, wherein, Upon receiving the read training request, the storage controller determines the time point during runtime when the read training operation will be performed.

15. The storage device of claim 1, wherein, The commands include programming data input commands.

16. The storage device of claim 15, wherein, The command also includes a command to read the training commands.

17. The storage device of claim 1, wherein: The training circuit includes a pattern generator, and The pattern generator generates multiple training patterns based on the user data.

18. The storage device of claim 17, wherein at least some of the plurality of training modes have different lengths from each other.

19. A storage controller, comprising: A controller interface that sends data signals, including commands and user data, to a non-volatile memory device; A pattern generator that generates training patterns that include at least a portion of the user data; A pattern buffer, wherein the pattern buffer stores the training pattern; and A comparator receives at least a portion of the user data from the non-volatile memory device and determines whether the training pattern stored in the pattern buffer corresponds to the at least a portion of the user data received from the non-volatile memory device.

20. A method for operating a storage device, the method comprising: The storage controller sends data signals, including commands and user data, to the non-volatile memory device; The data signal is received from the memory controller by the non-volatile memory device; as well as The training circuitry of the storage controller performs the training operation based on at least a portion of the user data.

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