Memory system and operating method of memory system

Abstract

A memory system and an operating method of the memory system are provided. The operating method of the memory system includes: transmitting a first access command to a first non-volatile memory device; checking a state of the first non-volatile memory device; and performing a first ZQ calibration on the first non-volatile memory device through a DQ pin of the first non-volatile memory device during a time when the first non-volatile memory device is in the busy state.

Description

Technical Field

[0001] This invention relates to a storage system including a non-volatile memory device and a method of operating the storage system. Background Technology

[0002] As electronic devices become faster and consume less power, storage devices used in electronic devices are expected to have high capacity and operate at high speeds.

[0003] As memory devices, which include multiple non-volatile memory devices, become more powerful, research into signal integrity (SI) for maintaining the memory interface is actively underway. Summary of the Invention

[0004] The present invention provides a storage system with improved SI (signal integrity) performance and a method of operating the storage system.

[0005] However, the invention is not limited to the aspects set forth herein. These and other aspects of the invention will become more apparent to those skilled in the art from the following detailed description of the invention.

[0006] According to one aspect of this disclosure, a method of operating a storage system includes: sending a first access command to a first non-volatile memory device; checking the state of the first non-volatile memory device; and performing a first ZQ calibration on the first non-volatile memory device via the DQ pin of the first non-volatile memory device during a period when the first non-volatile memory device is in a busy state.

[0007] According to one aspect of this disclosure, a storage system includes: a storage controller and a plurality of non-volatile memory devices connected to the storage controller via a first signal line for transmitting commands and addresses and a second signal line for transmitting data. The first and second signal lines are separate from each other. The storage controller uses the first signal line to send an access command, as the command, to a first non-volatile memory device among the plurality of non-volatile memory devices. During the time when the operation corresponding to the access command is performed on the first non-volatile memory device, the controller receives a logic level of a ready / busy signal using the R / B pin of the first non-volatile memory device, checks the state of the first non-volatile memory device on the first signal line, and performs ZQ calibration on the first non-volatile memory device in response to a logic level of the ready / busy signal indicating a busy state. After performing ZQ calibration, the controller checks the state of the first non-volatile memory device.

[0008] According to one aspect of this disclosure, a storage system includes: a plurality of non-volatile memory devices and a storage controller connected to the plurality of non-volatile memory devices. The storage controller performs a first ZQ calibration on the connected plurality of non-volatile memory devices, sends an access command via the DQ pin of each of the plurality of non-volatile memory devices, receives a busy status signal indicating a busy state from each of the plurality of non-volatile memory devices operating in response to the access command, performs a second ZQ calibration on the plurality of non-volatile memory devices, and checks whether the second ZQ calibration has been correctly performed on each of the plurality of non-volatile memory devices. Attached Figure Description

[0009] The above and other aspects and features of the present invention will become clearer from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings.

[0010] Figure 1 A storage system according to some embodiments is shown.

[0011] Figure 2 This is a block diagram illustrating a storage device according to some embodiments.

[0012] Figure 3 This is a conceptual diagram illustrating a semiconductor package according to some embodiments.

[0013] Figure 4 This is a flowchart illustrating a method of operating a storage system according to some embodiments.

[0014] Figure 5 This is a diagram illustrating a storage system according to some embodiments.

[0015] Figure 6 This illustrates some embodiments. Figure 5 Timing diagram of a non-volatile memory device performing ZQ calibration during a read operation.

[0016] Figure 7 This is used to explain, according to some embodiments, the ZQ calibration performed. Figure 5 The timing diagram of the channel status of the storage system.

[0017] Figure 8 This is used to explain, according to some embodiments, the ZQ calibration performed. Figure 5 The timing diagram of the channel status of the storage system.

[0018] Figure 9 This is used to explain, according to some embodiments, the ZQ calibration performed. Figure 5 The timing diagram of the channel status of the storage system.

[0019] Figure 10 and Figure 11 This is used to explain, according to some embodiments, the ZQ calibration performed. Figure 5 The timing diagram of the channel status of the storage system.

[0020] Figure 12 This is shown in some embodiments Figure 5 The timing diagram of ZQ calibration being performed when a non-volatile memory device performs a programming operation.

[0021] Figure 13 This is used to explain, according to some embodiments, the ZQ calibration performed. Figure 5 The timing diagram of the channel status of the storage system.

[0022] Figure 14 This illustrates some embodiments. Figure 5 Timing diagram of a non-volatile memory device performing ZQ calibration during an erase operation.

[0023] Figure 15 This is a conceptual diagram illustrating a storage system connected in an SCA manner according to some embodiments.

[0024] Figure 16 This illustrates some embodiments. Figure 15 Timing diagram of a non-volatile memory device performing ZQ calibration during a read operation.

[0025] Figure 17 This illustrates some embodiments. Figure 15 Timing diagram of a non-volatile memory device performing ZQ calibration during an erase operation.

[0026] Figure 18 This illustrates some embodiments. Figure 15 Timing diagram of non-volatile memory devices performing ZQ calibration during programming operations.

[0027] Figures 19 to 21 It is a timing diagram used to explain the operation method of a storage system according to some embodiments. Detailed Implementation

[0028] In the following text, reference will be made to Figures 1 to 21 A storage system according to some embodiments of the present invention is described.

[0029] Figure 1 A storage system according to some embodiments is shown.

[0030] Reference Figure 1The electronic system according to an embodiment of the present invention includes a host 2 and a storage system 1. The electronic system may be implemented as a personal computer (PC) or data server, a laptop computer, or a portable device. The portable device may be implemented as a mobile phone, smartphone, tablet PC, personal digital assistant (PDA), enterprise digital assistant (EDA), digital still camera, digital video camera, portable multimedia player (PMP), personal navigation device or portable navigation device (PND), handheld game console, or e-reader. In some embodiments, the electronic system may be implemented as a system-on-a-chip (SoC).

[0031] The host 2 may include a host control unit that controls the overall operation of the storage system 1. The host control unit can control the self-operation of the host 2 and the operation of the storage system 1. The host control unit can generate commands for controlling the operation of the storage system 1 and send the commands to the storage system 1.

[0032] Host 2 can request data processing operations (e.g., data read operations, data write (programming) operations, or data erase operations) from storage system 1. For example, host 2 can be a central processing unit (CPU), graphics processing unit (GPU), microprocessor, application processor (AP), etc.

[0033] Storage system 1 includes storage controller 200 and non-volatile memory device 100. Storage system 1 can be implemented as various types of storage devices (such as solid-state drive (SSD), embedded multimedia card (eMMC), universal flash storage device (UFS) or compact flash (CF), secure digital (SD), micro-secure digital (Micro-SD), mini-secure digital (Mini-SD), extreme digital (xD) or memory stick).

[0034] Storage controller 200 of storage system 1 may be integrated with host 2. Storage controller 200 may be configured to access non-volatile memory device (or NVM device) 100 in response to a request from host 2. For example, storage controller 200 may be implemented to control the overall operation of storage system 1. Storage controller 200 may perform various management operations, such as cache / buffer management, firmware management, garbage collection management, wear leveling management, data deduplication management, read refresh / reclaim management, bad block management, multi-stream management, host data and non-volatile memory mapping management, quality of service (QoS) management, system resource allocation management, non-volatile memory queue management, read level management, erase / programming management, hot / cold data management, power failure protection management, dynamic thermal management, and initialization management.

[0035] Although not clearly shown in the accompanying drawings, the storage controller 200 can be configured to provide an interface between the storage system 1 and the host 2. Furthermore, the storage controller 200 can be configured to drive the firmware for controlling the storage system 1 upon request from the host 2, or to drive the firmware for controlling the storage system 1 itself.

[0036] As an example, the storage controller 200 may also include known components such as memory, controller control unit, host interface and memory interface.

[0037] The host interface of storage controller 200 can operate according to a protocol used to perform data exchange between host 2 and storage controller 200. As an example, storage controller 200 can be configured to communicate with host 2 via at least one of various interface protocols, such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Fast (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol.

[0038] The memory can be used as at least one of the following: the operating memory of the controller control unit, the cache memory between storage system 1 and host 2, and the buffer memory between storage system 1 and host 2, and can be implemented as, for example, random access memory (RAM).

[0039] The memory interface of the memory controller 200 is electrically connected to the input / output interface circuit of the non-volatile memory device 100. The memory interface of the memory controller 200 can send signals to and receive signals from the non-volatile memory device 100 via multiple pins. Figure 5 and Figure 15 The details are described in the text.

[0040] The storage system 1 may include, for example, multiple non-volatile memory devices. The multiple non-volatile memory devices may communicate with the storage controller 200 via, for example, first channel CH1 to m-th channel CHm.

[0041] Figure 2 This is a block diagram illustrating a storage device according to some embodiments.

[0042] Reference Figure 2The storage system 1 may include a non-volatile memory device 100 and a storage controller 200. The storage system 1 may support multiple channels CH1 to CHm, and the non-volatile memory device 100 and the storage controller 200 may be connected via multiple channels CH1 to CHm. For example, the storage system 1 may be implemented as a storage device (such as a solid-state drive (SSD)).

[0043] The non-volatile memory device 100 may include a plurality of non-volatile memory devices NVM11 to NVMmn. Each of the non-volatile memory devices NVM11 to NVMmn may be connected to one of a plurality of channels CH1 to CHm via a corresponding way. For example, non-volatile memory devices NVM11 to NVM1n may be connected to a first channel CH1 via paths W11 to W1n, and non-volatile memory devices NVM21 to NVM2n may be connected to a second channel CH2 via paths W21 to W2n. In an exemplary embodiment, each of the non-volatile memory devices NVM11 to NVMmn may be implemented in any memory cell operable according to various instructions from the memory controller 200. For example, each of the non-volatile memory devices NVM11 to NVMmn may be implemented as a chip or a die. However, the invention is not limited thereto.

[0044] The storage controller 200 can send signals to and receive signals from the non-volatile memory device 100 via multiple channels CH1 to CHm. For example, the storage controller 200 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the non-volatile memory device 100 via channels CH1 to CHm, or it can receive data DATAa to DATAm from the non-volatile memory device 100.

[0045] The storage controller 200 can select one of the non-volatile memory devices connected to each channel via each channel, and can send signals to and receive signals from the selected non-volatile memory device. For example, the storage controller 200 can select non-volatile memory device NVM11 among the non-volatile memory devices NVM11 to NVM1n connected to the first channel CH1. The storage controller 200 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory device NVM11 via the first channel CH1, or can receive data DATAa from the selected non-volatile memory device NVM11.

[0046] The storage controller 200 can send signals in parallel to and receive signals in parallel from the non-volatile memory device 100 through multiple channels CH1 to CHm, which are different from each other. For example, the storage controller 200 can send the command CMDb to the non-volatile memory device 100 through the second channel CH2, while simultaneously sending the command CMDa to the non-volatile memory device 100 through the first channel CH1. For example, the storage controller 200 can receive data DATAb from the non-volatile memory device 100 through the second channel CH2, while simultaneously receiving data DATAa from the non-volatile memory device 100 through the first channel CH1. In some embodiments, the storage controller 200 can receive data DATAa to DATAm in parallel from the non-volatile memory device 100 through the first channel CH1 to the m-th channel CHm, respectively.

[0047] The memory controller 200 controls the overall operation of the non-volatile memory device 100. The memory controller 200 can send signals to channels CH1 to CHm to control each of the non-volatile memory devices NVM11 to NVM1n connected to channels CH1 to CHm. For example, the memory controller 200 can send a command CMDa and an address ADDRa to the first channel CH1 to control a selected one of the non-volatile memory devices NVM11 to NVM1n. In some embodiments, the memory controller 200 can send commands CMDa to CMDm and addresses ADDRa to ADDRm in parallel to channels CH1 to CHm.

[0048] Each of the non-volatile memory devices NVM11 to NVMmn can operate under the control of the memory controller 200. For example, non-volatile memory device NVM11 can program data DATAa according to the command CMDa and address ADDRa provided to the first channel CH1. For example, non-volatile memory device NVM21 can read data DATAb according to the command CMDb and address ADDRb provided to the second channel CH2, and can send the read data DATAb to the memory controller 200.

[0049] although Figure 2 The non-volatile memory device 100 communicates with the memory controller 200 through m channels CH1 to CHm, and each channel of the non-volatile memory device 100 includes n non-volatile memory devices, but the number of channels and the number of non-volatile memory devices per channel can be changed differently.

[0050] Figure 3 This is a conceptual diagram illustrating a semiconductor package according to some embodiments.

[0051] Reference Figure 3The semiconductor package 1000 may include a substrate PCB, a memory controller 200, and semiconductor structures (100-1, 100-2, ..., 100-k; hereinafter, 100). Hereinafter, the semiconductor structure 100 and the non-volatile memory device 100 are used interchangeably. The substrate PCB may be a printed circuit board (PCB). The substrate PCB may have a structure in which insulating layers and wiring layers are cross-stacked. In some embodiments, the semiconductor structure 100 may be associated with, for example, Figure 2 The non-volatile memory devices (e.g., NVM11 to NVM1n) connected to the same channel are shown in the diagram. For example, each of the semiconductor structures 100-1 to 100-k can be a memory chip.

[0052] The memory controller 200 and semiconductor structure 100 may be disposed on the upper surface of the substrate PCB. External connection terminals may be disposed on the lower surface of the substrate PCB. The external connection terminals may be laterally spaced from each other. For example, the external connection terminals may include solder balls or solder bumps.

[0053] The memory controller 200 can be electrically connected to the semiconductor structure 100 via at least one of a wiring layer and a pin connection (pin connection) inside the substrate PCB. In some embodiments, the pin connection may be connected to each of the semiconductor structures 100, and the memory controller 200 may be connected to a wiring layer of the substrate PCB, which is connected to the pin connection.

[0054] Semiconductor structures 100 may be configured to be stacked in a first direction (e.g., a direction perpendicular to the upper surface of the substrate PCB). Semiconductor structures 100 may be disposed on the substrate PCB as an offset stacked structure. For example, semiconductor structures 100 may be stacked at an angle in the first direction, which may take the form of rising, sloping steps. Therefore, a portion of the upper surface of each semiconductor structure may be exposed for connection to pin interconnects.

[0055] Each of the semiconductor structures 100 may include at least one non-volatile memory device. Each semiconductor structure is electrically connected to the substrate PCB and the memory controller 200 via pin connections (pin connections) to send and receive signals. Multiple pin connections (pin connections) may be made of a metallic material. For example, each of the multiple pin connections may be used as... Figure 2 The corresponding channels from CH1 to CHm.

[0056] The memory controller 200 can send independent control signals to each of the semiconductor structures 100. However, as the number of semiconductor structures 100 included in the semiconductor package 1000 increases, the frequency of the input / output signals from the memory controller 200 to each semiconductor structure increases, and signal integrity (SI) issues can increase due to the high-capacity packaging. Therefore, impedance (ZQ) calibration is important during the operation of sending signals to and receiving signals from each semiconductor package. In some embodiments, semiconductor structures 100 connected to the same pin connections can receive control signals from the memory controller 200. As the number of semiconductor structures 100 per channel increases (i.e., more non-volatile memory devices are stacked on top of each other), the length of the pin connections and the number of contacts with the semiconductor structures 100 increase, thereby degrading SI. The memory controller 200 can perform ZQ calibration operations for impedance matching between the memory controller 200 and the semiconductor structures 100. For example, the storage controller 200 can send a ZQ calibration signal to the semiconductor structure 100, and each of the semiconductor structures 100 can perform ZQ calibration in response to the ZQ calibration signal.

[0057] As the operating environment of the memory system 1 is subject to frequent changes in conditions such as process, voltage, and temperature (PVT), and variations in circuit impedance, ZQ calibration can stabilize the memory system 1 by reducing impedance mismatch between the memory controller 200 and the non-volatile memory devices in the semiconductor structure 100, and by using impedance codes corresponding to various operating environments, thus ensuring the operational reliability of the memory system 1 even when circuit impedance changes. In other words, ZQ calibration is used to equalize the driver strength of each semiconductor structure to maintain a constant operating environment.

[0058] However, multiple semiconductor structures included in the semiconductor package 1000 share the same ZQ calibration circuit. Since each semiconductor structure can only be calibrated based on the resistance of the shared ZQ calibration circuit, there is a limitation to serial signal operation. Therefore, as the capacity of the semiconductor package increases, the open-circuit time during ZQ calibration operations can increase. Therefore, it is necessary to shorten the open-circuit operation of ZQ calibration in multiple stacked semiconductor packages. Furthermore, even if ZQ calibration is performed during the first operation, because the operating environment of the memory system changes during runtime, a technique is needed to optimally set ZQ calibration even during runtime.

[0059] Figure 4 This is a flowchart illustrating a method of operating a storage system according to some embodiments.

[0060] Reference Figure 4When the storage system 1 is powered on (S10), an initial ZQ calibration is performed (S20). Based on the impedance code set in the initial ZQ calibration, the storage system 1 performs general operations during runtime (S30).

[0061] During runtime, storage system 1 monitors the interface between storage controller 200 and non-volatile memory device 100 to determine if ZQ calibration is required again (S40). If ZQ calibration is required again (S40, yes), storage controller 200 checks the status of non-volatile memory device 100 (S60) and sends an access command (e.g., a NAND access command such as a read command, programming command, or erase command) to non-volatile memory device 100 (S50). If non-volatile memory device 100 is found to be busy (S70, yes), ZQ calibration is performed again (S80). After re-performing ZQ calibration, the access operation continues according to S50 after checking whether ZQ calibration was successfully performed (passed) or not successfully performed (failed) when the signal integrity (SI) status of non-volatile memory device 100 is checked again (S90) and after checking whether ZQ calibration was successfully performed (passed) or not successfully performed (failed).

[0062] Figure 5 This is a diagram illustrating a storage system according to some embodiments.

[0063] The memory interface of the memory controller 200 can send signals to and receive signals from the input / output interface 110 of the non-volatile memory device 100A (also called interface circuitry) via multiple pins. For example, multiple pins can send and receive DQ (data queue), R / B (ready / busy), DQS (data strobe), RE (read enable), CE (chip enable), ALE (address latch enable), CLE (command latch enable), and WE (write enable) signals, respectively. Received signals can be sent to the memory cell array 120 via peripheral circuitry 130, and data stored in the memory cell array 120 or status signals of the non-volatile memory device 100A generated by peripheral circuitry 130 can be sent to the memory controller 200 via the input / output interface 110.

[0064] The DQ signal (or the signal on the DQ pin) is a data signal, and commands (CMD), addresses (ADDR), and data (DATA) can be transmitted. The DQ signal can be transmitted via multiple data signal lines. The R / B signal is a signal indicating the operating state of the non-volatile memory device 100A. For example, when the non-volatile memory device 100A is operating, the memory controller 200 can send a busy signal, and when the non-volatile memory device 100A is paused, the memory controller 200 can send a ready signal. For example, data can be encrypted for security or privacy. The DQS signal is a data strobe signal, and the RE signal is a read enable signal. The RE signal can be input as a data output control signal when reading data from the non-volatile memory device 100A. The RE signal can be used to generate the DQS signal. The CE signal is a chip enable signal, which is a signal used by the memory controller 200 to selectively activate and access at least one of the non-volatile memory devices 100A. The CLE signal is the command latch enable signal, and the ALE signal is the address latch enable signal. The CLE signal is enabled when the DQ signal includes the command CMD. The ALE signal is enabled when the DQ signal includes the address ADDR. The CLE or ALE signal is disabled when general-purpose data is sent to the DQ pin. The WE signal is the write enable signal, and the memory controller 200 can send the data signal DQ, including the command CMD or address ADDR, and the switched write enable signal WE to the non-volatile memory device 100A.

[0065] For example, the non-volatile memory device 100A can perform programming / reading / erasing operations by latching the command CMD or address ADD at the edge of the WE signal according to the CLE and ALE signals. For example, the CE signal is activated during a read operation, the CLE signal is activated in the command transmission segment, the ALE signal is activated in the address transmission segment, and the RE signal can be toggled in the segment where data is transmitted via the DQ pin. The DQS signal can be toggled at a frequency corresponding to the data input / output speed. Read data can be sequentially transmitted synchronously with the data strobe signal DQS.

[0066] Each of the multiple pins can send and receive signals independently of each other. According to some embodiments, when the memory controller 200 sends an access command and the address in a read / program / erase operation to the non-volatile memory device 100A via the DQ pin, the non-volatile memory device 100A sends an R / B signal indicating a busy state via the R / B pin, while simultaneously performing the operation corresponding to the access command. For example, when the signal is sent via the R / B pin, the DQ pin may not be used. When the R / B pin sends a busy state signal and the DQ pin is not used, ZQ calibration can be performed.

[0067] The non-volatile memory device 100A supports Plane Independent Command (PIC).

[0068] Figure 6 This illustrates some embodiments. Figure 5 Timing diagram of a non-volatile memory device performing ZQ calibration during a read operation.

[0069] Reference Figure 6 When the memory controller 200 sends a read command (NAND Read CMD) via the DQ pin, the non-volatile memory device 100A sends a logic-low ready / busy signal via the R / B pin, and simultaneously executes a read operation associated with the read command. In the timing diagram of the R / B pin, the logic-low segment that is busy due to the read operation is represented as tR. For example, the time period during which the ready / busy signal has a logic-low level corresponds to the read operation time tR of the read operation.

[0070] When a logic-low ready / busy signal is sent via the R / B pin, the memory controller 200 sends a status check command, and the non-volatile memory device 100A checks its internal status and returns as busy. When the memory controller 200 receives the busy return from the non-volatile memory device 100A, it performs a ZQ calibration with the non-volatile memory device 100A. Subsequently, the memory controller 200 checks whether the ZQ calibration was performed correctly (whether the status is pass or fail) using the status check of the non-volatile memory device 100A. In some embodiments, the non-volatile memory device 100A may have a status register, the stored value of which indicates whether the ZQ calibration was successful (i.e., performed correctly). For example, after performing a ZQ calibration on the non-volatile memory device 100A, the memory controller 200 may read specific bits in the status register to check the ZQ calibration result. When the non-volatile memory device 100A completes reading data from the memory cell array 120, the R / B pin sends a logic high signal indicating a ready state, and the non-volatile memory device 100A sends the read data (Data Out) through the DQ pin.

[0071] Figure 7 , Figure 8 and Figure 9 It is used to explain where ZQ is calibrated. Figure 5 The timing diagram of the channel states of the storage system. (Refer to...) Figure 1 , Figure 2 and Figure 3 The description includes the operation of a semiconductor structure 100 comprising multiple non-volatile memories (NVMs) and a memory controller 200 during a read operation. It is assumed that a first non-volatile memory device NVM 11 and a second non-volatile memory device NVM 12 are connected to a first channel, with the first non-volatile memory device NVM 11 connected to the first Way0 of the first channel CH1, and the second non-volatile memory device NVM 12 connected to the second Way1 of the first channel.

[0072] The first non-volatile memory device NVM11 and the second non-volatile memory device NVM12 send data from the memory cell array to the page buffer during the read operation time tR (i.e., the memory cell to buffer read time) when the read operation is performed, and send the data from the page buffer to the channel. Simultaneously, when the read operation is completed, the word line is discharged in the tRRC segment (i.e., the time from read-ready to new command tRRC). The tRRC segment is the time from the read-ready state to the new command, and tRRC shortens the length of the tR segment. Through the tRRC segment, the memory device changes its state (i.e., the external busy signal is enabled) to allow DMA (Direct Memory Access) before the internal read operation is completed.

[0073] The read operation time tR comprises three segments. During the first segment of the read operation time, an internal pump enable operation is performed to prepare for a regular data read operation. During the second segment of the read operation time tR, the regular read operation (or read core operation) is performed. During the third segment of the read operation time tR, an internal pump disable operation (such as pump restore) is performed. The third segment of the read operation time tR is redefined as the time tRRC from read read readiness to a new command, where tRRC represents the release of the idle DMA (Direct Memory Access) from its "externally busy" state. In other words, the read operation time tR refers to the time to access a memory cell and send data to the page buffer. The length of the read operation time tR can vary depending on whether the memory cell is a single-level or multi-level cell, the location of the memory cell to be accessed, etc. The length of the time tRRC from read read readiness to a new command can vary depending on the number of paths or channels to which data stored in the page buffer should be output. In a read operation of the first non-volatile memory device NVM11 of the first Way0 of the first channel CH1, data stored in the memory cell array 120 may be sent to the page buffer during a time period from time t1 to time t6, and the word line may be discharged during a time period from time t6 to time t7 (i.e., during the time period tRRC from read ready to new command). Figure 5 and Figure 6In this context, the non-volatile memory device 100A may be busy only until the time tRRC from read-ready to new command (externally busy).

[0074] Figure 7 This is used to explain, according to some embodiments, the ZQ calibration performed. Figure 5 The timing diagram of the channel status of the storage system.

[0075] Reference Figure 7 The first non-volatile memory device NVM11 and the second non-volatile memory device NVM12 begin their read operations sequentially according to the time of receipt of the read command from the memory controller 200. For example, the first non-volatile memory device NVM11 performs a read operation during the period from time t1 to time t6, and the second non-volatile memory device NVM12 performs a read operation during the period from time t2 to time t7. That is, the start time of the read operation of the first non-volatile memory device NVM11 (e.g., time t1) may be different from the start time of the read operation of the second non-volatile memory device NVM12 (e.g., time t2), and the start time of the read operation of the second non-volatile memory device NVM12 (e.g., time t2) may be later than the start time of the read operation of the first non-volatile memory device NVM11 (e.g., time t1).

[0076] Furthermore, read data from the first non-volatile memory device NVM11 and the second non-volatile memory device NVM12 can be serially output through channels without overlapping. The first non-volatile memory device NVM11 can output the data read at time t6 to channel (Dout Way0) through the first Way0, and the second non-volatile memory device NVM12 can output the read data to channel (Dout Way1) through the second Way1.

[0077] According to some embodiments, the memory controller 200 may perform ZQ calibration on each non-volatile memory device in a tR segment. The memory controller 200 may perform ZQ calibration on a first non-volatile memory device and a second non-volatile memory device serially. For example, the memory controller may perform ZQ calibration on the first non-volatile memory device starting at time t3, and may perform ZQ calibration on the second non-volatile memory device starting at time t4 when the calibration of the first non-volatile memory device is completed. However, ZQ calibration on each non-volatile memory device may be performed in a TP segment, where the R / B pins of all non-volatile memory devices are busy and the DQ pins of the channel are unused. For example, the TP segment may correspond to a time window in which the tR segments of all non-volatile memory devices in the same channel overlap, such that the DQ pins of the channel are unused during the TP segment, allowing the DQ pins to be used for ZQ calibration. For example, during the busy period (e.g., TP segment) of each non-volatile memory device in the same channel, ZQ calibration is performed on each of the non-volatile memory devices. For ease of description, in Figure 7 In this case, it is assumed that the channel has only two paths.

[0078] Figure 8 This is used to explain, according to some embodiments, the ZQ calibration performed. Figure 5 The timing diagram of the channel status of the storage system.

[0079] Reference Figure 8 According to some embodiments, when the tRRC segment is longer than the data output time tDOUT (tRRC>tDOUT), the storage controller can perform ZQ calibration in the tRRC segment.

[0080] For example, the first non-volatile memory device NVM11 and the second non-volatile memory device NVM12 each perform a read operation in response to a read command received from the memory controller 200 during read operation time tR. Then, the first non-volatile memory device NVM11 and the second non-volatile memory device NVM12 sequentially output the read data during the tRRC segment. The read data output from the first non-volatile memory device NVM11 to the channel may not overlap with the read data output from the second non-volatile memory device NVM12. However, with... Figure 7Unlike other devices, at the beginning of the first tRRC segment (e.g., time t1), ZQ calibration is performed on the first non-volatile memory device NVM11, and then the first data read from the first non-volatile memory device NVM11 can be output to the channel (Dout Way0) at time t2. At time t3, when the output of the first data is completed, the storage controller performs ZQ calibration on the second non-volatile memory device NVM12, and then the second non-volatile memory device NVM12 can output the second data read to the channel (Dout Way1) at time t4.

[0081] Figure 9 This is used to explain, according to some embodiments, the ZQ calibration performed. Figure 5 The timing diagram of the channel status of the storage system.

[0082] Reference Figure 9 According to some embodiments, if the tRRC segment is longer than the data output time tDOUT (tRRC>tDOUT), the storage controller can perform ZQ calibration within the tRRC segment. However, compared to... Figure 8 Unlike other calibration methods, ZQ calibration can be performed before all data from all non-volatile memory devices in the same channel is output.

[0083] For example, the storage controller 200 performs ZQ calibration (ZQ) on the first non-volatile memory device NVM11 immediately upon switching to the tRRC segment at time t1. If the second non-volatile memory device NVM12 operates within the tRRC segment between time t1 and time t2, ZQ calibration can be performed on the second non-volatile memory device NVM12 after the ZQ calibration of the first non-volatile memory device NVM11 has been completed. In some embodiments, if the second non-volatile memory device NVM12 switches to the tRRC segment at time t2 when the ZQ calibration of the first non-volatile memory device has been completed, then the storage controller 200 can then perform ZQ calibration on the second non-volatile memory device NVM12. For ease of description, Figure 9 In this context, it is assumed that the channel has only two paths. In some embodiments, ZQ calibration of all non-volatile memory devices on the same channel can be completed before data read from the non-volatile memory devices begins to be output through the channel.

[0084] After the ZQ calibration of all non-volatile memory devices NVM11 and NMV12 belonging to the same channel is completed at time t3, the non-volatile memory devices can sequentially output read data to the channel (Dout Way0, Dout Way1).

[0085] Figure 10 and Figure 11 This is used to explain, according to some embodiments, the ZQ calibration performed. Figure 5 The timing diagram of the channel states of the storage system. For example, the data output time D-Out can be longer than the time tRRC from read read readiness to a new command. For example, the time tRRC from read read readiness to a new command can be 5µs to 15µs, which is shorter than the data output time.

[0086] Reference Figure 10 According to some embodiments, the storage controller 200 can continuously send commands to the non-volatile memory device 100 (or... Figure 5 and Figure 6 (e.g., the non-volatile memory device 100A in the memory). For example, the memory controller 200 can continuously send commands to the non-volatile memory device 100 regardless of whether data is output.

[0087] exist Figure 10 In this process, the memory controller 200 sends a first read command, and when the first read operation of the first read command is completed in the non-volatile memory device 100 during the first read time P1 (that is, when it is completed during the tRRC segment of the first read time P1), the memory controller 200 continuously sends a second read command for a second read operation to be executed during the second read time P2. The non-volatile memory device 100 continuously executes the first read operation of the first read command during the first read time P1 and the second read operation of the second read command during the second read time P2. In some embodiments, the first read time P1 may include the memory cell to buffer read operation time tR and the time from read read readiness to a new command tRRC. In some embodiments, the first read time P1 may be equal to the second read time P2.

[0088] When the storage controller 200 sends a read command to the non-volatile memory device 100, such as Figure 4 The non-volatile memory device 100 described in the document or as such Figure 6 The non-volatile memory device 100A described herein checks its status between time t0 and time t1, then reads data from the memory cell and stores it in the page buffer between time t0 and time t1 (i.e., during the memory cell-to-buffer read operation time tR), while returning a busy return. Next, the non-volatile memory device 100 may perform ZQ calibration during the time tRRC from read-ready to new command (i.e., between time t1 and time t3). When ZQ calibration is complete, the non-volatile memory device 100 waits for the next read command after checking if the calibration was successful (Status Check).

[0089] After sending a read command corresponding to the first read operation performed during the first read time P1, the memory controller 200 continuously sends the next read command when the non-volatile memory device 100 enters the ready state.

[0090] The data stored in the page buffer is output to the memory controller 200 after the time tRRC from read ready to new command has elapsed (that is, after the time t3 of the second read operation for the next read command to the non-volatile memory device 100 begins), and the memory controller 200 receives the data of the first read operation performed during the first read time P1 between time t3 and time t4.

[0091] The non-volatile memory device 100 outputs data during time t6 to t7 after passing through the tR segment (t3 to t5) and the tRRC segment (t5 to t6), where data is read from the memory cell during the P2 segment by the next read command, and the word line is discharged. In some embodiments, the non-volatile memory device 100 outputs data between time t6 and time t7 after the tR segment (i.e., between time t3 and time t5) and the tRRC segment (i.e., between time t5 and time t6). During a second read operation performed in response to the next read command, data read from the memory cell during the second read operation may be output after the P2 segment.

[0092] Reference Figure 11 According to some embodiments, the storage controller 200 can send commands to the non-volatile memory device 100. However, compared with... Figure 10 different, Figure 11 The storage controller 200 can receive data associated with the first read command after the first read command is sent, and then send a second read command.

[0093] For example, the storage controller 200 may send a first read command and a second read command after the data of the first read operation (P1 segment) performed on the non-volatile memory device corresponding to the first read command has been output. That is, the first Way0 of the non-volatile memory device 100 may receive the next read command between the P1 segment and the P2 segment over a predetermined time interval (i.e., between time t3 and time t4), during which the data output D-Out of the first read operation is output to the channel.

[0094] For example, when the storage controller 200 sends a first read command to the non-volatile memory device 100, the non-volatile memory device 100 performs a first read operation in segment P1 using the first read command. For example, during time t0 to time t1, such as... Figure 4 or Figure 6 As described, after a status check, the non-volatile memory device 100 returns a Busy Return indicating whether the memory cell is busy, reads data from the memory cell, and stores the data in the page buffer (tR, time t0 to time t1). The non-volatile memory device 100 may perform ZQ calibration during the time tRRC from read-ready to new command, in which the word line is discharged (i.e., between time t1 and time t3). For example, the execution time of ZQ calibration may be shorter than the time tRRC from read-ready to new command.

[0095] When ZQ calibration is complete, the non-volatile memory device 100 outputs the first data read via the first read command to the channel after a status check confirms successful calibration. The memory controller 200 may send a second read command after the first data has been fully output at time t4.

[0096] Next, when the second read command is received after time t4, the non-volatile memory device 100 can perform the next data read operation in the P2 segment based on the reset channel state.

[0097] In other words, Figure 11 The non-volatile memory device 100 can receive commands discontinuously, and there can be time gaps between data outputs during segments P1 and P2. For example, the time gaps can correspond to the memory cell to buffer read operation time tR.

[0098] Figure 12 This is shown in some embodiments Figure 5 The timing diagram of ZQ calibration being performed when a non-volatile memory device performs a programming operation.

[0099] Reference Figure 12 When the memory controller 200 sends a programming command (NAND PGM CMD) and the data to be programmed (Data In) via the DQ pin, the non-volatile memory device 100 sends a logic-low ready / busy signal via the R / B pin during the programming operation time tPROG. In the timing diagram, since the programming operation is performed when the ready / busy signal is logic-low, it is represented as tPROG. For example, the time period during which the ready / busy signal has a logic-low level corresponds to tPROG.

[0100] When a logic-low ready / busy signal is sent via the R / B pin during tPROG, the memory controller 200 sends a status check command, the non-volatile memory device 100 responds with a busy state, and the memory controller 200 performs ZQ calibration with the non-volatile memory device 100. Afterward, the memory controller 200 restarts the status check of the non-volatile memory device 100 to verify that the ZQ calibration was successfully performed.

[0101] Figure 13 This is used to explain, according to some embodiments, the ZQ calibration performed. Figure 5 The timing diagram of the channel status of the storage system.

[0102] Reference Figure 13 The memory controller 200 can perform ZQ calibration on each page in either the tADL (address-to-data load) segment (i.e., address-to-data load time tADL) or the latch dump segment (tDBSY2) (i.e., latch dump time tDBSY2). The tADL segment is the time required to wait for a specific period of time during a programming operation without data input. For example, the address-to-data load time tADL indicates the waiting time after receiving the address for the programming operation and before data input begins in the programming operation (i.e., the delay between the address cycle and the data cycle). The address-to-data load time tADL may correspond to the reset time used to reset the page buffer. The latch dump segment (tDBSY2) is a segment where the R / B pin is briefly busy before subsequent data is input to the next page.

[0103] When data is programmed into three pages in a non-volatile memory device according to some embodiments, the non-volatile memory device 100 sends the data to be programmed for each page and performs data setting (data setting section), and then completes the programming operation (programming confirmation section) after checking that all programming data has been successfully programmed.

[0104] For example, the memory controller 200 sends the programming start command 80h and the addresses of the memory cell array (C1, C2, R1, R2, and R3) (or the page addresses of the non-volatile memory device) to the first page (1) of the non-volatile memory device. stThe memory controller 200 then sends the data to be programmed (W-Data) to page buffer 104, and sends a dump command C0h and a dump specification command 11h. The dump specification command 11h may be, for example, a page buffer address indicating the LSB page of the first page buffer PB1. According to some embodiments, the memory controller 200 may send a programming start command 80h, the address of a page of the non-volatile memory device, a programming confirmation command 88h, and a programming end command 10h to the non-volatile memory device.

[0105] The memory controller 200 can perform a first ZQ calibration (ZQ1) on the first page (i.e., the data path between the data pin DQ and the page buffer) after sending the programming start command and address and before sending the data to be programmed. After that, a second ZQ calibration (ZQ2) can be performed on the first page (i.e., the data path between the page buffer and the memory cell array) when the programming activation signal busy time tWB has passed after the dump specified command 11h and the R / B pin enters the latch dump segment (tDBSY2) state.

[0106] Similar to the first page, after sending the programming start command and address to each of the second and third pages and before sending the data to be programmed, the memory controller performs a first ZQ calibration on each of the second and third pages, and can perform a second ZQ calibration when the R / B pin enters the latch dump segment (tDBSY2) state.

[0107] After completing the second ZQ calibration of the third page, when the latch dump segment (tDBSY2) ends, the memory controller 200 outputs the addresses (C1, C2, R1, R2, and R3) in the confirmation sequence (i.e., programming confirmation command) 88h and in the order programmed via the DQ pin, and outputs the Level 3 Cell (TLC) command set (i.e., programming end command) 10h. The TLC command set 10h indicates the end of the programming commands. When the programming activation signal busy time tWB has passed after the output of the TLC command set 10h, the R / B pin outputs a programming busy signal during tPROG. The programming activation signal busy time tWB indicates the busy time during which no new commands are issued by the memory controller 200. The memory controller 200 may perform the third ZQ calibration ZQ3 during the tPROG segment in which the programming busy signal is being output from the R / B pin. After completing the third ZQ calibration, the storage controller 200 outputs the status register read command 70h, and the non-volatile memory device 100 sends the status information SR and completes the programming operation.

[0108] According to an embodiment, the storage controller 200 may perform a first ZQ calibration during programming operations. In some embodiments, the storage controller 200 may perform a second ZQ calibration during programming operations. According to an embodiment, the storage controller 200 may perform a third ZQ calibration during programming operations. In some embodiments, the storage controller 200 may perform at least two of the first, second, and third ZQ calibrations together during programming operations.

[0109] According to an embodiment, after data to be programmed into multiple non-volatile memory devices is sequentially input into the channel, the memory controller 200 can sequentially perform ZQ calibration on each non-volatile memory device by means of a segment in which the programming operation is performed in each non-volatile memory device NVM11 and NVM12 (e.g., a segment in which the R / B pins of all non-volatile memory devices overlap in a busy state).

[0110] After programming and full calibration of the data (e.g., ZQ3), the storage controller 200 may send a status read command (70h) to the non-volatile memory device. The storage controller 200 waits for a time tWHR after the command 70h to check the status of the non-volatile memory device after the read or program operation. The storage controller 200 may receive a status SR[0] from the non-volatile memory device indicating whether the previous read / program operation has been completed.

[0111] Figure 14 This illustrates some embodiments. Figure 5 Timing diagram of a non-volatile memory device performing ZQ calibration during an erase operation.

[0112] Reference Figure 14 When the memory controller 200 sends an erase command (NAND ERS CMD) via the DQ pin, the non-volatile memory device 100 sends a logic-low ready / busy signal via the R / B pin during the erase operation time tBERS. In the timing diagram, because the erase operation is performed when the ready / busy signal is logic-low, the timing period during which the ready / busy signal has a logic-low level corresponds to the erase operation time tBERS.

[0113] While a logic-low ready / busy signal is being transmitted via the R / B pin during the erase operation time tBERS, the memory controller 200 sends a status check command, the non-volatile memory device 100 returns to a busy state, and the memory controller 200 performs ZQ calibration with the non-volatile memory device 100. After that, the memory controller 200 restarts the status check of the non-volatile memory device 100.

[0114] Figure 15 This is a conceptual diagram illustrating a storage system connected in a separate command / address (SCA) manner according to some embodiments. Figure 5 The difference lies in Figure 15 In this configuration, the memory controller 200 and the non-volatile memory device 100B are connected via an SCA interface. For ease of explanation, Figure 5 Repeated descriptions will not be provided.

[0115] Reference Figure 15 In the SCA interface, multiple pins are connected between the memory controller 200 and the non-volatile memory device 100B in independent command / address modes (hereinafter, SCA mode). Figure 5 Unlike the PIC mode described in the text, in SCA mode, the signal lines for transmitting commands and the signal lines for transmitting addresses are separated from each other. Because the command signal lines and address signal lines are separated in SCA mode, the memory controller 200 can send command or address signals to other signal lines even while accessing the non-volatile memory device 100B via the DQ signal line. Multiple pins can respectively transmit signals such as DQ, R / B, DQS, RE, CA_CE, CA[0], CA[1], and CA_CLK. The DQ, R / B, DQS, and RE signals are referenced... Figure 5 They are described, therefore their detailed descriptions will not be provided.

[0116] CA_CE is the command address chip enable signal and is the signal that activates a specific non-volatile memory chip. The CA[0] signal is the signal line for transmitting commands, CA[1] is the signal line for transmitting addresses, and the CA_CLK signal is the clock signal line for the command signal line and the address signal line. According to various embodiments, CA[1:0] may be referred to as the command address signal line, and the DQ signal line may be referred to as the data signal line.

[0117] The CA_CLK signal is an external clock signal provided by the memory controller 200, and the non-volatile memory device 100B can generate multiple internal clocks from the CA_CLK signal by using phase shift or clock division techniques. The CA[0] signal can operate with one of the multiple internal clocks, and the CA[1] signal can operate with another of the multiple internal clocks.

[0118] Figure 16 This illustrates some embodiments. Figure 15 Timing diagram of a non-volatile memory device performing ZQ calibration during a read operation.

[0119] Reference Figure 16 When the storage controller 200 sends a read command (NAND Read CMD) via the CA[1:0] pin, the non-volatile memory device 100 sends a logic low ready / busy signal via the R / B pin during the read operation time tR.

[0120] When a logic-low ready / busy signal is being sent via the R / B pin, the memory controller 200 sends a status check command via the CA[1:0] pins. The non-volatile memory device 100 responds with a busy status, and the memory controller 200 performs ZQ calibration with the non-volatile memory device 100. Then, the memory controller 200 checks the status of the non-volatile memory device 100 again via the CA[1:0] pins. While the ZQ calibration on the CA[1:0] pins is being performed, the ZQ calibration on the DQ pin is also performed. In some embodiments, ZQ calibration can be performed simultaneously on both the first and second signal lines.

[0121] Figure 17 This illustrates some embodiments. Figure 15 Timing diagram of a non-volatile memory device performing ZQ calibration during an erase operation.

[0122] Reference Figure 17 When the memory controller 200 sends an erase command (NAND ERS CMD) via the CA[1:0] pin, the non-volatile memory device 100 sends a logic low ready / busy signal via the R / B pin during the erase operation time tBERS.

[0123] While a logic-low ready / busy signal is being sent via the R / B pin during the erase operation time tBERS, the memory controller 200 sends a status check command via the CA[1:0] pins. The non-volatile memory device 100 responds with a busy status, and the memory controller 200 performs ZQ calibration with the non-volatile memory device 100. While ZQ calibration is being performed on the CA[1:0] pins, ZQ calibration is also performed on the DQ pins.

[0124] Then, the storage controller 200 checks the status of the non-volatile memory device 100 again via the CA[1:0] pin, and sends a logic high ready signal to the R / B pin when the non-volatile memory device 100 has completed the erase operation.

[0125] Figure 18 This illustrates some embodiments. Figure 15 Timing diagram of non-volatile memory devices performing ZQ calibration during programming operations.

[0126] Reference Figure 18 When the memory controller 200 sends a programming command (NAND PGM CMD) via the CA[1:0] pin and sends data via the DQ pin, the non-volatile memory device 100 sends a logic low ready / busy signal via the R / B pin during the programming operation time tPROG.

[0127] While a logic-low ready / busy signal is being sent via the R / B pin during the programming operation time tPROG, the memory controller 200 sends a status check command via the CA[1:0] pins. The non-volatile memory device 100 responds with a busy status, and the memory controller 200 performs ZQ calibration with the non-volatile memory device 100. ZQ calibration is also performed on the DQ pin during the ZQ calibration of the CA[1:0] pins.

[0128] Subsequently, the storage controller 200 checks the status of the non-volatile memory device 100 again via the CA[1:0] pins, and when the non-volatile memory device 100 completes the programming operation, the R / B pin sends a logic high ready signal.

[0129] Figures 19 to 21 This is a timing diagram used to explain the operation of a storage system according to some embodiments. See also... Figure 1 and Figure 2The storage system 1 includes a storage controller 200 and multiple non-volatile memory devices NVM11, NVM12, NVM13, and NVM14 connected via four paths Way0, Way1, Way2, and Way3 of the first channel CH1. For ease of description, assume... Figure 2 The first channel CH1 has four paths Way0 to Way3 (i.e., four non-volatile memory devices NVM11 to NVM14).

[0130] Reference Figure 19 During the read operation time tR w of storage system 1, multiple non-volatile memory devices sequentially receive read commands through each of the connected ways, and output read data to the storage controller 200 connected to the channel in the order in which the read commands are received. After receiving the read command for each non-volatile memory device, the storage controller 200 may perform ZQ calibration (ZQ Cal) before the data is output (Dout).

[0131] exist Figure 20 In the example shown, the first non-volatile memory device NVM11 of the first path (Way0) receives, as... Figure 12 The programming commands described herein, and if the R / B pin is busy, the storage controller 200 performs ZQ calibration on the first non-volatile memory device NVM11.

[0132] The second non-volatile memory device NVM12 of the second channel (Way1) receives programming commands, and if the R / B pin is busy, the memory controller 200 performs ZQ calibration on the second non-volatile memory device NVM12.

[0133] The third non-volatile memory device NVM13 of the third channel (Way2) receives programming commands, and if the R / B pin is busy, the memory controller 200 performs ZQ calibration on the third non-volatile memory device NVM13.

[0134] The fourth non-volatile memory device NVM14 of the fourth channel (Way3) receives programming commands, and if the R / B pin is busy, the memory controller 200 performs ZQ calibration on the fourth non-volatile memory device NVM14.

[0135] In other words, referencing Figure 20During the programming operation of storage system 1, multiple non-volatile memory devices sequentially receive programming commands and data through their respective connected paths, and ZQ calibration can be performed (e.g., during tZQCS) in the order in which the programming commands and data are received. Although the non-volatile memory devices connected to each path are busy, ZQ calibration can be re-performed in cases where DMA (Direct Memory Access) and tPROG segments overlap, thereby improving SI performance, depending on changes in the operating environment.

[0136] Reference Figure 21 During the programming operation of storage system 1, multiple non-volatile memory devices sequentially receive programming commands and data through each connected path. Figure 20 The difference lies in Figure 21 In ZQ calibration, when a non-volatile memory device comprises memory cells of four levels (QLC) or more, if a defense code operation needs to be performed in the event of a first error bit determination, ZQ calibration is performed first during runtime before the next programming operation is executed, and subsequent programming commands and data are received during the tPROG segment. In other words, ZQ calibration is performed on each of the multiple non-volatile memory devices before outputting subsequent programming commands to them. The ZQ calibration operation performed during runtime allows the actual cell to perform error bit determination itself, rather than errors caused by the interface, thereby improving the operational performance of the memory system.

[0137] Although embodiments of the invention have been described above with reference to the accompanying drawings, the invention is not limited to the embodiments described above and can be made in various different forms. Those skilled in the art will understand that the invention can be embodied in other specific forms without altering the technical spirit or essential features of the invention. Therefore, the above embodiments should be understood in all respects as illustrative and not restrictive.

Claims

1. A method of operating a storage system, the method comprising: Send the first access command to the first non-volatile memory device; Check the status of the first non-volatile memory device; as well as During the period when the first non-volatile memory device is in a busy state, a first ZQ calibration is performed on the first non-volatile memory device via the DQ pin of the first non-volatile memory device.

2. The method of operating the storage system as described in claim 1, further comprising: Send the second access command to the second non-volatile memory device; Check the status of the second non-volatile memory device; Perform a second ZQ calibration on the second non-volatile memory device; as well as When each of the first access command and the second access command is a read command, data is sequentially output from the first non-volatile memory device and the second non-volatile memory device. The first non-volatile memory device and the second non-volatile memory device are connected to the first channel. Specifically, the first ZQ calibration and the second ZQ calibration are performed sequentially on the first non-volatile memory device and the second non-volatile memory device, which are in a busy state. The step of executing the output data is performed after the first ZQ calibration and the second ZQ calibration are completed.

3. The method of operating the storage system as described in claim 1, further comprising: Send the second access command to the second non-volatile memory device; Check the status of the second non-volatile memory device; Perform a second ZQ calibration on the second non-volatile memory device; as well as When each of the first access command and the second access command is a read command, data is sequentially output from the first non-volatile memory device and the second non-volatile memory device. The first non-volatile memory device and the second non-volatile memory device are connected to the first channel. Specifically, the first ZQ calibration is performed during the time tRRC from read read readiness to new command in the first non-volatile memory device. During the tRRC of the second non-volatile memory device, a second ZQ calibration is performed, and The steps for sequentially outputting data include: After completing the first ZQ calibration, the first data is output from the first non-volatile memory device, and After completing the second ZQ calibration, the second data is output from the second non-volatile memory device.

4. The method of operating the storage system as described in claim 1, wherein, The step of sending the first access command includes: when the first access command is a programming command, sending the page address of the first non-volatile memory device and a programming start command to the first non-volatile memory device, and Specifically, a first ZQ calibration is performed on the pages of the first non-volatile memory device during the address-to-data loading time.

5. The method of operating the storage system as described in claim 1, wherein, The step of sending the first access command includes: when the first access command is a programming command, sending the page address of the first non-volatile memory device and a programming start command to the first non-volatile memory device, and Specifically, after the busy time of the programming activation signal has passed and during the latch dump time, the page of the first non-volatile memory device is subjected to a first ZQ calibration.

6. The method of operating the storage system as described in claim 1, in, The step of sending the first access command includes: when the first access command is a programming command, sending the page address of the first non-volatile memory device, a programming confirmation command, a programming start command, and a programming end command to the first non-volatile memory device, and Specifically, during the programming operation time following the busy time of the programming activation signal, a first ZQ calibration is performed on the pages of the first non-volatile memory device, and the busy time of the programming activation signal follows the programming confirmation command.

7. A storage system, comprising: Storage controller; as well as Multiple non-volatile memory devices are connected to a memory controller using a first signal line for sending commands and addresses and a second signal line for sending data. The first signal line and the second signal line are separate from each other, and The storage controller is configured as follows: The access command, which is the command, is sent to the first non-volatile memory device among the plurality of non-volatile memory devices using the first signal line. The logic level of the ready / busy signal is received using the R / B pin of the first non-volatile memory device during the time when the operation corresponding to the access command is performed on the first non-volatile memory device. Check the status of the first non-volatile memory device on the first signal line; A logic level responding to the ready / busy signal indicates a busy state, and a ZQ calibration is performed on the first non-volatile memory device; and After performing ZQ calibration, check the status of the first non-volatile memory device.

8. The storage system of claim 7, wherein, The memory controller performs ZQ calibration simultaneously on the first and second signal lines of the first non-volatile memory device.

9. The storage system as described in claim 7, in, The access command is a read command, and The storage controller is configured as follows: During the busy period of each of the plurality of non-volatile memory devices, ZQ calibration is sequentially performed on the plurality of non-volatile memory devices, and data read from each of the plurality of non-volatile memory devices is sequentially received via a second signal line in the order in which the ZQ calibration is completed.

10. The storage system of claim 7, wherein, The storage controller is configured as follows: The multiple programming commands, which are said commands, are sequentially output to the multiple non-volatile memory devices, and ZQ calibration is performed on the plurality of non-volatile memory devices in the order in which the plurality of programming commands are output.

11. The storage system of claim 10, wherein, Before performing subsequent programming operations on the first non-volatile memory device, the memory controller performs ZQ calibration on the first non-volatile memory device.

12. The storage system of claim 10, wherein, After receiving the programming start command and the address as the command via the first signal line, ZQ calibration is performed on the pages of the first non-volatile memory device during the address-to-data loading time.

13. The storage system of claim 10, wherein, ZQ calibration is performed on the pages of the first non-volatile memory device during the latch dump time after the busy time of the programming activation signal has passed.

14. The storage system of claim 10, wherein, After the busy period following the programming activation signal after the programming confirmation command has passed, ZQ calibration is performed on the pages of the first non-volatile memory device during the programming operation time, and Among them, the time period of the logic level representing the busy state of the ready / busy signal corresponds to the programming operation time.

15. The storage system as described in claim 7, in, The access command is an erase command, and The storage controller sequentially performs ZQ calibration on each of the plurality of non-volatile memory devices during the busy period of each of the plurality of non-volatile memory devices.

16. A storage system, comprising: Multiple non-volatile memory devices; as well as A storage controller, connected to the plurality of non-volatile memory devices, is configured to: Perform a first ZQ calibration on the powered-on plurality of non-volatile memory devices. Access commands are sent via the DQ pin of each of the plurality of non-volatile memory devices. Each of the plurality of non-volatile memory devices that operates in response to an access command receives a busy status signal indicating a busy state. A second ZQ calibration is performed on the plurality of non-volatile memory devices, and Check whether the second ZQ calibration is performed correctly for each of the plurality of nonvolatile memory devices.

17. The storage system as claimed in claim 16, in, The access command is a read command, and The storage controller is configured as follows: During the busy period of each of the plurality of non-volatile memory devices, a second ZQ calibration is performed on the plurality of non-volatile memory devices; and Data read from the plurality of nonvolatile memory devices is received sequentially in the order in which the second ZQ calibration performed on the plurality of nonvolatile memory devices is completed.

18. The storage system as claimed in claim 16, in, The access command is a programming command, and The storage controller is configured as follows: Multiple programming commands, acting as access commands, are sequentially output to the multiple non-volatile memory devices; and The second ZQ calibration is performed on the plurality of non-volatile memory devices in the order in which the plurality of programming commands are output.

19. The storage system of claim 16, wherein, The storage controller is configured as follows: The multiple current programming commands, which are access commands, are sequentially output to the multiple non-volatile memory devices; and Before outputting subsequent programming commands to the plurality of non-volatile memory devices, a second ZQ calibration is performed on each of the plurality of non-volatile memory devices, and the subsequent programming commands follow each of the plurality of current programming commands.

20. The storage system of claim 16, wherein, The access command is an erase command, and The storage controller sequentially performs a second ZQ calibration on each of the plurality of non-volatile memory devices during the period when each of the plurality of non-volatile memory devices is in a busy state.

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