Data processing method, device and system, chip and electronic equipment

Abstract

The invention discloses a data processing method, device and system, a chip and electronic equipment, and relates to the technical field of circuits, and the method comprises the steps: firstly, receiving a USB packet, storing the USB packet in a first storage space, and determining the head information and address information of the USB packet; according to the header information and the data information of the USB packet, the USB packet is packaged, at least one TRB chain is obtained, and each TRB chain comprises chain link information; and in response to a transmission request, determining a TRB chain to be transmitted according to the chain link information and the address information. In this way, the method is not limited by the software processing speed, the time of USB packet aggregation (namely TRB chain assembly) is shortened by adopting the ASIC, FPGA and other processing methods, the workload of a processor is shared, the transmission efficiency of the USB controller is improved, and then the processing performance is effectively improved. And a plurality of TRB chains can be recycled, so that the window period of USB transmission is reduced, and the transmission efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a data processing method, apparatus, system, chip, and electronic device. Background Technology

[0002] In related technologies, Universal Serial Bus (USB) packet aggregation can be implemented through software before transmission. However, this software-based approach to USB packet aggregation is limited by software processing speed, resulting in slow performance and the inability to complete aggregation in a timely manner. This leads to scenarios where the USB controller remains idle, waiting for software to aggregate USB packets, thus reducing the USB controller's transmission efficiency. Summary of the Invention

[0003] In view of this, this application provides a data processing method, apparatus, system, chip, and electronic device. Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs) can be used to accelerate USB packet aggregation, replacing the software-based USB packet aggregation method in related technologies. An internal module can first receive USB packets, store them in a first storage space, and determine the header and address information of the USB packets. Then, based on the header and data information of the USB packets, the USB packets are encapsulated to obtain at least one Transmission Request Block (TRB) chain, where each TRB chain includes chain information. In response to a transmission request, the TRB chain to be transmitted is determined based on the chain information and address information. This method is not limited by software processing speed. Using ASICs and FPGAs reduces the time for USB packet aggregation (i.e., TRB chain assembly), reduces the workload of the processor, increases the transmission efficiency of the USB controller, and thus effectively improves processing performance. Furthermore, multiple TRB chains can be used cyclically, reducing the USB transmission idle period and improving transmission efficiency.

[0004] In a first aspect, this application provides a data processing method, including:

[0005] Receive a USB packet and store the USB packet in the first storage space;

[0006] Determine the header information of the USB packet and its address information in the first storage space;

[0007] Based on the header information and the data information of the USB packet, the USB packet is encapsulated to obtain at least one Transmission Request Block (TRB) chain, wherein each TRB chain includes chain information;

[0008] In response to a transmission request, the target TRB chain to be transmitted is determined based on the chain information and the address information.

[0009] Optionally, the header information of the USB packet is determined, including:

[0010] Obtain the descriptor information of the USB packet and the USB network card protocol type;

[0011] The header information is determined based on the descriptor information and the USB network card protocol type.

[0012] Optionally, the header information is determined based on the descriptor information and the USB network card protocol type, including:

[0013] The protocol header is determined based on the USB network card protocol type, and the Media Access Control (MAC) header is determined based on the descriptor information.

[0014] Optionally, based on the header information and the data information of the USB packet, the USB packet is encapsulated to obtain at least one TRB chain, including:

[0015] Generate the first TRB configuration information corresponding to the header information, and generate the second TRB configuration information corresponding to the data information of the USB packet;

[0016] Based on the first TRB configuration information and the second TRB configuration information, the USB packet is encapsulated to obtain at least one TRB chain.

[0017] Optionally, based on the first TRB configuration information and the second TRB configuration information, the USB packet is encapsulated to obtain at least one TRB chain, including:

[0018] Extract idle TRB chains from the TRB chain resource pool;

[0019] The idle TRB chains are assembled based on the first TRB configuration information and the second TRB configuration information to obtain the at least one TRB chain.

[0020] Optionally, the method further includes:

[0021] After the target TRB chain is transmitted, the first TRB configuration information and the second TRB configuration information corresponding to the target TRB chain are released and then enter the TRB chain resource pool as idle TRB chains.

[0022] Secondly, this application provides a data processing apparatus, comprising:

[0023] The acquisition module is used to receive USB packets;

[0024] Storage module, the storage module being used to store the USB package into a first storage space;

[0025] A protocol processing module is connected to the storage module and the acquisition module respectively. The protocol processing module is used to determine the header information of the USB packet and the address information in the first storage space.

[0026] A configuration module is connected to the protocol processing module and the storage module respectively. The configuration module is used to encapsulate the USB packet according to the header information and the data information of the USB packet to obtain at least one Transmission Request Block (TRB) chain, wherein each TRB chain includes chain information.

[0027] An interaction module, connected to the configuration module, is used to determine the target TRB chain to be transmitted based on the chain information and the address information in response to a transmission request.

[0028] Optionally, the protocol processing module is used to obtain the descriptor information of the USB packet and the USB network card protocol type; and determine the header information based on the descriptor information and the USB network card protocol type.

[0029] Optionally, the protocol processing module is used to determine the protocol header according to the USB network card protocol type and to determine the MAC header according to the descriptor information.

[0030] Optionally, the configuration module is used to generate first TRB configuration information corresponding to the header information, and to generate second TRB configuration information corresponding to the data information of the USB packet; based on the first TRB configuration information and the second TRB configuration information, the USB packet is encapsulated to obtain at least one TRB chain.

[0031] Optionally, the configuration module is used to extract idle TRB chains from the TRB chain resource pool; and assemble the idle TRB chains based on the first TRB configuration information and the second TRB configuration information to obtain the at least one TRB chain.

[0032] Optionally, the configuration module is further configured to release the first TRB configuration information and the second TRB configuration information corresponding to the target TRB chain after the target TRB chain transmission is completed, and then enter the TRB chain resource pool as an idle TRB chain after release.

[0033] Thirdly, this application provides a data processing system, including:

[0034] processor;

[0035] A USB controller, which is connected to the processor;

[0036] A data processing device, connected to the processor, is configured to receive a USB packet, store the USB packet in a first storage space in memory; determine the header information of the USB packet and its address information in the first storage space; encapsulate the USB packet according to the header information and the data information of the USB packet to obtain at least one TRB chain, wherein each TRB chain includes chain information; and, in response to a transmission request, determine the target TRB chain to be transmitted according to the chain information and the address information.

[0037] The processor is used to trigger the USB controller to start transmitting the target TRB chain.

[0038] Optionally, the data processing device is used to obtain the descriptor information of the USB packet and the USB network card protocol type; and to determine the header information based on the descriptor information and the USB network card protocol type.

[0039] Optionally, the data processing device is used to determine the protocol header according to the USB network card protocol type and to determine the MAC header according to the descriptor information.

[0040] Optionally, the data processing device is used to generate first TRB configuration information corresponding to the header information, and to generate second TRB configuration information corresponding to the data information of the USB packet; based on the first TRB configuration information and the second TRB configuration information, the USB packet is encapsulated to obtain at least one TRB chain.

[0041] Optionally, the data processing device is used to extract idle TRB chains from the TRB chain resource pool; and to assemble the idle TRB chains based on the first TRB configuration information and the second TRB configuration information to obtain the at least one TRB chain.

[0042] Optionally, the data processing device is further configured to release the first TRB configuration information and the second TRB configuration information corresponding to the target TRB chain after the target TRB chain transmission is completed, and then enter the TRB chain resource pool as an idle TRB chain after release.

[0043] Fourthly, this application provides a chip including the data processing apparatus described in the second aspect.

[0044] Fifthly, this application provides an electronic device, including the data processing apparatus described in the second aspect, or the data processing system described in the third aspect, or the chip described in the fourth aspect.

[0045] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This paper shows a schematic diagram of the structure of a data processing apparatus provided in an embodiment of the present application;

[0049] Figure 2 This paper shows a schematic diagram of the structure of a data processing system provided in an embodiment of this application;

[0050] Figure 3 A flowchart illustrating a data processing method provided in an embodiment of this application is shown;

[0051] Figure 4 A schematic diagram illustrating an example provided in an embodiment of this application is shown;

[0052] Figure 5 A schematic diagram illustrating another example provided in an embodiment of this application is shown;

[0053] Figure 6 A schematic diagram illustrating yet another example provided in the embodiments of this application is shown;

[0054] Figure 7 This illustration shows a structural schematic diagram of an electronic device provided in an embodiment of this application;

[0055] Figure 1 middle:

[0056] 11-Acquisition module, 12-Protocol processing module, 13-Configuration module, 14-Interaction module, 15-Storage module. Detailed Implementation

[0057] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0058] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0059] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0060] The present application will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in the embodiments of the present application can be combined with each other.

[0061] The following is combined Figure 1 This application describes a data processing device based on an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or the like, provided in an embodiment of this application.

[0062] This application provides a data processing apparatus, such as... Figure 1 As shown, it includes: acquisition module 11, protocol processing module 12, configuration module 13, interaction module 14, and storage module 15;

[0063] The acquisition module 11 is used to receive USB packets. In some examples, the acquisition module 11 can also obtain the descriptor information of the USB packets. For example, the acquisition module 11 receives the descriptor of the USB packets sent by the transport layer and parses the descriptor to obtain descriptor information such as the storage address, offset address, data length, and whether a MAC header is included in the USB packets. The acquisition module 11 can send the obtained descriptor information of the USB packets to the protocol processing module 12 to determine the header information of the USB packets.

[0064] Storage module 15 is connected to acquisition module 11. The storage module is used to store the USB package into the first storage space, such as the storage space in memory.

[0065] The protocol processing module 12 is connected to the acquisition module 11 and the storage module 15 respectively. The protocol processing module 12 is used to determine the header information of the USB packet and the address information in the first storage space.

[0066] In some embodiments, the protocol processing module 12 is used to obtain the descriptor information of the USB packet and the USB network card protocol type; then, based on the descriptor information of the USB packet and the USB network card protocol type, it determines the header information of the USB packet. The protocol processing module 12 can be responsible for encapsulating protocol headers according to protocols such as the Remote Network Driver Interface Specification (RNDIS), Network Control Model (NCM), and Mobile Broadband Interface Model (MBIM). If a Media Access Control (MAC) header is required, the protocol processing module 12 can also be responsible for adding the MAC header.

[0067] In some examples, the protocol processing module is used to determine the protocol header based on the USB network card protocol type and the MAC header based on the descriptor information. For example, it generates the corresponding protocol header based on the USB network card protocol type and generates the corresponding MAC header when it determines that a MAC header needs to be added based on the descriptor information, and then determines the header information based on the protocol header and the MAC header.

[0068] The configuration module 13 is connected to the protocol processing module 12 and the storage module 15 respectively. The configuration module 13 is used to encapsulate the USB packet according to the header information and data information of the USB packet to obtain at least one TRB chain. Each TRB chain includes chain information, which can be used to identify the TRB chain.

[0069] For example, configuration module 13 can be a TRB configuration module, responsible for configuring the USB network card TRB chain. Configuration module 13 generates first TRB configuration information corresponding to the header information and second TRB configuration information corresponding to the data information of the USB packet. Based on the generated first and second TRB configuration information, it assembles the TRB chain, that is, based on the first and second TRB configuration information, it encapsulates the USB packet to obtain at least one TRB chain. The TRB is used to manage the data structure of USB transmission, containing various information about the transmission request, including transmission length, transmission direction, transmission type, and the location of the transmission data buffer, as well as other necessary control information.

[0070] The interaction module 14, which can be a hardware / software interaction module, is responsible for data processing and interrupt handling for hardware / software interaction. The interaction module 14 is connected to the configuration module 13. In response to a transmission request, the interaction module 14 determines the target TRB chain to be transmitted based on the chain information and address information of the TRB chain. Subsequently, the interaction module 14 can instruct the processor to read the configuration information of the target TRB chain. This processor can be a Central Processing Unit (CPU), etc., so that the processor triggers the USB controller to start transmission based on the configuration information of the target TRB chain, such as transmitting USB protocol network data packets to the receiving end, which can be a Personal Computer (PC) terminal, etc.

[0071] One or more TRBs are prepared for each piece of data to be transmitted. These TRBs can be chained together to form a TRB chain, allowing the USB controller to execute a series of operations sequentially without waiting for new instructions, thus achieving continuous data transmission. In some examples, software processing can be used. Once the total length of the aggregated USB packets reaches a threshold or other conditions are met, one TRB points to the protocol header, and other TRBs point to the Internet Protocol (IP) packets in memory. Through chained TRBs, the protocol header and IP packets are linked together. After the TRB chain is complete, the software notifies the USB controller to start the transmission. This method of USB packet aggregation is limited by software processing speed, resulting in relatively slow processing performance. Furthermore, software execution depends on the processor, increasing the processor's workload and impacting the efficiency of other software tasks.

[0072] The technical solution of this application embodiment is processed by a data processing device based on ASIC, FPGA, etc. (i.e., a USB packet accelerator). The processing method of ASIC, FPGA, etc. reduces the time of USB packet aggregation (i.e. TRB chain assembly), which is equivalent to accelerating USB packet aggregation through logic such as ASIC and FPGA, and also reduces the workload of the processor, increases the transmission efficiency of the USB controller, and thus effectively improves the processing performance.

[0073] Optionally, the storage module 15 can be used to write the generated header information, USB packet data information, and corresponding TRB configuration information into memory. For example, the storage module can be a Direct Memory Access (DMA) module, responsible for writing data such as the MAC header, RNDIS / NCM / MBIM protocol header, and TRB configuration information into Double Data Rate (DDR) dynamic memory. The memory may include TRB space, protocol header space, and IP packet space. For the TRB space, a fixed memory segment is allocated in the DDR space to store TRB chain information; the TRB chain is used to notify the USB controller of the location and length of data transmission. For the protocol header space, a fixed memory segment is allocated in the DDR space to store the MAC header and RNDIS / NCM / MBIM protocol header. For the IP packet space, dynamically allocated memory space in the DDR space is used to store the data of each USB packet.

[0074] Optionally, the configuration module 13 is further configured to write the configuration information of the assembled target TRB chain into the waiting transmission queue; correspondingly, the interaction module 14 is further configured to determine the target TRB chain to be transmitted based on the configuration information of the target TRB chain written in the waiting transmission queue, i.e., in response to the transmission request, according to the chain information and address information of the target TRB chain, and determine to notify the processor to read the target TRB chain. In this way, the interaction module 14 can clearly notify the processor when to read.

[0075] For example, when the TRB chain breakage condition is met, the configuration module 13 writes information such as the index and starting address of the completed TRB chain into the First In First Out (FIFO)-0 queue (waiting for transmission) of the interaction module 14. The TRB chain breakage conditions include data length reaching a threshold, / or the number of TRBs reaching a threshold, and / or chain assembly timeout. After detecting that FIFO-0 is not empty, the interaction module 14 sends a TRB assembly completion interrupt high to the processor, notifying the processor to read the completed TRB chain.

[0076] Optionally, the interaction module 14 is further configured to release the header information, USB packet, and corresponding TRB configuration information of the target TRB chain from memory when the configuration information of the target TRB chain is detected to be written into the transmission completion queue. Specifically, the processor writes the configuration information of the target TRB chain into the transmission completion queue when it determines that the data transmission corresponding to the target TRB chain is complete. This method saves memory storage space by promptly releasing the corresponding stored data when the data transmission of the target TRB chain is complete.

[0077] For example, after the USB controller completes the transmission, it sends a transmission completion interrupt high to the processor. Upon receiving the transmission completion interrupt, the processor reads the start address of the completed TRB chain from the USB controller, obtains the index of the TRB chain, and finally writes the TRB chain index and start address into FIFO-1 of the interaction module 14, i.e., the transmission completion queue. After the interaction module 14 detects that FIFO-1 is not empty, it reads the data in FIFO-1 and releases the protocol header space and IP packet space of the TRB chain in memory according to the TRB chain index. The TRB chain can then be reused for subsequent chain transmissions.

[0078] Optionally, the configuration module 13 is specifically used to extract idle TRB chains from the TRB chain resource pool, and assemble the idle TRB chains based on the generated first TRB configuration information and second TRB configuration information to obtain at least one TRB chain. The TRB chain resource pool includes multiple TRB chains for assembly. After the target TRB chain is transmitted, the first TRB configuration information and second TRB configuration information corresponding to the target TRB chain are released, and after release, they enter the TRB chain resource pool as idle TRB chains. That is, the target TRB chain is released and then enters the TRB chain resource pool as an idle TRB chain for use.

[0079] For example, to improve the transmission efficiency of the USB controller, this data processing device can be configured to have multiple TRB chains available, each chain containing multiple TRBs and multiple protocol header spaces. When the USB controller transmits the first TRB chain, this data processing device begins assembling the second TRB chain. After assembly, the data is written to the waiting-to-transmit queue FIFO-0, and then the assembly of the third TRB chain begins. When the USB controller completes its transmission, the processor receives a transmission completion interrupt from the controller. The processor immediately reads the waiting-to-transmit queue FIFO-0, then notifies the USB controller to start the transmission of the second TRB chain. The processor then writes the first TRB chain information to the transmission completion queue FIFO-1, notifies the data processing device to release the first TRB chain, after which the first TRB chain can continue to be assembled.

[0080] Furthermore, embodiments of this application provide a chip, which may include, for example... Figure 1 The data processing apparatus shown may be a USB packet accelerator based on ASIC, FPGA, etc., and the chip may include the USB packet accelerator.

[0081] The following is combined Figure 2 This application describes a data processing system provided in an embodiment.

[0082] This application provides a data processing system, such as... Figure 2 As shown, it includes: a processor, a USB controller, and such as Figure 1 The data processing device shown.

[0083] The processor can be a CPU or similar device, and it can be connected to a data processing device and a USB controller.

[0084] The data processing device can be used to receive USB packets, store the USB packets in a first storage space in memory; determine the header information of the USB packet and the address information in the first storage space; encapsulate the USB packet according to the header information and the data information of the USB packet to obtain at least one TRB chain, wherein each TRB chain includes chain information; in response to a transmission request, determine the target TRB chain to be transmitted according to the chain information and the address information; subsequently, the processor can be notified to read the configuration information of the assembled target TRB chain. The processor can be used to trigger the USB controller to start transmitting the target TRB chain based on the configuration information of the target TRB chain.

[0085] Optionally, the data processing device can be used to obtain the descriptor information of the USB packet and the USB network card protocol type; and then determine the header information of the USB packet based on the descriptor information and the USB network card protocol type. For example, it can generate the corresponding protocol header based on the USB network card protocol type, and generate the corresponding MAC header when it is determined from the descriptor information that a MAC header needs to be added.

[0086] Optionally, the data processing device generates first TRB configuration information corresponding to the header information of the USB packet, and generates second TRB configuration information corresponding to the data information of the USB packet; based on the first TRB configuration information and the second TRB configuration information, it encapsulates the USB packet to obtain at least one TRB chain. The TRB is used to manage the data structure of USB transmission, containing various information about the transmission request, including transmission length, transmission direction, transmission type, and the location of the transmission data buffer, as well as other necessary control information.

[0087] Optionally, the data processing device is used to extract idle TRB chains from the TRB chain resource pool; and to assemble the idle TRB chains based on the first TRB configuration information and the second TRB configuration information to obtain at least one TRB chain.

[0088] Optionally, the data processing device is also used to release the first TRB configuration information and the second TRB configuration information corresponding to the target TRB chain after the target TRB chain transmission is completed, and then enter the TRB chain resource pool as an idle TRB chain after release.

[0089] USB packet aggregation can be accelerated using ASICs, FPGAs, etc., replacing the software-based approach used in related technologies. An internal module first receives USB packets, stores them in a first storage space, and determines the packet's header and address information. Then, based on the header and data, the USB packet is encapsulated to obtain at least one Transmission Request Block (TRB) chain, where each TRB chain includes a chain key. In response to a transmission request, the TRB chain to be transmitted is determined based on this chain key and address information. This method avoids the limitations of software processing speed, reduces the time for USB packet aggregation (i.e., TRB chain assembly) by using ASICs and FPGAs, distributes the processor's workload, increases the transmission efficiency of the USB controller, and thus effectively improves processing performance. Furthermore, multiple TRB chains can be used cyclically, reducing the USB transmission idle period and further improving transmission efficiency.

[0090] Furthermore, embodiments of this application also provide a data processing method, which can be executed by a data processing device, such as... Figure 3 As shown, the method includes:

[0091] Step 201: Receive the USB packet and store it in the first storage space.

[0092] Step 202: Determine the header information of the USB packet and the address information in the first storage space.

[0093] In some embodiments, the descriptor information of the USB packet and the USB network card protocol type can be obtained; the header information of the USB packet can be determined based on the descriptor information of the USB packet and the USB network card protocol type.

[0094] For example, the transport layer generates a USB packet descriptor based on information such as the address and length stored in the IP packet space, and then sends it to the data processing device. The data processing device parses the descriptor according to the descriptor format agreed upon with the transport layer to obtain descriptor information such as the IP packet's storage address, offset address, data length, and whether it includes a MAC header.

[0095] In some embodiments, the protocol header is determined based on the USB network card protocol type, and the MAC header is determined based on the descriptor information of the USB packet. For example, the data processing device can generate the corresponding protocol header based on the USB network card protocol type, and generate the corresponding MAC header when it is determined from the descriptor information that a MAC header needs to be added, thereby generating the header information.

[0096] Step 203: Based on the header information and data information of the USB packet, encapsulate the USB packet to obtain at least one TRB chain.

[0097] Each TRB chain includes chain information.

[0098] In some embodiments, first TRB configuration information corresponding to the header information is generated, and second TRB configuration information corresponding to the data information of the USB packet is generated; then, based on the first TRB configuration information and the second TRB configuration information, the USB packet is encapsulated to obtain at least one TRB chain.

[0099] In some examples, header information, USB packets, and corresponding TRB configuration information can be written into memory. For instance, the data processing device generates the corresponding protocol header based on the protocol type of the current network interface card (NIC). If a MAC header needs to be added, it also needs to be generated. The generated MAC header and protocol header are then interacted with the bus and written into the protocol header space. After the bus returns a signal indicating that the protocol header writing is complete, the information in the descriptor is updated, increasing the storage address and length of the protocol header. Based on the descriptor information, the TRB configuration information corresponding to the protocol header and the TRB configuration information of the USB data packet are generated. The TRB configuration mainly includes the storage address, length, and transmission mode. Based on the generated TRB configuration information, a TRB chain is assembled to obtain at least one TRB chain.

[0100] Step 204: In response to the transmission request, determine the target TRB chain to be transmitted based on the chain information and address information.

[0101] In some embodiments, when the aggregate length of the USB packet reaches a preset length threshold, and / or the number of assembled TRBs reaches a preset quantity threshold, and / or the assembly time reaches a preset time threshold, the target TRB chain that has been completed is determined.

[0102] In some examples, the configuration information of the completed target TRB chain can be written into the waiting transmission queue; then the data processing device determines to notify the processor to read based on the configuration information of the target TRB chain written in the waiting transmission queue.

[0103] In some embodiments, when the data processing device detects that the configuration information of the target TRB chain has been written into the transmission completion queue, it releases the header information and USB packet corresponding to the target TRB chain and the corresponding TRB configuration information from memory. The processor writes the configuration information of the target TRB chain into the transmission completion queue when it determines that the data transmission corresponding to the target TRB chain has been completed.

[0104] Furthermore, in some embodiments, idle TRB chains are extracted from the TRB chain resource pool; the idle TRB chains are assembled based on the first TRB configuration information and the second TRB configuration information to obtain at least one TRB chain. Correspondingly, after the target TRB chain is transmitted, the first TRB configuration information and the second TRB configuration information corresponding to the target TRB chain are released and then enter the TRB chain resource pool as idle TRB chains.

[0105] Based on the descriptions of the above embodiments, the following examples are given, but are not limited thereto:

[0106] For example, such as Figure 4 As shown, this application provides a data processing apparatus, which is equivalent to an apparatus for accelerating USB packet aggregation through ASIC logic, including as follows: Figure 1 The module shown includes the acquisition module 11, protocol processing module 12, configuration module 13, interaction module 14, and storage module 15. For example... Figure 4 As shown, the working process of the device may include (1) to (12).

[0107] (1) The transport layer generates a USB packet descriptor based on the address, length and other information stored in the IP packet space for the data to be transmitted to the receiving end (such as a PC terminal), and then sends it to the data processing device.

[0108] (2) The data acquisition module of the data processing device performs descriptor parsing according to the descriptor format agreed upon with the transport layer, and obtains information such as the storage address, offset address, data length, and whether or not there is a MAC header for the IP packet. After extracting the key information, it is handed over to the protocol processing module.

[0109] (3) The protocol processing module generates the corresponding protocol header according to the protocol type of the current transmission network card. If a MAC header needs to be added, a MAC header also needs to be generated. The generated MAC header and protocol header are then sent to the storage module, which interacts with the bus to write the protocol header space.

[0110] (4) After the bus returns the write protocol header completion signal, the protocol processing module updates the information in the descriptor, adds the storage address and length of the protocol header, and writes it to the configuration module;

[0111] (5) The configuration module generates TRB configuration information corresponding to the protocol header and TRB configuration information of the USB data packet based on the descriptor information. The TRB configuration mainly includes the storage address, length, transmission mode, etc.

[0112] (6) When the TRB chain breaks, the configuration module writes the index of the completed TRB chain and the TRB chain start address and other information into the FIFO-0 of the interaction module; among them, the TRB chain breaks include data length reaching the threshold, TRB number reaching the threshold, timeout, etc.

[0113] (7) After the interaction module detects that FIFO-0 is not empty, it pulls high the TRB assembly completion interrupt to the processor (such as CPU) to notify the processor to read the TRB chain that has been assembled.

[0114] (8) After receiving the TRB assembly completion interrupt, the processor reads the TRB chain index, TRB start address and other information from the FIFO-0 of the interaction module, and then notifies the USB controller to start the TRB chain transmission.

[0115] (9) The USB controller first reads the TRB chain information from the DDR space, then reads the protocol header and USB packet information from the DDR space into the controller's internal buffer according to the TRB chain information, and finally transmits the protocol header and USB packet to the receiving end (such as a PC terminal) in sequence.

[0116] (10) After the USB controller completes the transfer, it pulls the transfer completion interrupt high for the processor.

[0117] (11) After receiving the transmission completion interrupt, the processor reads the start address of the TRB chain that the transmission is complete from the USB controller, then obtains the index of the TRB chain, and finally writes the index and start address of the TRB chain into the FIFO-1 of the interaction module.

[0118] (12) After the interaction module detects that FIFO-1 is not empty, it reads the data of FIFO-1, releases the protocol header space and IP packet space of the TRB chain according to the TRB chain index, and reuses the TRB chain for chain transmission.

[0119] Furthermore, to improve the transmission efficiency of the USB controller, multiple TRB chains are available internally in the data processing device, each chain containing multiple TRBs and multiple protocol header spaces. When the USB controller transmits the first TRB chain, the data processing device begins assembling the second TRB chain. After assembly, the data is written to the waiting queue FIFO-0, and then the assembly of the third TRB chain begins.

[0120] When the USB controller completes the transfer, the processor receives a transfer completion interrupt from the USB controller. The processor immediately reads the waiting transfer queue FIFO-0, then notifies the USB controller to start the transfer of the second TRB chain. Next, the processor writes the first TRB chain information into the transfer completion queue FIFO-1, notifies the data processing device to release the first TRB chain, and after release, the first TRB chain can continue to be assembled.

[0121] like Figure 5 and Figure 6 As shown, in the initial or idle state, all four TRB chains are idle and cached in the TRB chain resource pool. When a USB packet needs to be transmitted, the data processing device retrieves a TRB chain from the TRB chain resource pool for assembly. When the transmission length corresponding to a TRB chain reaches a threshold, or the number of TRBs reaches a threshold, or the protocol header space reaches a threshold, the chain break condition is met. The TRB is written to the waiting transmission queue FIFO-0, and the assembly completion interrupt notification processor is pulled high. Then, another TRB chain is retrieved from the TRB chain resource pool for assembly. When the TRB chain resource pool is empty, the hardware pauses in the TRB chain request state, reverses the input of data packets, and waits for the TRB chain to be released after transmission is completed before reuse.

[0122] like Figure 6 As shown, the process of multiple TRB chains being used in a loop includes ① to ⑨.

[0123] ① The transport layer inputs the USB packet descriptor to the data processing device, which then assembles the descriptor into the allocated TRB chain-3; (if no TRB chain is allocated, then step ② is required).

[0124] ② The data processing device requests an idle TRB chain from the TRB chain resource pool;

[0125] ③ When TRB chain-2 reaches the disconnection condition, write the TRB chain-2 information into the waiting transmission queue FIFO-0;

[0126] ④ The data processing device pulls up the interrupt signal to signal the completion of processor assembly;

[0127] ⑤ The processor notifies the USB controller to initiate TRB chain-1 transfer;

[0128] ⑥ The USB controller sequentially transmits the protocol header and USB packet corresponding to TRB chain-1 to the receiving end (such as a PC terminal);

[0129] ⑦ After the USB controller completes the transfer, it pulls the transfer completion interrupt high for the processor;

[0130] ⑧ The processor writes the index and starting address of the completed TRB chain-0 into the transmission completion queue FIFO-1;

[0131] ⑨ The data processing device releases the memory of TRB chain-0 and then writes it into the TRB chain resource pool for reuse;

[0132] Using multiple TRB chains in a loop minimizes the USB controller's waiting time, allowing it to quickly initiate the next transfer once the current one is complete. Furthermore, assembling TRB chains using an ASIC is more than ten times faster than software-based assembly. The processor software only needs to handle interrupts, instruct the controller to start the transfer, and notify the data processing device to release the TRB chains, reducing the processor's workload and significantly improving the USB controller's transfer efficiency.

[0133] Furthermore, embodiments of this application provide an electronic device, including as follows: Figure 1 The data processing device shown, or as Figure 2 The data processing system shown, or the chip (which includes, for example, the following) Figure 1 (The data processing device shown).

[0134] like Figure 7 The diagram shown is a hardware structure schematic of an electronic device according to an embodiment of this application, including:

[0135] At least one processor 301;

[0136] Memory 302 communicatively connected to at least one of the processors 301;

[0137] Input device 303;

[0138] Display device 304.

[0139] The processor 301, memory 302, input device 303, and display device 304 can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0140] Input device 303 can receive user clicks and generate signal inputs related to user settings and function control for data processing methods. Display device 304 may include display screens or other display devices.

[0141] Optionally, the aforementioned electronic device may also include a user interface, a network interface, a camera, radio frequency (RF) circuitry, sensors, audio circuitry, a Wi-Fi module, etc. The user interface may include a display screen, input units such as a keyboard, etc., and optional user interfaces may also include USB interfaces, card reader interfaces, etc. The network interface may optionally include standard wired interfaces, wireless interfaces (such as Wi-Fi interfaces), etc.

[0142] Those skilled in the art will understand that the physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.

[0143] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0144] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A data processing method, characterized in that, include: Receive Universal Serial Bus (USB) packets and store the USB packets in the first storage space; Determine the header information of the USB packet and its address information in the first storage space; Based on the header information and the data information of the USB packet, the USB packet is encapsulated to obtain at least one Transmission Request Block (TRB) chain, wherein each TRB chain includes chain information; In response to a transmission request, the target TRB chain to be transmitted is determined based on the chain information and the address information.

2. The method according to claim 1, characterized in that, Determining the header information of the USB packet includes: Obtain the descriptor information of the USB packet and the USB network card protocol type; The header information is determined based on the descriptor information and the USB network card protocol type.

3. The method according to claim 2, characterized in that, The header information is determined based on the descriptor information and the USB network card protocol type, including: The protocol header is determined based on the USB network card protocol type, and the Media Access Control (MAC) header is determined based on the descriptor information.

4. The method according to claim 1, characterized in that, Based on the header information and the data information of the USB packet, the USB packet is encapsulated to obtain at least one TRB chain, including: Generate the first TRB configuration information corresponding to the header information, and generate the second TRB configuration information corresponding to the data information of the USB packet; Based on the first TRB configuration information and the second TRB configuration information, the USB packet is encapsulated to obtain at least one TRB chain.

5. The method according to claim 4, characterized in that, Based on the first TRB configuration information and the second TRB configuration information, the USB packet is encapsulated to obtain at least one TRB chain, including: Extract idle TRB chains from the TRB chain resource pool; The idle TRB chains are assembled based on the first TRB configuration information and the second TRB configuration information to obtain the at least one TRB chain.

6. The method according to claim 5, characterized in that, The method further includes: After the target TRB chain is transmitted, the first TRB configuration information and the second TRB configuration information corresponding to the target TRB chain are released and then enter the TRB chain resource pool as idle TRB chains.

7. A data processing apparatus, characterized in that, include: The acquisition module is used to receive Universal Serial Bus (USB) packets; Storage module, the storage module being used to store the USB package into a first storage space; A protocol processing module is connected to the storage module and the acquisition module respectively. The protocol processing module is used to determine the header information of the USB packet and the address information in the first storage space. A configuration module is connected to the protocol processing module and the storage module respectively. The configuration module is used to encapsulate the USB packet according to the header information and the data information of the USB packet to obtain at least one Transmission Request Block (TRB) chain, wherein each TRB chain includes chain information. An interaction module, connected to the configuration module, is used to determine the target TRB chain to be transmitted based on the chain information and the address information in response to a transmission request.

8. The apparatus according to claim 7, characterized in that, The protocol processing module is used to obtain the descriptor information of the USB packet and the USB network card protocol type; and to determine the header information based on the descriptor information and the USB network card protocol type.

9. The apparatus according to claim 8, characterized in that, The protocol processing module is used to determine the protocol header according to the USB network card protocol type and to determine the Media Access Control (MAC) header according to the descriptor information.

10. The apparatus according to claim 7, characterized in that, The configuration module is used to generate first TRB configuration information corresponding to the header information, and to generate second TRB configuration information corresponding to the data information of the USB packet; Based on the first TRB configuration information and the second TRB configuration information, the USB packet is encapsulated to obtain at least one TRB chain.

11. The apparatus according to claim 10, characterized in that, The configuration module is used to extract idle TRB chains from the TRB chain resource pool; and to assemble the idle TRB chains based on the first TRB configuration information and the second TRB configuration information to obtain the at least one TRB chain.

12. The apparatus according to claim 11, characterized in that, The configuration module is also used to release the first TRB configuration information and the second TRB configuration information corresponding to the target TRB chain after the target TRB chain is transmitted, and then enter the TRB chain resource pool as an idle TRB chain after release.

13. A data processing system, characterized in that, include: processor; A Universal Serial Bus (USB) controller, which is connected to the processor; A data processing device, connected to the processor, is used to receive Universal Serial Bus (USB) packets and store the USB packets in a first storage space in memory; Determine the header information of the USB packet and its address information in the first storage space; Based on the header information and the data information of the USB packet, the USB packet is encapsulated to obtain at least one Transmission Request Block (TRB) chain, wherein each TRB chain includes chain information; in response to the transmission request, the target TRB chain to be transmitted is determined based on the chain information and the address information. The processor is used to trigger the USB controller to start transmitting the target TRB chain.

14. The system according to claim 13, characterized in that, The data processing device is used to obtain the descriptor information of the USB packet and the USB network card protocol type; and to determine the header information based on the descriptor information and the USB network card protocol type.

15. The system according to claim 14, characterized in that, The data processing device is used to determine the protocol header according to the USB network card protocol type and to determine the Media Access Control (MAC) header according to the descriptor information.

16. The system according to claim 13, characterized in that, The data processing device is used to generate first TRB configuration information corresponding to the header information, and to generate second TRB configuration information corresponding to the data information of the USB packet; Based on the first TRB configuration information and the second TRB configuration information, the USB packet is encapsulated to obtain at least one TRB chain.

17. The system according to claim 16, characterized in that, The data processing device is used to extract idle TRB chains from the TRB chain resource pool; and to assemble the idle TRB chains based on the first TRB configuration information and the second TRB configuration information to obtain the at least one TRB chain.

18. The system according to claim 17, characterized in that, The data processing device is further configured to release the first TRB configuration information and the second TRB configuration information corresponding to the target TRB chain after the target TRB chain transmission is completed, and then enter the TRB chain resource pool as an idle TRB chain after release.

19. A chip, characterized in that, The data processing apparatus includes any one of claims 7 to 12.

20. An electronic device, characterized in that, It includes the data processing apparatus according to any one of claims 7 to 12, or the data processing system according to any one of claims 13 to 18, or the chip according to claim 19.

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