Chip system, method for processing virtual interrupt and corresponding device

Abstract

The invention discloses a chip system which is applied to the technical field of virtualization. The chip system comprises a source physical processor, a control device, an intermediate device, a sending device and a target physical processor, a host machine or a virtual machine runs on the source physical processor, and a register in the control device receives information written by the host machine or the virtual machine and used for triggering virtual interruption. The control device sends the information used for triggering the virtual interrupt in the register to the intermediate device; the intermediate device triggers the virtual interrupt according to the information for triggering the virtual interrupt and sends the virtual interrupt to the sending device; the transmission device transmits the virtual interrupt to the target physical processor. The scheme is used for reducing the overhead of switching from the virtual machine to the host machine or from the user mode of the host machine to the kernel mode of the host machine due to virtual interruption.

Description

[0001] This application is a divisional application. The original application has the application number 202011108332.3 and the original application date is October 15, 2020. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of virtualization technology, specifically to a chip system, a method for handling virtual interrupts, and a corresponding device. Background Technology

[0003] Virtual interrupts are an essential component of virtualization technology. Virtual machines (VMs) run on computer devices, and the notifications from hardware devices such as disks and input / output (I / O) devices to the VMs, as well as various synchronization and coordination tasks within the VMs, all rely on virtual interrupts. A virtual interrupt is an event that can originate from various sources. The handling of such events differs depending on their source, but each type of event will notify the VM as an interrupt received during runtime.

[0004] Regardless of the source of the virtual interrupt, before it finally reaches the virtual machine, the host machine needs to use its various mechanisms to send the virtual interrupt from its source to the destination virtual machine. During this process, the processor's control flow needs to switch from the currently executing virtual machine to the host machine, or from the host machine's user mode to the host machine's kernel mode, resulting in significant switching overhead. Summary of the Invention

[0005] This application provides a chip system, a method for handling virtual interrupts, and corresponding apparatus to reduce the switching overhead caused by virtual interrupts when switching from a virtual machine to the host machine, or from the host machine's user mode to the host machine's kernel mode. This application also provides corresponding computer equipment, computer storage media, and computer program products.

[0006] The first aspect of this application provides a chip system, including: a source physical processor, a control device, an intermediate device, a transmitting device, and a target physical processor. The source physical processor is used to run a host machine or a virtual machine. The control device includes a register for receiving information for triggering a virtual interrupt, which may come from the host machine or the virtual machine. The control device is used to: send the information for triggering a virtual interrupt in the register to the intermediate device. The intermediate device is used to: trigger a virtual interrupt according to the information for triggering a virtual interrupt and send the virtual interrupt to the transmitting device. The transmitting device is used to: receive the virtual interrupt from the intermediate device and send the virtual interrupt to the target physical processor.

[0007] In this application, the chip system can be a system-on-chip (SOC), where the source physical processor and the target physical processor can each be a processing unit, such as a physical core. The control device, intermediate device, and transmitting device can all be implemented through hardware circuitry or software. The source physical processor and the target physical processor can be physical cores in a multi-core processor. A multi-core processor includes multiple physical cores, which are integrated into the processor and are a type of processing unit. For example, a dual-core processor can be understood as a processor with two physical cores. The control device and the transmitting device can be deployed within the multi-core processor and coupled to the source physical processor and the target physical processor. The intermediate device can be deployed within the multi-core processor or on peripheral devices / components coupled to the multi-core processor. The system-on-chip can include a multi-core processor and peripheral devices / components coupled to the multi-core processor. Any physical processor in the chip system can serve as either a source physical processor or a target physical processor.

[0008] In this application, a virtual interrupt refers to an interrupt sent to the virtual machine (VM) by hardware devices in a computer system, the host machine, the virtual machine's clock, or the virtual machine's virtual processor. The hardware devices that generate this virtual interrupt can be disks, network cards, sound cards, mice, hard drives, etc., within the computer system. A physical interrupt refers to an interrupt sent to the physical processor by a hardware device. Physical interrupts are handled by the host machine, while virtual interrupts are handled by the virtual machine.

[0009] It should be noted that one specific implementation of the virtual processor mentioned in the various embodiments of this application can be a virtual central processing unit (vCPU). The term "vCPU" mentioned later can also be understood as "virtual processor".

[0010] In this application, virtual interrupts can include virtual local interrupts, virtual software interrupts, virtual device interrupts, and direct peripheral interrupts. A virtual local interrupt refers to an interrupt issued by a virtual local device simulated by the virtual machine or an interrupt issued by a local device of a specific vCPU of the virtual machine, such as a clock interrupt issued by a timer of a specific vCPU of the virtual machine. A virtual software interrupt is triggered by software, typically an interrupt issued by one vCPU of the virtual machine to another vCPU of the same virtual machine. A virtual machine can have multiple vCPUs, which can run on different physical processors at any given time to execute different tasks of the virtual machine. Virtual software interrupts occur when the tasks executed by different vCPUs have dependencies or require scheduling. A virtual device interrupt is an interrupt triggered by a hardware device simulated by the host machine, such as an interrupt generated by the host machine simulating a virtual machine disk controller or other hardware devices.

[0011] In this application, the control device may include at least one register, wherein each register may be used to receive one type of information for triggering a virtual interrupt. For example, it may include three registers: one register for receiving information for triggering a virtual local interrupt, one register for receiving information for triggering a virtual software interrupt, and one register for receiving information for triggering a virtual device interrupt. Of course, in this control device, only one register may be configured for virtual interrupts, and the information used to trigger each type of virtual interrupt is different; the type of virtual interrupt can be identified by the information received by the register.

[0012] There can be one or more intermediate devices. Each physical processor can have its own transmitting device, or multiple physical processors can share a single transmitting device.

[0013] As described in the first aspect above, this first aspect involves setting up a dedicated register in the control device for handling virtual interrupts. Thus, the host machine or virtual machine in user mode or kernel mode can directly write information for triggering virtual interrupts into this register. The control device can then send this information to an intermediate device, which triggers the virtual interrupt. The intermediate device then sends the virtual interrupt to a sending device, which in turn sends it to the target physical processor. In the solution provided by this application, both the host machine and the virtual machine can directly access the register to write information for triggering virtual interrupts, thereby sending the virtual interrupt out. Therefore, compared to the prior art, the solution provided by this application does not require the source physical processor to perform a switch from the virtual machine to the host machine, nor does it require the source physical processor to perform a switch from the host machine's user mode to the host machine's kernel mode, thereby reducing the switching overhead caused by handling virtual interrupts and improving the performance of the chip system.

[0014] In one possible implementation of the first aspect, the virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor; the register is used to: receive information written by the virtual machine to trigger the virtual local interrupt; the sending device is used to: send the virtual local interrupt to the first virtual processor vCPU of the virtual machine, the first vCPU running on the source physical processor.

[0015] In this possible implementation, because the virtual local interrupt is an in-kernel interrupt, the target physical processor and the source physical processor are the same physical processor. The intermediate device can be a timer, and the virtual local interrupt can be a clock interrupt. A physical processor will only run one vCPU of one virtual machine at a time. Sending the virtual local interrupt to that vCPU completes the operation of sending the virtual local interrupt to the virtual machine. As can be seen from this possible implementation, the process of handling the virtual local interrupt does not require the source physical processor to perform a switch from the virtual machine to the host machine, thereby reducing the switching overhead caused by handling virtual local interrupts and improving the performance of the chip system.

[0016] In one possible implementation of the first aspect, the virtual interrupt is a virtual software interrupt. The information used to trigger the virtual interrupt includes the identifier of the second vCPU written from the first vCPU of the virtual machine to the register, where the second vCPU is the vCPU of the virtual machine running on the target physical processor. The control device is used to: read the identifier of the second vCPU from the register and obtain the identifier of the virtual machine; and send the identifier of the virtual machine and the identifier of the second vCPU to an intermediate device. The intermediate device is used to: determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from a first correspondence relationship based on the identifier of the virtual machine and the identifier of the second vCPU; wherein the first correspondence relationship is used to record the correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; and send the virtual software interrupt to a sending device corresponding to the target physical processor. The sending device is used to: send the virtual software interrupt to the second vCPU running on the target physical processor.

[0017] In this possible implementation, the virtual software interrupt is an interrupt sent by the first vCPU of the virtual machine to the second vCPU of the same virtual machine. Therefore, when the first vCPU of the virtual machine triggers the virtual software interrupt, it needs to write the identifier of the second vCPU into a register. A virtual machine can have multiple vCPUs. VCPUs belonging to the same virtual machine can run on a single physical processor in a time-sharing manner. For example, vCPU1 of virtual machine 1 can run on physical processor 1 first. After physical processor 1 finishes running vCPU1, vCPU2 of virtual machine 1 can run. Multiple vCPUs belonging to the same virtual machine can also run on different physical processors. At any given time, different vCPUs can run on different physical processors. For example, vCPU1 of virtual machine 1 can run on physical processor 1, and vCPU2 of virtual machine 1 can run on physical processor 2. In this virtual software interrupt scenario, the first vCPU runs on the source physical processor, and the second vCPU runs on the target physical processor. The control device can obtain the identifier of the virtual machine from a register specifically used to store the identifier of the virtual machine running on the source physical processor. Because each virtual machine can have multiple vCPUs, and the vCPU identifiers of different virtual machines may be the same, the control device needs to send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device. The intermediate device can store the aforementioned first correspondence, which can be located in an in-situ vCPU identifier group. This in-situ vCPU identifier group records the correspondence between each physical processor in the chip system, the vCPU running on each physical processor, and the virtual machine to which the running vCPU belongs. This application can target the physical processor by searching the in-situ vCPU identifier group. From this possible implementation, it can be seen that the process of handling the virtual software interrupt does not require the source physical processor to perform a switch from the virtual machine to the host machine, thereby reducing the switching overhead caused by handling virtual software interrupts and improving the performance of the chip system.

[0018] In one possible implementation of the first aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written to the register by the host machine and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host machine simulates a hardware device. The control device is used to: read the target interrupt number and the identifier of the virtual machine from the register, and send the identifier of the virtual machine and the target interrupt number to the intermediate device. The intermediate device is used to: search for the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in a second correspondence relationship based on the identifier of the virtual machine and the target interrupt number. The second correspondence relationship is used to record the correspondence between the virtual machine, the target interrupt number, and the first vCPU. Based on the identifier of the virtual machine and the identifier of the first vCPU, determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU from a third correspondence relationship. The third correspondence relationship is used to record the correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine. The virtual device interrupt is sent to the sending device corresponding to the target physical processor. The sending device is used to: send the virtual device interrupt to the first vCPU running on the target physical processor.

[0019] In this possible implementation, the virtual device interrupt is triggered by the host machine in user mode simulating a hardware device. There can be various types of hardware devices, each with a different interrupt number. If the host machine is simulating a disk, then the target interrupt number is the disk's interrupt number. Because the host machine can manage multiple virtual machines, it needs to write the virtual machine's identifier and the target interrupt number into a register. The second mapping can be located in an interrupt affinity table. This interrupt affinity table can be configured by the virtual machine, so there is one for each virtual machine. Thus, the interrupt affinity table for that virtual machine can be found based on its identifier. Then, the corresponding vCPU is determined from the virtual machine's interrupt affinity table based on the target interrupt number. If the target interrupt number is 10, and interrupt number 10 corresponds to vCPU ID 1 in the interrupt affinity table, then the vCPU ID corresponding to the target interrupt number can be determined to be 1. After the routing device determines that vCPU ID is 1, it can find the physical processor corresponding to vCPU ID 1 based on the in-situ vCPU identifier group. The meaning of the in-situ vCPU identifier group can be understood by referring to the description in the aforementioned virtual software interrupt section, and the third correspondence can also be understood by referring to the aforementioned first correspondence. From this possible implementation, it can be seen that the process of handling the virtual device interrupt does not require the source physical processor to perform a switch from the host machine's user mode to the host machine's kernel mode, thereby reducing the switching overhead caused by handling virtual device interrupts and improving the performance of the chip system.

[0020] In one possible implementation of the first aspect, the intermediate device includes an address register for storing the address of the second correspondence in memory and the identifier of the virtual machine; the intermediate device is also used to: locate the address register according to the identifier of the virtual machine, and retrieve the second correspondence from memory according to the address in the address register.

[0021] In this possible implementation, the interrupt affinity table can be stored in an intermediate device or in memory. The intermediate device can provide an address register for each physical processor. This address register can be a base address register, which stores the memory address of the interrupt affinity table and the virtual machine's identifier. This avoids occupying too much storage space in the intermediate device.

[0022] In one possible implementation of the first aspect, the sending device is used to: write a virtual interrupt into a pending register of the target physical processor, the pending register being used to receive commands from the process executed by the target physical processor.

[0023] In this possible implementation, the pending register is used to receive the command that the target physical processor will execute next. Writing the virtual interrupt into the pending register allows the target physical processor to execute the virtual interrupt, thus interrupting the currently executing process and eliminating the need to switch to the host machine in existing solutions. This reduces the overhead of switching the target physical processor from the virtual machine to the host machine.

[0024] A second aspect of this application provides a chip system comprising a source physical processor, a control device, an intermediate device, a transmitting device, and a target physical processor. The source physical processor is used to run a host machine or a virtual machine. The chip system also includes hardware devices for direct communication between virtual machines. The intermediate device is used to: receive a pass-through peripheral interrupt triggered by the hardware device; look up the corresponding virtual machine identifier and virtual interrupt number in a virtual interrupt table based on the physical interrupt number of the pass-through peripheral interrupt, the virtual interrupt table recording the correspondence between physical interrupt numbers and virtual machine identifiers and virtual interrupt numbers; determine the corresponding interrupt affinity table based on the virtual machine identifier, and determine the identifier of the target virtual processor (vCPU) corresponding to the virtual machine identifier and virtual interrupt number from the interrupt affinity table, the interrupt affinity table recording the correspondence between virtual interrupt numbers and virtual processors; determine the target physical processor corresponding to the target vCPU identifier from the in-situ vCPU identifier group based on the target vCPU identifier; and send the pass-through peripheral interrupt to the transmitting device corresponding to the target physical processor. The transmitting device sends the pass-through peripheral interrupt to the virtual machine running on the target physical processor.

[0025] In this second aspect, a pass-through peripheral interrupt refers to an interrupt triggered by an external device passed through to the virtual machine, such as an interrupt generated by the graphics card passed through to the virtual machine. During the processing of pass-through peripheral interrupts, the virtual interrupt table, interrupt affinity table, and in-situ vCPU identifier group are used sequentially. The interrupt affinity table and in-situ vCPU identifier group can be understood by referring to the descriptions of possible implementations in the first aspect above. The virtual interrupt table is described below. The virtual interrupt table maintains the correspondence between physical interrupt numbers and virtual machine identifiers and virtual interrupt numbers. Inputting a physical interrupt number outputs the virtual machine identifier and virtual interrupt number. During the processing of pass-through peripheral interrupts, the intermediate device receives the physical interrupt number sent by the pass-through peripheral and uses this physical interrupt number to look up the corresponding virtual machine identifier and virtual interrupt number in the virtual interrupt table. For example, inputting a physical interrupt number 100 outputs the virtual machine identifier 1 and virtual interrupt number 10. Then, based on the virtual machine identifier 1 and virtual interrupt number 10, the interrupt affinity table is searched to find the corresponding vCPU ID, such as vCPU ID 1. Further, based on the vCPU ID, the corresponding physical processor is searched from the in-situ vCPU identifier group. For example, if physical processor 1 is found, the intermediate device can send the pass-through peripheral interrupt to the sending device corresponding to physical processor 1, and the sending device will then send the pass-through peripheral interrupt to the vCPU corresponding to vCPU ID 1.

[0026] The second aspect provides a process for handling pass-through peripheral interrupts, which can complete the transmission process by looking up three corresponding relationships, thus improving the flexibility of pass-through peripheral interrupt handling.

[0027] A third aspect of this application provides a control device applied to a chip system. The chip system further includes a source physical processor, an intermediate device, and a transmitting device. The source physical processor is used to run a host machine or a virtual machine. The control device includes a register. The register is used to receive information for triggering a virtual interrupt. The information for triggering the virtual interrupt comes from the host machine or the virtual machine. The control device is used to: read the information for triggering the virtual interrupt from the register and send the information for triggering the virtual interrupt to the intermediate device. The information for triggering the virtual interrupt is used to cause the intermediate device to trigger a virtual interrupt. The virtual interrupt is sent to the target physical processor by the transmitting device.

[0028] In one possible implementation of the third aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, the register is used to receive information written by the virtual machine to trigger the virtual local interrupt; the control device is used to: send the information to trigger the virtual local interrupt to the intermediate device, the information to trigger the virtual local interrupt is used to cause the intermediate device to trigger the virtual local interrupt, the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0029] In one possible implementation of the third aspect, the virtual interrupt is a virtual software interrupt. The information used to trigger the virtual interrupt includes the identifier of the second vCPU written to the register by the first vCPU of the virtual machine, the second vCPU being the vCPU of the virtual machine running on the target physical processor; the control device is used to: read the identifier of the second vCPU from the register and obtain the identifier of the virtual machine; and send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device, the identifier of the virtual machine and the identifier of the second vCPU being used by the intermediate device to determine the target physical processor and trigger the virtual software interrupt, the virtual software interrupt being sent by the sending device to the second vCPU of the target physical processor.

[0030] In one possible implementation of the third aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written to the register by the host and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device. The control device is used to: read the target interrupt number and the identifier of the virtual machine from the register, and send the identifier of the virtual machine and the target interrupt number to the intermediate device. The identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt. The virtual device interrupt is sent by the sending device to the first vCPU of the virtual machine of the target physical processor.

[0031] A fourth aspect of this application provides an intermediate device applied to a chip system. The chip system further includes a source physical processor, a control device, a transmitting device, and a target physical processor. The source physical processor is used to run a host machine or a virtual machine. The control device includes a register. The register is used to receive information for triggering a virtual interrupt. The information for triggering the virtual interrupt comes from the host machine or the virtual machine. The intermediate device is used to: receive the information for triggering the virtual interrupt from the control device, trigger a virtual interrupt according to the information for triggering the virtual interrupt, and send the virtual interrupt to the transmitting device. The virtual interrupt is sent by the transmitting device to the target physical processor.

[0032] In one possible implementation of the fourth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, the register is used to receive information written by the virtual machine to trigger the virtual local interrupt; the intermediate device is used to: trigger the virtual local interrupt according to the information to trigger the virtual local interrupt, and send the virtual local interrupt to the sending device, the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, the first vCPU runs on the source physical processor.

[0033] In one possible implementation of the fourth aspect, the virtual interrupt is a virtual software interrupt. The information used to trigger the virtual interrupt includes the identifier of the second vCPU written to the register of the first vCPU of the virtual machine, where the second vCPU is the vCPU of the virtual machine running on the target physical processor. The intermediate device is used to: receive the identifier of the virtual machine and the identifier of the second vCPU from the control device; determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from a first correspondence relationship based on the identifier of the virtual machine and the identifier of the second vCPU; wherein the first correspondence relationship is used to record the correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; trigger the virtual software interrupt; and send the virtual software interrupt to the sending device corresponding to the target physical processor, whereby the virtual software interrupt is sent by the sending device to the second vCPU of the target physical processor.

[0034] In one possible implementation of the fourth aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written to the register by the host and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device. The intermediate device is used to: receive the identifier of the virtual machine and the target interrupt number from the control device; search for the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in a second correspondence relationship based on the identifier of the virtual machine and the target interrupt number. The second correspondence relationship is used to record the correspondence between the virtual machine, the target interrupt number, and the first vCPU; determine the target physical processor corresponding to the identifier of the virtual machine and the first vCPU from a third correspondence relationship based on the identifier of the virtual machine and the identifier of the first vCPU. The third correspondence relationship is used to record the correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine; trigger the virtual device interrupt; and send the virtual device interrupt to the sending device corresponding to the target physical processor. The virtual device interrupt is sent by the sending device to the first vCPU of the target physical processor.

[0035] In one possible implementation of the fourth aspect, the intermediate device includes an address register for storing the address of the second correspondence in memory and the identifier of the virtual machine; the intermediate device is also used to: locate the address register according to the identifier of the virtual machine, and retrieve the second correspondence from memory according to the address in the address register.

[0036] The fifth aspect of this application provides a transmitting device applied to a chip system, the chip system further including a source physical processor, an intermediate device, and a target physical processor control device, the source physical processor being used to run a host machine or a virtual machine, and the control device including a register; the register being used to receive information for triggering a virtual interrupt, the information for triggering the virtual interrupt coming from the host machine or the virtual machine; the transmitting device being used to: receive a virtual interrupt from the intermediate device and send the virtual interrupt to the target physical processor.

[0037] In one possible implementation of the fifth aspect, the virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor; the sending device is used to: receive the virtual local interrupt from the intermediate device and send the virtual local interrupt to the first virtual processor vCPU of the virtual machine, the first vCPU running on the source physical processor.

[0038] In one possible implementation of the fifth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second vCPU written to the register by the first vCPU of the virtual machine, the second vCPU being the vCPU of the virtual machine running on the target physical processor; the sending device is used to: receive the virtual software interrupt from the intermediate device and send the virtual software interrupt to the second vCPU running on the target physical processor.

[0039] In one possible implementation of the fifth aspect, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes the target interrupt number written to the register by the host and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device. The sending device is used to: receive the virtual device interrupt from the intermediate device and send the virtual device interrupt to the first vCPU running on the target physical processor.

[0040] In one possible implementation of the fifth aspect, the sending device is used to: write a virtual interrupt into a pending register of the target physical processor, the pending register being used to receive commands from the process executed by the target physical processor.

[0041] The features and corresponding intentional effects described in aspects three through five above, as well as any of their possible implementations, can be understood by referring to the descriptions in aspect one and any of its possible implementations, and will not be repeated here.

[0042] A sixth aspect of this application provides a method for processing virtual interrupts. This method is applied to a control device in a chip system, which further includes a source physical processor, an intermediate device, a transmitting device, and a target physical processor. The source physical processor is used to run a host machine or a virtual machine. The control device includes registers; the registers are used to receive information for triggering a virtual interrupt, the information for triggering the virtual interrupt originating from the host machine or virtual machine. The method includes: reading the information for triggering the virtual interrupt from the registers; sending the information for triggering the virtual interrupt to the intermediate device, the information for triggering the virtual interrupt being used by the intermediate device to trigger a virtual interrupt; and the virtual interrupt being sent by the transmitting device to the target physical processor.

[0043] In one possible implementation of the sixth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, the register is used to receive information written by the virtual machine to trigger the virtual local interrupt; the information to trigger the virtual local interrupt is used to enable the intermediate device to trigger the virtual local interrupt, the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0044] In one possible implementation of the sixth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second vCPU written to the register of the first vCPU of the virtual machine, the second vCPU being the vCPU of the virtual machine running on the target physical processor; the method further includes: obtaining the identifier of the virtual machine; sending the identifier of the virtual machine to an intermediate device, the identifier of the virtual machine and the identifier of the second vCPU being used by the intermediate device to determine the target physical processor and trigger the virtual software interrupt, the virtual software interrupt being sent by the sending device to the second vCPU of the target physical processor.

[0045] In one possible implementation of the sixth aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written to the register by the host and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device. The identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt. The virtual device interrupt is sent by the sending device to the first vCPU of the target physical processor.

[0046] A seventh aspect of this application provides a method for processing virtual interrupts. This method is applied to an intermediate device in a chip system. The chip system further includes a source physical processor, a control device, a transmitting device, and a target physical processor. The source physical processor is used to run a host machine or a virtual machine. The control device includes registers. The registers are used to receive information for triggering a virtual interrupt, the information for triggering the virtual interrupt originating from the host machine or virtual machine. The method includes: receiving information from the control device for triggering a virtual interrupt; triggering a virtual interrupt based on the information for triggering the virtual interrupt; and sending the virtual interrupt to the transmitting device, the virtual interrupt being sent by the transmitting device to the target physical processor.

[0047] In one possible implementation of the seventh aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, the register is used to receive information written by the virtual machine to trigger the virtual local interrupt; the information to trigger the virtual local interrupt is used to trigger the virtual local interrupt, the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0048] In one possible implementation of the seventh aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second vCPU written to the register of the first vCPU of the virtual machine, the second vCPU being the vCPU of the virtual machine running on the target physical processor; the above step: triggering the virtual interrupt according to the information used to trigger the virtual interrupt includes: determining the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from a first correspondence relationship according to the identifier of the virtual machine and the identifier of the second vCPU; wherein, the first correspondence relationship is used to record the correspondence between the target physical processor, the second vCPU running on the target processor and the virtual machine; triggering the virtual software interrupt, the virtual software interrupt being sent by the sending device to the second vCPU of the target physical processor.

[0049] In one possible implementation of the seventh aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written to the host register and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device. The above steps: triggering the virtual interrupt according to the information used to trigger the virtual interrupt include: searching for the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in a second correspondence relationship based on the identifier of the virtual machine and the target interrupt number. The second correspondence relationship is used to record the correspondence between the virtual machine, the target interrupt number, and the first vCPU; determining the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU from a third correspondence relationship based on the identifier of the virtual machine and the identifier of the first vCPU; wherein, the third correspondence relationship is used to record the correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine; triggering the virtual device interrupt, which is sent by the sending device to the first vCPU of the target physical processor.

[0050] In one possible implementation of the seventh aspect, the method further includes: finding the address register based on the virtual machine's identifier, and obtaining the second correspondence from memory based on the address in the address register, wherein the address register is used to store the address of the second correspondence in memory and the virtual machine's identifier.

[0051] The eighth aspect of this application provides a method for processing virtual interrupts. The method is applied to a transmitting device in a chip system. The chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor. The source physical processor is used to run a host machine or a virtual machine. The control device includes a register. The register is used to receive information for triggering a virtual interrupt. The information for triggering the virtual interrupt comes from the host machine or the virtual machine. The method includes: receiving a virtual interrupt from the intermediate device; and sending the virtual interrupt to the target physical processor.

[0052] In one possible implementation of the eighth aspect, the virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor; the above step: sending the virtual interrupt to the target physical processor includes: sending the virtual local interrupt to the first virtual processor vCPU of the virtual machine, the first vCPU running on the source physical processor.

[0053] In one possible implementation of the eighth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second vCPU written to the register of the first vCPU of the virtual machine, the second vCPU being the vCPU of the virtual machine running on the target physical processor; the above step: sending the virtual interrupt to the target physical processor includes: sending the virtual software interrupt to the second vCPU running on the target physical processor.

[0054] In one possible implementation of the eighth aspect, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes the target interrupt number written to the host register and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device. The above step: sending the virtual interrupt to the target physical processor includes: sending the virtual device interrupt to the first vCPU running on the target physical processor.

[0055] In one possible implementation of the eighth aspect, the method further includes: writing a virtual interrupt into a pending register of the target physical processor, the pending register being used to receive commands from the process executed by the target physical processor.

[0056] The features and corresponding intentional effects described in aspects six through eight above, and any of their possible implementations, can be understood by referring to the description in aspect one, and any of its possible implementations, and will not be repeated here.

[0057] A ninth aspect of this application provides a control device applied in a chip system. The chip system further includes a source physical processor, an intermediate device, a transmitting device, and a target physical processor. The source physical processor is used to run a host machine or a virtual machine. The control device includes a register for receiving information for triggering a virtual interrupt. The information for triggering the virtual interrupt comes from the host machine or the virtual machine. The control device includes: a reading unit for reading the information for triggering the virtual interrupt from the register; and a transmitting unit for transmitting the information for triggering the virtual interrupt to the intermediate device. The information for triggering the virtual interrupt is used by the intermediate device to trigger a virtual interrupt, and the virtual interrupt is transmitted by the transmitting device to the target physical processor.

[0058] In one possible implementation of the ninth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, the register is used to receive information written by the virtual machine to trigger the virtual local interrupt; the information to trigger the virtual local interrupt is used to enable the intermediate device to trigger the virtual local interrupt, the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0059] In one possible implementation of the ninth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second vCPU written to the register of the first vCPU of the virtual machine, the second vCPU being the vCPU of the virtual machine running on the target physical processor; the control device further includes a processing unit for acquiring the identifier of the virtual machine; and a sending unit for sending the identifier of the virtual machine to an intermediate device, the identifier of the virtual machine and the identifier of the second vCPU being used by the intermediate device to determine the target physical processor and trigger the virtual software interrupt, the virtual software interrupt being sent by the sending device to the second vCPU of the target physical processor.

[0060] In one possible implementation of the ninth aspect, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes the target interrupt number written to the register by the host and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device. The identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt. The virtual device interrupt is sent by the sending device to the first vCPU of the target physical processor.

[0061] The tenth aspect of this application provides an intermediate device applied in a chip system. The chip system further includes a source physical processor, a control device, a transmitting device, and a target physical processor. The source physical processor is used to run a host machine or a virtual machine. The control device includes a register for receiving information for triggering a virtual interrupt, the information for triggering the virtual interrupt originating from the host machine or the virtual machine. The intermediate device includes: a receiving unit for receiving information for triggering a virtual interrupt from the control device; a processing unit for triggering a virtual interrupt based on the information for triggering the virtual interrupt; and a transmitting unit for transmitting the virtual interrupt to the transmitting device, the virtual interrupt being transmitted by the transmitting device to the target physical processor.

[0062] In one possible implementation of the tenth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, the register is used to receive information written by the virtual machine to trigger the virtual local interrupt; the information to trigger the virtual local interrupt is used to trigger the virtual local interrupt, the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0063] In one possible implementation of the tenth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second vCPU written to the register of the first vCPU of the virtual machine, the second vCPU being the vCPU of the virtual machine running on the target physical processor; a processing unit is used to determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from a first correspondence relationship based on the identifier of the virtual machine and the identifier of the second vCPU; wherein the first correspondence relationship is used to record the correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; and to trigger the virtual software interrupt, the virtual software interrupt being sent by the sending device to the second vCPU of the target physical processor.

[0064] In one possible implementation of the tenth aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written to the register by the host and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device. The processing unit is used to look up the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in a second correspondence relationship based on the identifier of the virtual machine and the target interrupt number. The second correspondence relationship is used to record the correspondence between the virtual machine, the target interrupt number, and the first vCPU. Based on the identifier of the virtual machine and the identifier of the first vCPU, the processing unit determines the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU from a third correspondence relationship. The third correspondence relationship is used to record the correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine. The virtual device interrupt is triggered and sent by the sending device to the first vCPU of the target physical processor.

[0065] In one possible implementation of the tenth aspect, the processing unit is further configured to locate the address register based on the identifier of the virtual machine, and retrieve the second correspondence from memory based on the address in the address register. The address register is used to store the address of the second correspondence in memory and the identifier of the virtual machine.

[0066] The eleventh aspect of this application provides a transmitting device applied in a chip system. The chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor. The source physical processor is used to run a host machine or a virtual machine. The control device includes a register for receiving information for triggering a virtual interrupt, the information for triggering the virtual interrupt coming from the host machine or the virtual machine. The transmitting device includes: a receiving unit for receiving a virtual interrupt from the intermediate device; and a transmitting unit for transmitting the virtual interrupt to the target physical processor.

[0067] In one possible implementation of the eleventh aspect, the virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor; the sending unit is used to send the virtual local interrupt to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0068] In one possible implementation of the eleventh aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second vCPU written to the register by the first vCPU of the virtual machine, the second vCPU being the vCPU of the virtual machine running on the target physical processor; and a sending unit for sending the virtual software interrupt to the second vCPU running on the target physical processor.

[0069] In one possible implementation of the eleventh aspect, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes the target interrupt number written to the register by the host and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device; and a sending unit is used to send the virtual device interrupt to the first vCPU running on the target physical processor.

[0070] In one possible implementation of the eleventh aspect, the sending unit is used to write the virtual interrupt into the pending register of the target physical processor, the pending register being used to receive commands from the process executed by the target physical processor.

[0071] The features and corresponding intentional effects described in aspects nine through eleven above, and in any of their possible implementations, can be understood by referring to the description in aspect one, and in any of its possible implementations, and will not be repeated here.

[0072] The twelfth aspect of this application provides a computer-readable storage medium storing one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor performs a method as described in the sixth aspect above or any possible implementation thereof.

[0073] The thirteenth aspect of this application provides a computer-readable storage medium storing one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor performs a method as described in the seventh aspect or any possible implementation thereof.

[0074] The fourteenth aspect of this application provides a computer-readable storage medium storing one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor performs a method as described in the eighth aspect above or any possible implementation thereof.

[0075] The fifteenth aspect of this application provides a computer program product storing one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor executes a method as described in the sixth aspect above or any possible implementation thereof.

[0076] The sixteenth aspect of this application provides a computer program product storing one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor executes a method as described in the seventh aspect or any possible implementation thereof.

[0077] The seventeenth aspect of this application provides a computer program product storing one or more computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processor executes a method as described in the eighth aspect or any possible implementation thereof.

[0078] The eighteenth aspect of this application provides a computer device comprising the chip system described in the first aspect or any possible implementation thereof.

[0079] The nineteenth aspect of this application provides a chip system including a source physical processor, a control device, a transmitting device, and a target physical processor. The control device is as described in the foregoing third aspect, ninth aspect, any possible implementation of the third aspect, or any possible implementation of the ninth aspect; the transmitting device is as described in the foregoing fifth aspect, eleventh aspect, or any possible implementation of the eleventh aspect, or any possible implementation of the fifth aspect.

[0080] In one implementation, the chip system may further include an intermediate device as described in any of the fourth, tenth, or fourth possible implementations of the aforementioned aspects.

[0081] In one implementation, the chip system provided in the nineteenth aspect is a processor. The source physical processor and the target physical processor are physical cores within this processor. A control device is a component located within the processor and coupled to the source physical processor, and a transmitting device is a component located within the processor and coupled to the target physical processor. It is understood that since any physical core in the processor can act as a receiver of a virtual interrupt, a physical core can function as both a source physical processor and a target physical processor. Correspondingly, the components coupled to this physical core can include both a control device and a transmitting device.

[0082] The chip system provided in this application embodiment includes a dedicated register in the control device for handling virtual interrupts. This allows the host machine or virtual machine in user mode to directly write information for triggering virtual interrupts into this register. The control device can then send this information to an intermediate device, which triggers the virtual interrupt. The intermediate device then sends the virtual interrupt to a sending device, which in turn sends it to the target physical processor. In this solution, both the host machine and the virtual machine can directly access the register to write the information for triggering virtual interrupts, thereby sending the virtual interrupt out. Therefore, compared to existing technologies, this solution eliminates the need for the source physical processor to switch from the virtual machine to the host machine, or from the host machine's user mode to its kernel mode, thus reducing the switching overhead associated with handling virtual interrupts and improving the performance of the chip system. Attached Figure Description

[0083] Figure 1 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application;

[0084] Figure 2 This is a schematic diagram of the types of virtual interrupts provided in the embodiments of this application;

[0085] Figure 3 This is a schematic diagram of the chip system provided in an embodiment of this application;

[0086] Figure 4 This is another schematic diagram of the chip system provided in the embodiments of this application;

[0087] Figure 5 This is a schematic diagram of a virtual clock interrupt provided in an embodiment of this application;

[0088] Figure 6 This is an example schematic diagram of an in-situ virtual processor identifier group provided in an embodiment of this application;

[0089] Figure 7 This is an example schematic diagram of a virtual software interruption provided in an embodiment of this application;

[0090] Figure 8 This is a schematic diagram of the routing device provided in an embodiment of this application;

[0091] Figure 9 This is a schematic diagram illustrating an example of a pass-through peripheral interrupt provided in an embodiment of this application;

[0092] Figure 10 This is a schematic diagram of a chip system in the RISC-V microarchitecture provided in the embodiments of this application;

[0093] Figure 11This is a schematic diagram of a process for handling clock interrupts in the RISC-V microarchitecture provided in this application embodiment;

[0094] Figure 12 This is a schematic diagram illustrating a process for handling virtual software interrupts in the RISC-V microarchitecture provided in this application embodiment;

[0095] Figure 13 This is a schematic diagram illustrating a process for handling virtual device interrupts in the RISC-V microarchitecture provided in this application embodiment;

[0096] Figure 14 This is a schematic diagram illustrating another process for handling virtual device interrupts in the RISC-V microarchitecture provided in this application embodiment;

[0097] Figure 15 This is a schematic diagram illustrating a process for handling pass-through peripheral interrupts in the RISC-V microarchitecture provided in this application embodiment;

[0098] Figure 16 This is a schematic diagram of an embodiment of the method for handling virtual interrupts provided in this application;

[0099] Figure 17 This is a schematic diagram of an embodiment of the control device provided in this application;

[0100] Figure 18 This is a schematic diagram of an embodiment of the intermediate device provided in this application;

[0101] Figure 19 This is a schematic diagram of an embodiment of the transmitting device provided in this application;

[0102] Figure 20 This is another structural schematic diagram of the computer device provided in the embodiments of this application. Detailed Implementation

[0103] The embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. As those skilled in the art will understand, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0104] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0105] This application provides a chip system, a method for handling virtual interrupts, and corresponding apparatus to reduce the switching overhead caused by virtual interrupts when switching from a virtual machine to the host machine, or from the host machine's user mode to the host machine's kernel mode. This application also provides corresponding computer devices, computer storage media, and computer program products. These will be described in detail below.

[0106] Virtualization is the process of virtualizing hardware resources (such as processors, memory, and network resources) in a computer device and sharing them among multiple virtual computers. A virtual computer is a general term for the runtime environment created by software in all types of virtualization devices; this concept includes virtual machines or containers.

[0107] like Figure 1 As shown, the computer device 100 includes a hardware layer 112, a host layer 109, and a virtualization layer. The virtualization layer contains virtual machines 101 and 102. The number of virtual machines can be more or less; only two are used as an example here. The hardware layer 112 includes a processor system 114, a memory 113, a communication interface 115, and an interrupt controller 116.

[0108] A virtual machine (VM) is a virtual machine simulated on a computer device using virtualization software. Figure 1 A guest operating system (guest OS) can be installed on (101 and 102). Figure 1 (105 and 106), the guest operating system has one or more applications running on it. Figure 1 (See sections 103 and 104). Virtual machines can also access network resources. For applications running in a virtual machine, it's as if they are working on a real computer.

[0109] Virtual processors (such as) Figure 1(107 and 108): In virtualization technology, virtual processors represent processing units provided to virtual computers in a shared or fragmented manner, such as virtual central processing units (vCPUs). A virtual computer can have one or more virtual processors serving it. When multiple virtual processors exist, typically one virtual processor is the master virtual processor, and the others are slave virtual processors. Virtual hardware resources, such as virtual memory, are included in the virtual machine. Figure 1 The virtual processor is not shown in the diagram. It is virtualized by virtualization software, and its operation is actually achieved by the host machine's processor or physical core reading and running the software program. For example, a physical core reads the software program and runs it in a specific mode of hardware-assisted virtualization (e.g., x86 non-root mode) to implement a virtual processor. Multiple virtual processors of a single virtual machine can reside on different physical cores. It should be noted that the vCPU mentioned in the various embodiments of this application is an optional specific implementation of a virtual processor. The term "vCPU" mentioned in the various embodiments can be understood as "virtual processor".

[0110] Virtual processor trap-in and trap-out: Virtualization systems include two modes: host mode and guest mode. Host mode can also be referred to as the privilege level of the host, such as the host's user mode or kernel mode. Guest mode can also be referred to as the privilege level of the VM, such as the VM's user mode or kernel mode. When a physical processor enters guest mode, it is called trap-in (virtualization), and the trap-in process can be understood as the physical processor switching from running the host machine to running the virtual machine. When the physical processor leaves guest mode, it is called trap-out (virtualization), and the trap-out process can also be understood as the physical processor switching from running the virtual machine to running the host machine. After trap-out, the physical processor will temporarily not execute the virtual processor's code, so at this time it can be understood that the virtual processor is not running. When a virtual machine runs on a physical processor, one virtual processor for that virtual machine will run. A virtual machine can have multiple virtual processors. A physical processor runs only one virtual processor of that virtual machine at any given time. Multiple virtual processors belonging to the same virtual machine can run on the same physical processor in a time-sharing manner. For example, vCPU1 of virtual machine 1 can run on physical processor 1 first. After physical processor 1 finishes running vCPU1, vCPU2 of virtual machine 1 can run. Multiple vCPUs belonging to the same virtual machine can also run on different physical processors. Different vCPUs can run on different physical processors at a time. For example, vCPU1 of virtual machine 1 can run on physical processor 1, and vCPU2 of virtual machine 1 can run on physical processor 2. The host layer 109 acts as the management layer, used to manage and allocate hardware resources, providing virtual machines with various virtual hardware resources, such as virtual processors (107, 108), virtual memory, virtual disks, virtual network cards, etc. It can also implement virtual machine scheduling and isolation. In some implementations, the host layer 109 may include a host operating system 111 and a virtual monitoring device, such as a virtual machine monitor (VMM) 110. The virtual monitor 110 can be deployed within or outside the host operating system 111. In other virtualization architectures, the virtual monitoring device may also be called a hypervisor or other types of virtual monitoring devices. The host layer 109 may also be called a virtualization platform, and sometimes the host layer is simply referred to as the host. The privilege levels of the host include user mode and kernel mode.

[0111] Hardware Layer 112: The hardware platform on which the virtualization environment runs. This hardware layer can include various types of hardware, such as... Figure 1As shown, the hardware layer may include a processor system 114 and a memory 113, and may also include a communication interface 115, such as a network interface card (NIC); it may also include an interrupt controller 116, input / output (I / O) devices, etc. The processor system 114 may include one or more processors, such as... Figure 1 The processors listed are processor 1 and processor 2. Each processor may include multiple physical cores, and may also include multiple registers, such as general-purpose registers and floating-point registers.

[0112] Processor system 114 may include multiple processors, such as Figure 1 Processor 1 and Processor 2 in the system. Figure 1 Processor 1 and Processor 2 in the system are both physical processors, such as a source physical processor and a target physical processor. Each physical processor can be understood as a physical core. The processor system 114 can be specifically a multi-core processor, which includes a source physical processor and a target physical processor. Virtual processors and physical cores can have a bound relationship, that is, a virtual processor is fixed to run on a certain physical core and cannot be scheduled to run on other physical cores, then the virtual processor is a bound core; a virtual processor can be scheduled to run on different physical cores as needed, then the virtual processor is a non-bound core.

[0113] Interrupt controller 116: Located between the hardware that triggers interrupt requests and the processor, it is mainly used to collect interrupt requests generated by various hardware components and send them to the processor according to certain priorities or other rules. For example, an advanced programmable interrupt controller (APIC).

[0114] An interrupt is an instruction that suspends the current program and allows the execution of an interrupt service routine. Interrupts can be virtual or physical. A virtual interrupt is an interrupt notified to the virtual machine (VM) by hardware devices, the host machine, the virtual machine's clock, or its virtual central processing unit (vCPU). The hardware devices that generate virtual interrupts can be computer devices such as disks, network cards, sound cards, mice, and hard drives. A physical interrupt is an interrupt notified to the physical processor by hardware devices. Physical interrupts are handled by the host machine, while virtual interrupts are handled by the virtual machine.

[0115] An interrupt service routine (ISR), also known as an interrupt handler, is a program used to handle interrupt requests. When the processor receives an interrupt request, it temporarily suspends the execution of the current program and executes the interrupt service routine corresponding to the interrupt request.

[0116] The storage space (address space) provided by memory 113 is divided for use by the virtual machine and the host machine. The host physical address (HPA) refers to the physical address space that the local host (host machine) can use; the host virtual address (HVA) is the virtual address space that the local host (host machine) can use. The guest physical address (GPA) is the physical address space that the guest operating system of the virtual machine can use; the guest virtual address (GVA) is the virtual address space that the guest operating system of the virtual machine can use.

[0117] Computer device 100 can be a physical device, such as a server or terminal device. Terminal device can be a handheld device with wireless connectivity, or other processing device connected to a wireless modem. Examples include mobile phones, personal computers (PCs), tablets, personal digital assistants (PDAs), mobile internet devices (MIDs), wearable devices, and e-book readers; it can also be portable, pocket-sized, handheld, computer-embedded, or vehicle-mounted mobile devices.

[0118] The virtual machine or host machine in the aforementioned computer device 100 can send information to trigger a virtual interrupt, and then the chip system provided in this application embodiment will complete the corresponding virtual interrupt processing. The chip system provided in this application embodiment may include the aforementioned... Figure 1 The interrupt controller and processor system in the system may also include the above-mentioned Figure 1 The interrupt controller or processor system in the system.

[0119] Target physical processor In the embodiments of this application, such as Figure 2As shown, virtual interrupts can include virtual local interrupts, virtual software interrupts, virtual device interrupts, and direct peripheral interrupts. Virtual local interrupts refer to interrupts simulated by the virtual machine, such as virtual timers, virtual mice, or local devices of a specific vCPU within the virtual machine. For example, an interrupt from a timer on a vCPU of the virtual machine is also called a clock interrupt, which refers to the interrupt issued by the timer when a time point configured by the virtual machine is reached. Virtual software interrupts are triggered by software, typically referring to interrupts sent from one vCPU of the virtual machine to another vCPU within the same virtual machine, such as... Figure 2 In a virtual machine, an interrupt is an interrupt sent from the first vCPU to the second vCPU within the same virtual machine. A virtual machine can have multiple vCPUs, which can run on different physical processors at any given time to execute different tasks. Virtual software interrupts occur when the tasks executed by different vCPUs have dependencies or require scheduling. Virtual device interrupts refer to interrupts triggered by hardware devices simulated by the host machine, such as interrupts generated by the host machine simulating the virtual machine's disk controller or other hardware devices. Passed-through peripheral interrupts refer to interrupts triggered by external devices passed through to the virtual machine, such as interrupts generated by passing through the virtual machine's graphics card.

[0120] Of the four types of virtual interrupts mentioned above, the handling of virtual partial interrupts, virtual software interrupts, and virtual device interrupts requires the physical processor running the virtual machine to switch from the virtual machine to the host machine, or from the host machine's user mode to the host machine's kernel mode, resulting in significant switching overhead. Therefore, this application provides a chip system that, during the handling of virtual interrupts, eliminates the need for the physical processor running the virtual machine to switch from the virtual machine to the host machine, or from the host machine's user mode to the host machine's kernel mode, thus saving switching overhead. The chip system provided in this application is described below with reference to the accompanying drawings.

[0121] like Figure 3As shown, the chip system provided in this application embodiment includes: a source physical processor, a control device, an intermediate device, a transmitting device, and a target physical processor. The source physical processor is used to run a host machine or a virtual machine. The control device includes a register for receiving information for triggering a virtual interrupt, which can come from the host machine or the virtual machine. The control device is used to send the information for triggering a virtual interrupt in the register to the intermediate device. The intermediate device is used to trigger a virtual interrupt according to the information for triggering a virtual interrupt and send the virtual interrupt to the transmitting device. The transmitting device is used to receive the virtual interrupt from the intermediate device and send the virtual interrupt to the target physical processor.

[0122] This chip system can be applied to the above. Figure 1 In the computer device shown, the chip system can be as described above. Figure 1 The interrupt controller or processor system in the system.

[0123] The chip system provided in this application embodiment can be a system-on-chip (SOC), where the source physical processor and the target physical processor can each be a processing unit. The source physical processor or the target physical processor can be a physical core located within the same processor; alternatively, the source physical processor and the target physical processor can be different processors located within the same chip system. The control device, intermediate device, and transmitting device can all be implemented using hardware circuitry. The control device and transmitting device can be deployed within the multi-core processor and coupled to the source physical processor and the target physical processor. The intermediate device can be deployed within the multi-core processor or on a peripheral device / component coupled to the multi-core processor. The system-on-chip can include a multi-core processor and peripheral devices / components coupled to the multi-core processor. Any physical processor in the chip system can serve as either a source physical processor or a target physical processor.

[0124] This application uses a source physical processor and a target physical processor. It should be noted that the source physical processor and the target physical processor can be two physical cores in a multi-core processor, or they can be two physical cores located in different processors. In one implementation, the source physical processor and the target physical processor can be the same physical entity. For example, in a virtual partial interrupt scenario, the source physical processor and the target physical processor can be the same physical processor.

[0125] In this application, the control device may include at least one register, wherein each register may be used to receive one type of information for triggering a virtual interrupt. For example, it may include three registers: one register for receiving information for triggering a virtual local interrupt, one register for receiving information for triggering a virtual software interrupt, and one register for receiving information for triggering a virtual device interrupt. Of course, in this control device, only one register may be configured for virtual interrupts, and the information used to trigger each type of virtual interrupt is different; the type of virtual interrupt can be identified by the information received by the register.

[0126] There can be one or more intermediate devices. Each physical processor can have its own transmitting device, or multiple physical processors can share a single transmitting device.

[0127] The chip system provided in this application embodiment has a dedicated register for handling virtual interrupts in the control device. In this way, the host machine or virtual machine in user mode can directly write the information for triggering virtual interrupts into the register. The control device can send the information for triggering virtual interrupts to an intermediate device, which then triggers the virtual interrupt. The intermediate device then sends the virtual interrupt to a sending device, which in turn sends the virtual interrupt to the target physical processor. This eliminates the need for the source physical processor to perform a switch from the virtual machine to the host machine, or a switch from the user mode of the host machine to the kernel mode of the host machine, thereby reducing the switching overhead caused by handling virtual interrupts and improving the performance of the chip system.

[0128] The above Figure 3 In this context, the intermediate device can be a virtual local interrupt generator or a routing device. If the virtual interrupt is a virtual local interrupt, the intermediate device can be called a local interrupt generator (e.g., a timer). If the virtual interrupt is a virtual software interrupt or a virtual device interrupt, the intermediate device can be called a routing device.

[0129] The aforementioned transmitting device Figure 2 The article introduced four types of virtual interrupts; the following section will combine them with... Figure 4 Taking register 1, register 2 and register 3 in the control device as an example, the process of handling these four types of virtual interrupts is introduced. Register 1 is used to receive information for triggering virtual device interrupts, register 2 is used to receive information for triggering virtual software interrupts, and register 3 is used to receive information for triggering virtual local interrupts.

[0130] Figure 4In the chip system shown, the source physical processor is used to run a host machine or a virtual machine. Both the host machine and the virtual machine can have a privilege level one and a privilege level two. Privilege level one can be user mode, and privilege level two can be kernel mode. The states corresponding to privilege level one and privilege level two may differ in different virtualization architectures; however, this embodiment does not impose any limitations on this.

[0131] This application Figure 4 The diagram uses four different lines to represent four types of virtual interrupts. The line marked with the number 1 represents the process of handling virtual local interrupts, the line marked with the number 2 represents the process of handling virtual software interrupts, the line marked with the number 3 represents the process of handling virtual device interrupts, and the line marked with the number 4 represents the process of handling pass-through peripheral interrupts.

[0132] 1. Virtual partial interrupt.

[0133] like Figure 4 As shown, register 3 is involved in handling virtual local interrupts, and the intermediate device can be called a local interrupt generator. Because virtual local interrupts are in-kernel interrupts, the target physical processor and the source physical processor are the same physical processor, and the sending device corresponds to the source physical processor.

[0134] The register is used to receive information written by the virtual machine to trigger virtual local interrupts.

[0135] The local interrupt generator is used to generate a virtual local interrupt based on the information used to trigger the virtual local interrupt.

[0136] The sending device is used to send a virtual local interrupt to the first virtual processor (vCPU) of the virtual machine, which runs on the source physical processor.

[0137] The virtual partial interrupt handling process provided in this application embodiment ensures that a physical processor runs only one virtual machine's vCPU at a time. Sending the virtual partial interrupt to that vCPU completes the operation of sending the virtual partial interrupt to the virtual machine. The above... Figure 4 The local interrupt generator can be a timer, and this virtual local interrupt can be a clock interrupt. For the implementation of this process in a clock interrupt scenario, please refer to [link to relevant documentation]. Figure 5 To understand. For example Figure 5 As shown, the virtual machine writes the interrupt time into the control device (this process can be found in [reference]). Figure 4(Understanding the third register in the system), the control device will write the interrupt time into the timer, and the timer will start. After the preset time is reached, the timer will issue a clock interrupt. After receiving the clock interrupt, the sending device will determine that the first vCPU of the virtual machine is running, and then send the clock interrupt to the first vCPU.

[0138] From the above Figure 4 and Figure 5 As can be seen from the process, the process of handling the virtual local interrupt does not require the source physical processor to perform a switch from the virtual machine to the host machine, thereby reducing the switching overhead caused by handling the virtual local interrupt and improving the performance of the chip system.

[0139] 2. Virtual software interrupted.

[0140] like Figure 4 As shown, register 2 is involved in handling virtual software interrupts, and the intermediate device can be called a routing device. The source physical processor runs the first vCPU of the virtual machine, and the target physical processor runs the second vCPU of the virtual machine.

[0141] The register is used to receive the identifier of the second vCPU written by the first vCPU.

[0142] The control device is used to: read the identifier of the second vCPU from the register and obtain the identifier of the virtual machine; and send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device.

[0143] The intermediate device is used to: determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from a first correspondence relationship based on the identifier of the virtual machine and the identifier of the second vCPU; wherein the first correspondence relationship is used to record the correspondence between the target physical processor, the second vCPU running on the target processor and the virtual machine; and send the virtual software interrupt to the sending device corresponding to the target physical processor.

[0144] The sending device is used to send virtual software interrupts to a second vCPU running on the target physical processor.

[0145] In the process of handling virtual software interrupts in this embodiment, the control device can obtain the identifier of the virtual machine from a register specifically used to store the identifier of the virtual machine running on the source physical processor. Since each virtual machine can have multiple vCPUs, and the vCPU identifiers of different virtual machines may be the same, the control device needs to send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device. The intermediate device can store the aforementioned first correspondence, which can be located in an in-situ vCPU identifier group. This in-situ vCPU identifier group records the correspondence between each physical processor in the chip system, the vCPU running on each physical processor, and the virtual machine to which the running vCPU belongs. This application can target the physical processor by searching the in-situ vCPU identifier group. As described above, the process of handling the virtual software interrupt does not require the source physical processor to perform a switch from the virtual machine to the host machine, thereby reducing the switching overhead caused by handling virtual software interrupts and improving the performance of the chip system.

[0146] The above-mentioned in-place vCPU identifier group can be found in [reference]. Figure 6 To understand. Figure 6 This means that: physical processor 1 runs vCPU1 of VM1, physical processor 2 runs vCPU2 of VM1, physical processor 3 runs vCPU1 of VM2, and physical processor 4 runs vCPU2 of VM2. If the routing device receives the identifiers of VM1 and vCPU2 from the control device, it can then... Figure 6 The in-place vCPU identifier group shown can determine that vCPU2 is running on physical processor 2, and can then send the virtual software interrupt to the sending device corresponding to physical processor 2, which in turn sends the virtual software interrupt to vCPU2 running on physical processor 2.

[0147] If the second vCPU is not found through the above-mentioned in-place vCPU identifier group, it means that the second vCPU is not currently running. In this case, the routing device can send the virtual software interrupt to the sending device of the source physical processor, and the sending device of the source physical processor will send the virtual software interrupt to the host machine. After the second vCPU comes online and runs, the host machine will send the virtual software interrupt to the second vCPU.

[0148] Because a physical processor may run different vCPUs at different times, the correspondence in the in-situ vCPU identifier group is changing. The in-situ vCPU identifier group in the aforementioned routing device may be managed by the host on the source physical processor.

[0149] The process of handling virtual software interruption in this application embodiment can be found in [reference]. Figure 7To understand this, a virtual machine runs on the source physical processor, and the virtual machine's first vCPU runs on the source physical processor. A second vCPU runs on another physical processor. When the first vCPU needs to send a virtual software interrupt to the second vCPU, it writes the second vCPU's identifier to register 2 of the control device. The control device finds the virtual machine's identifier and then sends both the virtual machine's identifier and the second vCPU's identifier to the routing device. The routing device then uses the virtual machine's identifier and the second vCPU's identifier to find, for example... Figure 6 The in-situ vCPU identifier group shown in the diagram determines that the physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU is the target physical processor. Then, the routing device sends the virtual software interrupt to the sending device corresponding to the target physical processor, and the sending device corresponding to the target physical processor sends the virtual software interrupt to the second vCPU, that is, to the virtual machine running on the target physical processor.

[0150] From the above Figure 4 , Figure 6 and Figure 7 As can be seen from the process, the virtual software interrupt handling process provided in this application embodiment does not require the source physical processor to perform a switch from the virtual machine to the host machine, thereby reducing the switching overhead caused by handling virtual software interrupts and improving the performance of the chip system.

[0151] 3. Virtual device interrupted.

[0152] like Figure 4 As shown, during the handling of virtual device interrupts, register 1 is involved, and the intermediate device is the routing device. The host machine runs on the source physical processor, and the host machine is in user mode.

[0153] The register is used to receive the target interrupt number and the virtual machine identifier written by the host machine. The target interrupt number is the identifier of the interrupt triggered when the host machine simulates a hardware device.

[0154] The control unit is used to: read the target interrupt number and the virtual machine identifier from the register, and send the virtual machine identifier and the target interrupt number to the intermediate unit.

[0155] The intermediate device is used to: search for the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in a second correspondence relationship, the second correspondence relationship being used to record the correspondence between the virtual machine, the target interrupt number, and the first vCPU; determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU from a third correspondence relationship, the third correspondence relationship being used to record the correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine; and send the virtual device interrupt to the sending device corresponding to the target physical processor.

[0156] The sending device is used to send virtual device interrupts to the first vCPU running on the target physical processor.

[0157] In this embodiment, the virtual device interrupt is an interrupt triggered by the host machine in user mode simulating a hardware device. There can be various types of hardware devices, each with a different interrupt number. If the host machine is simulating a disk, then the target interrupt number is the disk's interrupt number. Because the host machine can manage multiple virtual machines, it needs to write the virtual machine's identifier and the target interrupt number into a register. The second correspondence can be located in an interrupt affinity table. This interrupt affinity table can be configured by the virtual machine, so there is one interrupt affinity table for each virtual machine. Thus, the interrupt affinity table for the virtual machine can be found based on its identifier. Then, the corresponding vCPU is determined from the virtual machine's interrupt affinity table based on the target interrupt number. If the target interrupt number is 10, and interrupt number 10 corresponds to vCPU ID 1 in the interrupt affinity table, then the vCPU ID corresponding to the target interrupt number can be determined to be 1. After the routing device determines that the vCPU ID is 1, it can find the physical processor corresponding to the vCPU ID 1 according to the in-situ vCPU identifier group. The meaning of the in-situ vCPU identifier group can be understood by referring to the description in the aforementioned virtual software interrupt section. The third correspondence can also be understood by referring to the aforementioned first correspondence.

[0158] Refer to Table 1 below to understand the interrupt affinity table for virtual machines.

[0159] Table 1: Figure 4 Interrupt affinity table of virtual machines in

[0160] Interruption number vCPU ID 10 1 20 2 30 3 40 4

[0161] Table 1 above is just an example; in reality, it is not limited to the types listed in Table 1. There can be other corresponding representations, and the number of representations can also be greater. An additional column can be added to Table 1 to store... Figure 4 The identifier of the virtual machine.

[0162] The interrupt affinity table can be stored in a routing device or in memory. The routing device can provide an address register for each physical processor. This address register can be a base address register, which stores the memory address of the interrupt affinity table and the virtual machine's identifier. Figure 8 As shown, base address register 1 on the routing device corresponds to physical processor 1, base address register 2 corresponds to physical processor 2, base address register 3 corresponds to physical processor 3, and base address register 4 corresponds to physical processor 4. The address in each base address register points to an interrupt affinity table; for example, base address register 1 points to interrupt affinity table 1, base address register 2 points to interrupt affinity table 2, base address register 3 points to interrupt affinity table 3, and base address register 4 points to interrupt affinity table 4. If the same virtual machine is running on two physical processors, the addresses in the base address registers corresponding to the two physical processors can be the same, and the interrupt affinity tables they point to can be the same table.

[0163] Thus, during the handling of virtual device interrupts, the virtual machine writes the target interrupt number to register 1. The control device reads the identifier of the currently running virtual machine from a register specifically used to store virtual machines running on the source physical processor. Then, the control device sends the target interrupt number and the virtual machine identifier to the routing device. The routing device determines the corresponding interrupt affinity table based on the virtual machine identifier, and then uses the target interrupt number to look up the corresponding vCPU identifier in the interrupt affinity table. If the target interrupt number is 10, then the corresponding vCPU identifier can be determined to be 1. After determining that the vCPU identifier is 1, the routing device can then... Figure 6 The in-place vCPU identifier group shows that the processor corresponding to vCPU 1 is physical processor 1. The routing device can send the virtual device interrupt to the sending device corresponding to physical processor 1, and the sending device will then send the virtual device interrupt to the first vCPU corresponding to vCPU 1.

[0164] If the first vCPU is not found through the above-mentioned in-place vCPU identifier group, it means that the first vCPU is not currently running. In this case, the routing device can send the virtual software interrupt to the sending device of the source physical processor, and the sending device of the source physical processor will send the virtual software interrupt to the host machine. After the first vCPU comes online and runs, the host machine will send the virtual software interrupt to the first vCPU.

[0165] From the above Figure 4 Table 1 Figure 8 and Figure 6As can be seen from the process, the virtual device interrupt handling process provided in this application embodiment does not require the source physical processor to perform a switch from the host machine's user mode to the host machine's kernel mode, thereby reducing the switching overhead caused by handling virtual device interrupts and improving the performance of the chip system.

[0166] 4. Interruption of direct-access peripheral devices.

[0167] like Figure 4 As shown, a pass-through peripheral interrupt is an interrupt triggered by a hardware device that passes through the virtual machine, such as a graphics card. The intermediate device can be called a routing device. This type of interrupt handling can be completed through the routing device and the sending device. This process includes:

[0168] The intermediate device is used for: receiving a pass-through peripheral interrupt triggered by a hardware device; looking up the corresponding virtual machine identifier and virtual interrupt number from the virtual interrupt table based on the physical interrupt number of the pass-through peripheral interrupt, the virtual interrupt table recording the correspondence between physical interrupt numbers and virtual machine identifiers and virtual interrupt numbers; determining the corresponding interrupt affinity table based on the virtual machine identifier, determining the identifier of the target virtual processor (vCPU) corresponding to the virtual machine identifier and virtual interrupt number from the interrupt affinity table, the interrupt affinity table recording the correspondence between virtual interrupt numbers and virtual processors; determining the target physical processor corresponding to the target vCPU identifier from the in-situ vCPU identifier group based on the target vCPU identifier; and sending the pass-through peripheral interrupt to the sending device corresponding to the target physical processor.

[0169] The transmitting device is used to send a pass-through peripheral interrupt to a virtual machine running on the target physical processor.

[0170] In the process of handling pass-through peripheral interrupts, the embodiments of this application will sequentially use a virtual interrupt table, an interrupt affinity table, and an in-situ vCPU identifier group. The interrupt affinity table and the in-situ vCPU identifier group can be understood by referring to the previous description. The virtual interrupt table is introduced below.

[0171] The virtual interrupt table maintains the correspondence between physical interrupt numbers and virtual machine identifiers and virtual interrupt numbers. Inputting a physical interrupt number will output the virtual machine identifier and virtual interrupt number. This virtual interrupt table can be understood by referring to Table 2.

[0172] Table 2: Virtual Interrupt Table

[0173]

[0174]

[0175] As shown in Table 1, inputting a physical interrupt number 100 will output the virtual machine identifier 1 and the virtual interrupt number 10. The virtual interrupt table in this application can be stored in the routing device or in memory, with its location in memory indicated by another register similar to a base address register.

[0176] During the process of handling direct peripheral interrupts, such as Figure 9 As shown, the routing device receives the physical interrupt number sent by the pass-through peripheral. It then looks up the corresponding virtual machine identifier and virtual interrupt number in the virtual interrupt table using this physical interrupt number. For example, inputting a physical interrupt number 100 will output the virtual machine identifier 1 and virtual interrupt number 10. Next, based on the virtual machine identifier 1 and virtual interrupt number 10, it looks up the interrupt affinity table in Table 1 to find the corresponding vCPU identifier, such as vCPU identifier 1. Further, it uses this vCPU identifier to... Figure 6 The corresponding physical processor is searched in the in-place vCPU identifier group shown. For example, if physical processor 1 is found, the routing device can send the pass-through peripheral interrupt to the sending device corresponding to physical processor 1, and the sending device will send the pass-through peripheral interrupt to the first vCPU corresponding to vCPU 1.

[0177] If the first vCPU is not found through the above-mentioned in-place vCPU identifier group, it means that the first vCPU is not currently running. In this case, the routing device can send the virtual software interrupt to the sending device of the source physical processor, and the sending device of the source physical processor will send the virtual software interrupt to the host machine. After the first vCPU comes online and runs, the host machine will send the virtual software interrupt to the first vCPU.

[0178] From the above Figure 4 Table 2, Table 1 Figure 6 and Figure 9 As can be seen from the process, the direct-access peripheral interrupt handling process provided in this application embodiment can complete the sending process by looking up three corresponding relationships, which improves the flexibility of direct-access peripheral interrupt handling.

[0179] In handling the four types of virtual interrupts mentioned above, after receiving any one of the four types of virtual interrupts from the intermediate device, the sending device sends it to the corresponding target physical processor. This sending process can involve writing the virtual interrupts of each type into a pending register. This pending register is used to receive the command that the target physical processor will execute next. Once the virtual interrupt is written into the pending register, the target physical processor will then execute the virtual interrupt, thus interrupting the currently executing process. If the target vCPU is executing, the interrupt is sent to the target vCPU. If the host machine is executing, the interrupt is sent directly to the running host machine. After the corresponding target vCPU comes online, the host machine then passes the interrupt to the target vCPU. The target vCPU can be either the first vCPU or the second vCPU described above. Thus, the solution provided in this application can shield the switching to the host machine in existing solutions, reducing the switching overhead from the virtual machine to the host machine for the target physical processor.

[0180] The chip system provided in this application embodiment can be applied to the RISC-V microarchitecture, where RISC stands for Reduced Instruction Set Computing. Figure 10 The diagram shows a schematic of the chip system on RISC-V.

[0181] like Figure 10 As shown, the chip system includes control and transmission devices for interacting with the physical processor, and an interrupt router. The interrupt router includes the routing devices described in the above embodiments.

[0182] Figure 10In this context, RISC-V-CPU represents the central processing unit in the RISC-V architecture. V=0 represents the host machine, V=1 represents the virtual machine, HU-mode represents the host machine's user mode, HS-mode represents the host machine's kernel mode, VU-mode represents the virtual machine's user mode, and VS-mode represents the virtual machine's kernel mode. The supervisor generates inter-processor interrupt (sgenipi) logic to trigger information for virtual software interrupts, and the supervisor time compare (stimecmp) logic is used to register information for triggering virtual local interrupts. When V=1, i.e., when the virtual machine is running on the RISC-V-CPU, information for triggering virtual software interrupts can be sent via sgenipi to the virtual supervisor generate inter-processor interrupt (vsgenipi) register of the control device. This vsgenipi register is the register described in the above embodiment for receiving information for triggering virtual software interrupts, such as register 2. Information for triggering a virtual local interrupt can be sent to the virtual supervisor time compare (vstimecmp) register of the control device via stimecmp. This vstimecmp register is the register described in the above embodiments for receiving information for triggering a virtual local interrupt, such as register 3. The user-generated virtual supervisor external interrupt (ugenvsei) register is used to receive information for triggering a virtual device interrupt, as described in the above embodiments as register 1. The virtual device emulation logic in the host's user space can directly send information for triggering a virtual device interrupt to the ugenvsei register.

[0183] The interrupt router implementation includes registers for a virtual interrupt table (virtualhart shared interrupt mapping, vhsimap), registers for a set of virtual interrupt affinity tables (virtual table base, vtblbase) (1-n), and registers for a set of interrupt control interface mapping (ifmap) registers. The vhsimap (1-n) registers point to the virtual interrupt table stored in memory. Each vtblbase register in the set of vtblbase (1-n) registers corresponds to a physical processor within the RISC-V system and points to the virtual interrupt affinity table defined by the virtual machine to which the vCPU running on that physical processor belongs. A set of ifmap (1-n) registers, each corresponding to a physical processor within the system, is provided to record the vCPU identifier and the identifier of the virtual machine to which the vCPU running on that physical processor belongs.

[0184] In the above Figure 10 The process of handling virtual clock interrupts in the RISC-V architecture shown can be found in [reference needed]. Figure 11 To understand.

[0185] like Figure 11 As shown, the virtual machine uses stimecmp to write the interrupt time to the vstimecmp register, and the control device writes the time of the next virtual clock interrupt trigger to the virtual machine's dedicated clock device. When the interrupt time arrives, the virtual machine's dedicated clock device triggers a virtual clock interrupt. This virtual clock interrupt is then sent to the transmitting device.

[0186] The sending device determines the virtualization state V of the current CPU. If V=1, it directly sends a local interrupt to the virtual machine in VS-mode. If V=0, it sends it to the host machine in HS-mode, and the host machine handles it. That is, after the virtual machine comes online, the host machine passes the virtual clock interrupt to the virtual machine.

[0187] In the above Figure 10 The process of handling virtual software interrupts in the RISC-V architecture shown can be found in [reference needed]. Figure 12 To understand.

[0188] like Figure 12As shown, a virtual machine's vCPU (which can be called the source vCPU in this scenario) runs on CPU1. CPU1 can be the source physical processor in the aforementioned embodiment. The source vCPU writes the target vCPU's identifier to sgenipi, and then writes the target vCPU's identifier to the vsgenipi register in the control device via sgenipi. The control device obtains the virtual machine's identifier and sends the virtual machine's identifier and the target vCPU's identifier (vhartid: the identifier of the vCPU in RISC-V) to the interrupt router. The interrupt router looks up ifmapx; the sequence number x of the ifmapx register containing the VMID and vhartid is the identifier of the corresponding physical processor (mhartid: the identifier of the physical processor in RISC-V). In this scenario, the identifier of the physical processor is... Figure 12 The CPU2 mentioned above can also be understood by referring to the target physical processor in the aforementioned embodiments. The interrupt router sends a virtual software interrupt to the sending device of the aforementioned mhartid physical processor. The sending device determines the current virtualization state of the physical processor. If V=1, the sending device directly sends the virtual software interrupt to the virtual machine. If V=0, the sending device sends the virtual software interrupt to the host machine for processing. That is, after the virtual machine comes online, the host machine sends the virtual software interrupt to the virtual machine.

[0189] In the above Figure 10 The process of handling virtual device interrupts in the RISC-V architecture shown can be found in [reference needed]. Figure 13 To understand.

[0190] like Figure 13 As shown, the host machine in user mode writes the virtual machine's identifier and virtual interrupt number to ugenvsei. The control unit sends the virtual machine's identifier and virtual interrupt number to the interrupt router. The interrupt router searches the vtblbasex registers and finds one of the vtblbasex registers containing the virtual machine's identifier. It then searches the interrupt affinity table stored in the memory pointed to by that register. From the interrupt affinity table, it obtains the vhartid of the vCPU that handles the interrupt, as defined by the virtual machine. The interrupt router searches ifmapx and finds the physical processor number x corresponding to the register containing the VMID and vhartid. This x is the mhartid of the target physical processor. The interrupt router sends a virtual device interrupt to the sending device of the physical processor with the aforementioned mhartid. The sending device determines the current virtualization state of the CPU. If V=1, it directly sends the device interrupt to the virtual machine; if V=0, it sends it to the host machine for processing. That is, after the virtual machine comes online, the host machine sends the virtual device interrupt to the virtual machine.

[0191] In the above Figure 10In the RISC-V architecture shown, another process for handling virtual device interrupts can be found in [reference needed]. Figure 14 To understand.

[0192] like Figure 14 As shown, the host machine writes the virtual machine's identifier and virtual interrupt number to ugenvsei. The control device sends the virtual machine's identifier and virtual interrupt number to the interrupt router. The interrupt router does not implement vtblbasex and by default sends the virtual interrupt to any vCPU with the virtual machine. Then, the interrupt router looks up ifmapx to find the physical processor number x corresponding to the register with the virtual machine's identifier. This x is the mhartid of the target physical processor. The interrupt router sends a virtual device interrupt to the sending device of the physical processor with the aforementioned mhartid. The sending device determines the current virtualization state of the physical processor. If V=1, it directly sends the virtual device interrupt to the virtual machine; if V=0, it sends it to the host machine for processing. That is, after the virtual machine comes online, the host machine sends the virtual device interrupt to the virtual machine.

[0193] In the above Figure 10 The process of handling pass-through peripheral interrupts in the RISC-V architecture shown can be found in [reference needed]. Figure 15 To understand.

[0194] like Figure 15 As shown, a hardware device that communicates directly with the virtual machine triggers a pass-through peripheral interrupt. The interrupt router looks up the virtual interrupt table pointed to by vhlimap to find the identifier of the virtual machine to which the interrupt is passed, as well as the virtual interrupt number recognized by the virtual machine after the pass-through. The interrupt router looks up the vtblbasex registers to find one of the vtblbasex registers with the VM ID, and looks up the virtual interrupt affinity table stored in the memory pointed to by the register. From the interrupt affinity table, it obtains the vhartid of the vCPU that handles the interrupt as defined by the virtual machine. The interrupt router looks up ifmapx to find the physical processor number x corresponding to the register with the VM ID and vhartid, where x is the mhartid of the target physical processor. The interrupt router sends the pass-through peripheral interrupt to the sending device of the physical processor with the mhartid. The sending device determines the current virtualization state of the CPU. If V=1, it directly sends the pass-through peripheral interrupt to the virtual machine; if V=0, it sends it to the host machine for processing. That is, after the virtual machine comes online, the host machine sends the pass-through peripheral interrupt to the virtual machine.

[0195] The solutions provided in this application, through a control device, an intermediate device, and a sending device, enable virtual partial interrupts to occur from the partial interrupt device to the vCPU without trapping back to the host machine. Through the control device, routing device, and sending device, virtual software interrupts are implemented without software cooperation between the virtual machine and the host machine, ensuring no trapping back to the host machine from the sending vCPU to the receiving vCPU. Furthermore, through the control device, routing device, and sending device, virtual device interrupts are implemented from the host machine's simulated logic to the receiving host vCPU without context switching or trapping back to the host machine. Therefore, the solutions provided in this application can accelerate the performance of virtual machine I / O, clock, scheduling, etc. Simulation data shows that using this solution to handle virtual partial interrupts results in an 80% improvement for Redis and a 6% improvement for handling virtual software interrupts.

[0196] The above describes the process of handling virtual interrupts through hardware circuits. The process of handling virtual interrupts provided in this application embodiment can also be implemented in software. This software implementation can also be combined with the above-mentioned chip system, which includes a source physical processor, a control device, an intermediate device, and a transmitting device. The control device includes a register; the register is used to receive information for triggering virtual interrupts. The functions of the control device, intermediate device, and transmitting device can be implemented in the form of software code, which will be described below with reference to the accompanying drawings.

[0197] like Figure 16 As shown, one embodiment of the method for processing virtual interrupts provided in this application includes:

[0198] 101. The control device reads information from the register used to trigger a virtual interrupt.

[0199] The information used to trigger the virtual interrupt comes from the host machine or virtual machine running in the source physical processor.

[0200] 102. The control device sends the information used to trigger the virtual interrupt to the intermediate device, and the intermediate device receives the information used to trigger the virtual interrupt.

[0201] 103. The intermediate device triggers a virtual interrupt based on the information used to trigger the virtual interrupt.

[0202] 104. The intermediate device sends the virtual interrupt to the sending device, and the sending device receives the virtual interrupt accordingly.

[0203] 105. The sending device sends the virtual interrupt to the target physical processor. The solution provided in this application embodiment sets up a dedicated register for handling virtual interrupts in the control device. Thus, the host machine or virtual machine in user mode can directly write the information used to trigger the virtual interrupt into this register. The control device can send this information to an intermediate device, which triggers the virtual interrupt. The intermediate device then sends the virtual interrupt to the sending device, which in turn sends it to the target physical processor. In the solution provided in this application, both the host machine and the virtual machine can directly access the register to write the information used to trigger the virtual interrupt into the register, thereby sending the virtual interrupt out. Therefore, compared to the prior art, the solution provided in this application does not require the source physical processor to perform a switch from the virtual machine to the host machine, or a switch from the user mode of the host machine to the kernel mode of the host machine, thereby reducing the switching overhead caused by handling virtual interrupts and improving the performance of the chip system.

[0204] When the virtual interrupt is a virtual partial interrupt, the target physical processor and the source physical processor are the same physical processor; the register receives the information written by the virtual machine to trigger the virtual partial interrupt.

[0205] The intermediate device generates a virtual local interrupt based on the information used to trigger the virtual local interrupt.

[0206] The sending device will send the virtual local interrupt to the first virtual processor (vCPU) of the virtual machine, which runs on the source physical processor.

[0207] When the virtual interrupt is a virtual software interrupt, the information for triggering the virtual interrupt read from the register in step 101 above includes the identifier of the second vCPU written from the first vCPU of the virtual machine to the register, where the second vCPU is the vCPU of the virtual machine running on the target physical processor.

[0208] Before step 102, the control device obtains the identifier of the virtual machine; then step 103 specifically includes sending the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device.

[0209] Step 103 specifically includes the intermediate device determining the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from the first correspondence relationship based on the identifier of the virtual machine and the identifier of the second vCPU; wherein, the first correspondence relationship is used to record the correspondence between the target physical processor, the second vCPU running on the target processor and the virtual machine; and triggering a virtual software interrupt.

[0210] Step 104 includes: the intermediate device sending the virtual software interrupt to the sending device corresponding to the target physical processor.

[0211] Step 105 includes: the sending device sending a virtual software interrupt to a second vCPU running on the target physical processor.

[0212] When the virtual interrupt is a virtual device interrupt, the information for triggering the virtual interrupt read from the register in step 101 above includes the target interrupt number written to the register by the host and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device.

[0213] Step 102 includes: the control device sending the virtual machine's identifier and target interrupt number to the intermediate device.

[0214] Step 103 includes: the intermediate device searching for the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in a second correspondence relationship based on the identifier of the virtual machine and the target interrupt number; the second correspondence relationship is used to record the correspondence between the virtual machine, the target interrupt number and the first vCPU; determining the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU from a third correspondence relationship based on the identifier of the virtual machine and the identifier of the first vCPU; wherein, the third correspondence relationship is used to record the correspondence between the target physical processor, the first vCPU running on the target processor and the virtual machine; and generating a virtual device interrupt.

[0215] Step 104 includes: the intermediate device sending the virtual device interrupt to the sending device corresponding to the target physical processor.

[0216] Step 105 includes: the sending device sending a virtual device interrupt to the first vCPU running on the target physical processor.

[0217] The functions of the control device, intermediate device, and transmitting device implemented through software are described above. Figures 2 to 15 The relevant content in the corresponding embodiments will be understood and will not be repeated here.

[0218] The above describes a method for handling virtual interrupts using software. The following section, with reference to the accompanying drawings, describes the apparatus for implementing the above method for handling virtual interrupts.

[0219] like Figure 17 As shown, one embodiment of the control device 20 provided in this application includes: the control device 20 is applied to a chip system, the chip system further includes a source physical processor, an intermediate device, a transmitting device, and a target physical processor, the source physical processor is used to run a host machine or a virtual machine, and the control device includes a register; the register is used to receive information for triggering a virtual interrupt, the information for triggering the virtual interrupt comes from the host machine or the virtual machine, and the control device 20 includes:

[0220] The read unit 201 is used to read information from the register for triggering a virtual interrupt.

[0221] The sending unit 202 is used to send the information for triggering a virtual interrupt read by the reading unit 201 to the intermediate device. The information for triggering a virtual interrupt is used by the intermediate device to trigger a virtual interrupt, and the virtual interrupt is sent by the sending device to the target physical processor.

[0222] Optionally, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, the register is used to receive information written by the virtual machine to trigger the virtual local interrupt; the information to trigger the virtual local interrupt is used to enable the intermediate device to trigger the virtual local interrupt, the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0223] Optionally, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second vCPU written to the register of the first vCPU of the virtual machine, the second vCPU being the vCPU of the virtual machine running on the target physical processor; the control device 20 also includes a processing unit 203.

[0224] Processing unit 203 is used to obtain the identifier of the virtual machine.

[0225] The sending unit 202 is used to send the identifier of the virtual machine to the intermediate device. The identifier of the virtual machine and the identifier of the second vCPU are used by the intermediate device to determine the target physical processor and trigger a virtual software interrupt. The virtual software interrupt is sent by the sending device to the second vCPU of the target physical processor.

[0226] Optionally, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written to the register by the host and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device. The identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt. The virtual device interrupt is sent by the sending device to the first vCPU of the target physical processor.

[0227] like Figure 18 As shown, one embodiment of the intermediate device 30 provided in this application includes: the intermediate device 30 is applied to a chip system, the chip system further includes a source physical processor, a control device, a transmitting device, and a target physical processor, the source physical processor is used to run a host machine or a virtual machine, the control device includes a register; the register is used to receive information for triggering a virtual interrupt, the information for triggering a virtual interrupt comes from the host machine or the virtual machine, and the intermediate device 30 includes:

[0228] The receiving unit 301 is used to receive information from the control device for triggering a virtual interrupt.

[0229] The processing unit 302 is used to trigger a virtual interrupt based on the information used to trigger the virtual interrupt.

[0230] The sending unit 303 is used to send a virtual interrupt to the sending device, and the virtual interrupt is sent by the sending device to the target physical processor.

[0231] Optionally, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, the register is used to receive information written by the virtual machine to trigger the virtual local interrupt; the information to trigger the virtual local interrupt is used to trigger the virtual local interrupt, the virtual local interrupt is sent by the sending device to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0232] Optionally, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second vCPU written to the register by the first vCPU of the virtual machine, where the second vCPU is the vCPU of the virtual machine running on the target physical processor.

[0233] The processing unit 302 is configured to determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from a first correspondence relationship based on the identifier of the virtual machine and the identifier of the second vCPU; wherein the first correspondence relationship is used to record the correspondence between the target physical processor, the second vCPU running on the target processor and the virtual machine; and trigger a virtual software interrupt, which is sent by the sending device to the second vCPU of the target physical processor.

[0234] Optionally, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written to the register by the host and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device.

[0235] The processing unit 302 is configured to: search for the identifier of the first vCPU of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number in a second correspondence relationship based on the identifier of the virtual machine and the target interrupt number; the second correspondence relationship is used to record the correspondence between the virtual machine, the target interrupt number, and the first vCPU; determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first vCPU from a third correspondence relationship based on the identifier of the virtual machine and the identifier of the first vCPU; wherein the third correspondence relationship is used to record the correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine; and trigger a virtual device interrupt, which is sent by the sending device to the first vCPU of the target physical processor.

[0236] Optionally, the processing unit 302 is further configured to locate the address register based on the virtual machine's identifier, and retrieve the second correspondence from memory based on the address in the address register. The address register is used to store the address of the second correspondence in memory and the virtual machine's identifier.

[0237] like Figure 19 As shown, one embodiment of the transmitting device 40 provided in this application includes: the transmitting device 40 is applied to a chip system, the chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor, the source physical processor is used to run a host machine or a virtual machine, the control device includes a register; the register is used to receive information for triggering a virtual interrupt, the information for triggering a virtual interrupt comes from the host machine or the virtual machine, and the transmitting device 40 includes:

[0238] The receiving unit 401 is used to receive a virtual interrupt from the intermediate device.

[0239] The sending unit 402 is used to send the virtual interrupt to the target physical processor.

[0240] Optionally, the virtual interrupt is a virtual partial interrupt, and the target physical processor and the source physical processor are the same physical processor; the sending unit 402 is used to send the virtual partial interrupt to the first virtual processor vCPU of the virtual machine, and the first vCPU runs on the source physical processor.

[0241] Optionally, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second vCPU written to the register by the first vCPU of the virtual machine, where the second vCPU is the vCPU of the virtual machine running on the target physical processor.

[0242] The sending unit 402 is used to send virtual software interrupts to a second vCPU running on the target physical processor.

[0243] Optionally, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written to the register by the host and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host simulates a hardware device.

[0244] The sending unit 402 is used to send the virtual device interrupt to the first vCPU running on the target physical processor.

[0245] Optionally, the sending unit 402 is used to write the virtual interrupt into the pending register of the target physical processor, and the pending register is used to receive the commands of the process executed by the target physical processor.

[0246] above Figures 17 to 19 The described solution can be found in the above reference. Figures 2 to 15 The relevant content in the corresponding embodiments will be understood and will not be repeated here.

[0247] Figure 20 The diagram shown illustrates a possible logical structure of a computer device 50 provided in an embodiment of this application. The computer device 50 may include the aforementioned... Figures 17 to 19 The control device, intermediate device, or transmitting device described herein, the computer device 50, includes: a processor 501, a communication interface 502, a memory 503, and a bus 504. The processor 501, communication interface 502, and memory 503 are interconnected via the bus 504. In embodiments of this application, the processor 501 is used to control and manage the operations of the computer device 50; for example, the processor 501 is used to execute... Figure 16 Steps 101 or 103 in the method embodiments. Memory 503 is used to store program code and data of the computer device 50. Communication interface 502 can be used to execute... Figure 16 Steps 102, 104, or 105 in the method embodiments.

[0248] The processor 501 can be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor 501 can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, etc. The bus 504 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 20 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0249] In another embodiment of this application, a computer-readable storage medium is also provided, which stores computer-executable instructions. When the processor of the device executes the computer-executable instructions, the device performs the aforementioned... Figure 16 The method of handling virtual interrupts executed by the control device, intermediate device or transmitting device in the process.

[0250] In another embodiment of this application, a computer program product is also provided, the computer program product including computer-executable instructions stored in a computer-readable storage medium; when the processor of the device executes the computer-executable instructions, the device performs the above-described... Figure 16 The method of handling virtual interrupts executed by the control device, intermediate device or transmitting device in the process.

[0251] Another embodiment of this application provides a chip system, which includes a source physical processor, a control device, a transmitting device, and a target physical processor. The control device is as described above. Figures 2 to 15 The control device described in the embodiments, the transmitting device as described above Figures 2 to 15 The transmitting apparatus described in the embodiments.

[0252] In one possible embodiment, the chip system may further include the components described above. Figures 2 to 15 The intermediate device described in the embodiments.

[0253] In one possible embodiment, the chip system is a processor, where the source physical processor and the target physical processor are physical cores within the processor. A control device is a component located within the processor and coupled to the source physical processor, and a transmitting device is a component located within the processor and coupled to the target physical processor. It is understood that since any physical core in the processor can act as a receiver of a virtual interrupt, a physical core can function as both a source and a target physical processor. Correspondingly, the components coupled to this physical core can include both a control device and a transmitting device.

[0254] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0255] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0256] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0257] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0258] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0259] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this application, essentially, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0260] The above are merely specific embodiments of this application, but the protection scope of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the protection scope of this application. Therefore, the protection scope of this application should be determined by the scope of the claims.

Claims

1. A chip system, characterized in that, include: The system includes a source physical processor, a control device, and a target physical processor. The source physical processor is used to run a virtual machine. The control device includes a register for receiving information for triggering a virtual interrupt. The information for triggering the virtual interrupt comes from the virtual machine, and the virtual interrupt is a virtual software interrupt. The control device is configured to: send the information for triggering a virtual interrupt in the register, wherein the information for triggering a virtual interrupt is used to trigger the virtual software interrupt; The target physical processor is used to: receive the virtual software interrupt.

2. The chip system according to claim 1, characterized in that, The chip system also includes an intermediate device, which is used to receive information sent by the control device for triggering a virtual interrupt, and to trigger the virtual software interrupt according to the information for triggering the virtual interrupt.

3. The chip system according to claim 2, characterized in that, The information used to trigger the virtual interrupt includes the identifier of the second virtual processor written by the first virtual processor of the virtual machine into the register, wherein the second virtual processor is the virtual processor of the virtual machine running on the target physical processor; The control device is configured to: read the identifier of the second virtual processor from the register and obtain the identifier of the virtual machine; and send the identifier of the virtual machine and the identifier of the second virtual processor to the intermediate device; The intermediate device is used for: Based on the identifier of the virtual machine and the identifier of the second virtual processor, the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second virtual processor is determined from the first correspondence relationship; wherein, the first correspondence relationship is used to record the correspondence between the target physical processor, the second virtual processor running on the target processor, and the virtual machine; The virtual software interrupt is sent to the target physical processor.

4. The chip system according to claim 3, characterized in that, The intermediate device includes an address register, which is used to store the address of the second correspondence in memory and the identifier of the virtual machine; The intermediate device is further configured to: locate the address register based on the identifier of the virtual machine, and obtain the second correspondence from the memory based on the address in the address register.

5. A chip system, characterized in that, include: The system comprises a source physical processor, a control device, an intermediate device, and a target physical processor. The control device includes a register for receiving information for triggering a virtual interrupt. The information for triggering the virtual interrupt comes from a host machine or a virtual machine, which runs on the source physical processor. The control device is used to: send the information in the register used to trigger a virtual interrupt to the intermediate device; The intermediate device is configured to: trigger the virtual interrupt according to the information for triggering the virtual interrupt, and send the virtual interrupt to the target physical processor; The target physical processor is used to: receive the virtual interrupt from the intermediate device.

6. The chip system according to claim 5, characterized in that, The chip system also includes a transmitting device for receiving the virtual interrupt from the intermediate device and sending the virtual interrupt to the target physical processor.

7. The chip system according to claim 6, characterized in that, The virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor; The register is used to: receive information written by the virtual machine for triggering the virtual local interrupt; The sending device is used to send the virtual local interrupt to the first virtual processor of the virtual machine, the first virtual processor running on the source physical processor.

8. The chip system according to claim 6, characterized in that, The virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second virtual processor written by the first virtual processor of the virtual machine into the register, wherein the second virtual processor is the virtual processor of the virtual machine running on the target physical processor; The control device is configured to: read the identifier of the second virtual processor from the register and obtain the identifier of the virtual machine; and send the identifier of the virtual machine and the identifier of the second virtual processor to the intermediate device; The intermediate device is used for: Based on the identifier of the virtual machine and the identifier of the second virtual processor, the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second virtual processor is determined from the first correspondence relationship; wherein, the first correspondence relationship is used to record the correspondence between the target physical processor, the second virtual processor running on the target processor, and the virtual machine; The virtual software interrupt is sent to the sending device corresponding to the target physical processor; The sending device is used to send the virtual software interrupt to the second virtual processor running on the target physical processor.

9. The chip system according to claim 6, characterized in that, The virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written to the register by the host machine and the identifier of the virtual machine. The target interrupt number is the identifier of the interrupt triggered when the host machine simulates a hardware device. The control device is configured to: read the target interrupt number and the identifier of the virtual machine from the register, and send the identifier of the virtual machine and the target interrupt number to the intermediate device; The intermediate device is used for: Based on the identifier of the virtual machine and the target interrupt number, the identifier of the first virtual processor of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number is found in the second correspondence relationship. The second correspondence relationship is used to record the correspondence between the virtual machine, the target interrupt number and the first virtual processor. Based on the identifier of the virtual machine and the identifier of the first virtual processor, the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first virtual processor is determined from the third correspondence relationship; wherein, the third correspondence relationship is used to record the correspondence between the target physical processor, the first virtual processor running on the target processor, and the virtual machine; The virtual device interrupt is sent to the sending device corresponding to the target physical processor; The sending device is used to send the virtual device interrupt to the first virtual processor running on the target physical processor.

10. The chip system according to claim 5, characterized in that, The intermediate device includes an address register, which is used to store the address of the second correspondence in memory and the identifier of the virtual machine; The intermediate device is further configured to: locate the address register based on the identifier of the virtual machine, and obtain the second correspondence from the memory based on the address in the address register.

11. A method for handling virtual interrupts, the method being applied to a chip system, the chip system including a source physical processor, a control device, and a target physical processor, the source physical processor being used to run a virtual machine, the control device including a register for receiving information for triggering a virtual interrupt, the information for triggering the virtual interrupt originating from the virtual machine, the virtual interrupt being a virtual software interrupt, characterized in that... The method includes: The control device sends the information for triggering the virtual interrupt from the register, and the information for triggering the virtual interrupt is used to trigger the virtual software interrupt; The target physical processor receives the virtual software interrupt.

12. The method according to claim 11, characterized in that, The chip system also includes an intermediate device that receives information sent by the control device to trigger a virtual interrupt and triggers the virtual software interrupt according to the information.

13. The method according to claim 12, characterized in that, The information used to trigger the virtual interrupt includes the identifier of the second virtual processor written by the first virtual processor of the virtual machine into the register, wherein the second virtual processor is the virtual processor of the virtual machine running on the target physical processor; The control device reads the identifier of the second virtual processor from the register and obtains the identifier of the virtual machine; and sends the identifier of the virtual machine and the identifier of the second virtual processor to the intermediate device; The intermediate device determines the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second virtual processor from a first correspondence relationship based on the identifier of the virtual machine and the identifier of the second virtual processor; wherein, the first correspondence relationship is used to record the correspondence between the target physical processor, the second virtual processor running on the target processor, and the virtual machine; The virtual software interrupt is sent to the target physical processor.

14. A method for handling virtual interrupts, the method being applied to a chip system, the chip including a source physical processor, a control device, an intermediate device, and a target physical processor, the control device including a register for receiving information for triggering a virtual interrupt, the information for triggering the virtual interrupt originating from a host machine or a virtual machine, the host machine or the virtual machine running on the source physical processor, characterized in that: The control device sends the information in the register used to trigger a virtual interrupt to the intermediate device. The intermediate device triggers the virtual interrupt based on the information used to trigger the virtual interrupt, and sends the virtual interrupt to the target physical processor; The target physical processor receives the virtual interrupt from the intermediate device.

15. The method according to claim 14, characterized in that, The chip system also includes a transmitting device that receives the virtual interrupt from the intermediate device and sends the virtual interrupt to the target physical processor.

16. The method according to claim 15, characterized in that, The virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second virtual processor written by the first virtual processor of the virtual machine into the register, wherein the second virtual processor is the virtual processor of the virtual machine running on the target physical processor; The control device reads the identifier of the second virtual processor from the register and obtains the identifier of the virtual machine; and sends the identifier of the virtual machine and the identifier of the second virtual processor to the intermediate device; The intermediate device determines the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second virtual processor from a first correspondence relationship based on the identifier of the virtual machine and the identifier of the second virtual processor; wherein, the first correspondence relationship is used to record the correspondence between the target physical processor, the second virtual processor running on the target processor, and the virtual machine; The virtual software interrupt is sent to the sending device corresponding to the target physical processor; The sending device sends the virtual software interrupt to the second virtual processor running on the target physical processor.

17. The method according to claim 14, characterized in that, The intermediate device includes an address register, which is used to store the address of the second correspondence in memory and the identifier of the virtual machine; The intermediate device locates the address register based on the identifier of the virtual machine, and retrieves the second correspondence from the memory based on the address in the address register.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 11-13, or, when executed, it implements the method as described in any one of claims 14-17.

19. A computer device, characterized in that, The computer device includes the chip system described in any one of claims 1-4, or the chip system described in claims 5-10.

Images