Thread bundle construction device and method and processor

Abstract

The invention discloses a thread bundle construction device and method and a processor. A thread block dimension register and a mode configuration register respectively store thread block dimension information and mode configuration information in a thread bundle construction request; the loop controller responds to the thread bundle construction request, reads thread block dimension information and mode configuration information to calculate the total loop number, and controls the thread bundle calculation construction array to execute and stop thread coordinate calculation; the thread beam calculation construction array starts a specified thread beam calculation construction unit according to the mode configuration information under the control of the loop controller so as to circularly execute thread coordinate calculation according to a clock period and output thread coordinates obtained through calculation; wherein the specified thread bundle calculation construction unit performs boundary judgment and thread coordinate adjustment according to thread block dimension information in the thread coordinate calculation process. According to the method, linear and Zig-Zag thread arrangement modes can be supported, Z-axis-crossing continuous coordinate calculation is achieved, and then the hardware utilization efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of artificial intelligence chip, and particularly relates to a thread bundle construction device and method and a processor. BACKGROUND

[0002] Before an artificial intelligence chip executes a computing task, a set of threads (i.e., a thread block) needs to be grouped to construct a thread bundle (usually 32 threads in a group), and each thread is assigned a unique coordinate (i.e., a thread ID) to achieve the mapping between the computing task and the hardware execution resources. The existing thread bundle construction device has the following limitations when processing irregular thread blocks or non-continuous thread arrangement modes: (1) When the size of the thread block in a certain dimension is not a fixed value, or the XY plane size is not an integer multiple of 32, thread coordinate calculation is difficult, and since Z-axis continuous coordinate calculation cannot be achieved, incomplete thread bundles (thread number < 32) are easily generated, reducing hardware utilization efficiency.

[0003] (2) Only linear arrangement is supported, Zig-Zag arrangement cannot be achieved, and it is difficult to meet the needs of computing scenarios such as block data access required by texture sampling. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a thread bundle construction device, method and processor, which supports linear and Zig-Zag thread arrangement modes through a configurable thread bundle construction array, can efficiently and continuously complete multi-dimensional thread coordinate calculation and boundary processing in each clock cycle, and thus realizes continuous coordinate calculation across the Z-axis.

[0005] The first embodiment of the first aspect of the present application provides a thread bundle construction device, comprising: a thread block dimension register configured to store thread block dimension information carried in a thread bundle construction request; a mode configuration register configured to store mode configuration information carried in the thread bundle construction request; a cycle controller configured to, in response to the thread bundle construction request, read the thread block dimension information and the mode configuration information after entering a thread bundle construction state, calculate a total cycle number, and control a thread bundle calculation construction array to perform thread coordinate calculation; a thread bundle calculation construction array configured to, under the control of the cycle controller, enable a specified thread bundle calculation construction unit according to the mode configuration information, perform thread coordinate calculation in a clock cycle, and output the calculated thread coordinates; wherein the specified thread bundle calculation construction unit performs boundary judgment and thread coordinate adjustment according to the thread block dimension information during thread coordinate calculation. The cycle controller is further configured to control the specified thread bundle calculation and construction unit to stop thread coordinate calculation when the number of cycles of the specified thread bundle calculation and construction unit reaches the total number of cycles.

[0006] Optionally, the thread bundle construction request is initiated by an external task allocation unit.

[0007] Optionally, the mode configuration information comprises a thread arrangement mode and a number of arithmetic logic units called per clock cycle; the thread arrangement mode comprises a linear mode, an N-shaped mode or a Z-shaped mode; and the number of arithmetic logic units is used to represent a calculation granularity.

[0008] Optionally, the thread bundle calculation and construction array comprises M1 thread bundle calculation and construction units in a linear mode, M2 thread bundle calculation and construction units in an N-shaped mode, M3 thread bundle calculation and construction units in a Z-shaped mode, and a multiplexer; the multiplexer is used to enable a specified thread bundle calculation and construction unit and output a calculated thread coordinate according to the mode configuration information; M1≥1; M2≥1; and M3≥1.

[0009] Optionally, the enabling of the specified thread bundle calculation and construction unit to perform thread coordinate calculation in a clock cycle comprises: calculating all thread coordinates in a current clock cycle based on a thread coordinate initial value of the current clock cycle according to an increment rule defined by a corresponding thread arrangement mode through the specified thread bundle calculation and construction unit; comparing each dimension coordinate value of the currently calculated thread coordinate with a dimension size determined by the thread block dimension information to obtain a corresponding comparison result during the calculation of each thread coordinate; if the comparison result is that no dimension coordinate value is out of bounds, maintaining the currently calculated thread coordinate; if the comparison result is that there is a dimension coordinate value out of bounds, resetting the dimension coordinate value out of bounds to an initial value and carrying over to a higher dimension coordinate value; taking the last thread coordinate calculated in the current clock cycle as a thread coordinate initial value of a next clock cycle until the number of cycles reaches the total number of cycles.

[0010] Optionally, the resetting of the dimension coordinate value out of bounds to the initial value and the carrying over to the higher dimension coordinate value comprise: resetting the dimension coordinate value out of bounds to 0 and adding 1 to a coordinate value of a higher dimension; if the coordinate value of the higher dimension is out of bounds after adding 1, resetting the coordinate value of the higher dimension to 0 and continuing to add 1 to a coordinate value of a higher dimension.

[0011] Optionally, the arithmetic logic unit is multiplexed between the thread bundle calculation construction units.

[0012] Optionally, when the thread arrangement mode is the N-shaped mode or the Z-shaped mode, sizes corresponding to the X dimension and the Y dimension in the thread block dimension information respectively have an integer multiple relationship with sizes of corresponding thread arrangement granularities in the X dimension and the Y dimension.

[0013] Optionally, the calculated thread coordinates are output to an external thread bundle coordinate buffer.

[0014] The second aspect embodiment of the present application provides a thread bundle construction method, which is suitable for the thread bundle construction device of any one of the first aspect embodiments, and the method comprises the following steps: The thread block dimension information carried in the thread bundle construction request is stored in the thread block dimension register; The mode configuration information carried in the thread bundle construction request is stored in the mode configuration register; After the loop controller responds to the thread bundle construction request and enters the thread bundle construction state, the thread block dimension information and the mode configuration information are read, the total number of loops is calculated, and the thread bundle calculation construction array is controlled to execute thread coordinate calculation; The thread bundle calculation construction array is controlled by the loop controller, and according to the mode configuration information, a specified thread bundle calculation construction unit is enabled to execute thread coordinate calculation in a clock cycle loop and output the calculated thread coordinates; wherein, in the thread coordinate calculation process, the specified thread bundle calculation construction unit performs boundary judgment and thread coordinate adjustment according to the thread block dimension information; When the number of loops of the specified thread bundle calculation construction unit reaches the total number of loops, the loop controller controls the specified thread bundle calculation construction unit to stop thread coordinate calculation.

[0015] The third aspect embodiment of the present application provides a processor comprising the thread bundle construction device of any one of the first aspect embodiments.

[0016] Compared with the prior art, the thread bundle construction device, method and processor provided by the embodiment of the present application have the following beneficial effects: the embodiment of the present application supports multiple linear and Zig-Zag thread arrangement modes by using a configurable thread bundle calculation construction array, and can efficiently and flexibly process thread blocks of different dimensions and sizes; meanwhile, the specified thread bundle calculation construction unit performs thread coordinate calculation in a clock cycle, can realize continuous iteration of thread coordinates, and can perform boundary judgment and thread coordinate adjustment according to the thread block dimension information in the thread coordinate calculation process, so as to realize continuous coordinate calculation across the Z axis, to construct as many complete thread bundles as possible, and to improve hardware utilization efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a schematic diagram of an embodiment of thread bundle division provided by the related art; Figure 2 is a schematic diagram of another embodiment of thread bundle division provided by the related art; FIG. 3(a) is a schematic diagram of an embodiment of a linear arrangement mode provided by the present application; FIG. 3(b) is a schematic diagram of an embodiment of an N-type Zig-Zag mode provided by the present application; FIG. 3(c) is a schematic diagram of an embodiment of a Z-type Zig-Zag mode provided by the present application; Figure 4 is a structural schematic diagram of an embodiment of a thread bundle construction device provided by the present application; Figure 5 is a structural schematic diagram of an embodiment of a thread bundle calculation construction unit provided by the present application; Figure 6 is a structural schematic diagram of another embodiment of a thread bundle calculation construction unit provided by the present application; Figure 7 is a schematic diagram of an embodiment of thread X coordinate calculation provided by the present application; Figure 8 is a flow schematic diagram of an embodiment of a thread bundle construction method provided by the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the protection scope of the present application.

[0019] The artificial intelligence processor involved in the present application can be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), an NPU (Neural network Processing Unit), a DPU (Deeplearning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit), as determined when the embodiments of the present application are applied to specific products or technologies.

[0020] It should be noted that, as Figure 1 shown, is a schematic diagram of an embodiment of thread bundle division provided by the related art. In Figure 1 each small square represents a thread, and a set of threads is a thread block. Each thread has a corresponding coordinate, and 32 threads form a thread bundle (Warp). In the existing programming model of GPGPU, the coordinates of each thread need to be calculated before the running of the calculation task can be started.

[0021] On the one hand, the related art usually defaults to a fixed value of the number of threads in each direction (X, Y, Z dimension) of the thread block, and if the size in a certain dimension is not a fixed value, it is difficult to implement the construction of the thread bundle. In addition, since the related art cannot be continuous in the Z axis when calculating the thread coordinates, when the number of threads in the XY plane is not equal to 32*N (N is a positive integer), an incomplete thread bundle (the number of threads < 32) will be generated, as Figure 2 shown, is a schematic diagram of another embodiment of thread bundle division provided by the related art.

[0022] On the other hand, the related art only supports linear arrangement (such as FIG. 3(a)), however, in related calculation scenarios such as texture sampling, texture data is usually stored in the form of pixel blocks, and correspondingly, the threads in the thread block should also be arranged in a similar tile mode, such as the N-shaped (N-type Zig-Zag) arrangement shown in FIG. 3(b) or the Z-shaped (Z-type Zig-Zag) arrangement shown in FIG. 3(c). The related art lacks Zig-Zag arrangement mode, which limits its applicability and performance in different calculation tasks.

[0023] Referring toFigure 4 is a structural schematic diagram of an embodiment of the thread bundle construction device provided by the present application.

[0024] To solve the above technical problems, the first aspect embodiment of the present application provides a thread bundle construction device, comprising: a thread block dimension register 100, configured to store thread block dimension information carried in a thread bundle construction request; a mode configuration register 200, configured to store mode configuration information carried in the thread bundle construction request; a loop controller 300, configured to read the thread block dimension information and the mode configuration information after entering a thread bundle construction state in response to the thread bundle construction request, calculate a total loop number, and control a thread bundle calculation construction array 400 to execute thread coordinate calculation; the thread bundle calculation construction array 400, configured to enable a specified thread bundle calculation construction unit to execute thread coordinate calculation in a clock cycle according to the mode configuration information under the control of the loop controller 300, and output the calculated thread coordinates; wherein the specified thread bundle calculation construction unit performs boundary judgment and thread coordinate adjustment according to the thread block dimension information in the thread coordinate calculation process; the loop controller 300 is further configured to control the specified thread bundle calculation construction unit to stop thread coordinate calculation when the loop number of the specified thread bundle calculation construction unit reaches the total loop number.

[0025] It should be noted that, as shown in Figure 4 the thread bundle construction device mainly comprises the thread block dimension register 100, the mode configuration register 200, the loop controller 300 and the thread bundle calculation construction array 400. The working principle of the thread bundle construction device is as follows: An external task allocation unit initiates a thread bundle construction request to the thread bundle construction device, and stores thread block dimension information and related mode configuration information carried in the thread bundle construction request into the thread block dimension register 100 and the mode configuration register 200 respectively.

[0026] The thread block dimension information includes the size of the to-be-split thread block in each dimension (i.e. the number of threads in each dimension, such as thread_block_x_size, thread_block_y_size and thread_block_z_size), which is used for boundary judgment in the calculation process of the thread bundle construction calculation unit, and for the loop controller 300 to calculate the total loop number; The mode configuration information includes: a thread arrangement mode and an arithmetic logic unit (ALU) number called per clock cycle; the thread arrangement mode includes: a linear mode, an N-type Zig-Zag mode or a Z-type Zig-Zag mode; and the ALU number represents a calculation granularity (i.e., the number of thread coordinates calculated per cycle).

[0027] The loop controller 300 internally contains a state machine, after receiving a thread bundle construction request and entering a thread bundle construction state, thread block dimension information is input through the thread block dimension register 100 to obtain the total thread number, and the ALU number is input through the mode configuration register 200; further, the total loop number is calculated by taking the total thread number / ALU number and rounding up. The loop controller 300 is also used to control the specified thread bundle calculation construction unit in the thread bundle calculation construction array 400 to perform thread coordinate calculation, and when the loop number reaches the total loop number, the specified thread bundle calculation construction unit is controlled to stop operation and return to the idle (IDLE) state.

[0028] The thread bundle calculation construction array 400 is composed of a plurality of configurable thread bundle construction calculation units (thread bundle calculation construction units in one / two / three-dimensional linear mode, thread bundle calculation construction units in two / three-dimensional N-type Zig-Zag mode, and thread bundle calculation construction units in two / three-dimensional Z-type Zig-Zag mode) and a multiplexer. Each thread bundle construction calculation unit adapts to different mode configuration information. The thread bundle calculation construction array 400 automatically enables the matching specified thread bundle calculation construction unit through the multiplexer according to the mode configuration information transmitted by the mode configuration register 200; under the control of the loop controller 300, the specified thread bundle calculation construction unit performs loop calculation with the thread coordinates calculated by the ALU number per clock cycle, and boundary judgment and coordinate adjustment are performed in real time during the calculation process according to the thread block dimension information in the thread block dimension register 100.

[0029] Exemplarily, when calculating the X-axis coordinate of a three-dimensional thread block, if the current X-axis coordinate is the size W of the X dimension, the current X-axis coordinate is reset to 0 (reset to 0), and the Y-axis coordinate is triggered to carry over (add 1); if the Y-axis coordinate is the size H of the Y dimension, the Y-axis coordinate is reset to 0, and the Z-axis coordinate is triggered to carry over (add 1), so as to ensure that the thread coordinate value (x, y, z) is always within the valid range of “0≤xW, 0≤y<H, 0≤z<D”, avoid out-of-bound errors, and enable continuous coordinate calculation across the Z-axis to construct as many complete thread bundles as possible; where D is the size of the Z dimension.

[0030] Further, the thread bundle calculation construction unit is also configured to output the calculated thread coordinates to a thread bundle coordinate buffer outside the thread bundle construction device for storage, for subsequent operation scheduling.

[0031] In an optional embodiment, the mode configuration information comprises: a thread arrangement mode and a number of arithmetic logic units called per clock cycle; wherein the thread arrangement mode comprises: a linear mode, an N-shaped mode or a Z-shaped mode; and the number of arithmetic logic units is used to represent a calculation granularity.

[0032] Further, when the thread arrangement mode is the N-shaped mode or the Z-shaped mode, the sizes corresponding to the X dimension and the Y dimension in the thread block dimension information respectively have an integer multiple relationship with the sizes of the corresponding thread arrangement granularity in the X dimension and the Y dimension.

[0033] It should be noted that the N-shaped mode comprises a regular N-shaped Zig-Zag mode or an inverse N-shaped Zig-Zag mode; and the Z-shaped mode comprises a regular Z-shaped Zig-Zag mode or an inverse Z-shaped Zig-Zag mode.

[0034] The size of the thread arrangement granularity corresponding to the N-shaped mode is 2xk (threads are arranged in small blocks with a unit of 2xk), as shown in FIG. 3(b) is a regular N-shaped Zig-Zag mode, the size of the thread arrangement granularity is 2x2, the number of ALUs selected is 4 (4 thread coordinates are calculated per clock cycle) and the thread bundle construction calculation unit of the regular N-shaped Zig-Zag mode is used to calculate the coordinates; wherein k≥2.

[0035] The size of the thread arrangement granularity corresponding to the Z-shaped mode is mx2 (threads are arranged in small blocks with a unit of mx2), as shown in FIG. 3(c) is an inverse Z-shaped Zig-Zag mode, the size of the thread arrangement granularity is 2x2, the number of ALUs selected is 4 (4 thread coordinates are calculated per clock cycle) and the thread bundle construction calculation unit of the inverse Z-shaped Zig-Zag mode is used to calculate the coordinates; wherein m≥2.

[0036] Further, in the Zig-Zag mode, how the threads are arranged according to the thread arrangement granularity and how many thread coordinates are calculated per clock cycle are corresponding, and the number of ALUs called by the thread bundle calculation construction unit of the Zig-Zag mode is also corresponding.

[0037] In particular, for Zig-Zag mode, the size of the X dimension and the Y dimension of the thread block has the following constraints: the number of threads of the thread block in the X direction and the Y direction, respectively, must be divisible by the X direction size and the Y direction size of the corresponding thread arrangement granularity, and the total number of threads of the thread block in the XY plane is even. Since the thread arrangement granularity determines the number of ALUs called by the Zig-Zag thread bundle calculation construction unit, the total number of threads of the thread block in the XY plane is also divisible by the number of ALUs called.

[0038] In an optional embodiment, the thread bundle calculation construction array 400 includes: M1 thread bundle calculation construction units of a linear mode, M2 thread bundle calculation construction units of an N-shaped mode, M3 thread bundle calculation construction units of a Z-shaped mode, and a multiplexer; wherein the multiplexer is configured to enable a specified thread bundle calculation construction unit and output the calculated thread coordinates according to the mode configuration information; M1≥1; M2≥1; M3≥1.

[0039] Further, the arithmetic logic units of the thread bundle calculation construction units are multiplexed.

[0040] It should be noted that, as shown in Figure 4 The thread bundle calculation construction array 400 includes three types of thread bundle calculation construction units (linear mode, N-shaped Zig-Zag mode, and Z-shaped Zig-Zag mode). Each type of thread bundle calculation construction unit is composed of a plurality of ALUs, which are responsible for performing the calculation task of thread coordinates; wherein the number of ALUs directly determines the number of thread coordinates that can be calculated by the unit per clock cycle. In the thread bundle construction process, the corresponding thread bundle calculation construction unit is enabled according to the working mode selected by the mode configuration information in the mode configuration register 200, and the result is stored in the thread coordinate cache after the coordinate calculation.

[0041] The "configurable" in the embodiment of the application means that the thread bundle calculation construction array 400 can determine the number of ALUs (i.e. the number of thread coordinates calculated per clock cycle) of different thread bundle calculation construction units at the design time; in other words, the thread bundle calculation construction array 400 can integrate a plurality of different types and a plurality of different calculation granularities of thread bundle calculation construction units in advance at the design time, so as to be selected by the mode configuration information.

[0042] Specifically, if the thread bundle computation building unit in linear mode contains j ALUs, then j thread coordinates will be calculated each clock cycle; if the threads in the thread block are arranged non-linearly and are arranged in small blocks of 2×k or m×2, then the thread bundle computation building unit will also perform coordinate calculations with a computation granularity of 2×k or m×2, that is, 2×k or m×2 ALUs will be called for calculation each clock cycle.

[0043] The values ​​of j, k, and m mentioned above are determined and fixed during the design phase of each thread-beam computing building unit. However, different thread-beam computing building units can reuse ALUs. For example, a linear-mode thread-beam computing building unit configured with 4 ALUs (j=4) and an N-type Zig-Zag-mode thread-beam computing building unit configured with 6 ALUs (k=3, 2×3=6) can share all or part of the computing components in the 4 ALUs, thereby reducing the consumption of hardware resources.

[0044] like Figure 5 The diagram shown is a structural schematic of an embodiment of the thread beam computing building unit provided by the present invention. Figure 5 It includes four ALUs (i.e., coordinate calculation granularity is 4), namely ALU0, ALU1, ALU2, and ALU3; the mode configuration register is used to determine the key parameters of the specified thread bundle calculation building unit, such as the number of ALUs and the incrementing rule defined by the thread arrangement mode; the thread block dimension register is used to store thread block dimension information, providing a basis for boundary judgment during the coordinate calculation process. In linear mode, Figure 5 Each ALU in the system receives the X, Y, and Z coordinates of the previous thread, processes them internally, outputs the X, Y, and Z coordinates of the current thread, and passes them to the next ALU, thereby enabling continuous calculation of coordinates for multiple threads.

[0045] like Figure 6 The diagram shows a structural schematic of another embodiment of the thread bundle computation building unit provided by this invention. Each ALU includes at least three sets of adders (corresponding to the increment operation of coordinates in the X, Y, and Z dimensions, respectively), a comparator, and a selector for each dimension. The comparator is used to determine whether the coordinates in the corresponding dimension are out of bounds, such as whether the X coordinate is equal to the size tg_size_x of the X dimension. The selector is used to select "increment coordinates by 1" or "reset coordinates to 0" based on the comparison result. The activation of each computation component of the ALU is determined by an incremental rule based on the corresponding thread arrangement mode, and the coordinate transfer between ALUs also follows an incremental rule. Clearly, the linear mode transfers coordinates forward one ALU at a time, while the Zig-Zag mode may also involve transfers across ALUs.

[0046] Furthermore, whether each ALU uses the corresponding dimension's computational components for computation is determined by the mode configuration register and the thread block dimension register. For simplified illustration, in... Figure 6 The diagram only schematically shows the adders and selectors for each dimension of the six ALUs, while the comparators are not explicitly shown.

[0047] In this embodiment of the invention, ALU reuse is performed between scenarios with the same dimension but different computational granularities. The following are some specific embodiments of ALU reuse between thread bundle computation building units for reference: Example 1: Figure 7 The diagram shown is a schematic representation of an embodiment of thread X-coordinate calculation provided by the present invention. Figure 7 (a) A thread bundle computation building block for calculating 4 thread coordinates per cycle in a one-dimensional linear pattern. Figure 7 (b) A thread bundle computation building block for calculating 6 thread coordinates per cycle in a one-dimensional linear pattern. This is because both use X-dimensional linear coordinate computation links, and Figure 7 The calculated trajectory (incrementing rule) of the four thread coordinates in (a) and Figure 7 In (b), the coordinates of the first four threads are completely identical, therefore Figure 7 (a) Can be directly reused Figure 7 (b) All computational components of the first four ALUs. In this reuse scenario, each ALU only activates the computational components in the X dimension (i.e., only the adders, comparators, and selectors in the X dimension participate in the operation). Of course, in the two-dimensional linear mode, each enabled ALU activates the computational components in the Y dimension to perform the Y-coordinate increment operation whenever the X coordinate goes out of bounds.

[0048] Figure 7The X coordinate calculation flow is shown as follows: the adder performs a plus 1 operation on the X coordinate of the previous thread to generate a candidate incremental coordinate (such as performing p0_x+1 on p0_x to obtain the candidate value of p1_x); the comparator performs an equality comparison between the current candidate incremental coordinate and the size tg_size_x of the X dimension of the thread block, and outputs a logic signal of "whether to overflow"; the selector performs a two-way output according to the logic signal of the comparator, and if the current candidate incremental coordinate is equal to tg_size_x (overflow), 0 is selected as the output (the X coordinate is reset to the initial value), otherwise the candidate incremental coordinate is selected as the output (no overflow, the X coordinate is normally incremented). During the coordinate calculation process, calculate_num is the total number of cycles for the thread bundle calculation construction unit to calculate, and the calculation is stopped when the cycle count reaches calculate_num. To ensure the continuity of multi-cycle calculation, at the end of each cycle, the clock signal will trigger the D-type flip-flop to store the X coordinate (denoted as pixel_offset_x_old) output by the ALU at the last cycle of the current cycle, which will be used as the initial X coordinate of the next cycle.

[0049] Example 2: For Zig-Zag patterns such as Z-type and N-type, the multiplicity of the ALU is limited by the difference in the calculation trajectory. The part with the same calculation trajectory can reuse all the calculation components of the ALU, while the part with the difference in the calculation trajectory usually only reuses part of the calculation components of the ALU (such as the adder). If the calculation trajectory of the thread bundle calculation construction unit 2 is the same as that of the thread bundle calculation construction unit 1, the thread bundle calculation construction unit 2 can reuse all the calculation components of the thread bundle calculation construction unit 1. Figure 6 is the thread bundle calculation construction unit 1 of the anti-Zig-Zag pattern, the size of the thread arrangement granularity is 3x2, and it has 6 ALUs (ALU0 to ALU5 in turn). When the mode configuration register selects to enable the thread bundle calculation construction unit 2 of the anti-Zig-Zag pattern with a thread arrangement granularity size of 2x2, because the calculation trajectory of "the 1st thread coordinate -> the 2nd thread coordinate" is the same in the anti-Zig-Zag patterns of 2x2 and 3x2, while the calculation trajectory of "the last coordinate of the previous cycle -> the 1st thread coordinate" and the subsequent "the 2nd thread coordinate -> the 3rd thread coordinate -> the 4th thread coordinate" is different, the thread bundle calculation construction unit 2 can reuse all the calculation components of ALU1 in the thread bundle calculation construction unit 1, and the required dimension corresponding part of the calculation components (such as the adder) in ALU0, ALU2 and ALU3.

[0050] Of course, if Figure 6is a linear mode thread bundle computation building unit 3, and the thread arrangement granularity size thereof is 6x1.When the mode configuration register selects to enable the linear mode thread bundle computation building unit 4 with a thread arrangement granularity size of 4x1, because the calculation trajectory of the thread coordinates of the linear mode thread bundle computation building unit 4 is consistent with the calculation trajectory of the first 4 thread coordinates in the thread bundle computation building unit 3, the linear mode thread bundle computation building unit 4 can reuse all the calculation components of ALU0-ALU3 in the thread bundle computation building unit 3.

[0051] In an optional embodiment, the enabling the specified thread bundle computation building unit to perform thread coordinate calculation in a clock cycle loop comprises: By the specified thread bundle computation building unit, based on the thread coordinate initial value of the current clock cycle, all thread coordinates in the current clock cycle are calculated according to the increment rule defined by the corresponding thread arrangement mode; In the calculation process of each thread coordinate, the dimension coordinate values of the currently calculated thread coordinate are compared with the dimension size determined by the thread block dimension information to obtain a corresponding comparison result; If the comparison result is that no dimension coordinate value is out of bounds, the currently calculated thread coordinate is maintained; If the comparison result is that there is a dimension coordinate value out of bounds, the dimension coordinate value out of bounds is reset to the initial value and a carry is added to the coordinate value of a higher dimension; The last thread coordinate calculated in the current clock cycle is taken as the thread coordinate initial value of the next clock cycle, and the loop count is updated until the loop count reaches the total loop count.

[0052] Further, the resetting of the dimension coordinate value out of bounds to the initial value and the addition of a carry to the coordinate value of a higher dimension comprise: The dimension coordinate value out of bounds is reset to 0, and the coordinate value of a higher dimension is added by 1; If the coordinate value of the higher dimension is out of bounds after being added by 1, the coordinate value of the higher dimension is reset to 0, and the coordinate value of a higher dimension is continuously added by 1.

[0053] It should be noted that in the thread coordinate calculation, the embodiment of the application follows the loop logic of "thread coordinate initial value setting-batch calculation in a clock cycle-boundary judgment and coordinate adjustment-thread coordinate initial value updating", which ensures the continuity and accuracy of thread coordinate calculation in different dimensions and different arrangement modes.

[0054] Taking a three-dimensional thread block as an example, the thread coordinate initial value of the specified thread bundle computation building unit in the first loop is (0, 0, 0), and the last thread coordinate calculated in the previous clock cycle is directly used as the thread coordinate initial value in the subsequent loop to realize continuous iterative calculation of the thread coordinates.

[0055] The embodiment of the present application supports three types of thread arrangement modes, and the coordinate increment rules of each mode are as follows: The increment rule of the linear mode: taking FIG. 3(a) as an example, threads are generated in linear increment in X→Y→Z dimensions (i.e., the X axis is preferentially incremented, the Y axis is secondarily incremented, and the Z axis is lastly incremented).

[0056] The increment rule of the N-type Zig-Zag mode: taking FIG. 3(b) as an example, threads are incremented in a regular "N" shaped path, i.e., a "zigzag" arrangement in a local region is formed by extending along the Y axis direction first and then extending along the X axis direction.

[0057] The increment rule of the Z-type Zig-Zag mode: taking FIG. 3(c) as an example, threads are incremented in an inverse "Z" shaped path, i.e., another type of "zigzag" arrangement in a local region is formed by extending along the X axis direction first and then extending along the Y axis direction.

[0058] The designated thread bundle computation construction unit synchronously completes parallel computation of multiple thread coordinates in one clock cycle according to the number of ALUs of the unit.

[0059] In the computation process of each thread coordinate, the dimension coordinate values of the thread coordinate currently computed are compared with the corresponding dimension boundary values one by one to obtain the comparison results (out of bounds or not out of bounds) of each dimension. If the comparison results of all dimensions are not out of bounds, the thread coordinate currently computed is maintained and can be directly output as a valid computation result to the thread coordinate buffer area. If the coordinate value of a dimension is out of bounds (e.g., the X axis coordinate value is equal to thread_block_x_size), the "out-of-bound dimension coordinate reset + high dimension coordinate carry" operation is performed, which specifically includes the following steps: reset / reinitialize the out-of-bound dimension coordinate value to an initial value (usually 0) and add 1 to the coordinate value of the higher level dimension (e.g., when the X axis is out of bounds, the X axis is reset to 0 and the Y axis is added by 1); if the coordinate value of the higher level dimension added by 1 is also out of bounds (e.g., the Y axis added by 1 is equal to thread_block_y_size), continue to reset the coordinate value of the higher level dimension to 0 and add 1 to the coordinate value of the higher level dimension (e.g., the Y axis is reset to 0 and the Z axis is added by 1), and so on, until the coordinate values of all dimensions are within the valid range.

[0060] ​​​​​​​​Taking thread_block_x_size=8 as an example, when the coordinate of thread7 (index from 0, corresponding to the 8th position of the X axis) is calculated, the X axis coordinate value of thread7 is 7, which is less than thread_block_x_size, at this time the comparison result is that the X direction is not out of bounds; but when the coordinate of thread8 is calculated, the X axis coordinate value of thread8 is 8, which is equal to thread_block_x_size, at this time the comparison result is that the X axis is out of bounds, and the X axis coordinate needs to be reset to 0, and the Y axis coordinate is added by 1.

[0061] In summary, the thread bundle construction device provided by the embodiment of the application has the following beneficial effects: (1) High flexibility, can adapt to thread blocks of different sizes and different dimensions; for three-dimensional thread blocks, continuous calculation of thread coordinates can be performed across the Z axis.

[0062] (2) Simple logic, low implementation cost.

[0063] (3) Support for multiple thread arrangement modes: not only linearly constructed thread bundles, but also able to adapt to special thread arrangements such as N-type Zig-Zag and Z-type Zig-Zag.

[0064] (4) High calculation efficiency, and by flexibly configuring the number of ALUs (such as 1, 2, 4, 8, etc.), different numbers of thread coordinates can be calculated per clock cycle, thereby dynamically expanding according to actual hardware resources and performance requirements.

[0065] Reference Figure 8 is a flowchart of an embodiment of the thread bundle construction method provided by the application.

[0066] The second aspect embodiment of the application provides a thread bundle construction method, which is applicable to the thread bundle construction device of any one of the above-mentioned first aspect embodiments, and the method comprises steps S1 to S5, which are as follows: Step S1: storing the thread block dimension information carried in the thread bundle construction request through a thread block dimension register; Step S2: storing the mode configuration information carried in the thread bundle construction request through a mode configuration register; Step S3: responding to the thread bundle construction request through a loop controller, reading the thread block dimension information and the mode configuration information after entering the thread bundle construction state, calculating the total number of loops, and controlling the thread bundle calculation construction array to execute thread coordinate calculation; Step S4: under the control of the loop controller, the specified thread bundle calculation and construction unit is enabled to perform thread coordinate calculation in a clock cycle loop according to the mode configuration information, and the calculated thread coordinates are output; wherein, in the thread coordinate calculation process, the specified thread bundle calculation and construction unit performs boundary judgment and thread coordinate adjustment according to the thread block dimension information; Step S5: when the number of loops of the specified thread bundle calculation and construction unit reaches the total number of loops, the loop controller controls the specified thread bundle calculation and construction unit to stop thread coordinate calculation.

[0067] It should be noted that the thread bundle construction method provided by the embodiment of the present application can realize all the processing procedures in the thread bundle construction device described in any embodiment of the first aspect. The specific implementation schemes and technical effects achieved by the thread bundle construction method correspond to the same as those of the thread bundle construction device described in any embodiment of the first aspect, and will not be repeated here.

[0068] The third aspect embodiment of the present application provides a processor comprising the thread bundle construction device described in any embodiment of the first aspect.

[0069] The processor can be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit). The thread bundle construction device is a special hardware module inside the processor, which is used to generate the coordinates of each thread in the thread bundle for the calculation unit of the processor to schedule.

[0070] The above is only the preferred embodiment of the present application, and it should be noted that for those skilled in the art, without departing from the technical principles of the present application, a number of improvements and modifications can be made, and these improvements and modifications should be considered as the protection scope of the present application.

Claims

1. A thread bundle construction device, characterized in that, include: The thread block dimension register is used to store the thread block dimension information carried in the thread bundle construction request; A mode configuration register is used to store the mode configuration information carried in the thread bundle construction request; A loop controller is used to respond to the thread bundle construction request, and after entering the thread bundle construction state, read the thread block dimension information and the mode configuration information, calculate the total number of loops, and control the thread bundle calculation and construction array to perform thread coordinate calculation. A thread beam computation building array is used, under the control of the loop controller, to enable a specified thread beam computation building unit according to the mode configuration information, so as to perform thread coordinate calculation cyclically according to the clock cycle and output the calculated thread coordinates; wherein, the specified thread beam computation building unit performs boundary judgment and thread coordinate adjustment according to the thread block dimension information during the thread coordinate calculation process; The loop controller is further configured to control the designated thread bundle calculation building unit to stop calculating thread coordinates when the number of loops of the designated thread bundle calculation building unit reaches the total number of loops.

2. The thread bundle construction apparatus as described in claim 1, characterized in that, The thread bundle construction request is initiated by an external task allocation unit.

3. The thread bundle construction apparatus as described in claim 1, characterized in that, The mode configuration information includes: thread arrangement mode and the number of arithmetic logic units called per clock cycle; wherein, the thread arrangement mode includes: linear mode, N-shaped mode or Z-shaped mode; the number of arithmetic logic units is used to characterize the computational granularity.

4. The thread bundle construction apparatus as described in claim 1, characterized in that, The thread bundle computation array includes: M1 linear mode thread bundle computation units, M2 N-shaped mode thread bundle computation units, M3 Z-shaped mode thread bundle computation units, and a multiplexer; wherein, the multiplexer is used to enable a specified thread bundle computation unit and output the calculated thread coordinates according to the mode configuration information; M1≥1; M2≥1; M3≥1.

5. The thread bundle construction apparatus as described in claim 3, characterized in that, The step of enabling a specified thread beam computation building unit to perform thread coordinate calculations cyclically according to a clock cycle includes: By specifying the thread bundle calculation building unit, based on the initial value of the thread coordinates in the current clock cycle, and according to the incrementing rule defined by the corresponding thread arrangement pattern, the coordinates of all threads in the current clock cycle are calculated. During the calculation of each thread coordinate, the coordinate values ​​of each dimension of the currently calculated thread coordinate are compared with the dimension size determined by the thread block dimension information to obtain the corresponding comparison result. If the comparison result is that the coordinates of the dimensionless coordinates are out of bounds, then the currently calculated thread coordinates are maintained. If the comparison result indicates that a dimension coordinate value is out of bounds, then the out-of-bounds dimension coordinate value is reset to its initial value and carried over to the coordinate value of the higher dimension. The last thread coordinate calculated in the current clock cycle is used as the initial thread coordinate value for the next clock cycle, until the total number of loops is reached.

6. The thread bundle construction apparatus as described in claim 5, characterized in that, The step of resetting the out-of-bounds dimensional coordinate values ​​to their initial values ​​and carrying over to higher-dimensional coordinate values ​​includes: Reset the out-of-bounds dimension coordinates to 0, and increment the coordinates of the next higher dimension by 1; If the coordinate value of the next higher dimension exceeds the limit after being incremented by 1, the coordinate value of the next higher dimension is reset to 0, and the process continues to increment the coordinate value of the next higher dimension by 1.

7. The thread bundle construction apparatus as described in claim 4, characterized in that, The reuse of arithmetic logic units is supported among the various thread bundle computation building units.

8. The thread bundle construction apparatus as described in claim 3, characterized in that, When the thread arrangement pattern is an N-shaped pattern or a Z-shaped pattern, the dimensions corresponding to the X and Y dimensions in the thread block dimension information are integer multiples of the dimensions of the corresponding thread arrangement granularity in the X and Y dimensions, respectively.

9. The thread bundle construction apparatus as described in claim 1, characterized in that, The calculated thread coordinates are output to an external thread beam coordinate buffer.

10. A method for constructing a thread bundle, characterized in that, The method, applicable to any one of claims 1 to 9, comprises: The thread block dimension information carried in the thread bundle construction request is stored in the thread block dimension register; The mode configuration information carried in the thread bundle construction request is stored in the mode configuration register; The loop controller responds to the thread bundle construction request, enters the thread bundle construction state, reads the thread block dimension information and the mode configuration information, calculates the total number of loops, and controls the thread bundle calculation and construction array to perform thread coordinate calculation. Under the control of the loop controller, the array constructed by thread beam computation enables a designated thread beam computation construction unit according to the mode configuration information to perform thread coordinate calculation cyclically according to the clock cycle and output the calculated thread coordinates; wherein, the designated thread beam computation construction unit performs boundary judgment and thread coordinate adjustment according to the thread block dimension information during the thread coordinate calculation process; When the loop controller controls the designated thread bundle calculation building unit to stop calculating thread coordinates when the number of loops in the designated thread bundle calculation building unit reaches the total number of loops, the loop controller controls the designated thread bundle calculation building unit to stop calculating thread coordinates.

11. A processor, characterized in that, Includes the thread bundle construction apparatus as described in any one of claims 1 to 9.

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