Data communication method of hybrid deployment operating system and industrial control equipment

Abstract

The invention relates to the technical field of industrial control, and discloses a data communication method of a hybrid deployment operating system and industrial control equipment, the method is applied to the industrial control equipment, and the method comprises the following steps: determining an inter-process shared memory of a non-real-time operating system and a target shared memory corresponding to a target real-time operating system; the inter-process shared memory is used for storing lock signals; the lock signal is used for indicating the accessible state of the target shared memory; the target shared memory is a memory shared by the first processor core and the second processor core; the first processor core is used for running a non-real-time operating system; the second processor core is used for running a target real-time operating system; writing the data and the length of the data into the target shared memory based on the lock signal and the memory address of the target shared memory; sending a first interrupt signal to a second processor; the first interrupt signal is used for indicating the real-time operating system to read the data from the target shared memory based on the length of the data. According to the invention, data conflicts can be avoided while the efficiency of inter-core communication is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of industrial control, and particularly relates to a data communication method of a hybrid deployment operating system and an industrial control device. BACKGROUND

[0002] With the rapid development of information technology, a multi-core processor system has become a core component of a computing architecture and is widely applied to fields such as industrial control, automatic driving, and edge computing, which have relatively high real-time requirements. In the multi-core processor system, efficient cooperation between different processor cores (or processor cores) is a key to guarantee the overall performance of the system. A core-to-core communication mechanism is usually used to realize data communication between multiple processor cores. Existing core-to-core communication mechanisms include message passing, shared memory, and remote procedure call.

[0003] However, as application scenarios become more complex, the amount of data required to be transmitted between processor cores also increases, and therefore, when data communication is performed based on the existing core-to-core communication mechanism, multiple data copying and frequent interrupt notifications are usually required, which leads to low efficiency of data communication. SUMMARY

[0004] Embodiments of the present application provide a data communication method of a hybrid deployment operating system and an industrial control device, which can improve the efficiency of core-to-core communication.

[0005] In a first aspect, embodiments of the present application provide a data communication method of a hybrid deployment operating system, applied to an industrial control device, which includes: determining a process inter-process shared memory shared by a process of a non-real-time operating system and a target shared memory corresponding to a target real-time operating system; wherein the process inter-process shared memory is used to store a lock signal; the lock signal is used to indicate an accessible state of the target shared memory; the target shared memory is a memory shared by a first processor core and a second processor core; the first processor core is used to run the non-real-time operating system; the second processor core is used to run the target real-time operating system; based on the lock signal and a memory address of the target shared memory, writing data and a length of the data into the target shared memory; sending a first interrupt signal to the second processor core; wherein the first interrupt signal is used to instruct the target real-time operating system to read the data from the target shared memory based on the length of the data and the memory address of the target shared memory.

[0006] Based on the implementation, the one-time transmission of the to-be-processed data from the non-real-time system to the real-time system can be realized based on the inter-core shared memory and the inter-process shared memory, so as to reduce the communication delay and the read-write resource overhead, and improve the communication efficiency between the non-real-time system and the real-time system. Moreover, in the process of data communication between the user process and the target real-time system, the lock signal is set for the target real-time system, so as to avoid the data writing conflict caused by the simultaneous data communication of multiple user processes with the same target real-time system, and ensure the consistency of data writing.

[0007] In a possible implementation, before writing the data and the length of the data into the target shared memory based on the lock signal and the memory address of the target shared memory, the method further includes: obtaining the address of the inter-process shared memory; obtaining the lock signal from the inter-process shared memory based on the address of the inter-process shared memory; and determining whether the target shared memory is in an accessible state based on the lock signal.

[0008] Based on the implementation, the lock signal is set for the inter-process shared memory corresponding to the target real-time system, so as to ensure the synchronization and safety of the inter-core communication process based on the lock signal, avoid data conflict, and improve the reliability of communication.

[0009] In another possible implementation, the writing of the data and the length of the data into the target shared memory based on the lock signal and the memory address of the target shared memory includes: in the case that the target shared memory is in an accessible state, writing the data and the length of the data into the target shared memory based on the address of the target shared memory.

[0010] Based on the implementation, the target shared memory is accessed in the case that it is determined to be in an accessible state based on the lock signal, so as to avoid the access conflict of the target shared memory caused by the simultaneous data communication of multiple user processes with the same target real-time system, and ensure the consistency of data writing.

[0011] In yet another possible implementation, the determination of whether the target shared memory is in an accessible state based on the lock signal includes: determining whether the lock signal is a first signal; the first signal is used to indicate that the target shared memory is in an accessible state; and in the case that the lock signal is the first signal, it is determined that the target shared memory is in an accessible state.

[0012] Based on the implementation, the value of the lock signal is determined, so as to write data in the target shared memory when the lock signal is available, and avoid the long-time blocking of the writing task; and when the lock signal is not available, the waiting state is entered until the lock signal is released, so as to ensure the fairness and stability of the inter-core communication process.

[0013] In yet another implementation manner, the method further comprises: updating the lock signal to a second signal by using an atomic operation; wherein the second signal is used to indicate that the target shared memory is in an inaccessible state.

[0014] Based on the implementation manner, in the case that multiple user processes access the same target real-time system at the same time, the atomic operation is used to respond to the call of one of the user processes and change the signal value of the lock signal corresponding to the target real-time system, so that data conflict can be avoided.

[0015] In yet another possible implementation manner, the target shared memory comprises a first target shared memory and a second target shared memory; and the writing, in the case that the target shared memory is in an accessible state, of the data and the length of the data into the target shared memory based on the address of the target shared memory comprises: writing, in the case that the target shared memory is in an accessible state, the data into the first target shared memory based on the address of the first target shared memory; and writing the length information of the data into the second target shared memory based on the address of the second target shared memory.

[0016] Based on the implementation manner, by dividing the target shared memory into the first target shared memory and the second target shared memory, the data and the length of the data can be stored in different regions, so as to facilitate the reading and writing of the data and the length of the data respectively.

[0017] In yet another possible implementation manner, the method further comprises: in response to a second interrupt signal sent by the second processor core, obtaining the length of a return message from the target shared memory based on the lock signal and the memory address of the target shared memory; wherein the second interrupt signal is used to indicate that the non-real-time operating system reads the return message from the target shared memory; the return message is related to or unrelated to the data; and the return message is read from the target shared memory by the non-real-time operating system based on the memory address of the target shared memory and the length of the return message.

[0018] Based on the implementation manner, the to-be-processed data can be transmitted from the real-time system to the non-real-time system at one time based on the inter-core shared memory and the inter-process shared memory, so as to avoid multiple data reading and writing and multiple sending of interrupt signals, thereby significantly reducing communication delay and reading and writing resource overhead, and realizing efficient communication between the non-real-time system and the real-time system. Moreover, in the process of data communication between the user process and the target real-time system, the lock signal set for the target real-time system can avoid the problem of data writing conflict caused by the simultaneous attempt of multiple user processes to communicate data with the same target real-time system, so as to ensure the atomicity and consistency of data writing.

[0019] In a further possible implementation, the target shared memory comprises a third target shared memory and a fourth target shared memory; the second interrupt signal is used to instruct the non-real-time operating system to read the return message from the third target shared memory; and the obtaining, in response to the second interrupt signal sent by the second processor core, of the length of the return message from the target shared memory based on the lock signal and the memory address of the target shared memory comprises: obtaining, in response to the second interrupt signal sent by the second processor core, the length of the return message from the third target shared memory based on the lock signal and the memory address of the third target shared memory; and the reading, by the non-real-time operating system, of the return message from the target shared memory based on the memory address of the target shared memory and the length of the return message comprises: reading, by the non-real-time operating system, the return message from the fourth target shared memory based on the memory address of the fourth target shared memory and the length of the return message.

[0020] According to the present implementation, by dividing the target shared memory into the third target shared memory and the fourth target shared memory, the return message and the length of the return message can be stored in different regions, so as to facilitate reading and writing of the return message and the length of the return message.

[0021] In a further possible implementation, the target shared memory corresponding to the target real-time operating system is determined by: obtaining an identifier of the target real-time operating system; and determining the target shared memory based on the identifier of the target real-time operating system and a preset mapping relationship, wherein the preset mapping relationship is used to indicate a mapping relationship between a real-time operating system and a corresponding inter-core shared memory, the real-time operating system comprises the target real-time operating system, and the inter-core shared memory comprises the target shared memory.

[0022] According to the present implementation, when the number of deployed real-time systems is multiple, independent target shared memories can be allocated to each real-time system and a mapping relationship can be established, so that a user process can access different real-time systems and resource isolation can be achieved when multiple real-time systems perform data writing operations.

[0023] In a second aspect, the embodiments of the present application further provide a data communication apparatus of a hybrid deployment operating system, configured in an industrial control device, comprising: a first determining module configured to determine a process inter-shared memory shared by processes of a non-real-time operating system and a target shared memory corresponding to a target real-time operating system; wherein the process inter-shared memory is used to store a lock signal; the lock signal is used to indicate an accessible state of the target shared memory; the target shared memory is a memory shared by a first processor core and a second processor core; the first processor core is used to run the non-real-time operating system; the second processor core is used to run the target real-time operating system; a writing module configured to write data and a length of the data into the target shared memory based on the lock signal and a memory address of the target shared memory; a sending module configured to send a first interrupt signal to the second processor core; wherein the first interrupt signal is used to instruct the target real-time operating system to read the data from the target shared memory based on the length of the data and the memory address of the target shared memory.

[0024] In a possible implementation, the apparatus further comprises a first obtaining module, a second obtaining module and a second determining module; the first obtaining module is configured to obtain an address of the process inter-shared memory; the second obtaining module is configured to obtain the lock signal from the process inter-shared memory based on the address of the process inter-shared memory; and the second determining module is configured to determine whether the target shared memory is in the accessible state based on the lock signal.

[0025] In another possible implementation, the writing module is specifically configured to write the data and the length of the data into the target shared memory based on the address of the target shared memory in the case that the target shared memory is in the accessible state.

[0026] In yet another possible implementation, the second determining module is specifically configured to determine whether the lock signal is a first signal; wherein the first signal is used to indicate that the target shared memory is in the accessible state; and in the case that the lock signal is the first signal, it is determined that the target shared memory is in the accessible state.

[0027] In yet another possible implementation, the apparatus further comprises a resource updating module; the resource updating module is configured to update the lock signal to a second signal by using an atomic operation; wherein the second signal is used to indicate that the target shared memory is in an inaccessible state.

[0028] In a further possible implementation, the target shared memory includes a first target shared memory and a second target shared memory; and the writing module is specifically configured to: in a case where the target shared memory is in an accessible state, write the data into the first target shared memory based on an address of the first target shared memory; and write length information of the data into the second target shared memory based on an address of the second target shared memory.

[0029] In a further possible implementation, the apparatus further includes a third obtaining module and a reading module; the third obtaining module is configured to: in response to a second interrupt signal sent by the second processor core, obtain, based on the lock signal and a memory address of the target shared memory, a length of a return message from the target shared memory; the second interrupt signal is used to instruct the non-real-time operating system to read the return message from the target shared memory; the return message is related to or unrelated to the data; and the reading module is configured to: based on the memory address of the target shared memory and the length of the return message, read, by the non-real-time operating system, the return message from the target shared memory.

[0030] In a further possible implementation, the target shared memory includes a third target shared memory and a fourth target shared memory; the second interrupt signal is used to instruct the non-real-time operating system to read a return message from the third target shared memory; the third obtaining module is configured to: in response to the second interrupt signal sent by the second processor core, obtain, based on the lock signal and a memory address of the third target shared memory, a length of the return message from the third target shared memory; and the reading module is configured to: based on a memory address of the fourth target shared memory and the length of the return message, read, by the non-real-time operating system, the return message from the fourth target shared memory.

[0031] In a further possible implementation, the first determining module is specifically configured to: obtain an identifier of the target real-time operating system; and determine the target shared memory based on the identifier of the target real-time operating system and a target mapping relationship; the target mapping relationship is used to indicate a mapping relationship between a real-time operating system and a corresponding inter-core shared memory, the real-time operating system includes the target real-time operating system, and the inter-core shared memory includes the target shared memory.

[0032] In a third aspect, an embodiment of the present application further provides a workpiece processing device, including: a processor and a memory; the processor and the memory are coupled; the memory is used to store program instructions; and the processor is used to execute the program instructions to perform the method in any one of the above first aspect.

[0033] In a fourth aspect, an embodiment of the present application provides a chip, which is configured to execute the method according to any one of the first aspect.

[0034] In a fifth aspect, an embodiment of the present application provides a computer readable storage medium, which stores computer execution instructions, and the computer execution instructions are executed by a computer to implement the method according to any one of the first aspect.

[0035] In a sixth aspect, an embodiment of the present application provides a program product, which comprises a computer program, and the computer program is executed by a processor to implement the method according to any one of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A scenario diagram of a data communication method for hybrid deployment of an operating system according to an embodiment of the present application;

[0037] Figure 2 A flowchart of a data communication method for hybrid deployment of an operating system according to an embodiment of the present application;

[0038] Figure 3 A schematic diagram of inter-core shared memory according to an embodiment of the present application;

[0039] Figure 4 A schematic diagram of the relationship between a real-time system and inter-process shared memory according to an embodiment of the present application;

[0040] Figure 5 A schematic diagram of inter-core communication according to an embodiment of the present application;

[0041] Figure 6 A flowchart of another data communication method for hybrid deployment of an operating system according to an embodiment of the present application;

[0042] Figure 7 A schematic diagram of another inter-core communication according to an embodiment of the present application;

[0043] Figure 8 A flowchart of still another data communication method for hybrid deployment of an operating system according to an embodiment of the present application;

[0044] Figure 9 A schematic diagram of a data communication device for hybrid deployment of an operating system according to an embodiment of the present application;

[0045] Figure 10 A schematic diagram of an industrial control device according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In order to clearly describe the technical solutions in the embodiments of the present application, the first, second, and the like descriptions in the embodiments of the present application are only used for indicating and distinguishing the description objects, and do not have the order, and do not represent the special limitation of the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0047] The data communication method for mixed deployment of operating systems provided in the embodiments of the present application can be applied to a computing device, which can be an industrial control device. The industrial control device is deployed with a real-time operating system (hereinafter referred to as a real-time system) and a non-real-time operating system (hereinafter referred to as a non-real-time system). When the data communication between the real-time system and the non-real-time system is implemented based on the data communication method for mixed deployment of operating systems provided in the embodiments of the present application, efficient data communication can be achieved based on inter-core shared memory and inter-process shared memory.

[0048] Figure 1 A scene diagram of the data communication method for mixed deployment of operating systems provided in the embodiments of the present application is shown in FIG. 1. Figure 1 As shown in FIG. 1, the industrial control device 100 is configured with one or more multi-core processors 10, and the multi-core processor 10 includes a plurality of processor cores (or processor cores). The processor core can be a central processing unit (CPU) core of ARM architecture or X86 architecture.

[0049] In some embodiments, the non-real-time system 11 and the real-time system (RTOS) 12 can be deployed on different processor cores in the multi-core processor 10, or the non-real-time system 11 and the real-time system 12 can be deployed on different processor cores in different multi-core processors 10. For example, the non-real-time system 11 can be deployed on a first processor core, and the real-time system can be deployed on a second processor core. One or more real-time systems can be deployed on the second processor core. The non-real-time operating system 11 (such as Windows, Linux) usually adopts a time-sharing scheduling algorithm, all tasks have the same priority, and therefore the non-real-time operating system 11 is suitable for running ordinary application programs, and cannot ensure high real-time performance of task execution.

[0050] The real-time system 12 is an operating system capable of responding to external events or data within a specified time and scheduling resources to complete real-time tasks. The core function of the real-time system 12 is to schedule and manage real-time tasks to ensure that all tasks run in coordination. The real-time system 12 adopts a multi-task running mechanism, and the kernel of the real-time system 12 schedules multiple external event threads to run simultaneously on the processor to achieve concurrent execution of tasks. In addition, the real-time system 12 also adopts a pre-emptive task scheduling mechanism, so that when the real-time system 12 is executing a task, if a higher priority task enters the executable state, the current processor resource is immediately pre-empted and the low-priority task is exited to prioritize the high-priority task. The pre-emptive task scheduling mechanism can ensure that high-priority tasks are processed in a timely manner and meet real-time requirements.

[0051] The non-real-time system 11 is used to display a user graphical interface and perform image rendering, file downloading, database queries, log recording and other tasks that do not have high real-time requirements. The real-time system 12 is used to execute high real-time tasks, such as motion control of industrial equipment, industrial equipment emergency stop triggering, power system overload protection and other tasks that need to strictly ensure task execution time and execution order. The non-real-time system 11 has a richer software and hardware ecosystem than the real-time system 12 and can implement more diverse functions, and users can integrate more third-party software and hardware in the non-real-time system 11.

[0052] The controlled device 110 can include industrial equipment (such as a numerical control machine tool, a robot, an industrial camera), medical equipment, a laser radar and a brake device in an autonomous driving system, an aircraft and other devices that have high real-time requirements for data transmission. The real-time system 12 and the controlled device 110 can communicate through a real-time Ethernet communication protocol, such as the EtherCAT (ethernet for control automation technology) protocol, the time-sensitive networking (TSN) protocol, the process field network protocol, etc.

[0053] In some embodiments, the industrial control device 100 can include one or more memories, which can be dynamic random-access memory (DRAM), static random-access memory (SRAM), synchronous dynamic random-access memory (SDRAM), etc., which are not limited in the present embodiment. The non-real-time system 11 can divide the inter-core shared memory and the inter-process shared memory in the total memory area corresponding to one or more memory modules. The inter-core shared memory and the inter-process shared memory are independent memory areas, and the inter-core shared memory and the inter-process shared memory can be located on the same memory or on different memories. The number of inter-core shared memories can be one; the number of inter-process shared memories is equal to the number of deployments of the real-time system, and there is a one-to-one correspondence between the inter-process shared memory and the real-time system. Moreover, the inter-core shared memory can be divided into one or more sub-inter-core shared memories based on the number of real-time systems, and the number of sub-inter-core shared memories is equal to the number of deployments of the real-time system, and there is a one-to-one correspondence between the sub-inter-core shared memory and the real-time system.

[0054] In some embodiments, the non-real-time system 11 and the real-time system 12 can realize inter-core communication and data transmission based on the inter-core shared memory and the inter-process shared memory. For example, the non-real-time system 11 runs a user process, which is a process used by an application program running on the non-real-time system 11. The user process in the non-real-time system 11 and the real-time system 12 can communicate through inter-core communication to transmit data, so that the user process can transmit data (hereinafter referred to as to-be-processed data) required by the application program in the non-real-time system 11 to the real-time system 12 through inter-core communication. The to-be-processed data can include control instructions for the controlled device 110, working state information of the controlled device 110, etc. The non-real-time system 11 also runs a resource management process, which is used to assist communication between the user process and the real-time system, and manage the lock signals and state signals corresponding to the inter-process shared memory, so as to realize data transmission between the user process in the non-real-time system 11 and the real-time system 12, and avoid resource conflict problems when multiple user processes access the same process shared memory.

[0055] In some embodiments, in the case that the data to be processed received by the real-time system 12 is the working state information of the controlled device 110, the real-time system 12 can store the data in a memory buffer used by the real-time system 12 alone. In the case that the data to be processed received by the real-time system is a control instruction, the real-time system 12 can send the control instruction to the controlled device 110 to implement control over the controlled device 110; and the real-time system 12 can collect the execution result of the controlled device 110 to the control instruction and transmit the execution result to the non-real-time system 11. Further, the resource management process in the non-real-time system 11 can assist the user process to obtain the execution result based on the inter-process shared memory and the inter-core shared memory.

[0056] It should be noted that the multi-core processor 10 can be a multi-core system on chip (SoC) including a plurality of processor cores and memories. For example, Figure 1 The first processor core, the second processor core, the inter-process shared memory and the inter-core shared memory are integrated in the same multi-core system on chip.

[0057] Figure 2 A flowchart of a data communication method of a hybrid deployment operating system provided by the embodiment of the present application is shown. It should be noted that the data communication method of a hybrid deployment operating system provided by the embodiment of the present application is executed by an industrial control device, specifically, a processor or a processor core in the industrial control device. The method steps executed by the processes or software described in the embodiment of the present application are actually the method steps executed by the processor or the processor core calling the processes or software, and the actual execution subject is the processor or the processor core.

[0058] As shown in Figure 2 The method includes steps 210 to 230.

[0059] In step 210, the inter-process shared memory shared by the processes of the non-real-time operating system and the target shared memory corresponding to the target real-time operating system are determined.

[0060] In some embodiments, the deployment personnel can define the size and the physical address (which is the first address of the inter-core shared memory) of the inter-core shared memory in the configuration file in advance through the kernel start parameters (such as the cmd line parameter in the Linux operating system). For example, the size of the inter-core shared memory is defined as 8 GB and the physical address is 0x1800000. The size of the inter-core shared memory can be determined according to the maximum data transmission amount in the actual use scenario to reserve sufficient memory space for the inter-core communication data transmission process, thereby reducing the number of data copying and the number of sending of interrupt signals in the inter-core communication process.

[0061] In the deployment of the non-real-time system and the real-time system, the kernel of the non-real-time system loads the kernel startup parameters in the configuration file through a bootloader, and performs a memory mapping operation based on the size and the physical address of the inter-core shared memory defined in the kernel startup parameters, so as to reserve a memory region in a total memory region on the multi-core processor as the inter-core shared memory. After the deployment of the non-real-time system and the real-time system on the multi-core processor is completed, the non-real-time system and the real-time system can perform read and write operations on data in the inter-core shared memory. In addition, part of the remaining memory region in the total memory region can be used as a memory region used by the non-real-time system and the real-time system respectively and individually.

[0062] A resource management process can be run in the non-real-time system, and the resource management process allocates inter-process shared memories to the real-time systems respectively, and determines the size and the physical address (the first address) of each inter-process shared memory. The inter-process shared memory is a memory region in the total memory region except for the inter-core shared memory and the memory regions used by the non-real-time system and the real-time system respectively and individually, and is used for data communication between a user process and the resource management process in the non-real-time system.

[0063] In some embodiments, in addition to defining the size and the physical address (the physical address is the first address of the inter-core shared memory) of the inter-core shared memory through the kernel startup parameters in the configuration file in advance, the deployment personnel can also define the size and the physical address (the physical address is the first address of the sub-inter-core shared memory) of the sub-inter-core shared memory corresponding to each real-time system in the inter-core shared memory.

[0064] Reference is made to Figure 3 FIG. 1 shows a schematic diagram of an inter-core shared memory, and Figure 3 In the deployment of the non-real-time system and the real-time system, the kernel of the non-real-time system loads the kernel startup parameters in the configuration file through a bootloader, and performs a memory mapping operation based on the size and the physical address of each sub-inter-core shared memory defined in the kernel startup parameters, so as to divide the inter-core shared memory into the sub-inter-core shared memories corresponding to the real-time systems.

[0065] In some examples, a preset mapping relationship can be established between the real-time systems and the physical addresses of the sub-inter-core shared memories, such as a preset mapping relationship between the identifiers of the real-time systems and the physical addresses of the sub-inter-core shared memories; wherein the identifier of each real-time system corresponds to a unique physical address of the sub-inter-core shared memory. For example, as Figure 3 shown in FIG. 2, the sub-inter-core shared memory A corresponds to the real-time system A, the sub-inter-core shared memory B corresponds to the real-time system B, and the sub-inter-core shared memory C corresponds to the real-time system C.

[0066] In some embodiments, the resource management process can initialize the inter-process shared memory in the total memory region. Wherein, the number of inter-process shared memories can be one or more; the number of inter-process shared memories is determined according to the number of deployments of the real-time system, that is, the number of inter-process shared memories is equal to the number of deployments of the real-time system, that is, there is a one-to-one correspondence between the real-time system and the inter-process shared memory.

[0067] In some examples, a preset mapping relationship can also be established between the real-time system and the inter-process shared memory, such as establishing a preset mapping relationship between the identifier of the real-time system and the identifier of the inter-process shared memory; wherein the identifier of the real-time system corresponds to the identifier of the unique inter-process shared memory. Referring to Figure 4 The relationship between a real-time system and an inter-process shared memory is shown in the schematic diagram as shown in Figure 4 As shown, the inter-process shared memory A corresponds to the real-time system A, the inter-process shared memory B corresponds to the real-time system B, and the inter-process shared memory C corresponds to the real-time system C.

[0068] In some embodiments, after determining the inter-process shared memory corresponding to the real-time system, the resource management process can also initialize the lock signal and the state signal corresponding to the real-time system to determine the initial value of the lock signal and the initial value of the state signal corresponding to the real-time system, and write the lock signal and the state signal into the inter-process shared memory corresponding to the real-time system. Wherein, the initial value of the lock signal and the initial value of the state signal are both first signals (such as 0). As Figure 4 As shown, after initializing the lock signal a and the state signal a corresponding to the real-time system A, the lock signal a and the state signal a can be written into the inter-process shared memory A corresponding to the real-time system A.

[0069] Wherein, the lock signal is used to indicate whether the user process can currently use the shared memory corresponding to the real-time system for data communication. For example, it can be set that in the case that the value of the lock signal is a first signal (such as 1), it indicates that the user process can currently use the shared memory corresponding to the real-time system for data communication with the real-time system; and it can be set that in the case that the value of the lock signal is a second signal (such as 0), it indicates that the user process cannot currently use the shared memory corresponding to the real-time system for data communication with the real-time system, and enters a waiting state (or a blocking state) until the value of the lock signal is the first signal.

[0070] Status signals are semaphore resources used to indicate whether a user process is currently able to communicate with the real-time system. For example, a status signal value of 1 indicates that the user process can communicate with the real-time system; and a status signal value of 0 indicates that the user process enters a waiting state until the status signal value changes back to the first signal, at which point the user process can be woken up from the waiting state by the resource management process.

[0071] In some embodiments, after the non-real-time system has allocated inter-core shared memory and inter-process shared memory, applications running on the non-real-time system can communicate with the real-time system through user processes within the non-real-time system, based on the inter-core shared memory and inter-process shared memory. For example, when multiple real-time systems are deployed, different user processes can communicate with different real-time systems separately, or different user processes can communicate with the same real-time system.

[0072] For example, a user process can first determine the real-time system to be communicated with (hereinafter referred to as the target real-time system) among all real-time systems, determine which real-time system to send the data to, and determine the memory address (such as a virtual address) of the inter-core shared memory (hereinafter referred to as the target shared memory) corresponding to the target real-time system. In some examples, the user process can determine the identifier of the real-time system to be communicated with (the target real-time system), where different real-time systems have unique identifiers. Then, it calls the first interface provided by the non-real-time system (hereinafter referred to as the inter-core communication initialization interface), transmitting the identifier of the target real-time system to the inter-core communication initialization interface. This allows the user process to obtain a pre-defined mapping relationship between the real-time system and inter-process shared memory from the non-real-time system. Based on this pre-defined mapping relationship and the identifier of the target real-time system, the user process determines the physical address of the inter-process shared memory corresponding to the target real-time system and returns it to the user process. Additionally, the user process obtains a pre-defined mapping relationship between the real-time system and sub-core shared memory from the non-real-time system, and based on this pre-defined mapping relationship and the identifier of the target real-time system, determines the physical address of the target shared memory corresponding to the target real-time system and returns it to the user process. The inter-core communication initialization interface is used for data communication between the user process and the non-real-time system.

[0073] For example, such as Figure 3 As shown, if the target real-time system corresponding to the user process is target real-time system A, then the user process can determine that the inter-core shared memory corresponding to target real-time system A is target shared memory A; for example... Figure 4As shown, if the corresponding target real-time system of the user process is target real-time system A, the user process can determine that the inter-process shared memory corresponding to target real-time system A is inter-process shared memory A.

[0074] In some examples, after obtaining the physical address of the inter-process shared memory, the user process can perform virtual address mapping on the physical address of the inter-process shared memory corresponding to the target real-time system to obtain the virtual address of the inter-process shared memory corresponding to the target real-time system; and perform virtual address mapping on the physical address of the target shared memory to obtain the virtual address of the target shared memory.

[0075] At step 220, based on the lock signal and the memory address of the target shared memory, the data and the length of the data are written into the target shared memory.

[0076] Next, the user process can determine the to-be-processed data to be sent and the data length of the data. Referring to Figure 5 As shown in a schematic diagram of inter-core communication, as shown in Figure 5 As shown, the user process can call the inter-core communication interface to write the data and the length of the data into the target shared memory based on the memory address of the target shared memory through the inter-core communication interface.

[0077] In some embodiments, after obtaining the physical address of the inter-process shared memory corresponding to the target real-time system, the user process can call a second interface (hereinafter referred to as an inter-core communication message sending interface) provided by the non-real-time system to read the lock signal in the inter-process shared memory corresponding to the target real-time system based on the physical address of the inter-process shared memory corresponding to the target real-time system through the inter-core communication message sending interface. The lock signal in the inter-process shared memory corresponding to the target real-time system is used to indicate the accessible state of the target shared memory corresponding to the target real-time system.

[0078] The user process can determine whether the current value of the lock signal of the inter-process shared memory corresponding to the target real-time system is equal to a first signal (e.g., 1) through the inter-core communication message sending interface, that is, whether the target shared memory corresponding to the target real-time system is currently in an accessible state. The first signal is used to indicate that the target shared memory is in an accessible state. For example, the inter-core communication message sending interface can periodically poll the value of the lock signal, so that the user process can perform a data writing operation in time when the value of the lock signal changes from a second signal to the first signal. The second signal is used to indicate that the target shared memory is in an inaccessible state.

[0079] In some embodiments, if the current value of the lock signal corresponding to the target shared memory is equal to the first signal (e.g., 1), indicating that the target shared memory is currently in an accessible state, the user process can write data and the length of the data into the target shared memory based on the address of the target shared memory. Moreover, the inter-core communication message sending interface can change the value of the lock signal to the second signal (e.g., 0) using an atomic operation, to indicate that the target shared memory is currently in an inaccessible state, i.e., the current user process is currently communicating data with the target real-time system, so that other user processes in the non-real-time system cannot currently communicate data with the target real-time system (e.g., cannot access the inter-process shared memory corresponding to the target real-time system, cannot write data into the target shared memory), to avoid data conflicts. Wherein, the atomic operation refers to the case where multiple user processes access the same target real-time system at the same time, the inter-core communication message sending interface can only respond to the call of one of the user processes and change the signal value of the lock signal corresponding to the target real-time system.

[0080] For example, taking the case that the user process A acquires the lock signal a in the inter-process shared memory A corresponding to the target real-time system A as an example, if the current value of the lock signal a is equal to 1, the inter-core communication message sending interface sets the value of the lock signal a to 0, to indicate that the current user process A is accessing the target shared memory A corresponding to the target real-time system A.

[0081] In some embodiments, if the value of the lock signal corresponding to the target real-time system is equal to the second signal (e.g., 0), the user process enters a state of waiting for the lock signal until the value of the lock signal is equal to the first signal (e.g., 1). Continuing the above example, if the value of the lock signal a is 0, and if the user process B needs to access the inter-process shared memory A at this time, the user process B cannot access the inter-process shared memory A because the value of the lock signal a in the inter-process shared memory A is 0. Therefore, the user process B enters a state of waiting for the lock signal until the user process A releases the lock signal a so that the value of the lock signal a is equal to 1, and then the user process B can acquire the lock signal and access the inter-process shared memory A.

[0082] Step 230, sending a first interrupt signal to the second processor.

[0083] In some embodiments, after the user process performs the above write operation, the user process can send a processing request to the resource management process. Wherein, the processing request is used to instruct the resource management process to read the length of the data in the target shared memory corresponding to the target real-time system. As shown in Figure 5 Then, the resource management process reads the length of the data from the target shared memory based on the memory address (e.g., physical address) of the target shared memory corresponding to the target real-time system in response to the processing request sent by the user process.

[0084] In some embodiments, the state signal corresponding to the target real-time system can include two associated state signals, one of which (hereinafter referred to as the first state signal) is the state signal corresponding to the time when the resource management process receives the processing request sent by the user process, and the other (hereinafter referred to as the second state signal) is the state signal corresponding to the time when the resource management process sends the processing result to the user process. The initial values of the first state signal and the second state signal can both be set to 0.

[0085] After the user process writes data and data length into the target shared memory corresponding to the target real-time system, it can send a processing request for the first state signal in the target shared memory corresponding to the target real-time system to the resource management process, and perform a V operation (semPost operation) on the first state signal to apply for data communication between the target real-time system and the resource management process. The state signal includes the first state signal. After the user process sends a processing request to the resource management process, it enters a waiting state, i.e., waits for the resource management process to return a message.

[0086] In some embodiments, after the resource management process receives the processing request for the first state signal from the user process, if there is no other user process currently using the first state signal of the target real-time system, the resource management process can respond to the processing request and allow the user process to call the semPost interface to increase the value of the first state signal by a preset step. For example, if the preset step is 1, the value of the first state signal is increased by 1. It can be understood that if a user process has used the state signal corresponding to the target real-time system and has not released it, other user processes cannot obtain the state signal corresponding to the inter-process shared memory, so they cannot obtain the state signal corresponding to the inter-process shared memory, thereby avoiding the problem of multiple user processes competing for the same state signal.

[0087] For example, if the user process A sends a processing request for the first state signal a1 to the resource management process, the resource management process can allow the user process to increase the value of the first state signal a1 by 1, and the current value of the first state signal a1 is 1.

[0088] In some embodiments, after the user process obtains the first state signal, the resource management process can decrease the value of the first state signal by a preset step. That is, the resource management process can perform a P operation (i.e., semWait operation) on the first state signal to indicate that there is currently a user process using the first state signal of the target real-time system.

[0089] In some embodiments, after the user process obtains the first status signal, the resource management process can determine the memory address of the target shared memory corresponding to the first status signal based on the first status signal, and read the data length written by the user process from the target shared memory based on the memory address of the target shared memory.

[0090] Subsequently, the resource management process sends the memory address of the target shared memory and the read data length to the target real-time system, and sends an interrupt signal (hereinafter referred to as a first interrupt signal) to the target real-time system. Illustratively, the resource management process can send the first interrupt signal, the memory address of the target shared memory, and the data length to the target real-time system through an rpmsg_send interface of a remote processor messaging (rpmsg) sending interface; wherein the first interrupt signal is used to instruct the target real-time operating system to read data from the target shared memory based on the data length and the memory address of the target shared memory.

[0091] The target real-time system can receive and respond to the first interrupt signal through the rpmsg_send interface, read data from the target shared memory based on the received data length and the memory address of the target shared memory; that is, the target real-time system reads data of the corresponding length from the memory address of the target shared memory according to the data length information. Illustratively, the target real-time system can call a receiving service when detecting the first interrupt signal, and read data from the target shared memory through the receiving service.

[0092] In some embodiments, the non-real-time system can also divide the target shared memory corresponding to the target real-time system into a first target shared memory and a second target shared memory. Wherein the first target shared memory is used to store data, and the second target shared memory is used to store the length of the data. Thus, in the case that the target shared memory corresponding to the target real-time system is in an accessible state, the user process can write data into the first target shared memory corresponding to the target real-time system based on the memory address of the first target shared memory; and write the length information of the data into the second target shared memory based on the address of the second target shared memory.

[0093] And, the resource management process can read the length information of the data from the second target shared memory based on the memory address (such as the physical address) of the second target shared memory corresponding to the target real-time system in response to the processing request sent by the user process. Then, the resource management process can send the first interrupt signal, the memory address of the first target shared memory and the read data length to the target real-time system, so that the target real-time system receives and responds to the first interrupt signal, reads the data from the first target shared memory based on the received data length and the memory address of the first target shared memory; that is, the target real-time system reads the data of the corresponding length from the memory address of the first target shared memory according to the data length information.

[0094] In some embodiments, after obtaining the data, if the data is the working state information of the controlled device, the target real-time system can store the data in the memory buffer used by the target real-time system alone; if the data is the control instruction to the controlled device, the target real-time system can send the control instruction to the controlled device to control the controlled device.

[0095] Through the above scheme, the one-time transmission of the to-be-processed data from the non-real-time system to the real-time system can be realized based on the inter-core shared memory and the inter-process shared memory, so as to avoid multiple data reading and writing and multiple sending of interrupt signals, thereby significantly reducing the communication delay and the reading and writing resource overhead, and realizing efficient communication between the non-real-time system and the real-time system. Moreover, the user process can determine the addresses of the target shared memory and the inter-process shared memory corresponding to the target real-time system based on the identification of the target real-time system through the inter-core communication initialization interface, so as to realize data communication between the user process and the target real-time system.

[0096] Moreover, in the process of data communication between the user process and the real-time system, by setting the lock signal for each real-time system, the problem of data writing conflict caused by multiple user processes simultaneously attempting to communicate data with the same real-time system can be avoided, and the consistency of data writing is ensured.

[0097] Figure 6 Another flowchart of the data communication method of the hybrid deployment operating system provided by the embodiments of the present application is shown in Figure 6 The above method further includes steps 610 to 620.

[0098] Step 610, in response to the second interrupt signal sent by the second processor core, the length of the return message is obtained from the target shared memory based on the lock signal and the memory address of the target shared memory.

[0099] In some embodiments, the target real-time system may also send data to a non-real-time system (hereinafter referred to as a return message). This return message may be the processing result obtained after processing the data sent by the non-real-time system.

[0100] For example, after receiving and processing data sent by the user process, the target real-time system can obtain the processing result. The target real-time system can call a receiving service and read the data written by the user process based on the address of the first target shared memory. If the data is the working status information of the controlled device, it can be written to a memory buffer used separately by the target real-time system through the receiving service. The application in the target real-time system can then directly read and process the data from this memory buffer. For example, in industrial automation, the application in the target real-time system can filter and perform calculations on the data collected by sensors from the controlled device. If the data is a control command for the controlled device, the target real-time system can send the control command to the controlled device to control it and obtain the execution result (i.e., the processing result) of the control command by the controlled device.

[0101] In some embodiments, the return message sent by the target real-time system to the non-real-time system may also be information unrelated to the data sent by the non-real-time system, such as the working status information of industrial control equipment automatically collected by the target real-time system. That is, the return message may or may not be related to the data sent by the non-real-time system.

[0102] refer to Figure 7 Another schematic diagram of inter-core communication is shown, such as Figure 7 As shown, the target real-time system can call the inter-core communication interface and, based on the memory address of the target shared memory corresponding to the target real-time system, write the return message and its length into the target shared memory through the inter-core communication interface. Furthermore, the target real-time system can send a second interrupt signal to the non-real-time system via the rpmsg_send interface. This second interrupt signal instructs the non-real-time operating system to read the return message from the target shared memory.

[0103] Next, the second processor core can respond to the second interrupt signal by calling the resource management process, so that the resource management process can read the length of the return message from the target shared memory based on the memory address of the target shared memory corresponding to the target real-time system.

[0104] In some embodiments, when configuring the target shared memory corresponding to the target real-time system, the non-real-time system can further divide the target shared memory into a third target shared memory and a fourth target shared memory. The third target shared memory is used to store the length of the returned message, and the fourth target shared memory is used to store the returned message itself. For example, the real-time system can write the length of the returned message to the third target shared memory based on its memory address, and write the returned message to the fourth target shared memory based on its memory address. Thus, the resource management process can read the length of the returned message from the third target shared memory based on its memory address.

[0105] Step 620: Based on the memory address of the target shared memory and the length of the returned message, read the returned message from the target shared memory using a non-real-time operating system.

[0106] In some embodiments, after obtaining the length of the returned message, the resource management process can obtain the second status signal in the inter-process shared memory corresponding to the target real-time system, and increment the value of the second status signal according to a preset step, so as to change the value of the second status signal from the initial first signal to the second signal. For example, if the preset step is 1, the value of the second status signal is incremented by 1.

[0107] like Figure 7 As shown, after the resource management process changes the value of the second status signal from the initial first signal (e.g., 0) to the second signal (e.g., 1), it can wake up the user process so that the user process ends the waiting state and reads the return message from the target shared memory based on the virtual address of the target shared memory corresponding to the second status signal and the length of the return message.

[0108] For example, consider a user process A communicating with a target real-time system A, where the target real-time system A corresponds to inter-process shared memory A and a target shared memory A, and the inter-process shared memory A includes a second status signal a2. Then, after the resource management process reads the length of the returned message from the target shared memory A, it retrieves the second status signal a2 from the inter-process shared memory A and increments the value of the second status signal a2 by 1. The current value of the second status signal a2 changes from its initial value of 0 to 1.

[0109] In some embodiments, after obtaining the processing result, the user process can update the value of the lock signal from the second signal to the first signal to release the lock signal. For example, after obtaining the return message sent by the target real-time system and resource management process, the user process can call the inter-core communication message sending interface to change the value of the lock signal from the second signal (e.g., 0) to the first signal (e.g., 1) through the inter-core communication message sending interface, i.e., release the lock signal in the inter-process shared memory corresponding to the target real-time system.

[0110] Through the above scheme, during the process of waiting for the return message sent by the target real-time system and resource management process, the resource management process can determine whether to wake up the user process based on the value of the second state signal. Thus, different user processes can detect different second state signals when waiting for return messages sent by different real-time systems, thereby avoiding the problem of data conflict. Moreover, after obtaining the return message, the user process releases the lock signal in the inter-process shared memory corresponding to the target real-time system to restore the lock signal to an available state, so that other user processes can obtain the lock signal in the inter-process shared memory corresponding to the target real-time system and perform data communication with the target real-time system.

[0111] In some embodiments, after obtaining the processing result and returning it to the application, if the life cycle of the user process ends, the user process can call a third interface (hereinafter referred to as an inter-core communication de-initialization interface) provided by the non-real-time system to remove the mapping relationship between the virtual address and the physical address of the inter-process shared memory and the mapping relationship between the virtual address and the physical address of the inter-core shared memory through the inter-core communication de-initialization interface; and the user process can close the state signal through the inter-core communication de-initialization interface to remove the association between the state signal and the user process.

[0112] In some embodiments, if it is necessary to destroy the real-time system deployed in the non-real-time system, the resource management process can wake up the resources related to the real-time system for destruction. For example, the resource management process can first determine whether all lock signals and state signals are initial values, i.e., whether there is currently a user process still communicating data with the real-time system. If all lock signals and state signals are initial values, the resource management process can delete the real-time system, call a destroy interface to destroy the state signal corresponding to the real-time system, and then destroy the inter-process shared memory corresponding to the real-time system. At the same time when the inter-process shared memory is destroyed, the lock signal corresponding to the real-time system is also destroyed.

[0113] Figure 8Another flowchart of a data communication method for operating a hybrid deployment operating system is provided in embodiments of the present application, as shown in FIG. 8, which includes steps 801-811. Figure 8

[0114] At step 801, the first processor core acquires a lock signal from the inter-process shared memory based on the address of the inter-process shared memory corresponding to the target real-time system via the user process in the non-real-time system.

[0115] It can be understood that the implementation of step 801 can refer to the description of steps 210 and 220, which will not be repeated here.

[0116] At step 802, in the case of determining that the target shared memory corresponding to the target real-time system is in an accessible state based on the lock signal, the first processor core writes data and the length of the data into the target shared memory based on the memory address of the target shared memory via the user process.

[0117] It can be understood that the implementation of step 802 can refer to the description of step 220, which will not be repeated here.

[0118] At step 803, the first processor core sends a processing request to the resource management process via the user process.

[0119] It can be understood that the implementation of step 803 can refer to the description of step 230, which will not be repeated here.

[0120] At step 804, the first processor core reads the length of the data from the target shared memory based on the memory address of the target shared memory via the resource management process in response to the processing request.

[0121] It can be understood that the implementation of step 804 can refer to the description of step 230, which will not be repeated here.

[0122] At step 805, the first processor core sends the memory address of the target shared memory, the length of the data, and a first interrupt signal to the second processor core via the resource management process.

[0123] It can be understood that the implementation of step 805 can refer to the description of step 230, which will not be repeated here.

[0124] At step 806, the second processor core reads the data from the target shared memory based on the length of the data and the memory address of the target shared memory via the target real-time system in response to the first interrupt signal.

[0125] It can be understood that the implementation of step 806 can refer to the description of step 230, which will not be repeated here.

[0126] ​At step 807, the second processor core writes the return message and the length of the return message into the target shared memory through the target real-time system based on the memory address of the target shared memory.

[0127] It can be understood that the implementation of step 807 can refer to the description of step 610, and will not be described here.

[0128] At step 808, the second processor core sends a second interrupt signal to the first processor core through the target real-time system.

[0129] It can be understood that the implementation of step 808 can refer to the description of step 610, and will not be described here.

[0130] At step 809, the first processor core reads the length of the return message from the target shared memory through the resource management process based on the memory address of the target shared memory in response to the second interrupt signal.

[0131] It can be understood that the implementation of step 809 can refer to the description of step 620, and will not be described here.

[0132] At step 810, the first processor core wakes up the user process through the resource management process, and reads the return message from the target shared memory through the user process based on the memory address of the target shared memory and the length of the return message.

[0133] It can be understood that the implementation of step 810 can refer to the description of step 620, and will not be described here.

[0134] At step 811, the first processor core releases the lock signal of the inter-process shared memory corresponding to the target real-time system through the user process.

[0135] It can be understood that the implementation of step 811 can refer to the description of step 520, and will not be described here.

[0136] The above technical solution is applied, based on the inter-core shared memory and the process shared memory, so that single data reading / writing operation is performed in the process of transmitting data, and a single inter-core interrupt notification is performed, thereby improving the efficiency of inter-core communication. Moreover, the mutual exclusion lock is implemented through atomic operation, and the independent inter-core shared memory and state signal are allocated for each real-time system, thereby ensuring resource isolation; meanwhile, in the concurrent scenario of multiple user processes, the data confusion and lock competition problems can be avoided, thereby improving the stability of inter-core communication. In addition, the resource initialization and release processes are uniformly managed by the resource management process of the non-real-time side, and the user process only needs to call the standardized interface (such as initialization, sending, and de-initialization) to obtain the resource and related memory address and the like data, so that the user side does not need to pay attention to the underlying data interaction process, thereby improving the user experience. Moreover, the number and size of the inter-process shared memory and the second shared memory can be dynamically adjusted according to the deployment quantity of the real-time system and the business demand, thereby ensuring the flexibility of deployment.

[0137] Figure 9 A schematic diagram of a data communication device of a hybrid deployment operating system is provided for the embodiments of the present application. As shown in Figure 9 The data communication device 900 of the hybrid deployment operating system can be configured in an industrial control device; the data communication device 900 of the hybrid deployment operating system includes a first determination module 901, a writing module 902, and a sending module 903.

[0138] The first determination module 901 is configured to determine the inter-process shared memory shared by the process of the non-real-time operating system and the target shared memory corresponding to the target real-time operating system.

[0139] The inter-process shared memory is used to store a lock signal; the lock signal is used to indicate the accessible state of the target shared memory; the target shared memory is a memory shared by a first processor core and a second processor core; the first processor core is used to run the non-real-time operating system; and the second processor core is used to run the target real-time operating system.

[0140] The writing module 902 is configured to write the data and the length of the data into the target shared memory based on the lock signal and the memory address of the target shared memory.

[0141] The sending module 903 is configured to send a first interrupt signal to the second processor core.

[0142] The first interrupt signal is used to instruct the target real-time operating system to read the data from the target shared memory based on the length of the data and the memory address of the target shared memory.

[0143] As Figure 9As shown, the data communication apparatus 900 for hybrid deployment operating system further includes a first obtaining module 904, a second obtaining module 905 and a second determining module 906.

[0144] In some embodiments, the first obtaining module 904 is configured to obtain an address of the inter-process shared memory; the second obtaining module 905 is configured to obtain the lock signal from the inter-process shared memory based on the address of the inter-process shared memory; and the second determining module 906 is configured to determine whether the target shared memory is in the accessible state based on the lock signal.

[0145] In some embodiments, the writing module 902 is specifically configured to write the data and the length of the data into the target shared memory based on the address of the target shared memory in the case that the target shared memory is in the accessible state.

[0146] In some embodiments, the second determining module 906 is specifically configured to determine whether the lock signal is a first signal; wherein the first signal is used to indicate that the target shared memory is in the accessible state; and in the case that the lock signal is the first signal, it is determined that the target shared memory is in the accessible state.

[0147] As shown in Figure 9 The data communication apparatus 900 for hybrid deployment operating system further includes a resource updating module 907.

[0148] In some embodiments, the resource updating module 907 is configured to update the lock signal to a second signal by using an atomic operation; wherein the second signal is used to indicate that the target shared memory is in the inaccessible state.

[0149] In some embodiments, the target shared memory includes a first target shared memory and a second target shared memory; and the writing module 902 is specifically configured to write the data into the first target shared memory based on the address of the first target shared memory and write the length information of the data into the second target shared memory based on the address of the second target shared memory in the case that the target shared memory is in the accessible state.

[0150] As shown in Figure 9 The data communication apparatus 900 for hybrid deployment operating system further includes a third obtaining module 908 and a reading module 909.

[0151] In some embodiments, the third obtaining module 908 is configured to, in response to the second interrupt signal sent by the second processor core, obtain the length of the return message from the target shared memory based on the lock signal and the memory address of the target shared memory; the second interrupt signal is used to instruct the non-real-time operating system to read the return message from the target shared memory; the return message is related to the data or is not related to the data; and the reading module 909 is configured to read the return message from the target shared memory by the non-real-time operating system based on the memory address of the target shared memory and the length of the return message.

[0152] In some embodiments, the target shared memory includes a third target shared memory and a fourth target shared memory; the second interrupt signal is used to instruct the non-real-time operating system to read the return message from the third target shared memory; the third obtaining module 908 is configured to, in response to the second interrupt signal sent by the second processor core, obtain the length of the return message from the third target shared memory based on the lock signal and the memory address of the third target shared memory; and the reading module 909 is configured to read the return message from the fourth target shared memory by the non-real-time operating system based on the memory address of the fourth target shared memory and the length of the return message.

[0153] In some embodiments, the first determining module 901 is specifically configured to obtain the identification of the target real-time operating system; and determine the target shared memory based on the identification of the target real-time operating system and a target mapping relationship; the target mapping relationship is used to indicate the mapping relationship between the real-time operating system and the corresponding inter-core shared memory, the real-time operating system includes the target real-time operating system, and the inter-core shared memory includes the target shared memory.

[0154] Figure 10 A schematic diagram of an industrial control device is provided for some embodiments of the present application. The industrial control device includes one or more processors and a memory. The memory is configured to store one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the data communication method of the mixed deployment operating system in the above embodiments.

[0155] As shown in Figure 10 , the industrial control device 1000 includes a processor 1001 and a memory 1002. The industrial control device 1000 may, for example, also include a communications interface 1003 and a communications bus 1004.

[0156] The processor 1001, the memory 1002, and the communications interface 1003 complete communication with each other through the communications bus 1004. The communications interface 1003 is used to communicate with network elements such as clients or other servers, etc.

[0157] In some embodiments, the processor 1001 is configured to execute programs 1005, and particularly can execute the related steps in the data communication method embodiments of the hybrid-deployed operating system described above. Specifically, the programs 1005 can include program codes containing computer-executable instructions.

[0158] For example, the processor 1001 can be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement some embodiments of the present application. The industrial control device 1000 can include one or more processors, which can be the same type of processor, such as one or more CPUs; or can be different types of processors, such as one or more CPUs and one or more ASICs.

[0159] In some embodiments, the memory 1002 is configured to store the programs 1005. The memory 1002 can include a high-speed RAM memory, and can also include a non-volatile memory (NVM), such as at least one disk memory.

[0160] The programs 1005 can be specifically invoked by the processor 1001 to cause the industrial control device 1000 to perform the data communication method operations of the hybrid-deployed operating system.

[0161] Some embodiments of the present application provide a computer-readable storage medium storing at least one executable instruction, which, when executed on the industrial control device 1000, causes the industrial control device 1000 to perform the data communication method of the hybrid-deployed operating system in the above embodiments.

[0162] The executable instructions can be specifically used to cause the industrial control device 1000 to perform the data communication method operations of the hybrid-deployed operating system.

[0163] For example, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0164] The beneficial effects that can be achieved by the readable storage medium provided by some embodiments of the present application can refer to the beneficial effects of the corresponding data communication method of the hybrid-deployed operating system provided above, which will not be described here.

[0165] It is to be understood that the phrases "in one embodiment" or "implementing the embodiment" as used herein does not necessarily refer to the same embodiment, although it may. Further, the terms "comprises", "comprising", or other any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0166] Each of the embodiments described in this specification has at least one aspect. Relatively, the same or similar parts among the embodiments can be mutually referred to, and each embodiment focuses on the difference from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiments.

[0167] The logic and / or steps represented in the flowcharts and / or described herein, for example, can be considered as a sequence of executable instructions for implementing logic functions, and can be specifically embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus or device, such as a computer-based system, a system including a processor or other system that can fetch the instructions from the instruction execution system, apparatus or device and execute the instructions, or in conjunction with these instructions execution systems, apparatus or devices.

[0168] For the purpose of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate or transport a program for use by or in connection with an instruction execution system, apparatus or device, or in conjunction with these instruction execution systems, apparatus or devices.

[0169] More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection having one or more wires (electronic devices), a portable computer diskette (magnetic devices), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM).

[0170] Additionally, the computer readable medium can even be paper or other suitable medium upon which the program is printed, as the program can be electronically captured, for instance via an optical scanner, then compiled, interpreted, or otherwise processed, as necessary, to create electronic data representing the program, which data then can be stored in computer memory. It should be understood that parts of this application can be implemented in hardware, software, firmware, or combinations thereof, and that software or firmware implementations could be implemented with the aid of a suitable digital processing system.

[0171] In the embodiments described above, the steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any of the following technologies, known in the art, or combinations thereof, can be used: a discrete logic circuit having logic gates for implementing logic functions upon data signals, an application specific integrated circuit having appropriate combinational logic gates, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0172] The above described embodiments are merely exemplary and are not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made on the basis of the technical solutions of the present application shall be included in the scope of the present application.

Claims

1. A data communication method for hybrid operating system deployment, applied to industrial control equipment, characterized in that, The method includes: The inter-process shared memory shared by processes of a non-real-time operating system and the target shared memory corresponding to a target real-time operating system are determined; wherein, the inter-process shared memory is used to store lock signals; the lock signals are used to indicate the accessibility status of the target shared memory; the target shared memory is memory shared by a first processor core and a second processor core; the first processor core is used to run the non-real-time operating system; the second processor core is used to run the target real-time operating system; Based on the lock signal and the memory address of the target shared memory, the data and the length of the data are written into the target shared memory; Send a first interrupt signal to the second processor core; wherein the first interrupt signal is used to instruct the target real-time operating system to read the data from the target shared memory based on the length of the data and the memory address of the target shared memory.

2. The method according to claim 1, characterized in that, Before writing the data and the length of the data into the target shared memory based on the lock signal and the memory address of the target shared memory, the method further includes: Obtain the address of the inter-process shared memory; Based on the address of the inter-process shared memory, obtain the lock signal from the inter-process shared memory; Based on the lock signal, it is determined whether the target shared memory is in an accessible state.

3. The method according to claim 2, characterized in that, The step of writing data and the length of the data into the target shared memory based on the lock signal and the memory address of the target shared memory includes: When the target shared memory is in an accessible state, data and the length of the data are written to the target shared memory based on the address of the target shared memory.

4. The method according to claim 2 or 3, characterized in that, Determining whether the target shared memory is in an accessible state based on the lock signal includes: Determine whether the lock signal is a first signal; wherein the first signal is used to indicate that the target shared memory is in an accessible state; When the lock signal is the first signal, it is determined that the target shared memory is in an accessible state.

5. The method according to claim 4, characterized in that, The method further includes: The lock signal is updated to a second signal using an atomic operation; wherein the second signal is used to indicate that the target shared memory is in an inaccessible state.

6. The method according to any one of claims 3-5, characterized in that, The target shared memory includes a first target shared memory and a second target shared memory; When the target shared memory is in an accessible state, writing data and the length of the data into the target shared memory based on the address of the target shared memory includes: When the target shared memory is in an accessible state, the data is written to the first target shared memory based on the address of the first target shared memory; Based on the address of the second target shared memory, the length information of the data is written into the second target shared memory.

7. The method according to claim 1, characterized in that, The method further includes: In response to a second interrupt signal sent by the second processor core, the length of the return message is obtained from the target shared memory based on the lock signal and the memory address of the target shared memory; wherein, the second interrupt signal is used to instruct the non-real-time operating system to read the return message from the target shared memory; the return message may or may not be related to the data; Based on the memory address of the target shared memory and the length of the returned message, the returned message is read from the target shared memory through the non-real-time operating system.

8. The method according to claim 7, characterized in that, The target shared memory includes a third target shared memory and a fourth target shared memory; the second interrupt signal is used to instruct the non-real-time operating system to read a return message from the third target shared memory; The step of responding to the second interrupt signal sent by the second processor core, and obtaining the length of the return message from the target shared memory based on the lock signal and the memory address of the target shared memory, includes: In response to the second interrupt signal sent by the second processor core, the length of the return message is obtained from the third target shared memory based on the lock signal and the memory address of the third target shared memory; The step of reading the return message from the target shared memory based on the memory address of the target shared memory and the length of the return message through the non-real-time operating system includes: Based on the memory address of the fourth target shared memory and the length of the returned message, the returned message is read from the fourth target shared memory through the non-real-time operating system.

9. The method according to any one of claims 1-8, characterized in that, Determine the target shared memory corresponding to the target real-time operating system, including: Obtain the identifier of the target real-time operating system; Based on the identifier of the target real-time operating system and the preset mapping relationship, the target shared memory is determined; wherein, the preset mapping relationship is used to indicate the mapping relationship between the real-time operating system and the corresponding inter-core shared memory, the real-time operating system includes the target real-time operating system, and the inter-core shared memory includes the target shared memory.

10. An industrial control device, characterized in that, include: Memory and processor; The memory and processor are coupled; Memory, used to store program instructions; The processor is used to execute the program instructions to cause the industrial control equipment to perform the data communication method of the hybrid deployment operating system as described in any one of claims 1-9.

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