Storage device, error address cache and error address cache method

Abstract

The invention provides a storage device, an error address cache and an error address cache method. The storage device comprises a plurality of memory grains and a standby grain, wherein the standby grain is stacked in the memory grains and repairs a target memory grain in the plurality of memory grains. Each of the backup die and the memory die may include an error address cache that records error address information of the storage device. The error address cache receives an input address signal and outputs a hit signal or a miss signal indicating whether the input address signal hits an error address stored in the error address cache. The storage device controls access to the memory die and the standby die according to the hit signal or the miss signal.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device, and more particularly, to a stacked memory device having a repair mechanism to improve yield, an error address cache and a method thereof. BACKGROUND

[0002] Wafer stacking technology has been used to stack logic wafers (i.e., system on chip wafers) and memory wafers together to form a stacked memory. However, in wafer on wafer stacking technology, good dies are often not selected for stacking. If there is a defective die in the stacked memory, the stacked memory should be repaired to improve the yield of the stacked memory. Therefore, there is a need for a novel technology that can effectively repair defective dies in a memory device and improve the yield of the memory device. SUMMARY

[0003] The present invention provides a memory device, an error address cache and a method thereof that effectively improve the above problems.

[0004] The memory device of the present invention includes a plurality of memory dies and a spare die stacked to the memory dies, the spare die configured to repair a target memory die of the plurality of memory dies. Each of the spare die and the memory dies can include an error address cache configured to record error address information of the memory device. The error address cache is configured to receive an input address signal and output a hit signal or a miss signal, the hit signal or the miss signal indicating whether the input address signal hits a failed address stored in the error address cache. The memory device is configured to control access to the memory dies and the spare die based on the hit signal or the miss signal.

[0005] The present invention provides a method of operating a memory device including a plurality of memory dies and a spare die stacked to each other, each of the spare die and the memory dies including an error address cache configured to record error address information of the memory device. The method includes receiving, by the error address cache of the spare die or one of the memory dies, an input address signal; outputting, by the error address cache of the spare die or one of the memory dies, a hit signal or a miss signal, the hit signal or the miss signal indicating whether the input address signal hits a failed address stored in the error address cache; and controlling access to the memory dies and the spare die based on the hit signal or the miss signal.

[0006] Embodiments of the present application provide a memory device including a spare die and a plurality of memory dies, wherein each of the spare die and the memory dies includes an error address cache to record error address information of the memory device. When an input address signal is input to the error address cache, the error address cache can determine whether the input address signal hits an error address stored in the error address cache. When the error address cache in the spare die hits, the error address cache in the spare die allows access to a memory array in the spare die. When the error address cache in the spare die misses, the error address cache in the spare die blocks access to the memory array in the spare die. When the error address cache in the memory die hits, the error address cache in the memory die blocks access to a memory array in the memory die. When the error address cache in the memory die misses, the error address cache in the memory die allows access to the memory array in the memory die. In this way, the error address cache stored in each of the spare die and the memory dies can be used to effectively repair a failed bank group, a failed bank, and / or a failed row in a target memory die.

[0007] In order to make the above features and advantages of the present application more comprehensible, specific embodiments accompanied with drawings are described in detail as follows. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1A is a schematic diagram of a semiconductor stack wafer forming a memory device according to an embodiment of the present application;

[0009] Figure 1B is a schematic diagram of a memory device including a plurality of dies stacked with each other according to an embodiment of the present application;

[0010] Figure 2A is a schematic diagram of an error address cache located in a spare die according to an embodiment of the present application;

[0011] Figure 2B is a schematic diagram of an error address cache located in a normal die according to an embodiment of the present application;

[0012] Figure 3A and Figure 3B is a schematic diagram of an error address cache recording an error bank group address and an error bank address according to an embodiment of the present application;

[0013] Figure 4A is a flowchart of determining whether an input bank group address signal or an input bank address signal hits using an error address cache according to an embodiment of the present application;

[0014] Figure 4B and Figure 4Cis a flowchart of controlling access to a storage device based on a hit signal or a miss signal according to an embodiment of the present invention;

[0015] Figure 5A is a schematic diagram of an error address cache recording error row addresses according to an embodiment of the present invention;

[0016] Figure 5B is a schematic diagram of a module of an error row address field of an error address cache according to an embodiment of the present invention;

[0017] Figure 5C is a flowchart of generating a hit signal or a miss signal upon receiving an input row address signal according to an embodiment of the present invention;

[0018] Figure 6A and Figure 6B is a schematic diagram of an error address cache recording error row addresses according to an embodiment of the present invention;

[0019] Figure 7A and Figure 7B is a flowchart of generating a hit signal or a miss signal according to an embodiment of the present invention;

[0020] Figure 8 is a flowchart of a method of operating a storage device according to an embodiment of the present invention.

[0021] BRIEF DESCRIPTION OF DRAWINGS

[0022] 100: semiconductor stack wafer

[0023] 110a, 110b: error address cache

[0024] 111a, 111b: hit-miss signal

[0025] 120a, 120b: access control block

[0026] 130a, 130b: memory array

[0027] 200: storage device

[0028] 201: storage bank group field

[0029] 202, 304, 602a, 602b: correctness field

[0030] 203, 301: error block identifier field

[0031] 204: error storage bank group address field

[0032] 205: replacement storage bank group address field

[0033] 302: error memory bank address field

[0034] 303: replacement memory bank address field

[0035] 501, 510: first correctness field

[0036] 502, 520: block identifier field

[0037] 503, 530: error memory bank group field

[0038] 504, 540: second correctness field

[0039] 550_1: N-bit module

[0040] 550_2: M-bit module

[0041] 550_3: K-bit module

[0042] 601a, 601b: index field

[0043] 603a, 603b: error row address field

[0044] A, B: signal

[0045] ADDR: input address signal

[0046] ADDR1, ADDR2: error row address

[0047] BG_CACHE, BK_CACHE, ROW_CACHE, ROW_CACHE_a, ROW_CACHE_b: error address cache

[0048] BG0-BG3: memory bank group

[0049] BK0-BK15: memory bank

[0050] CACHE_TITLE: cache title field

[0051] D: die

[0052] D0: logic die

[0053] D1: spare die

[0054] D2-D3: memory die

[0055] Dx: normal die

[0056] F_ROW_ADDR: error row address field

[0057] ROW_ADDR: input row address

[0058] S401-S406, S407b-S407c, S408b-S408c, S409b-S409c, S501-S506, S701a-S705a, S701b-S702b, S703b_1-S703b_3, S704a-S705a, S704b-S705b, S810-S830: steps

[0059] W0-W3: wafer DETAILED DESCRIPTION

[0060] Reference will now be made in detail embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0061] Figure 1A And Figure 1B is a schematic diagram of a semiconductor stacked wafer 100 according to an embodiment of the present application. The semiconductor stacked wafer 100 includes a plurality of wafers W0-W3 stacked with each other. The wafers W0-W3 of the semiconductor stacked wafer 100 can be stacked with each other using a wafer-on-wafer stacking technique. Each of the wafers W0-W3 includes a plurality of dies D, and the dies in the wafers W0-W3 can be stacked with each other to form a memory device. The memory device is a dynamic random access memory (DRAM), but the present application is not limited thereto. The present application is not intended to limit the type of the memory device, the number of the wafers W0-W3 in the semiconductor stacked wafer 100, and the number of the dies D in each wafer.

[0062] The wafers W0-W3 of the semiconductor stacked wafer 100 can include a logic wafer, a spare wafer, and a plurality of memory wafers. The spare wafer of the semiconductor stacked wafer 100 can be determined by programming a fuse. For simplicity, the wafer W0 of the semiconductor stacked wafer 100 is referred to as a logic wafer, the wafer W1 is referred to as a spare wafer, and the wafers W2-W3 are referred to as memory wafers.

[0063] The present application does not limit the number of the logic wafers, the number of the spare wafers, and the number of the memory wafers in the semiconductor stacked wafer 100. In addition, the positions and arrangements of the logic wafers, the spare wafers, and the memory wafers in the semiconductor stacked wafer 100 can vary according to design requirements.

[0064] Figure 1BFIG. 1 is a schematic diagram of a memory device 200 including a plurality of dies D0-D3 stacked with each other according to an embodiment of the present application. The dies D0-D3 are dies of wafers W0-W3, respectively. The memory device 200 is composed of a logic die D0 of a logic wafer, a spare die D1 of a spare wafer, and memory dies D2-D3 of a memory wafer. It is understood that the spare die D1 can be determined by programming a fuse (not shown) after the memory device 200 is packaged. The memory device 200 can include memory blocks (not shown), each of which corresponds to some of the dies D0-D3. Each of the dies D0-D3 can include a plurality of bank groups BG0-BG3, and each of the bank groups BG0-BG3 can include a plurality of memory banks BK0-BK15. Each of the memory banks BK0-BK15 can include a plurality of memory rows (not shown). Each of the dies D0-D3 of the memory device 200 can include an error address cache and be used to record error address information (i.e., an erroneous memory block, an erroneous bank group, an erroneous memory bank, an erroneous memory row) and / or a piece of information about repair information (i.e., a replacement memory block, a replacement bank group, a replacement memory bank, a replacement memory row).

[0065] Figure 2A FIG. 1 is a schematic diagram of a memory device 200 including a plurality of dies D0-D3 stacked with each other according to an embodiment of the present application. The dies D0-D3 are dies of wafers W0-W3, respectively. The memory device 200 is composed of a logic die D0 of a logic wafer, a spare die D1 of a spare wafer, and memory dies D2-D3 of a memory wafer. It is understood that the spare die D1 can be determined by programming a fuse (not shown) after the memory device 200 is packaged. The memory device 200 can include memory blocks (not shown), each of which corresponds to some of the dies D0-D3. Each of the dies D0-D3 can include a plurality of bank groups BG0-BG3, and each of the bank groups BG0-BG3 can include a plurality of memory banks BK0-BK15. Each of the memory banks BK0-BK15 can include a plurality of memory rows (not shown). Each of the dies D0-D3 of the memory device 200 can include an error address cache and be used to record error address information (i.e., an erroneous memory block, an erroneous bank group, an erroneous memory bank, an erroneous memory row) and / or a piece of information about repair information (i.e., a replacement memory block, a replacement bank group, a replacement memory bank, a replacement memory row). Figure 2A

[0066] ​The access control block 120a can receive the hit-miss signal 111a from the error address cache 110a and is configured to transmit or block the input address signal ADDR and / or a command associated with the input address signal ADDR to the memory array 130a. The command can be a read command for performing a read operation on the input address signal ADDR or a write command for performing a write operation. When the hit-miss signal 111a is a hit signal, the access control block 120a is configured to transmit the input address signal ADDR and / or the command to the memory array 130a. In other words, when the error address cache 110a of the spare die Dl outputs a hit signal, the access control block 120a allows access to the memory array 130a. When the hit-miss signal 111a is a miss signal, the access control block 120a is configured to block the input address signal ADDR and / or the command from being transmitted to the memory array 130a. In other words, when the error address cache 110a of the spare die Dl outputs a miss signal, the access control block 120a blocks access to the memory array 130a.

[0067] Figure 2B FIG. 2 is a schematic diagram of an error address cache 110b located in a normal die Dx (i.e., a memory die D2 or D3 of the memory wafer of FIG. 1) according to an embodiment of the present application. As shown, the normal die Dx can include the error address cache 110b, an access control block 120b, and a memory array 130b. The error address cache 110b can receive an input address signal ADDR and determine whether the input address signal ADDR hits one of the failed addresses recorded in the error address cache 110b and output a hit signal or a miss signal according to the determination. Figure 2B Figure 2B The information stored in the error address cache 110b is the same as the information stored in the error address cache 110a shown in FIG. 1. Figure 2A When the input address signal ADDR hits a failed address recorded in the error address cache 110b, the error address cache 110b outputs a hit signal, and when the input address signal ADDR misses all the failed addresses recorded in the error address cache 110b, the error address cache 110b outputs a miss signal. The hit signal and the miss signal can be collectively referred to as a hit-miss signal 111b output by the error address cache 110b.

[0068] ​The access control block 120b can receive the hit-miss signal 111b from the error address cache 110b and is configured to transmit or block the input address signal ADDR and / or the command associated with the input address signal ADDR to the memory array 130b. When the hit-miss signal 111b is a hit signal, the access control block 120b is configured to block the input address signal ADDR and / or the command from being transmitted to the memory array 130b. In other words, when the error address cache 110b of the normal die Dx outputs a hit signal, the access control block 120b blocks the access to the memory array 130b. When the hit-miss signal 111b is a miss signal, the access control block 120b is configured to transmit the input address signal ADDR and / or the command to the memory array 130b. In other words, when the error address cache 110b of the normal die Dx outputs a miss signal, the access control block 120b allows the access to the memory array 130b. Figure 2A and Figure 2B The functions of the access control blocks 120a and 120b in FIG. 1 can be implemented in the error address caches 110a and 110b, respectively.

[0069] Figure 3A FIG. 2 is a schematic diagram of an error address cache BG_CACHE recording error storage bank group addresses according to an embodiment of the present application. The error address cache BG_CACHE can be stored in each die of the storage device 200, including the spare die Dl and the memory dies D2-D3. The error address cache BG_CACHE can record information of the error storage bank groups of the storage device 200.

[0070] The error address cache BG_CACHE can include a bank group field 201, a correctness field 202, an error block identifier field 203, an error bank group address field 204, and a replacement bank group address field 205. The bank group field 201 can record information of error bank groups in the die of the memory device 200. The correctness field 202 can record correctness status of each error bank group. The error block identifier (ID) field 203 can record block identifiers of memory blocks containing error bank groups. The error bank group address field 204 can record addresses of error bank groups in the memory device 200. The replacement bank group address field 205 can record addresses of replacement bank groups for replacing error bank groups. The replacement bank group refers to a bank group in the spare die Dl of the spare wafer, which is used to replace an error bank group in one of the memory dies (i.e., the memory die D2 of the memory wafer or the memory die D3 of the memory wafer). The input address signal is an input bank group address signal, and the error address cache BG_CACHE can determine a hit or a miss of the input bank group address signal with respect to the failed bank group address stored in the error address cache BG_CACHE.

[0071] Figure 3B FIG. 1 is a diagram illustrating an error address cache BK_CACHE for recording error bank addresses according to an embodiment of the present application. The error address cache BK_CACHE can be stored in each die (including the spare die Dl and the memory dies D2-D3) of the memory device 200. The error address cache BK_CACHE can record information related to error banks of the memory device 200.

[0072] The error address cache BK_CACHE can include an error block identifier field 301, an error bank address field 302, a replacement bank address field 303, and a correctness field 304. The error block identifier (ID) field 301 can record block identifiers of memory blocks containing error banks. The error bank address field 302 can record addresses of error banks in the memory device 200. The replacement bank address field 303 can record addresses of replacement banks for replacing error banks in the memory device 200. The replacement bank refers to a bank of the spare die Dl, which is used to replace an error bank in one of the memory dies (i.e., the memory die D2 of the memory wafer or the memory die D3 of the memory wafer). The correctness field 304 can record correctness status of each error bank in the error address cache BK_CACHE.

[0073] When the input address signal is an input bank group address signal, Figure 3AThe error address cache BG_CACHE in the memory device 200 can be used to determine a hit or miss of the input bank group address signal. When the input address signal is the input bank group address signal, Figure 3B The error address cache BK_CACHE in the memory device 200 can be used to determine a hit or miss of the input bank address signal.

[0074] Figure 4A is a flowchart illustrating a process of determining whether an input bank group address signal or an input bank address is a hit using an error address cache according to an embodiment of the present application. In step S401, an input address signal ADDR is input to the error address cache stored in each die of the memory device 200. The input address signal ADDR can be an input bank group address signal, which can identify a bank group of the memory device 200. In some alternative embodiments, the input address signal ADDR can be an input bank address signal, which can identify a bank of the memory device 200.

[0075] In step S402, the error address cache (i.e., the error address cache BG_CACHE or the error address cache BK_CACHE) is configured to check a correctness status of the error bank group or the error bank recorded in the error address cache. In step S403, the error address cache is configured to check whether a block identifier associated with the input address signal ADDR matches an error block identifier recorded in the error address cache. In step S404, the error address cache is configured to check whether the input address signal ADDR matches an error bank group address or an error bank address recorded in the error address cache.

[0076] The input address signal ADDR is an input bank group address signal, which can identify a bank group of the memory device 200. Accordingly, Figure 3AThe error address cache BG_CACHE can output a hit signal or a miss signal upon receiving the input bank group address signal. The error address cache BG_CACHE can determine whether the input bank group address signal matches one of the erroneous bank group addresses recorded in the error address cache BG_CACHE (step S404). At the same time, the error address cache BG_CACHE can determine whether the validity status in the error address cache BG_CACHE is valid (step S402), and determine whether the block identifier associated with the input bank group address signal matches the erroneous block identifier in the error address cache BG_CACHE (step S403). In response to determining that the input bank group address signal matches an erroneous bank group address in the error address cache BG_CACHE, the validity status of the erroneous bank group address in the error address cache BG_CACHE is valid, and the block identifier associated with the input bank group address signal matches the erroneous block identifier of the erroneous bank group in the error address cache BG_CACHE, the error address cache BG_CACHE outputs a hit signal (step S405). In response to determining that the input bank group address signal does not match all of the erroneous bank group addresses in the error address cache BG_CACHE, the validity status of the erroneous bank group address in the error address cache BG_CACHE is not valid, and / or the block identifier associated with the input bank group address signal does not match the erroneous block identifier of the erroneous bank group in the error address cache BG_CACHE, the error address cache BG_CACHE outputs a miss signal (step S406).

[0077] The input address signal ADDR is an input bank address signal that can identify a bank of the memory device 200. Thus, Figure 3BThe error address cache BK_CACHE can output a hit signal or a miss signal upon receiving an input bank address. The error address cache BK_CACHE can determine whether the input bank address signal matches one of the failed bank addresses recorded in the error address cache BK_CACHE (step S404). At the same time, the error address cache BK_CACHE can determine whether the validity status in the error address cache BK_CACHE is valid (step S402), and determine whether the block identifier associated with the input bank address signal matches the error block identifier recorded in the error address cache BK_CACHE (step S403). In response to determining that the input bank address signal matches a failed bank address in the error address cache BK_CACHE, the validity status of the failed bank address in the error address cache BK_CACHE is valid, and the block identifier associated with the input bank address signal matches the error block identifier of the failed bank in the error address cache BK_CACHE, the error address cache BK_CACHE outputs a hit signal (step S405). In response to determining that the input bank address signal does not match all the failed bank addresses in the error address cache BK_CACHE, the validity status of the failed bank address in the error address cache BK_CACHE is not valid, and / or the block identifier associated with the input bank address signal does not match the error block identifier of the failed bank in the error address cache BK_CACHE, the error address cache BK_CACHE outputs a miss signal (step S406).

[0078] Figure 4B is a flowchart of controlling access to a memory device based on a hit signal according to an embodiment of the present application. In step S405, a hit signal is outputted by an error address cache (i.e. Figure 3A in Figure 3BThe miss signal is outputted by the error address cache (i.e. the error address cache BG_CACHE in the backup die Dl or the error address cache BK_CACHE in the normal die Dx) in step S407b. When it is determined that the error address cache is located in the backup die Dl, the error address cache allows the access to the memory array by transmitting the replaced bank group address or the replaced bank address to the memory array (step S408b). In step S408b, the error address cache can further transmit the command (i.e. the read command or the write command) associated with the input address signal ADDR to the memory array. When it is determined that the error address cache is located in the normal die Dx, the error address cache can block the access to the memory array by blocking the transmission of the input bank group address signal, or the input bank address and its associated command to the memory array (step S409b). In other words, the error address cache in the backup die allows the access to the memory array when the error address cache in the backup die is hit, while the error address cache in the normal die Dx blocks the access to the memory array when the error address cache in the normal die Dx is hit.

[0079] Figure 4C The flowchart of controlling the access to the memory device based on the miss signal is shown according to an embodiment of the present application. In step S406, the miss signal is outputted by the error address cache (i.e. the error address cache BG_CACHE in the backup die Dl or the error address cache BK_CACHE in the normal die Dx) in step S407b. When it is determined that the error address cache is located in the backup die Dl, the error address cache allows the access to the memory array by transmitting the replaced bank group address or the replaced bank address to the memory array (step S408b). In step S408b, the error address cache can further transmit the command (i.e. the read command or the write command) associated with the input address signal ADDR to the memory array. When it is determined that the error address cache is located in the normal die Dx, the error address cache can block the access to the memory array by blocking the transmission of the input bank group address signal, or the input bank address and its associated command to the memory array (step S409b). In other words, the error address cache in the backup die allows the access to the memory array when the error address cache in the backup die is hit, while the error address cache in the normal die Dx blocks the access to the memory array when the error address cache in the normal die Dx is hit. Figure 3A Figure 3B The miss signal is outputted by the error address cache (i.e. the error address cache BG_CACHE in the backup die Dl or the error address cache BK_CACHE in the normal die Dx) in step S407b. When it is determined that the error address cache is located in the backup die Dl, the error address cache allows the access to the memory array by transmitting the replaced bank group address or the replaced bank address to the memory array (step S408b). In step S408b, the error address cache can further transmit the command (i.e. the read command or the write command) associated with the input address signal ADDR to the memory array. When it is determined that the error address cache is located in the normal die Dx, the error address cache can block the access to the memory array by blocking the transmission of the input bank group address signal, or the input bank address and its associated command to the memory array (step S409b). In other words, the error address cache in the backup die allows the access to the memory array when the error address cache in the backup die is hit, while the error address cache in the normal die Dx blocks the access to the memory array when the error address cache in the normal die Dx is hit.

[0080] Figure 5A ​is a diagram illustrating an error address cache ROW CACHE recording error row addresses according to embodiments of the present application. The error address cache ROW CACHE can record address information of error rows in a memory device 200 (i.e. Figure 1B

[0081] As shown in Figure 5A , the error address cache ROW CACHE can include a cache title field CACHE_TITLE and an error row address field F_ROW_ADDR. The cache title field CACHE_TITLE is configured to record cache title information of the error address cache ROW_CACHE. The cache title field CACHE_TITLE can include a first correctness field 501, a block identifier field 502, and an error storage bank group field 503. The first correctness field 510 can record a correctness status of the cache title, the block identifier field 520 can record identification information of a block including an error row, and the error storage bank group field 530 can record addresses of error storage bank blocks including the error row.

[0082] The error row address field F_ROW_ADDR can include a second correctness field 540 and a plurality of multi-bit modules. The second correctness field 540 can record a correctness status of the error row address field F_ROW_ADDR, and the multi-bit modules can record row addresses of error rows of the memory device 200. As shown in Figure 5A , the error row address field F_ROW_ADDR can include an N-bit module 550_1, an M-bit module 550_2, and a K-bit module 550_3. The N-bit module 550_1, the M-bit module 550_2, and the K-bit module 550_3 are configured to record row addresses of error rows in the memory device 200.

[0083] Figure 5B is a diagram illustrating storage of row addresses of error rows in the N-bit module 550_1, the M-bit module 550_2, and the K-bit module 550_3 according to embodiments of the present application. As shown in Figure 5B , a row address of an error row can be represented by ADDR<13:0>, where data bits ADDR<13:9> are resolved into the N-bit module, data bits ADDR<8:4> are represented as the M-bit module, and data bits ADDR<3:0> are represented as the K-bit module. Further, the present application is not intended to limit the number of bits of the row address, or the number of modules in the error row address field F_ROW_ADDR of the error address cache ROW_CACHE.

[0084] Figure 5C ​is a flowchart illustrating the use of the error address cache ROW CACHE to generate a hit signal or a miss signal when receiving an input row address signal according to an embodiment of the present application. In step S501, an input row address ROW ADDR is input to the error address cache ROW CACHE. In step S502, the error address cache ROW CACHE can check whether the cache tag associated with the input row address ROW ADDR matches the cache tags stored in the error address cache ROW CACHE. In step S503, the error address cache ROW CACHE can check whether the validity status of the validity field in the error address cache ROW CACHE is valid. That is, the error address cache ROW CACHE can check whether the validity status stored in the first validity field 501 and the second validity field 504 is valid. In step S504, the error address cache ROW CACHE can check whether the multi-bit module associated with the input row address ROW ADDR matches the multi-bit module stored in the error row address field F_ROW_ADDR in the error address cache ROW CACHE.

[0085] In response to determining that the multi-bit module associated with the input row address ROW ADDR matches the multi-bit module stored in the error row address field F_ROW_ADDR in the error address cache ROW CACHE (step S504), that the cache tag associated with the input row address ROW ADDR matches the cache tag in the error address cache ROW CACHE (step S502), and that the validity status in the first validity field 501 and the second validity field 504 is valid (step S503), the error address cache ROW CACHE outputs a hit signal, which represents that the input row address ROW ADDR hits one of the error rows stored in the error address cache ROW CACHE.

[0086] In response to determining that the multi-bit module associated with the input row address ROW ADDR does not match the multi-bit module stored in the error row address field F_ROW_ADDR in the error address cache ROW CACHE (step S504), or that the cache tag associated with the input row address ROW ADDR does not match the cache tag in the error address cache ROW CACHE (step S502), or that the validity status in the first validity field 501 and the second validity field 504 is not valid (step S503), the error address cache ROW CACHE outputs a miss signal, which represents that the input row address ROW ADDR misses all the error rows stored in the error address cache ROW CACHE.

[0087] The ROW_CACHE error cache can allow or block memory access based on a hit or miss signal and the memory die storing the ROW_CACHE. For example, the ROW_CACHE in a spare die can allow memory access when a hit signal is output and block memory access when a miss signal is output. The ROW_CACHE in a normal die (Dx) can block memory access when a hit signal is output and allow memory access when a miss signal is output. This control of memory access based on the hit or miss signal of the ROW_CACHE may be related to… Figure 4B and Figure 4C The processing procedure shown in the image is the same.

[0088] Figure 6A This is a schematic diagram of an error address cache ROW_CACHE_a used to record the address of an erroneous row, according to an embodiment of the present invention. The error address cache ROW_CACHE_a can record the address information of erroneous rows in the storage device 200. Furthermore, the error address cache ROW_CACHE_a can be stored in each die of the storage device 200.

[0089] like Figure 6A As shown, the error address cache ROW_CACHE_a may include an index field 601a, a correctness field 602a, and an error row address field 603a. The index field 601a records the index value of each row in the error address cache ROW_CACHE_a, the correctness field 602a records the correctness status of each row in the error address cache ROW_CACHE_a, and the error row address field 603a records the information of the storage device (i.e., the correctness status of each row in the error address cache ROW_CACHE_a) in each row. Figure 1B The storage device 200) stores the error row address of the erroneous row. The index value stored in the index field 601a can be a 5-bit value, the correctness status can be a 1-bit value, and the error row address stored in the error row address field 603a can be a 9-bit value. This invention does not intend to limit the number of bits in the values ​​stored in the index field 601a, the correctness field 602a, and the error row address field 603a of the error address cache ROW_CACHE_a. Figure 6A As shown, each index value in index field 601a can correspond to an error row address (i.e., a 1-1 mapping) in error row address field 603a.

[0090] Figure 6Bis a diagram illustrating an error address cache ROW CACHE_b to record error row addresses according to embodiments of the present application. The error address cache ROW CACHE_b can record address information of error rows in the memory device 200. In addition, the error address cache ROW_CACHE_b can be stored in each die of the memory device 200.

[0091] As shown in Figure 6B , the error address cache ROW_CACHE_b can include an index field 601b, a validity field 602b, and an error row address field 603b. Figure 6B The index field 601b and the validity field 602b of the error address cache ROW_CACHE_b can be the same as Figure 6A the index field 601a and the validity field 602a of the error address cache ROW_CACHE_a, and thus, detailed descriptions of the index field 601b and the validity field 602b are omitted herein. Figure 6B The error address cache ROW_CACHE_b in Figure 6A differs from the error address cache ROW_CACHE_a in in that each index of the error address cache ROW_CACHE_b can correspond to a plurality (i.e., two) of error row addresses ADDR1 and error row address ADDR2. In other words, each index value in the index field 601b can correspond to a plurality of error row addresses (i.e., 1-n mapping) in the error row address field 603b.

[0092] Figure 7A is a flowchart illustrating the error address cache ROW_CACHE_a outputting a hit signal or a miss signal upon input of a row address signal according to embodiments of the present application. The input row address signal (not shown) can include an input access index and an input row address.

[0093] In step S701a, the input access index is input to the error address cache ROW_CACHE_a. In step S702a, the error address cache ROW_CACHE_a can check a validity state corresponding to the input access index; in step S702a, the error address cache ROW_CACHE_a can compare the input row address with the error row addresses stored in the error address cache ROW_CACHE_a.

[0094] In response to determining that the validity status corresponding to the input access index is valid (step S702a) and that the input row address matches the error row address corresponding to the input access index in the error address cache ROW_CACHE_a (step S703a), the error address cache ROW_CACHE_a outputs a hit signal (step S703a). In response to determining that the validity status corresponding to the input access index is invalid (step S702a) or that the input row address does not match the error row address corresponding to the input access index in the error address cache ROW_CACHE_a (step S704a), the error address cache ROW_CACHE_a outputs a miss signal (step S705a).

[0095] Figure 7B FIG. 7B is a flowchart showing the error address cache ROW_CACHE_b outputting a hit signal or a miss signal in response to an input row address signal according to an embodiment of the present application. The input row address signal (not shown) can include an input access index, a first input row address, and a second input row address.

[0096] In step S701b, the input access index is inputted into the error address cache ROW_CACHE_b. In step S702b, the error address cache ROW_CACHE_b can check the validity status corresponding to the input access index. If the validity status corresponding to the input access index is invalid, the error address cache ROW_CACHE_b outputs a miss signal (step S705b). If the validity status corresponding to the input access index is valid, the error address cache ROW_CACHE_b proceeds to step S703b_1 and step S703b_2.

[0097] In step S703b_1 and step S703b_2, the error address cache ROW_CACHE_b can compare the first input row address and the second input row address with the first error row address and the second error row address corresponding to the input access index. Specifically, in step S703b_1, the error address cache ROW_CACHE_b can compare the first input row address with the first error row address stored in the error address cache ROW_CACHE_b and output a signal A indicating the comparison result. When the first input row address matches the first error row address, the signal A shows "same"; when the first input row address does not match the first error row address, the signal A shows "not same".

[0098] In step S703b_2, the error address cache ROW_CACHE_b compares the second input row address with the second error row address stored in the error address cache ROW_CACHE_b, and outputs a signal B to display the comparison result. When the second input row address matches the second error row address, signal B displays "same"; when the second input row address does not match the second error row address, signal B displays "different".

[0099] In step S703b_3, the error address cache ROW_CACHE_b can determine whether the first input row address and the second input row address match the first error row address and the second error row address according to predetermined logic. In some embodiments, the predetermined logic may correspond to an OR logic operation (i.e., the predetermined logic in Table 1 below). As shown in Figure 1, when both signals A and B output "different" results, the error address cache ROW_CACHE_b outputs a miss signal. Conversely, the error address cache ROW_CACHE_b outputs a hit signal.

[0100] Table 1: Pre-defined logic for determining whether a cache hit or misses an error address

[0101] Signal A Signal B Result Same Same Hit Same Not Same Hit Not Same Same Hit Not Same Not Same Miss

[0102] Figure 6A The error address cache ROW_CACHE_a and Figure 6B The error address cache ROW_CACHE_b in the memory can allow or block memory access based on a hit or miss signal and the memory die storing the error address cache ROW_CACHE. For example, the error address caches ROW_CACHE_a and ROW_CACHE_b in the spare die can allow memory access when a hit signal is output and block memory access when a miss signal is output. The error address caches ROW_CACHE_a and ROW_CACHE_b in the normal die Dx can block memory access when a hit signal is output and allow memory access when a miss signal is output. Controlling memory access based on the hit or miss signals of the error address caches ROW_CACHE_a and ROW_CACHE_b can be integrated with... Figure 4B and Figure 4C The process shown in the image is the same.

[0103] Figure 8is a flowchart illustrating a method of operating a memory device according to embodiments of the present application. The memory device can include a plurality of memory dies and a spare die stacked with each other, and each of the spare die and the memory dies can include an error address cache for recording error address information of the memory device. In step S810, the error address cache of the spare die or one of the memory dies receives an input address signal. In step S820, the error address cache of the spare die or one of the memory dies outputs a hit signal or a miss signal indicating whether the input address signal hits an error address stored in the error address cache. In step S830, access to the memory dies and the spare die is controlled according to the hit signal or the miss signal.

[0104] The memory device includes a spare die for repairing an error bank group, an error bank, and an error row of the memory dies of the memory device. In addition, the spare die can be selected after the memory device is packaged. Accordingly, a yield of manufacturing the memory device can be improved. In addition, each of the spare die and the memory dies of the memory device can include an error address cache for recording error bank group information, error bank information, and error row information of the memory device. When the error address cache of the spare die hits, the error address cache allows access to the memory by transmitting an input address signal and a command associated with the input address signal to the memory. When the error address cache of the spare die misses, the error address cache blocks access to the memory by blocking the input address signal and the command associated with the input address signal from being transmitted to the memory. When the error address cache of the normal die hits, the error address cache blocks access to the memory by blocking the input address signal and the command associated with the input address signal from being transmitted to the memory. When the error address cache of the normal die misses, the error address cache allows access to the memory by transmitting the input address signal and the command associated with the input address signal to the memory. Accordingly, the error bank group, the error bank, and / or the error row of the memory device can be effectively repaired.

[0105] While the present application has been disclosed in connection with the embodiments presented, it should be understood that certain modifications can be made to the present application and the foregoing description without departing from the spirit and scope of the application. Therefore, the scope of the application should be determined not with reference to the description, but should be given to the appended claims.

[0106] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A storage device, comprising: Multiple memory chips; as well as Spare dies are stacked onto the plurality of memory dies and configured to repair the target memory die between the plurality of memory dies. Each of the spare die and each of the plurality of memory dies includes an error address cache, which records the error address information of the storage device. The error address cache is used to receive the input address signal and output a hit signal or a miss signal. The hit signal or the miss signal indicates whether the input address signal hits an error address stored in the error address cache. The storage device is configured to control access to the plurality of memory chips and the spare chips based on the hit signal or the miss signal.

2. The storage device according to claim 1, characterized in that, In response to the error address cache of the spare die, the hit signal is output, the input address signal and the command associated with the input address signal are transmitted to the spare die of the storage device, and In response to the error address cache of the spare die, the miss signal is output, blocking the transmission of the input address signal and the command associated with the input address signal to the spare die of the storage device.

3. The storage device according to claim 1, characterized in that, In response to the erroneous address cache of the plurality of memory chips, the hit signal is output, blocking the transmission of the input address signal and the command associated with the input address signal to the plurality of memory chips of the storage device. In response to the error address cache of the plurality of memory chips, the miss signal is output, and the input address signal and the command associated with the input address signal are transmitted to the plurality of memory chips of the storage device.

4. The storage device according to claim 1, characterized in that, The fault address cache in each of the spare die and the plurality of memory dies includes: The repository group field is used to record information about the error repository group of the plurality of memory dies in each row of the error address cache; The correctness field is used to record the correctness status of each line in the erroneous address cache; The block identifier field is used to record the block identifier of the faulty memory block that includes the faulty repository group; The error repository group address field records the error repository group address of the error address cache in each row; and Replace the repository group address field to record the replacement repository group address used to replace the erroneous repository group in the error address cache for each row.

5. The storage device according to claim 1, characterized in that, The error address cache in each of the spare die and the plurality of memory dies includes: The Error Repository Address field is used to record the error repository address of the error repository in the error address cache for each row; The Replace Repository Address field is used to record the replacement repository address used to replace the erroneous repository in the error address cache for each row; The correctness field is used to record the correctness status of the cached address for each row; and The block identifier field is used to record the block identifier of the erroneous memory block that includes the erroneous repository.

6. The storage device according to claim 1, characterized in that, The error address cache in each of the spare die and the plurality of memory dies includes an error cache header field and an error line address field, wherein the error cache header field includes: The first correctness field is used to record the correctness status of the cache title; The block identifier field is used to record the block identifier of the erroneous memory block, including the address of the error bar; The repository group field is used to record the erroneous repository group, including the address of the erroneous line. The error line address field includes: A second correctness field is used to record the correctness status of the erroneous line address; and At least one multi-bit module is used to record the address of the error line.

7. The storage device according to claim 1, characterized in that, The erroneous address cache in each of the spare die and the plurality of memory dies includes: The index field is used to record the index value of the cached error address for each row; The error line address field records the error line address of each line whose error address is cached; and The correctness field is used to record the correctness status of the erroneous address cache in each row.

8. A method for operating a storage device, characterized in that, The storage device includes a plurality of memory dies stacked on top of each other and spare dies, each of the spare dies and the plurality of memory dies including an error address cache that records error address information of the storage device, the method comprising: The input address signal is received from the error address cache of the spare die or one of the plurality of memory dies; The error address cache of one of the spare die or the plurality of memory dies outputs a hit signal or a miss signal, the hit signal or the miss signal indicating whether the input address signal hits an error address stored in the error address cache; and Access to the plurality of memory dies and the spare die is controlled according to the hit signal or the miss signal.

9. The method according to claim 8, characterized in that, Also includes: When the hit signal is output in response to the error address cache of the spare die, the command associated with the input address signal is transmitted to the spare die of the storage device. as well as When the miss signal is output from the error address cache of the spare die, the transmission of the input address signal and the command associated with the input address signal to the spare die of the storage device is blocked.

10. The method according to claim 8, characterized in that, Also includes: In response to the error address cache outputting the hit signal of the plurality of memory chips, the transmission of the input address signal and the command associated with the input address signal block to the plurality of memory chips of the storage device is blocked. When the miss signal is output in response to the error address cache of the plurality of memory chips, the input address signal and the command associated with the input address signal block are transmitted to the plurality of memory chips of the storage device.

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