Test method and device, computer equipment and storage medium

Abstract

The invention discloses a test method and device, computer equipment and a storage medium. The method can comprise the steps that state detection is conducted on each SPI node in M SPI nodes; according to the state detection result of each SPI node, whether a first SPI node exists in the M SPI nodes or not is determined, the state detection result of the first SPI node is a first state detection result, and an SPI link formed by connecting the first SPI node and an SPI controller is a first SPI link; under the condition that a first SPI node exists in the M SPI nodes and a data sending port and a data receiving port of the SPI controller are connected, loopback testing is conducted on the SPI controller through the testing data, and a loopback testing result of the SPI controller is obtained; and determining a target test result of the first SPI link according to the loopback test result of the SPI controller. Automatic testing of the SPI link can be realized, so that the testing efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a testing method, apparatus, computer equipment, and storage medium. Background Technology

[0002] Serial Peripheral Interface (SPI) is a high-speed, full-duplex, synchronous serial communication protocol widely used for data transmission between microcontrollers and peripheral devices such as sensors and memory. SPI communication employs a master-slave architecture, typically consisting of one master device and one or more slave devices. A master device includes multiple SPI controllers, each connected to multiple slave devices via four signal lines for efficient communication. Each slave device corresponds to an independent SPI node in the system. The key advantages of SPI communication are that it eliminates the need for addressing, directly specifying the slave device via a chip select signal, and its high data transmission rate meets the demands of scenarios with high real-time requirements.

[0003] However, the reliability of SPI communication is highly dependent on the integrity of the hardware connection and the accuracy of the software configuration. Any deviation at the hardware or software level, such as hardware connection errors, can lead to SPI communication anomalies. SPI communication is a full-duplex synchronous data transmission protocol implemented through the SPI link. Therefore, how to test the SPI link is currently a hot research topic. Summary of the Invention

[0004] This application provides a testing method, apparatus, computer device, and storage medium that can automate the testing of SPI links, thereby improving testing efficiency.

[0005] In a first aspect, this application provides a testing method applied to a computer device, the computer device including an SPI device, the SPI device including an SPI controller, the SPI controller being connected to each of M SPI nodes through a data port, where M is a positive integer, the SPI controller and the SPI nodes forming an SPI link, the data port including a data transmission port and a data reception port, the method comprising: performing state detection on each of the M SPI nodes to obtain a state detection result for each SPI node, the state detection result being used to indicate the node state of the SPI node; determining, based on the state detection results of each SPI node, whether a first SPI node exists among the M SPI nodes, the state detection result of the first SPI node being a first state detection result, and the SPI link formed by the first SPI node and the SPI controller being a first SPI link; if a first SPI node exists among the M SPI nodes, and the data transmission port and data reception port of the SPI controller are connected, performing a loopback test on the SPI controller using test data to obtain a loopback test result for the SPI controller; and determining a target test result for the first SPI link based on the loopback test result of the SPI controller, the target test result including a first target test result and a second target test result.

[0006] As can be seen, status detection is performed on each of the M SPI nodes to obtain the status detection results for each SPI node. By accurately locating abnormal nodes, blind testing of the entire SPI system is avoided, allowing for rapid focus on potentially problematic nodes and significantly improving testing efficiency. Furthermore, loopback testing is only performed when a first SPI node with a status detection result matching the first status detection result is identified and the testing conditions are met, avoiding unnecessary testing operations, reducing testing time and resource consumption, and further improving testing efficiency.

[0007] In one possible implementation, the method may further include: determining the SPI node whose status detection result is a second status detection result as a second SPI node based on the status detection results of each SPI node, and the SPI link formed by the connection between the second SPI node and the SPI controller as a second SPI link; and directly determining the target test result of the second SPI link as a second target detection result based on the second status detection result of the second SPI node.

[0008] As can be seen, based on the status detection results of each SPI node, the second SPI node can be determined from M SPI nodes. By distinguishing the status detection results of different nodes and refining the test to the corresponding SPI link, the fault can be classified and located more accurately.

[0009] In one possible implementation, when a first SPI node exists among the M SPI nodes and the data transmit port and data receive port of the SPI controller are connected, performing a loopback test on the SPI controller using test data to obtain the loopback test result of the SPI controller may include: when a first SPI node exists among the M SPI nodes and the data transmit port and data receive port of the SPI controller are connected, controlling the SPI controller to send test data through the data transmit port of the SPI controller and receive data through the data receive port of the SPI controller to obtain the data to be verified; and obtaining the loopback test result of the SPI controller based on the test data and the data to be verified.

[0010] As can be seen, by directly comparing the test data and the data to be verified, it is possible to accurately detect whether errors, loss, or distortion have occurred in the data during transmission.

[0011] In one possible implementation, obtaining the loopback test result of the SPI controller based on the test data and the data to be verified may include: comparing the test data and the data to be verified to obtain a data comparison result; if the data comparison result indicates that the test data matches the data to be verified, the loopback test result of the SPI controller is obtained as the first loopback test result, which indicates that the loopback test was successful; if the data comparison result indicates that the test data does not match the data to be verified, the loopback test result of the SPI controller is obtained as the second loopback test result, which indicates that the loopback test failed.

[0012] As can be seen, the data comparison process directly compares the test data and the data to be verified bit by bit or as a whole, which can accurately detect whether there are any differences between the two. The loop closure test is considered successful only when the test data and the data to be verified are completely matched; if there is even one mismatch, the loop closure test is considered to have failed.

[0013] In one possible implementation, the method may further include: configuring test parameters for the SPI controller; constructing test data; wherein, when a first SPI node exists among the M SPI nodes and the data transmission port and data reception port of the SPI controller are connected, controlling the SPI controller to send test data through the data transmission port of the SPI controller may include: when a first SPI node exists among the M SPI nodes and the data transmission port and data reception port of the SPI controller are connected, controlling the SPI controller to send test data through the data transmission port of the SPI controller according to the configured test parameters.

[0014] As can be seen, different parameters can be configured according to actual hardware requirements, making the test closer to the actual application scenario and ensuring that the SPI controller can work normally on different hardware platforms.

[0015] In one possible implementation, the above test parameters include one or more of the following: SPI mode parameters, clock speed parameters, and bit width parameters.

[0016] It is evident that different hardware systems place varying requirements on the SPI controller, including operating modes, clock speeds, and data bit widths. By configuring multiple parameter combinations during testing, the SPI controller can be better adapted to various hardware environments. Comprehensive parameter testing ensures that the SPI controller can function correctly on different hardware platforms, improving the versatility and compatibility of SPI devices.

[0017] In one possible implementation, the above method may further include: generating a test report for the SPI controller based on the target test results of the first SPI link and the target test results of the second SPI link.

[0018] As can be seen, a test report for the SPI controller can be generated based on the target test results of the first SPI link and the target test results of the second SPI link. Testers can obtain the test results of the SPI controller from the test report, thereby classifying and locating faults.

[0019] In one possible implementation, the SPI device includes N SPI controllers, and there are multiple SPI controllers under test among the N SPI controllers, where N is a positive integer. Among the SPI nodes corresponding to the SPI controllers under test, there is a first SPI node. The method may also include: when the data transmission port and data reception port of each SPI controller under test are connected, using test data to perform parallel loopback tests on the multiple SPI controllers under test to obtain the loopback test results of each SPI controller under test.

[0020] As can be seen, parallel loopback testing can simultaneously obtain loopback test results from multiple SPI controllers under test. If an anomaly occurs in the test result of a controller, such as a data transmission error or response timeout, the faulty controller can be quickly located without having to troubleshoot each controller individually, thus improving testing efficiency.

[0021] Secondly, embodiments of this application provide a testing apparatus, which includes a detection unit, a testing unit, and a processing unit. The detection unit is used to perform state detection on each of the M SPI nodes, obtaining a state detection result for each SPI node. The state detection result indicates the node state of the SPI node, where M is a positive integer. The processing unit is used to determine, based on the state detection results of each SPI node, whether a first SPI node exists among the M SPI nodes. The state detection result of the first SPI node is a first state detection result, and the SPI link formed by the first SPI node and the SPI controller is a first SPI link. The testing unit is used to perform a loopback test on the SPI controller using test data when a first SPI node exists among the M SPI nodes and the data transmission port and data reception port of the SPI controller are connected, obtaining a loopback test result for the SPI controller. The processing unit is further used to determine a target test result for the first SPI link based on the loopback test result of the SPI controller. The target test result includes a first target test result and a second target test result.

[0022] In one possible implementation, the processing unit is further configured to determine the SPI node whose status detection result is the second status detection result as the second SPI node based on the status detection results of each SPI node, and the SPI link formed by the connection between the second SPI node and the SPI controller is the second SPI link; and to directly determine the target test result of the second SPI link as the second target detection result based on the second status detection result of the second SPI node.

[0023] In one possible implementation, the test unit is further configured to, when a first SPI node exists among the M SPI nodes and the data transmission port and data reception port of the SPI controller are connected, control the SPI controller to send test data through the data transmission port of the SPI controller and receive data through the data reception port of the SPI controller to obtain the data to be verified; and obtain the loopback test result of the SPI controller based on the test data and the data to be verified.

[0024] In one possible implementation, the test unit is further configured to compare the test data and the data to be verified to obtain a data comparison result; if the data comparison result indicates that the test data matches the data to be verified, the loopback test result of the SPI controller is obtained as the first loopback test result, which indicates that the loopback test was successful; if the data comparison result indicates that the test data does not match the data to be verified, the loopback test result of the SPI controller is obtained as the second loopback test result, which indicates that the loopback test failed.

[0025] In one possible implementation, the test unit is also used to configure test parameters for the SPI controller; construct test data; and, if a first SPI node exists among the M SPI nodes and the data transmission port and data reception port of the SPI controller are connected, control the SPI controller to send test data through the data transmission port of the SPI controller according to the configured test parameters.

[0026] In one possible implementation, the above test parameters include one or more of the following: SPI mode parameters, clock speed parameters, and bit width parameters.

[0027] In one possible implementation, the processing unit is further configured to generate a test report for the SPI controller based on the target test results of the first SPI link and the target test results of the second SPI link.

[0028] In one possible implementation, the aforementioned SPI device includes N SPI controllers, and among the N SPI controllers, there are multiple SPI controllers under test, where N is a positive integer. The SPI node corresponding to each SPI controller under test contains a first SPI node. The test unit is further configured to perform parallel loopback testing on the multiple SPI controllers under test using test data, with the data transmission and data reception ports of each SPI controller under test connected, to obtain the loopback test results for each SPI controller under test.

[0029] Thirdly, embodiments of this application provide an electronic device, which includes: a memory for storing a program; and a processor for executing the program stored in the memory. When the program is executed by the processor, the processor executes a method as described in any of the possible implementations of the first aspect.

[0030] Fourthly, embodiments of this application provide a computer storage medium storing a computer program, the computer program including program instructions, and when the program instructions are executed by a processor, the processor performs a method as described in the first aspect and any possible implementation thereof.

[0031] Fifthly, embodiments of this application provide a computer program product, which includes: instructions or a computer program; when the instructions or the computer program are executed, the method in the first aspect and any possible implementation of the first aspect is implemented.

[0032] Sixthly, embodiments of this application provide a chip, the chip including a processor, the processor being configured to execute instructions, such that when the processor executes the instructions, the chip performs the method as described in the first aspect and any possible implementation thereof. Attached Figure Description

[0033] Figure 1 A schematic diagram of an SPI communication system architecture provided for an embodiment of this application;

[0034] Figure 2 A schematic diagram of a system architecture provided for an embodiment of this application;

[0035] Figure 3 A flowchart illustrating a testing method provided in an embodiment of this application;

[0036] Figure 4 A flowchart illustrating another testing method provided in an embodiment of this application;

[0037] Figure 5 This is a schematic diagram of the structure of a testing device provided in an embodiment of this application;

[0038] Figure 6 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0039] The embodiments of this application will now be described with reference to the accompanying drawings.

[0040] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0041] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0042] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0043] The terms “component,” “module,” “system,” etc., used in this specification are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0044] First, some of the terms used in this application will be explained to facilitate understanding by those skilled in the art.

[0045] I. SPI Communication

[0046] SPI is a high-speed, full-duplex, synchronous serial communication protocol that is widely used for data transmission between microcontrollers and peripheral devices such as sensors and memory.

[0047] 1. SPI communication system

[0048] An SPI communication system typically consists of a master device and one or more slave devices.

[0049] The master device is the core initiator and controller of SPI communication, integrating multiple SPI controllers. The SPI controller acts as a "bridge" between the master and external slave devices. Each SPI controller has independent configuration and control capabilities, enabling it to independently manage communication tasks with different slave devices. For example, in a complex embedded system, the master device might be a high-performance microprocessor integrating four SPI controllers, each used to connect to different types of slave devices. Each SPI controller connects to multiple slave devices via four signal lines: Serial Clock (SCLK), Chip Select / Slave Select (CS / SS), Master Output / Slave Input (MOSI), and Master Input / Slave Output (MISO). SCLK provides a synchronization clock for data transmission; CS / SS is used by the master to select the slave device to communicate with; MOSI is used by the master to send data to the slave; and MISO is used by the slave to send data to the master. Through these functions, the SPI controller can precisely control the timing and method of data transmission with slave devices.

[0050] Slave devices are passive participants in SPI communication, receiving and sending data according to the master device's instructions. Slave devices come in various types, commonly including sensors, memory, and displays. Different types of slave devices play different roles in SPI communication, but all follow the SPI communication protocol for data interaction. Each slave device corresponds to an independent SPI node in the system. The master device activates a specific SPI node by selecting the corresponding chip select signal, thereby enabling communication with the corresponding slave device. SPI nodes are named SPI node XY, where X represents the index (or number) of the SPI controller in the master device, used to distinguish different SPI controllers; Y represents the channel number (or CS / SS number) of the slave device under the current SPI controller, used to distinguish different slave devices connected to the same SPI controller.

[0051] For example, such as Figure 1 As shown, Figure 1This is a schematic diagram of an SPI communication system architecture provided in an embodiment of this application. The SPI communication system consists of a master device and multiple slave devices. The master device integrates multiple SPI controllers, including SPI controller 1 (numbered 0), SPI controller 2 (numbered 1), ..., SPI controller x (numbered y). SPI controller 1 is connected to slave devices a (numbered 0) and b (numbered 1) via four signal lines; SPI controller 2 is connected to slave device c (numbered 0) via four signal lines; and SPI controller x is connected to slave devices d (numbered 0) and e (numbered 1) via four signal lines.

[0052] The SPI node corresponding to device a is SPI node 0.0; the SPI node corresponding to device b is SPI node 0.1; the SPI node corresponding to device c is SPI node 1.0; the SPI node corresponding to device d is SPI node y.0; and the SPI node corresponding to device e is SPI node y.1.

[0053] 2. SPI Communication Process

[0054] During the initialization phase, the master device first initializes and configures each SPI controller, including setting parameters such as clock frequency, clock polarity and phase, and data bits. These parameters need to be set according to the requirements of the connected slave devices to ensure that the master and slave devices can communicate correctly. Simultaneously, the master device sets the CS / SS of all slave devices to a high level, thus deselecting all slave devices.

[0055] When a master device needs to communicate with a slave device, it sets the CS / SS of the slave device to a low level, thus selecting the slave device. At this time, a communication connection is established between the master device and the selected slave device.

[0056] During the data transmission phase, the master device's SPI controller begins generating an SCLK. Within each clock cycle, the master device sends one bit of data to the selected slave device via the MOSI line, while the slave device simultaneously sends one bit of data back to the master via the MISO line. Data is transmitted bit by bit, driven by the clock signal, until the transmission of a byte or word is complete. For example, if the data bit width is set to 8 bits, the master and slave devices will complete the transmission of one byte within 8 clock cycles.

[0057] After data transmission is complete, the master device sets the CS / SS of the corresponding slave device to a high level, cancels the selection of the slave device, and ends the communication.

[0058] 3. SPI communication mode

[0059] SPI communication has four different modes, determined by two parameters: clock polarity (CPOL) and clock phase (CPHA).

[0060] In Mode 0 (CPOL=0, CPHA=0), the clock signal is low in the idle state, and data is sampled on the first rising edge of the clock signal and changes on the second rising edge. That is, when there is no data transmission, the clock signal remains low, and data is read or written when the clock signal changes from low to high (rising edge).

[0061] In Mode 1 (CPOL=0, CPHA=1), the clock signal is low in the idle state, and data is sampled on the first falling edge of the clock signal and changes on the second falling edge. That is, when there is no data transmission, the clock signal remains low, and data is read or written when the clock signal changes from high to low (falling edge).

[0062] In Mode 2 (CPOL=1, CPHA=0), the clock signal is high in the idle state, and data is sampled on the first falling edge of the clock signal and changes on the second falling edge. That is, when there is no data transmission, the clock signal remains high, and data is read or written when the clock signal changes from high to low (falling edge).

[0063] In Mode 3 (CPOL=1, CPHA=1), the clock signal is high in the idle state, and data is sampled on the first rising edge of the clock signal and changes on the second rising edge. That is, when there is no data transmission, the clock signal remains high, and data is read or written when the clock signal changes from low to high (rising edge).

[0064] It is important to note that the master and slave devices must use the same communication mode for normal data transmission. By appropriately selecting the SPI mode, clock synchronization and reliable data transmission between the master and slave devices can be ensured, thereby meeting the needs of different application scenarios.

[0065] 4. Characteristics of SPI communication

[0066] SPI communication uses a synchronous clock signal for data transmission, and the clock frequency can be set quite high, enabling high-speed data transmission. This is a significant advantage for applications requiring real-time transmission of large amounts of data, such as video data transmission and high-speed sensor data acquisition. For example, in some high-performance embedded systems, SPI communication clock frequencies can reach tens of megahertz or even higher, enabling the transmission of large amounts of data in a short time. SPI also supports full-duplex communication, meaning that the master and slave devices can simultaneously send and receive data. This communication method improves data transmission efficiency and reduces communication time.

[0067] Meanwhile, in SPI communication, the master device can communicate with multiple slave devices simultaneously through multiple SPI controllers, and the parameters of each SPI controller can be flexibly configured as needed to adapt to the requirements of different slave devices. This flexibility enables SPI communication to be widely used in various application scenarios. For example, in a smart home system, the master device can connect to multiple slave devices such as temperature sensors, humidity sensors, and light sensors through different SPI controllers to achieve real-time monitoring and control of the indoor environment.

[0068] However, because SPI communication involves strict timing coordination of multiple signals (SCLK, MOSI, MISO, CS / SS), any deviation at the hardware or software level can lead to SPI communication anomalies. SPI communication is a full-duplex synchronous data transmission protocol implemented through the SPI link. Therefore, how to test the SPI link is currently a hot research topic. An inadequately tested SPI link may cause data loss, system crashes, or even equipment damage during SPI communication, with potentially disastrous consequences, especially in safety-critical fields such as medical and aerospace.

[0069] In view of this, embodiments of this application provide a testing method, apparatus, computer equipment, and storage medium that can automatically detect the status of all SPI nodes in the system and automatically perform loopback testing on the SPI controller containing the first SPI node, thereby improving testing efficiency. Furthermore, it clearly distinguishes between node status issues and data transmission errors of SPI nodes, preventing testers from wasting time on the wrong things. At the same time, the final test report includes clear error information, enabling testers to understand the essence of the problem more quickly and take targeted measures.

[0070] The following describes a system architecture applicable to the embodiments of this application.

[0071] Please see Figure 2 , Figure 2 This is a schematic diagram of a system architecture provided for an embodiment of this application. Figure 2As shown, the system architecture includes a first device 101 and a second device 102, with the second device 102 including an SPI device 103. The SPI device 103 can be the master device in the aforementioned SPI communication system, and the first device 101 and the second device 102 can communicate via wired or wireless means. The number of first devices 101, second devices 102, and SPI devices 103 are for illustrative purposes only and do not constitute a limitation on the embodiments of this application.

[0072] The first device 101 can be a device used by an object, such as a developer, test engineer, network security engineer, operations and maintenance personnel, or product manager. The first device 101 can be a smartphone, tablet, smart wearable device, smart voice interaction device, smart home appliance, personal computer, in-vehicle terminal, embedded development board, virtual machine, virtual reality device (such as augmented reality (AR) device), etc., and this application does not limit it.

[0073] The second device 102 includes an SPI device 103, which may be a computer device. The SPI device 103 includes one or more SPI controllers. Each SPI controller can be connected to each of the one or more SPI nodes through a data port. The connection between the SPI controller and the SPI node forms an SPI link. The data port includes a clock signal port, a chip select signal port, a data transmit port, and a data receive port.

[0074] In this embodiment, the first device 101 can send a test request message to the second device 102. The second device 102 responds to the test request message sent by the first device 101, performs status checks on all SPI nodes in the system, and performs a loopback test on the SPI controller containing the first SPI node, provided that the data transmission port and data reception port of the SPI controller are connected. Based on the status check results of all SPI nodes and the loopback test results of the SPI controller containing the first SPI node, a test report is generated. The second device 102 then sends the generated test report to the first device 101.

[0075] The test methods provided in the embodiments of this application are described below.

[0076] Please see Figure 3 , Figure 3This is a flowchart illustrating a testing method provided in an embodiment of this application. The testing method can be applied to a second device 102, which includes an SPI device 103, and the SPI device 103 includes an SPI controller. In this embodiment, the SPI device 103 includes an SPI controller as an example. This SPI controller can be connected to each of M SPI nodes through a data port, where M is a positive integer.

[0077] like Figure 3 As shown, the testing method may include, but is not limited to, the following steps:

[0078] S301, perform status detection on each of the M SPI nodes and obtain the status detection results of each SPI node.

[0079] In Linux systems, SPI devices typically interact with user space through SPI device files. These SPI device files are located in the " / dev" directory, follow specific naming rules, and are dynamically created by the SPI driver in the kernel. The naming format for SPI device files is typically "spidev". <bus> . <chipselect> ”。" <bus>Number the SPI controller (starting from 0); <chipselect>" represents the chip select signal number (starting from 0). For example, "spidev0.0" is the 0th chip select device corresponding to the SPI controller with number 0; "spidev1.1" is the 1st chip select device corresponding to the SPI controller with number 1.

[0080] In one possible implementation, a program can automatically scan the " / dev" directory to identify M SPI nodes that match the naming format of the SPI device files. Each of the M SPI nodes undergoes a status check, yielding a status check result. This result indicates the node's state and includes a first status check result and a second status check result. The first result indicates a normal node state, while the second result indicates an abnormal node state. Reasons for an abnormal node state might include driver not being loaded, device not being registered, hardware connection failure, etc.

[0081] In one possible implementation, a node status detection function can be called to perform status checks on each of the M SPI nodes and obtain the status detection results for each SPI node. For example, the node status detection function could be either the access() function or the stat() function.

[0082] The `access()` function can be used to check the current process's access permissions (existence, readability, writeability, etc.) to a specified SPI device file. The return value of `access()` provides the status detection result of the SPI node corresponding to the specified SPI device file. If the return value of `access()` is "0", it indicates that the status detection result of the SPI node corresponding to the specified SPI device file is the first status detection result, meaning the SPI node's status is normal, and it is marked as the first SPI node. If the return value of `access()` is "-1", it indicates that the status detection result of the SPI node corresponding to the specified SPI device file is the second status detection result, meaning the SPI node's status is abnormal, and it is marked as the second SPI node.

[0083] The `stat()` function retrieves detailed information about a specified SPI device file (such as size, permissions, and type), and indirectly determines whether the SPI device file exists, thus obtaining the status detection result of the SPI node corresponding to the SPI device file. If the `stat()` function returns "0", it indicates that the status detection result of the SPI node corresponding to the specified SPI device file is the first status detection result, meaning the SPI node's status is normal, and the SPI node is marked as the first SPI node. If the `stat()` function returns "-1", it indicates that the status detection result of the SPI node corresponding to the specified SPI device file is the second status detection result, meaning the SPI node's status is abnormal, and the SPI node is marked as the second SPI node.

[0084] S302, based on the status detection results of each SPI node, determine whether the first SPI node exists among the M SPI nodes.

[0085] In this system, the status detection result of the first SPI node is the first status detection result, and the SPI link formed by the connection between the first SPI node and the SPI controller is the first SPI link. The first status detection result is used to indicate that the node status of the SPI node is normal. Based on the status detection results of each SPI node, it is determined whether there is a first SPI node among the M SPI nodes whose status detection result is the first status detection result, that is, it is determined whether there is an SPI node among the M SPI nodes whose node status is normal.

[0086] In one possible implementation, the return value of the node status detection function of each SPI device file can be used to determine whether there exists a first SPI node among the M SPI nodes with a first status detection result. The SPI node corresponding to the SPI device file whose node status detection function returns "0" is marked as the first SPI node.

[0087] S303: When there is a first SPI node among M SPI nodes, and the data transmission port and data reception port of the SPI controller are connected, a loopback test is performed on the SPI controller using test data to obtain the loopback test result of the SPI controller.

[0088] In one possible implementation, where a first SPI node exists among M SPI nodes, and the data transmit and data receive ports of the SPI controller are connected, the SPI controller is controlled to send test data through its data transmit port and receive data through its data receive port to obtain the data to be verified. Based on the test data and the data to be verified, the loopback test result of the SPI controller is obtained.

[0089] Loopback testing is a method to verify the integrity of a device's internal functions by directly feeding back the device's output signal to its input. In SPI communication, loopback testing can detect the correctness of the SPI controller, bus, or driver without requiring external devices.

[0090] In one possible implementation, a controllable connection line, such as the analog switch chip TS3A24159, is added between the data transmit and receive ports of the SPI controller. This connection line is driven by a control signal (Loopback_En), which switches between high and low levels to physically connect and disconnect the data. When Loopback_En = 0, the controllable connection line between the data transmit and receive ports of the SPI controller is disconnected, entering normal communication mode. When Loopback_En = 1, the data transmit and receive ports of the SPI controller are connected via the controllable connection line, entering loopback test mode. This automates the testing process and improves testing efficiency.

[0091] In one possible implementation, if a first SPI node exists among the M SPI nodes, the control signal (Loopback_En) is set to "1" to establish a connection between the data transmit and receive ports of the SPI controller, entering loopback test mode. It is also ensured that the clock signal and chip select signal are in normal working order; specifically, the chip select signal corresponding to the first SPI node must be set to low to activate communication.

[0092] Configure test parameters for the SPI controller, including one or more of the following: SPI mode parameters, clock speed parameters, and bit width parameters. The SPI mode parameters are determined by the combination of clock polarity (CPOL) and clock phase (CPHA), with a total of four modes. You can choose to test one mode or iterate through all four modes to verify data consistency. The clock speed parameter determines the SPI communication transmission rate and must not exceed the SPI controller's maximum clock frequency. For example, the maximum clock speed of STM32 SPI1 is 54MHz. At high clock speeds, factors such as bus length, impedance matching, and noise suppression must be considered. The default bit width parameter is 8 bits, but some SPI controllers support non-standard bit widths (such as 4 bits, 16 bits, and 32 bits). Consult the SPI controller's datasheet to confirm the supported bit width range.

[0093] Next, based on the actual situation, test data is constructed. Test data can be fixed data, random data, increasing or decreasing sequences, etc. With the data transmit and receive ports of the SPI controller connected, the SPI controller is controlled to send test data through its data transmit port according to the configured test parameters, and the data in the receive buffer is received through its data receive port to obtain the data to be verified.

[0094] In one possible implementation, with the SPI controller's data transmit and receive ports connected, a full-duplex SPI transmission can be initiated by calling the `ioctl(SPI_IOC_MESSAGE(N))` function or a specific SPI library function. Full-duplex SPI transmission is a communication mode that simultaneously supports bidirectional data exchange between master and slave devices. Initiating a full-duplex SPI transmission with the SPI controller's data transmit and receive ports connected verifies whether the SPI controller can correctly send and receive data without relying on an external slave device. The test data sent by the SPI controller from its data transmit port is directly transmitted back to the SPI controller's data receive port via a jumper wire, obtaining the data to be verified and forming an internal data loop. In this case, the SPI controller acts as both the sender and receiver.

[0095] After obtaining the data to be verified, the loopback test results of the SPI controller can be obtained based on the test data and the data to be verified, thereby verifying whether the full-duplex communication function of the SPI controller is normal.

[0096] In one possible implementation, the test data and the data to be verified are compared byte by byte to obtain the comparison result. If the comparison result indicates that the test data matches the data to be verified, the loopback test result of the SPI controller is obtained as the first loopback test result, indicating that the loopback test was successful. If the comparison result indicates that the test data does not match the data to be verified, the loopback test result of the SPI controller is obtained as the second loopback test result, indicating that the loopback test failed.

[0097] Understandably, if the first SPI node is not present among the M SPI nodes, then there is no need to perform a loopback test on the SPI controller.

[0098] For example, the SPI controller can connect to each of the three SPI nodes via a data port. The SPI controller is numbered 0, and the three SPI nodes are SPI node 0.0, SPI node 0.1, and SPI node 0.2. Status detection is performed on each of the three SPI nodes. The status detection result of SPI node 0.0 is taken as the second status detection result, and SPI node 0.0 is marked as the second SPI node. The status detection result of SPI node 0.1 is taken as the second status detection result, and SPI node 0.1 is marked as the second SPI node. The status detection result of SPI node 0.2 is taken as the first status detection result, and SPI node 0.2 is marked as the first SPI node.

[0099] Since there is a first SPI node, namely SPI node 0.2, among SPI nodes 0.0, SPI node 0.1 and SPI node 0.2, a loopback test is required for the SPI controller.

[0100] It is understandable that if there is no first SPI node among SPI nodes 0.0, SPI nodes 0.1 and SPI nodes 0.2, that is, if the status detection results of the three SPI nodes are all second status detection results, then there is no need to perform loopback testing on the SPI controller.

[0101] When performing a loopback test on the SPI controller corresponding to SPI node 0.2 (i.e., the SPI controller numbered 0), it is necessary to first connect the data transmit port and data receive port of the SPI controller, and ensure that the clock signal and chip select signal are in normal working condition. Specifically, the chip select signal corresponding to SPI node 0.2 in the SPI controller must be set to a low level to activate communication. Next, configure the test parameters for the SPI controller and construct test data. With the data transmit port and data receive port of the SPI controller connected, control the SPI controller to send test data through the data transmit port according to the configured test parameters, and receive the data in the receive buffer through the data receive port of the SPI controller to obtain the data to be verified.

[0102] The test data can be set to "0x3A,0x7F,0x1C,0x92". If the data to be verified received by the SPI controller is "0x3A,0x7F,0x1C,0x92", the test data and the data to be verified are compared byte by byte to obtain the comparison result. If the comparison result indicates that the test data and the data to be verified match, then the SPI controller's loopback test result is the first loopback test result, indicating that the loopback test was successful. If the data to be verified is "0x3A,0x00,0x1C,0x92", the test data and the data to be verified are compared byte by byte to obtain the comparison result. If the comparison result indicates that the test data and the data to be verified do not match, and the second byte in the data to be verified is different from the second byte in the test data, then the SPI controller's loopback test result is the second loopback test result, indicating that the loopback test failed.

[0103] S304, determine the target test result of the first SPI link based on the loopback test result of the SPI controller.

[0104] The target test results include a first target test result and a second target test result. The first target test result indicates that the SPI link test result is normal, and the second target test result indicates that the SPI link test result is abnormal. The first SPI link is the SPI link formed by the connection between the SPI controller and the first SPI node.

[0105] The loopback test result of the SPI controller is the first loopback test result, meaning the target test result of the first SPI link is the first target test result. In this case, the first target test result indicates that the first SPI link test result is normal. The reason for the normal first SPI link test result is that the node status is normal and the loopback test is successful. The loopback test result of the SPI controller is the second loopback test result, meaning the target test result of the first SPI link is the second target test result. In this case, the second target test result indicates that the first SPI link test result is abnormal. The reason for the abnormal first SPI link test result is that the node status is normal, but the loopback test failed.

[0106] In one possible implementation, based on the status detection results of each SPI node, the SPI node whose status detection result is a second status detection result is identified as the second SPI node, and the SPI link formed by the connection between the second SPI node and the SPI controller is identified as the second SPI link. The target test result of the second SPI link can be directly determined as the second target test result based on the second status detection result of the second SPI node. Here, the second status detection result indicates that the node status of the SPI node is abnormal. The target test result of the second SPI link can also be directly determined as the second target test result based on the second status detection result of the second SPI node; in this case, the second target test result indicates that the test result of the second SPI link is abnormal. The reason for the abnormal test result of the second SPI link is an abnormal node status.

[0107] In one possible implementation, a test report for the SPI controller can be generated based on the target test results of the first SPI link and the target test results of the second SPI link. The SPI controller test report includes the target test results of each SPI link formed by the connection between the SPI controller and its corresponding SPI nodes, as well as the reasons for the formation of the target test results for each SPI link. Testers can obtain the test results of the SPI controller from the test report, thereby classifying and locating faults.

[0108] In one possible implementation, the SPI device may include N SPI controllers, and among these N SPI controllers are multiple SPI controllers under test, where N is a positive integer. Each SPI controller under test has multiple first SPI nodes within its corresponding SPI node. With the data transmit and receive ports of each SPI controller under test connected, parallel loopback testing is performed on the multiple SPI controllers under test using test data to obtain the loopback test results for each controller. This parallel loopback testing allows for the simultaneous acquisition of loopback test results from multiple SPI controllers under test, improving testing efficiency.

[0109] Based on the loopback test results of each SPI controller under test, the target test result for each first SPI link is determined. Each first SPI link is an SPI link formed by connecting each SPI controller to its corresponding first SPI node. Based on the status detection results of all SPI nodes corresponding to N SPI controllers, the SPI node with a second status detection result is identified as the second SPI node. Then, based on the second status detection result of the second SPI node, the target test result for the second SPI link is directly determined as the second target test result. The second SPI link is an SPI link formed by connecting the second SPI node to its corresponding SPI controller.

[0110] For example, the SPI device includes three SPI controllers: SPI controller 1, numbered 0, corresponds to SPI node 0.0; SPI controller 2, numbered 1, corresponds to SPI nodes 1.0 and 1.1; and SPI controller 3, numbered 2, corresponds to SPI node 2.0.

[0111] The status of each of the four SPI nodes is detected, and the status detection results of SPI node 0.0, SPI node 1.0, SPI node 1.1, and SPI node 2.0 are determined as the first SPI node. From these four SPI nodes, SPI node 0.0, SPI node 1.0, and SPI node 2.0 are identified as the first SPI node, and SPI node 1.1 is identified as the second SPI node.

[0112] Based on the second state detection result of SPI node 1.1, the target test result of the second SPI link can be directly determined as the second target test result. In this case, the second target test result indicates that the second SPI link test result is abnormal. The reason for the abnormal second SPI link test result is an abnormal node state. The second SPI link is the SPI link formed by the connection between SPI node 1.1 and SPI controller 2.

[0113] Based on the first state detection results of SPI nodes 0.0, 1.0, and 2.0, SPI controllers 1, 2, and 3 are identified as the SPI controllers under test. With the data transmission and reception ports of each SPI controller connected, parallel loopback tests are performed on each SPI controller using test data (0x3A, 0x7F, 0x1C, 0x92). The loopback test result of SPI controller 1 is the first loopback test result, the loopback test result of SPI controller 2 is the second loopback test result, and the loopback test result of SPI controller 3 is the third loopback test result. Specifically, the data to be verified received by SPI controller 1 is "0x3A, 0x7F, 0x1C, 0x92", the data to be verified received by SPI controller 2 is "0x3A, 0x7F, 0x1C, 0x00", and the data to be checked received by SPI controller 3 is "0xFF, 0xFF, 0xFF, 0xFF".

[0114] Based on the loopback test results of SPI controller 1, the target test result for the first SPI link 1 is determined as the first target test result. This first target test result indicates that the first SPI link 1 test result is normal. The reason for the normal test result of the first SPI link 1 is that the node status is normal and the loopback test is successful. Based on the loopback test results of SPI controller 2, the target test result for the first SPI link 2 is determined as the second target test result. This second target test result indicates that the first SPI link 2 test result is abnormal. The reason for the abnormal test result of the first SPI link 2 is that the node status is normal, but the loopback test failed. Based on the loopback test results of SPI controller 3, the target test result for the first SPI link 3 is determined as the second target test result. This second target test result indicates that the first SPI link 3 test result is abnormal. The reason for the abnormal test result of the first SPI link 3 is that the node status is normal, but the loopback test failed. Here, the first SPI link 1 is the SPI link formed by connecting SPI controller 1 and SPI node 0.0; the first SPI link 2 is the SPI link formed by connecting SPI controller 2 and SPI node 1.0; and the first SPI link 3 is the SPI link formed by connecting SPI controller 3 and SPI node 2.0.

[0115] Finally, a test report for the SPI controller can be generated based on the target test results of the first SPI link 1, the first SPI link 2, the first SPI link 3, and the second SPI link.

[0116] The test report is as follows:

[0117] SPI Node 0.0 (First SPI Link 1): First target test result, that is, the test result is normal and the test data is completely consistent with the data to be verified;

[0118] The test results are normal because the node status is normal and the loopback test was successful.

[0119] SPI Node 1.0 (First SPI Link 2): Second target test result, i.e. test result abnormal, the 4th byte of the data to be verified is incorrect (0x92 sent, 0x00 received);

[0120] The reason for the abnormal test results is that the node status is normal, but the loopback test failed (data error).

[0121] SPI Node 1.1 (Second SPI Link): Second target test result, i.e., test result is abnormal, node status is abnormal;

[0122] The abnormal test results were due to an abnormal node status.

[0123] SPI Node 2.0 (First SPI Link 3): Second target test result, i.e., test result is abnormal, all data to be verified is 0xFF;

[0124] The reason for the abnormal test results is that the node status is normal, but the loopback test failed (invalid data).

[0125] According to the test report, SPI controller 1 corresponding to SPI node 0.0 is normal and can be used normally. The loopback test for SPI controller 2 corresponding to SPI node 1.0 failed, and the 4th byte of the received verification data was incorrect. This may be due to issues such as SPI mode mismatch, incorrect clock speed parameters, or improper chip select signal control. SPI node 1.1 has an abnormal node status, which may be due to issues such as driver not being loaded, device not being registered, or hardware connection failure. The loopback test for SPI controller 2 corresponding to SPI node 2.0 failed, and all received verification data was 0xFF. This may be due to issues such as incorrect shorting of MOSI and MISO on SPI controller 2, SPI controller 2 not being enabled or misconfigured, or level mismatch.

[0126] As can be seen, by implementing the testing method provided in this application, the program automatically locates SPI nodes, executes tests, compares results, and generates reports, eliminating the need for manual input of complex commands. This eliminates the tedious and time-consuming steps of manually entering commands one by one, waiting for responses, and recording results, compressing what might have taken minutes or even tens of minutes of manual testing into seconds. It avoids test failures or false alarms caused by incorrect manual input, omitted test steps, or misjudgments, improving the accuracy and reliability of the tests. Furthermore, it clearly distinguishes between node status issues and data transmission errors, enabling developers or maintenance personnel to more quickly understand the nature of the problem and take targeted measures.

[0127] Please see Figure 4 , Figure 4 This is a flowchart illustrating another testing method provided in an embodiment of this application. This testing method can be applied to a second device 102, which includes an SPI device 103 and an SPI controller.

[0128] like Figure 4 As shown, the testing method may include, but is not limited to, the following steps:

[0129] S401, obtain P SPI nodes.

[0130] In this embodiment, the program automatically scans the " / dev" directory to identify P SPI nodes that match the naming format of the SPI device files. Here, P is a positive integer, and the P SPI nodes can correspond to the same SPI controller or to different SPI controllers.

[0131] S402, perform status detection on each of the P SPI nodes and obtain the status detection results of each SPI node.

[0132] In this embodiment, a node status detection function can be invoked to perform status detection on each of the P SPI nodes, obtaining the status detection result for each SPI node. The status detection result indicates the node status of the SPI node, and includes a first status detection result and a second status detection result. The first status detection result indicates that the node status of the SPI node is normal, and the second status detection result indicates that the node status of the SPI node is abnormal.

[0133] The node status detection function can be the `access()` function; alternatively, it can also be the `stat()` function. Based on the return value of the node status detection function, the status detection results of each SPI node are obtained.

[0134] S403, Is the state detection result the same as the first state detection result?

[0135] In this embodiment, if the node status detection function returns "0", it means that the status detection result of the SPI node corresponding to the specified SPI device file is the first status detection result, that is, the node status of the SPI node is normal; if the node status detection function returns "-1", it means that the status detection result of the SPI node corresponding to the specified SPI device file is the second status detection result, that is, the node status of the SPI node is abnormal.

[0136] S404 is marked as the first SPI node.

[0137] In this embodiment of the application, if the state detection result of the SPI node is the first state detection result, the SPI node is marked as the first SPI node.

[0138] The number of first SPI nodes can be one or more. When there are multiple first SPI nodes, the SPI controller corresponding to each first SPI node can be the same; alternatively, the SPI controller corresponding to each first SPI node can be a different SPI controller.

[0139] S405 is marked as the second SPI node.

[0140] In this embodiment of the application, if the state detection result of the SPI node is not the first state detection result, then the state detection result of the SPI node is the second state detection result, and the SPI node is marked as the second SPI node.

[0141] The number of second SPI nodes can be one or more. When there are multiple second SPI nodes, the SPI controller corresponding to each second SPI node can be the same; alternatively, the SPI controller corresponding to each second SPI node can also be a different SPI controller.

[0142] S406, the target test result of the second SPI link is directly determined as the second target test result based on the second state detection result of the second SPI node.

[0143] In this embodiment, the second SPI link is the SPI link formed by connecting the SPI controller corresponding to the second SPI node and the second SPI node. Based on the second state detection result of the second SPI node, the target test result of the second SPI link can be directly determined as the second target test result. In this case, the second target test result is used to indicate that the second SPI link test result is abnormal. The reason for the abnormal second SPI link test result is an abnormal node state.

[0144] For example, if the second SPI node includes SPI node 1.1 and SPI node 2.1, then the SPI controllers corresponding to these two second SPI nodes are different SPI controllers. Specifically, the SPI controller corresponding to SPI node 1.1 is the SPI controller numbered 1, and the SPI controller corresponding to SPI node 2.1 is the SPI controller numbered 2.

[0145] Based on the second state detection result of SPI node 1.1, the target test result of the second SPI link 1 is directly determined as the second target test result. In this case, the second target test result indicates that the test result of the second SPI link 1 is abnormal. The reason for the abnormal test result of the second SPI link 1 is an abnormal node state. Based on the second state detection result of SPI node 2.1, the target test result of the second SPI link 2 is directly determined as the second target test result. In this case, the second target test result indicates that the test result of the second SPI link 2 is abnormal. The reason for the abnormal test result of the second SPI link 2 is an abnormal node state. Specifically, the second SPI link 1 is the SPI link formed by connecting the SPI controller numbered 1 with SPI node 1.1; the second SPI link 2 is the SPI link formed by connecting the SPI controller numbered 2 with SPI node 2.1.

[0146] S407, with the data transmission port and data reception port of the SPI controller corresponding to the first SPI node connected, a loopback test is performed on the SPI controller corresponding to the first SPI node using test data to obtain the loopback test result of the SPI controller corresponding to the first SPI node.

[0147] In this embodiment, when a first SPI node exists among the P SPI nodes, and the data transmission port and data reception port of the SPI controller corresponding to the first SPI node are connected, test parameters are configured, test data is constructed, and the SPI controller corresponding to the first SPI node is controlled to send the test data through the data transmission port of the SPI controller corresponding to the first SPI node according to the configured test parameters. Data is then received through the data reception port of the SPI controller corresponding to the first SPI node to obtain the data to be verified. Based on the test data and the data to be verified, the loopback test result of the SPI controller corresponding to the first SPI node is obtained.

[0148] For example, among the P SPI nodes, there are two first SPI nodes, namely SPI node 1.0 and SPI node 2.0. Connect the data transmit port and data receive port of the SPI controller with number 1 corresponding to SPI node 1.0, and connect the data transmit port and data receive port of the SPI controller with number 2 corresponding to SPI node 2.

[0149] Configure test parameters and construct test data. Control SPI controller number 1 to send test data through its data transmission port according to the configured test parameters. Simultaneously, control SPI controller number 2 to send test data through its data transmission port according to the configured test parameters. Data is received through the data reception ports of both SPI controllers number 1 and number 2 to obtain the data to be verified for SPI controller number 1 and number 2, respectively. Based on the test data and the data to be verified, obtain the loopback test results for SPI controller number 1 and number 2.

[0150] S408, determine the target test result of the first SPI link based on the loopback test result of the SPI controller corresponding to the first SPI node.

[0151] In this embodiment, the target test result includes a first target test result and a second target test result. The first SPI link is an SPI link formed by connecting the first SPI node and the SPI controller corresponding to the first SPI node. If the loopback test result of the SPI controller corresponding to the first SPI node is the first loopback test result, indicating that the loopback test was successful, then the target test result of the first SPI link is the first target test result. In this case, the first target test result is used to indicate that the first SPI link test result is normal. The reason for the first SPI link test result being normal is that the node status is normal and the loopback test was successful. If the loopback test result of the SPI controller corresponding to the first SPI node is the second loopback test result, indicating that the loopback test failed, then the target test result of the first SPI link is the second target test result. In this case, the second target test result is used to indicate that the first SPI link test result is abnormal. The reason for the first SPI link test result being abnormal is that the node status is normal, but the loopback test failed.

[0152] S409, Based on the target test results of the first SPI link and the target test results of the second SPI link, generate a test report for the SPI controller.

[0153] In this embodiment, test reports for each SPI link formed by connecting each SPI controller and its corresponding SPI nodes can be generated based on the target test results of the first SPI link and the target test results of the second SPI link. The test reports may include the target test results for each SPI link and the reasons for those results.

[0154] As can be seen, the testing method provided in this application can automatically acquire all SPI nodes in the system, eliminating the risk of missing some nodes during manual inspection. Status detection is performed on all SPI nodes, and loopback testing is only performed on the SPI controllers corresponding to SPI nodes in a normal state. Loopback testing is not performed on the SPI controllers corresponding to SPI nodes in an abnormal state, thus improving testing efficiency.

[0155] The testing apparatus provided in the embodiments of this application is described below.

[0156] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a testing device provided in an embodiment of this application. The testing device 500 may include a detection unit 510, a processing unit 520, and a testing unit 530.

[0157] The detection unit 510 is used to perform status detection on each of the M SPI nodes and obtain the status detection result of each SPI node. The status detection result is used to indicate the node status of the SPI node, where M is a positive integer.

[0158] The processing unit 520 is used to determine whether a first SPI node exists among the M SPI nodes based on the status detection results of each SPI node. The status detection result of the first SPI node is the first status detection result, and the SPI link formed by the connection between the first SPI node and the SPI controller is the first SPI link.

[0159] Test unit 530 is used to perform a loopback test on the SPI controller using test data when the first SPI node exists among M SPI nodes and the data transmission port and data reception port of the SPI controller are connected, and to obtain the loopback test result of the SPI controller.

[0160] The processing unit 520 is also used to determine the target test result of the first SPI link based on the loopback test result of the SPI controller. The target test result includes the first target test result and the second target test result.

[0161] In one possible implementation, the processing unit 520 is further configured to determine the SPI node whose status detection result is the second status detection result as the second SPI node based on the status detection results of each SPI node, and the SPI link formed by the connection between the second SPI node and the SPI controller is the second SPI link; and to directly determine the target test result of the second SPI link as the second target detection result based on the second status detection result of the second SPI node.

[0162] In one possible implementation, the test unit 530 is further configured to, when a first SPI node exists among the M SPI nodes and the data transmission port and data reception port of the SPI controller are connected, control the SPI controller to send test data through the data transmission port of the SPI controller and receive data through the data reception port of the SPI controller to obtain the data to be verified; and obtain the loopback test result of the SPI controller based on the test data and the data to be verified.

[0163] In one possible implementation, the test unit 530 is further configured to compare the test data and the data to be verified to obtain a data comparison result; if the data comparison result indicates that the test data matches the data to be verified, the loopback test result of the SPI controller is obtained as the first loopback test result, which indicates that the loopback test was successful; if the data comparison result indicates that the test data does not match the data to be verified, the loopback test result of the SPI controller is obtained as the second loopback test result, which indicates that the loopback test failed.

[0164] In one possible implementation, the test unit 530 is also used to configure test parameters for the SPI controller; construct test data; and, if a first SPI node exists among the M SPI nodes and the data transmission port and data reception port of the SPI controller are connected, control the SPI controller to send test data through the data transmission port of the SPI controller according to the configured test parameters.

[0165] In one possible implementation, the above test parameters include one or more of the following: SPI mode parameters, clock speed parameters, and bit width parameters.

[0166] In one possible implementation, the processing unit 520 is further configured to generate a test report for the SPI controller based on the target test results of the first SPI link and the target test results of the second SPI link.

[0167] In one possible implementation, the aforementioned SPI device includes N SPI controllers, and among the N SPI controllers, there are multiple SPI controllers under test, where N is a positive integer. The SPI node corresponding to each SPI controller under test contains a first SPI node. The test unit 530 is further configured to perform parallel loopback testing on the multiple SPI controllers under test using test data, with the data transmission and data reception ports of each SPI controller under test connected, to obtain the loopback test results for each SPI controller under test.

[0168] For a description of the technical effects of the testing device and any of its possible implementations, please refer to the description of the technical effects of the foregoing method embodiments; further details will not be repeated here.

[0169] According to the embodiments of this application, Figure 5 The various units in the test apparatus shown can be individually or entirely combined into one or more other units, or some of the units can be further divided into multiple functionally smaller units. This can achieve the same operation without affecting the technical effects of the embodiments of this application. The above units are based on logical function division. In practical applications, the function of one unit can also be implemented by multiple units, or the function of multiple units can be implemented by one unit.

[0170] This application also provides a computer device; please refer to [link / reference]. Figure 6 , Figure 6 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application.

[0171] like Figure 6 As shown, the computer device may include one or more processors 610, one or more memories 630, one or more communication interfaces 620, and a bus 640, wherein the processors 610, memories 630, and communication interfaces 620 are connected via the bus 640. The computer device may be the testing apparatus described above.

[0172] The memory 630 is used to store a program; the processor 610 is used to execute the program stored in the memory. When the program is executed, the processor 610 performs the method in any possible implementation of the test method described above.

[0173] It should be understood that, in the embodiments of this application, the memory 630 mentioned above includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CDROM), as well as external memory other than computer memory and processor cache. A portion of the memory 630 may also include non-volatile random access memory. For example, the memory 630 may also store device type information.

[0174] The processor 610 described above can be one or more Central Processing Units (CPUs). If the processor 610 is a CPU, it can be a single-core CPU or a multi-core CPU. The processor 610 can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0175] The steps performed in the foregoing embodiments can be based on the above. Figure 6 The computer device shown is implemented such that the processor 610 can execute the implementation described in any optional embodiment of the test method provided in this application, or it can execute the implementation of the test apparatus described in this application. The memory 630 can provide cache when the processor 610 executes the implementation of the test apparatus described in this application, and it can also store the computer programs required by the processor 610 to execute the implementation of the test apparatus described in this application.

[0176] This application also provides a computer storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, enable the processor to implement the above-mentioned functions. Figure 3 or Figure 4 The method shown.

[0177] This application also provides a computer program product, which includes: instructions or a computer program; when the instructions or the computer program are executed, the above-mentioned functions can be achieved. Figure 3 or Figure 4 The method shown.

[0178] This application also provides a chip, which includes a processor. The processor executes instructions, enabling the chip to achieve the aforementioned... Figure 3 or Figure 4 The method shown.

[0179] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by hardware related to computer programs. The computer programs can be stored in computer storage media, and when executed, they can implement the processes of the above method embodiments. The aforementioned computer storage media include various media capable of storing computer program code, such as read-only memory (ROM) or random access memory (RAM), magnetic disks, or optical disks.< / chipselect> < / bus> < / chipselect> < / bus>

Claims

1. A test method characterized by, The application is applied to a computer device, the computer device comprises a serial peripheral interface (SPI) device, the SPI device comprises an SPI controller, the SPI controller is connected with each SPI node in M SPI nodes through a data port, M is a positive integer, the SPI controller and the SPI node form an SPI link, the data port comprises a data sending port and a data receiving port, the method comprises: detecting the state of each of the M SPI nodes to obtain a state detection result of each of the SPI nodes, the state detection result is used to indicate the node state of the SPI node; determining whether there is a first SPI node in the M SPI nodes according to the state detection result of each of the SPI nodes, the state detection result of the first SPI node is a first state detection result, and the SPI link formed by the first SPI node and the SPI controller is a first SPI link; in the case that the M SPI nodes have the first SPI node and the data sending port and the data receiving port of the SPI controller are connected, the SPI controller is tested by loop using test data to obtain a loop test result of the SPI controller; determining the target test result of the first SPI link according to the loop test result of the SPI controller, the target test result comprises a first target test result and a second target test result.

2. The method of claim 1, wherein, The method further comprises: determining the SPI node with the second state detection result as the second SPI node according to the state detection result of each of the SPI nodes, and the SPI link formed by the second SPI node and the SPI controller is a second SPI link; directly determining the target test result of the second SPI link as the second target test result according to the second state detection result of the second SPI node.

3. The method of claim 1 or 2, wherein, In the case that the M SPI nodes have the first SPI node and the data sending port and the data receiving port of the SPI controller are connected, the SPI controller is tested by loop using test data to obtain a loop test result of the SPI controller, comprising: in the case that the M SPI nodes have the first SPI node and the data sending port and the data receiving port of the SPI controller are connected, the SPI controller is controlled to send test data through the data sending port of the SPI controller and receive data through the data receiving port of the SPI controller to obtain to-be-verified data; obtaining the loop test result of the SPI controller according to the test data and the to-be-verified data.

4. The method of claim 3, wherein, The loop test result of the SPI controller is obtained according to the test data and the to-be-verified data, comprising: comparing the test data and the to-be-verified data to obtain a data comparison result; In a case where the data comparison result indicates that the test data matches the to-be-verified data, a loopback test result of the SPI controller is obtained as a first loopback test result, and the first loopback test result indicates that the loopback test is successful; In a case where the data comparison result indicates that the test data does not match the to-be-verified data, a loopback test result of the SPI controller is obtained as a second loopback test result, and the second loopback test result indicates that the loopback test fails.

5. The method of claim 3, wherein, The method further comprises: performing test parameter configuration on the SPI controller; constructing the test data; In a case where the first SPI node exists in the M SPI nodes and the data sending port and the data receiving port of the SPI controller are connected, the SPI controller is controlled to send the test data through the data sending port of the SPI controller, including: In a case where the first SPI node exists in the M SPI nodes and the data sending port and the data receiving port of the SPI controller are connected, the SPI controller is controlled to send the test data through the data sending port of the SPI controller according to the configured test parameters.

6. The method of claim 2, wherein, The method further comprises: generating a test report of the SPI controller according to the target test result of the first SPI link and the target test result of the second SPI link.

7. The method of claim 1, wherein, The SPI device includes N SPI controllers, and a plurality of to-be-tested SPI controllers exist in the N SPI controllers, N is a positive integer, the first SPI node exists in an SPI node corresponding to the to-be-tested SPI controller, and the method further comprises: In a case where the data sending port and the data receiving port of each to-be-tested SPI controller are connected, a plurality of to-be-tested SPI controllers are subjected to parallel loopback tests by using test data, and loopback test results of the to-be-tested SPI controllers are obtained.

8. A test device, characterized by The test device comprises: a detection unit configured to perform state detection on each SPI node in M SPI nodes to obtain a state detection result of each SPI node, the state detection result being used to indicate a node state of the SPI node; M is a positive integer; a processing unit configured to determine whether a first SPI node exists in the M SPI nodes according to the state detection result of each SPI node, the state detection result of the first SPI node being a first state detection result; a test unit configured to perform loopback test on the SPI controller by using test data in a case where the first SPI node exists in the M SPI nodes and a data sending port and a data receiving port of the SPI controller are connected, and obtain a loopback test result of the SPI controller; the processing unit is further configured to determine a first target test result of a first SPI link according to the loopback test result of the SPI controller, the first SPI link being an SPI link formed by the SPI controller and the first SPI node.

9. A computer device, comprising: comprise: a memory and a processor; and wherein: The memory is configured to store a computer program, and the computer program comprises program instructions. The processor is configured to invoke the program instructions, so that the computer device executes the method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the method according to any one of claims 1-7.

Images