Data transmission method and electronic device

Abstract

The present disclosure relates to the technical field of computers, and discloses a data transmission method and an electronic device. The method is suitable for a host computer. A plurality of data channels are arranged between the host computer and a graphics processor. The host computer is provided with a buffer area corresponding to the data channels. The method comprises the following steps: determining the scheduling priorities of the plurality of data channels based on first communication data of the plurality of data channels and a target scheduling model; determining a target data channel from the plurality of data channels based on the scheduling priorities; writing to-be-sent data in a shared cache space to obtain a target address of the to-be-sent data in the shared cache space; and writing the target address to a target buffer area corresponding to the target data channel. The graphics processor is configured to read the target address in the target buffer area through the target data channel, and read and process the to-be-sent data in the shared cache space according to the target address. The present disclosure can solve the problem of data loss in the data interaction scenario between the host computer and the graphics processor.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, specifically to data transmission methods and electronic devices. Background Technology

[0002] In data interaction scenarios between the host computer and the graphics processing unit (GPU) chip, an independent circular buffer is configured for each data channel. The host writes the data to be sent into the circular buffer, and the GPU reads the data from the circular buffer and processes it. Since the storage size of the circular buffer is fixed, if the amount of data to be sent exceeds the storage size of the circular buffer, data loss can easily occur because unread data is overwritten. Summary of the Invention

[0003] In view of this, the present disclosure provides a data transmission method and an electronic device to solve the problem of data loss in data interaction scenarios between a host and a graphics processor.

[0004] In a first aspect, this disclosure provides a data transmission method applicable to a host computer, wherein the host computer has multiple buffers deployed thereon, and multiple data channels are provided between the host computer and a graphics processor, with the buffers corresponding to the data channels; the method includes:

[0005] Acquire the data to be sent and the first communication data of the multiple data channels;

[0006] Based on the first communication data and the target scheduling model, the scheduling priority of the multiple data channels is determined;

[0007] The target data channel is determined from the multiple data channels based on the scheduling priority.

[0008] Write the data to be sent into the shared cache space to obtain the target address of the data to be sent in the shared cache space;

[0009] The target address is written into the target buffer corresponding to the target data channel; wherein the graphics processor is configured to read the target address in the target buffer through the target data channel, and read and process the data to be sent in the shared cache space according to the target address.

[0010] Secondly, the present invention provides an electronic device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the above-described data transmission method by executing the computer instructions.

[0011] The data transmission method disclosed herein first determines the scheduling priority of multiple data channels using a target scheduling model and the first communication data of multiple data channels. Then, based on the scheduling priority, a target data channel for data transmission is determined among the multiple data channels. Therefore, the scheduling priority of the data channels can be adaptively adjusted according to the communication status of the data channels to improve data transmission efficiency and avoid data backlog. Next, the data to be transmitted is written into a shared buffer space, and the target address of the data to be transmitted in the shared buffer space is written into the target buffer corresponding to the target data channel, so that the graphics processor reads and processes the data to be transmitted in the shared buffer space according to the target address in the target buffer. Therefore, only a small amount of target address needs to be stored in the target buffer of the target data channel, without storing the complete data to be transmitted, thus avoiding the overwriting of unread data in the buffer due to the large amount of data to be transmitted, and preventing data loss.

[0012] For the beneficial effects of electronic devices, please refer to the beneficial effects of data transmission methods; further details will not be elaborated here. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram illustrating the interaction between a host computer and a graphics processor according to an embodiment of the present disclosure;

[0015] Figure 2 This is a flowchart illustrating a data transmission method according to an embodiment of the present disclosure;

[0016] Figure 3 This is a structural block diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0018] In data interaction scenarios between the host and the Graphics Processing Unit (GPU) chip, traditional multi-channel Direct Memory Access (DMA) systems exhibit significant technical bottlenecks. Existing solutions configure a separate DMA module for each data channel, leading to a linear increase in GPU chip area and power consumption with the number of channels, resulting in a sharp increase in hardware costs when the number of channels is large. Simultaneously, the circular buffer directly stores the actual data with a fixed size. When the data volume is smaller than the circular buffer's storage size, space is wasted; when the data volume is larger, data loss is easily caused by unread data being overwritten, resulting in low memory utilization. Furthermore, data channel switching relies on a time-slice polling mechanism, making it difficult to respond to sudden traffic demands in real time. High-priority data channels may experience processing delays due to time slices not being reached, affecting the real-time performance of critical data transmissions. For data distributed across multiple memory blocks, traditional DMA requires multiple independent transfers, significantly increasing transmission latency and failing to meet the demands of efficient data processing.

[0019] In view of the above, according to the embodiments of this disclosure, a data transmission method embodiment is provided. It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowcharts, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0020] This embodiment provides a data transmission method that can be used on a host, see [link to documentation]. Figure 1 The host computer has a shared cache space and multiple buffers, such as buffers 0 to n. Multiple data channels, such as data channels 0 to m, are established between the host computer and the graphics processor (GPU). These data channels are deployed on the GPU, and buffers correspond to these data channels. The GPU can access the buffers and shared cache space on the host computer through the data channels and the direct memory access module. Optionally, the buffers are circular buffers.

[0021] Figure 2 This is a flowchart illustrating a data transmission method according to an embodiment of the present disclosure, as shown below. Figure 2 As shown, the process includes the following steps:

[0022] Step S201: Obtain the data to be sent and the first communication data of multiple data channels.

[0023] It should be noted that the data obtained in step S201 above is the first communication data of each data channel.

[0024] Optionally, the first communication data for each data channel includes the current throughput, current data flow, and first service type of the data channel.

[0025] Step S202: Based on the first communication data and the target scheduling model, determine the scheduling priority of multiple data channels.

[0026] The target scheduling model is used to quantify the first communication data of a data channel into the scheduling priority of the data channel based on the pre-learned relationship between the communication data and the scheduling priority of the data channel.

[0027] Optionally, scheduling priority can be represented by weights. The weight of a data channel is positively correlated with the scheduling priority, that is, the greater the weight of the data channel, the higher the scheduling priority.

[0028] Optionally, the target scheduling model is obtained by training a preset scheduling model based on historical communication data from multiple data channels and corresponding historical scheduling priorities.

[0029] Step S203: Determine the target data channel from multiple data channels based on scheduling priority.

[0030] Specifically, multiple data channels are sorted in descending order of scheduling priority, and the data channel with the highest scheduling priority is selected as the target data channel.

[0031] If the scheduling priority is represented by the weight of the data channel, and the weight of the data channel is positively correlated with the scheduling priority, then multiple data channels are sorted in descending order of their weights, and the data channel with the largest weight is selected as the target data channel.

[0032] Step S204: Write the data to be sent into the shared cache space to obtain the target address of the data to be sent in the shared cache space.

[0033] The target address is the indirect address of the data to be sent in the shared cache space.

[0034] Specifically, before writing data to be sent into the shared cache space, the host first registers the target data channel in the host. The host then drives the graphics processor to open the corresponding target data channel, thereby ensuring efficient and orderly data transmission between multiple data channels. Unregistered data channels do not operate within the graphics processor chip, thus reducing internal chip power consumption.

[0035] Step S205: Write the target address into the target buffer corresponding to the target data channel; wherein, the graphics processor is configured to read the target address in the target buffer through the target data channel, and read and process the data to be sent in the shared cache space according to the target address.

[0036] The target address is written to the target buffer in the form of a pointer; that is, the target buffer stores the pointer corresponding to the target address, and the target address is stored in the pointer.

[0037] Specifically, the host maintains write pointers for each buffer. Based on the write pointer of the target buffer, the host writes the data to be sent into the shared buffer space. After the data is written, the host writes the target address into the target buffer based on the write pointer of the target buffer and updates the write pointer synchronously. The graphics processing unit (GPU) internally maintains read pointers for each buffer. The GPU obtains the target address from the target buffer through the read pointer of the target buffer and the target data channel, and reads the data to be sent from the shared buffer space based on the obtained target address. Then, the GPU distributes the read data to the direct memory access module for data processing, and synchronously updates the read pointer of the target buffer after processing.

[0038] Understandably, the pointers stored in the target buffer are contiguous, but the target addresses stored in the pointers may be non-contiguous. For example, if the target address of the data block pointed to by pointer 0 is 100 and the target address of the data block pointed to by pointer 1 is 300, then the target addresses are 100 and 300. That is, non-contiguous data blocks can be linked together by linking pointers.

[0039] The data transmission method provided in this embodiment first determines the scheduling priority of multiple data channels through a target scheduling model and the first communication data of multiple data channels. Then, based on the scheduling priority, a target data channel for data transmission is determined among the multiple data channels. Therefore, the scheduling priority of the data channels can be adaptively adjusted according to the communication status of the data channels to improve data transmission efficiency and avoid data backlog. Next, the data to be sent is written into the shared buffer space, and the target address of the data to be sent in the shared buffer space is written into the target buffer corresponding to the target data channel, so that the graphics processor reads and processes the data to be sent in the shared buffer space according to the target address in the target buffer. Therefore, only a small amount of target address needs to be stored in the target buffer of the target data channel, without storing the complete data to be sent, thereby avoiding the overwriting of unread data in the buffer due to the large amount of data to be sent, and thus preventing data loss.

[0040] In some optional implementations, step S202 above, which determines the scheduling priority of multiple data channels based on the first communication data and the target scheduling model, includes:

[0041] Step a1: Compare the current throughput with the historical throughput to obtain the throughput matching degree.

[0042] Specifically, a sliding window mechanism is used to quantify the data channel status. Within a preset period, the current throughput is compared with the peak historical throughput to obtain the throughput matching degree. The throughput matching degree is determined by the ratio of the current throughput to the peak historical throughput, and the throughput matching degree is normalized to the interval [0,1].

[0043] Optionally, the preset period can be 10ms or 15ms, and there is no limitation here.

[0044] The normalized throughput matching degree reflects the load intensity of the data channel. When the throughput matching degree is greater than or equal to the preset matching degree threshold, it indicates that the data channel is under high load intensity. When the throughput matching degree is less than the preset matching degree threshold, it indicates that the data channel is under low load intensity.

[0045] Optionally, the preset matching threshold can be set by the user or calculated by the target scheduling model, and there is no limitation here.

[0046] Step a2: Determine the traffic correction coefficient based on the comparison between the current data traffic and the preset traffic threshold.

[0047] Specifically, a sliding window is used to detect sudden changes in traffic. If the current data traffic is greater than or equal to a preset traffic threshold, the traffic correction coefficient is determined to be the first preset coefficient. If the current data traffic is less than the preset traffic threshold, the traffic correction coefficient is determined to be the second preset coefficient. The first preset coefficient is greater than the second preset coefficient.

[0048] Optionally, the first preset coefficient is 1.5 and the second preset coefficient is 1.0.

[0049] Optionally, the preset traffic threshold is a preset multiple of the historical data traffic, such as 3 times the historical data traffic or 5 times the historical data traffic, without limitation.

[0050] Step a3: Determine the target transmission delay sensitivity of multiple data channels based on the first service type and the pre-configured correspondence between service types and transmission delay sensitivity.

[0051] Specifically, based on the transmission delay requirements of different service types, the correspondence between service types and transmission delay sensitivity is pre-configured. For example, the transmission delay sensitivity of real-time control services is set to 1.0, and the transmission delay sensitivity of streaming media services is set to 0.6. The registers can be dynamically adjusted to adjust the transmission delay sensitivity corresponding to different service types.

[0052] It should be noted that the first service type of the data channel is related to the service type of the data historically transmitted by the data channel and the data transmission status of the data channel for different service types.

[0053] Specifically, for each data channel, after obtaining the first service type of the data channel, the target transmission delay sensitivity of the data channel is obtained based on the pre-configured correspondence between the service type and the transmission delay sensitivity.

[0054] Step a4: Input the throughput matching degree, traffic correction coefficient and target transmission delay sensitivity into the target scheduling model to obtain the scheduling priority of multiple data channels.

[0055] The target scheduling model is used to calculate the scheduling priority of each data channel by weighted summation of throughput matching degree, traffic correction coefficient and target transmission delay sensitivity based on the weighted round-robin algorithm.

[0056] In some optional implementations, step a4 above, which involves inputting throughput matching degree, traffic correction coefficient, and target transmission delay sensitivity into the target scheduling model to obtain the scheduling priority of multiple data channels, includes: for each data channel, inputting throughput matching degree, traffic correction coefficient, and target transmission delay sensitivity into the target scheduling model, and performing a weighted summation of throughput matching degree, traffic correction coefficient, and target transmission delay sensitivity according to a weighted round-robin algorithm to obtain the scheduling priority of the data channel.

[0057] Specifically, the scheduling priority of the data channel is obtained using the following formula:

[0058] ;

[0059] Where Wch is the weight of the data channel, and the scheduling priority of the data channel is represented by Wch; Tch is the throughput matching degree; α is the weight of the throughput matching degree; Dch is the target transmission delay sensitivity; β is the weight of the target transmission delay sensitivity; Bch is the traffic correction coefficient; γ is the weight of the traffic correction coefficient; and α+β+γ=1.

[0060] Specifically, the weights of each data channel are obtained based on a weighted round-robin algorithm. These weights are then used to generate a scheduling queue in descending order to determine the scheduling priority of each data channel. The weights of each data channel are positively correlated with its scheduling priority; the higher the weight of a data channel, the higher its scheduling priority.

[0061] The data transmission method provided in this embodiment uses a weighted round-robin algorithm to perform a weighted summation of throughput matching degree, traffic correction coefficient and target transmission delay sensitivity, and generates a scheduling queue in descending order of the weights of each data channel. This quantifies the scheduling priority of each data channel, ensuring that data channels with higher scheduling priority are scheduled first, thereby improving data transmission efficiency.

[0062] In some optional implementations, the data processing method of this disclosure further includes:

[0063] Step b1: Obtain the second communication data, which includes the host's transmission delay violation rate, throughput compliance rate, and channel switching count; the transmission delay violation rate is used to characterize the proportion of the host's transmission delay that does not meet the preset transmission delay requirements.

[0064] Optionally, the preset transmission delay requirement can be determined according to the current business needs. For example, the preset transmission delay requirement is that the host's transmission delay is less than a preset delay threshold, etc., which is not limited here.

[0065] Specifically, the transmission delay violation rate represents the proportion of times the host's actual transmission delay fails to meet the preset transmission delay requirement out of the total number of communications. The throughput compliance rate represents the proportion of times the host's actual data transmission volume per unit time is greater than or equal to the preset throughput threshold. The channel switching count represents the total number of times the host switches data channels during communication.

[0066] Step b2: Based on the target reward function and the second communication data, determine the target reward value. The transmission delay violation rate and the number of channel switching are negatively correlated with the target reward value, while the throughput achievement rate is positively correlated with the target reward value.

[0067] It should be noted that the target reward function is a calculation related to the second communication data, used to balance system performance based on transmission delay violation rate, throughput achievement rate, and channel switching count.

[0068] Specifically, the transmission delay violation rate, throughput achievement rate, and channel switching count are input into the target reward function to calculate the target reward value. The target reward function is represented by the following formula:

[0069] R = k1 (1 - transmission delay violation rate) + k2 (throughput compliance rate) - k3 (number of channel switching times);

[0070] Where R is the target reward value, k1 is the weight corresponding to the transmission delay violation rate, k2 is the weight corresponding to the throughput compliance rate, and k3 is the weight corresponding to the number of channel switching times.

[0071] Optionally, k1 is 10, k2 is 5, and k3 is 2, which can be adjusted according to the actual situation.

[0072] Step b3: When the target reward value exceeds the preset reward value range, the parameters of the target scheduling model are adjusted with the goal of minimizing the throughput compliance rate and the transmission delay violation rate. The parameters of the target scheduling model include the weight of throughput matching degree, the weight of traffic correction coefficient, and the weight of target transmission delay sensitivity.

[0073] It should be noted that the determination of the preset reward value range should avoid frequent adjustments to the weights of throughput matching, traffic correction coefficient, and target transmission delay sensitivity, and should also avoid excessive fluctuations in the weights of these three factors. The preset reward value range can be set by the user or obtained from training the target scheduling model; no limitation is made here.

[0074] Specifically, when the target reward value exceeds the preset reward value range, the optimization objectives are to minimize the throughput compliance rate and the transmission delay violation rate. The weights of throughput matching degree, traffic correction coefficient, and target transmission delay sensitivity are dynamically adjusted to keep the target reward value within the preset reward value range.

[0075] Understandably, when a host's high transmission delay violation rate leads to a decrease in the target reward value, the target scheduling model adjusts the weight of the second communication data to increase the weight of the target transmission delay sensitivity. This prioritizes the scheduling of service data with high transmission delay sensitivity, thereby reducing the transmission delay violation rate and increasing the target reward value. For example, if the transmission delay violation rate exceeds a preset violation rate threshold and the target reward value decreases compared to the previous period, the target scheduling model increases the weight of the target transmission delay sensitivity to prioritize the scheduling of service data with high transmission delay sensitivity. When the number of channel switching is too frequent, the penalty term in the target reward function prompts the target scheduling model to adjust the weight of the second communication data to avoid excessive weight fluctuations and reduce meaningless data channel switching.

[0076] The data transmission method provided in this embodiment obtains second communication data such as host transmission latency violation rate, throughput compliance rate, and channel switching count, inputs the second communication data into a target reward function, calculates a target reward value using the target reward function, and dynamically adjusts the weight of the second communication data based on the comparison relationship between the target reward value and a preset reward value range. This can further optimize the data channel scheduling strategy, reduce latency violation rate, reduce invalid switching, and thus improve the overall communication performance of the host.

[0077] In some optional implementations, step S204 above, which involves writing the data to be sent into the shared buffer space to obtain the target address of the data to be sent in the shared buffer space, includes:

[0078] Step c1: Configure the time slice of the target data channel based on the scheduling priority of the target data channel. The duration of the time slice is positively correlated with the scheduling priority.

[0079] Specifically, the duration of a time slice is set based on a base time slice, and the duration of a time slice is a multiple of the base time slice. This multiple is related to the scheduling priority of the target data channel. For example, when the base time slice is 100ns, the duration of a time slice with a high scheduling priority is 300ns, and the duration of a time slice with a low scheduling priority is 50ns.

[0080] Optionally, the base time slice is 100ns, and the base time slice can be adjusted according to the actual situation.

[0081] Step c2: If the time slice of the target data channel has expired, the target data channel is redefined.

[0082] Specifically, when the time slice of the target data channel expires, the target data channel is redefined to switch the data transmission channels between the host and the graphics processor.

[0083] The data transmission method provided in this embodiment determines the time slice of the target data channel based on the data channel scheduling priority, and dynamically switches the target data channel when the time slice is exhausted. This achieves efficient resource allocation, avoids long-term blocking of data channels with low scheduling priority, and improves data transmission efficiency and resource utilization.

[0084] In some optional implementations, the data transmission method of this disclosure further includes: if the data volume of the target buffer reaches a preset data volume threshold, the target buffer is empty, or the shared cache space triggers a write protection threshold, then the target data channel is re-determined based on the scheduling priority.

[0085] In some optional implementations, the step S204 or step c2 above, which involves writing the data to be sent into the shared buffer space to obtain the target address of the data to be sent in the shared buffer space, includes:

[0086] Step d1: Obtain the fragmentation rate of the shared cache space, the amount of data to be sent, and the data block characteristics corresponding to the second service type of the data to be sent. The data block characteristics are determined based on the historical data block size of the second service type.

[0087] The fragmentation rate characterizes the proportion of free blocks smaller than a preset size (e.g., 2KB) in the shared cache space. It reflects the degree of fragmentation in the shared cache space; a higher fragmentation rate indicates greater fragmentation. When the fragmentation rate is high, smaller data block sizes are preferentially selected as candidate data block sizes. The fragmentation rate ranges from [0,1].

[0088] Optionally, the second service type can be audio, image, control command, etc. Data block characteristics are used to characterize the preference of the second service type for data block size.

[0089] Understandably, different service types have different preferences for data block sizes. For example, audio data, due to its larger volume, prefers contiguous and larger data blocks. Control command data, on the other hand, due to its smaller volume, prefers smaller data blocks. In practical applications, statistical analysis of historical data block sizes for different service types can be performed to obtain the historical data block sizes for different service types, thus determining the historical data block sizes for a second service type.

[0090] Step d2: Determine the target data block size based on the target decision model, fragmentation rate, amount of data to be sent, and data block characteristics.

[0091] The target decision model is obtained by training a preset decision model based on the historical fragmentation rate of the shared cache space, the amount of historical data sent, the data block characteristics of the business type corresponding to the historical data sent, and the data block size corresponding to the historical data sent.

[0092] Step d3: Write the data to be sent into the shared cache space based on the target data block size to obtain the target address.

[0093] Specifically, the data to be sent is divided into multiple target data blocks according to the size of the target data blocks. These multiple target data blocks are then written into a shared buffer space, and their addresses within the shared buffer space are obtained, thus yielding the target address. The target address includes the addresses of the multiple target data blocks within the shared buffer space. The addresses of the multiple target data blocks are stored in the target buffer as pointers.

[0094] The data transmission method provided in this embodiment dynamically determines the target data block size based on the fragmentation rate of the shared buffer space, the amount of data to be sent, and data block characteristics. Based on the target data block size, the data to be sent is written into the shared buffer space to obtain the target address. The target address is stored in a pointer within the target buffer corresponding to the target data channel. Therefore, only a small amount of target address needs to be stored in the target buffer of the target data channel, without storing the complete data to be sent. This avoids the problem of unread data in the buffer being overwritten due to an excessive amount of data to be sent, thus preventing data loss.

[0095] In some optional implementations, step d2 above, which determines the target data block size based on the target decision model, fragmentation rate, the amount of data to be sent, and data block characteristics, includes:

[0096] Step d21: Input the fragmentation rate, the amount of data to be sent, and the data block characteristics into the target decision model to determine the set of data block sizes, which includes multiple candidate data block sizes.

[0097] Specifically, a set of data block sizes is constructed based on the fragmentation rate, the amount of data to be sent, and the characteristics of the data blocks. The set of data block sizes includes multiple candidate data blocks.

[0098] It should be noted that the multiple candidate data blocks in the data block size set can be the data blocks that appear most frequently according to the statistics of the target decision model. In addition, the user can specify the data block size set, which is not limited here.

[0099] Step d22: Determine the target data block size from the set of data block sizes using the following formula:

[0100] ;

[0101] Where Size is the target data block size, argmin is the function used to select the minimum value, s is the candidate data block size, S1 is the set of data block sizes, S2 is the amount of data to be sent, c is the penalty value of the candidate data block size, and λ is the dynamic weight, which is determined based on the comparison between the candidate data block size and the minimum free block size in the shared cache space, and λ is related to the host's bandwidth utilization and data transmission pressure.

[0102] Specifically, the candidate data block size, the amount of data to be sent, and a penalty term for the candidate data block size are input into the target decision model, and the target data block size is determined according to the above formula. The penalty value c characterizes how much the candidate data block size exacerbates the fragmentation of the shared cache space.

[0103] Understandably, if the candidate data block size is greater than the minimum free block size of the shared cache space, the penalty value is determined to be a first preset value; if the candidate data block size is less than or equal to the minimum free block size of the shared cache space, the traffic correction coefficient is determined to be a second preset value. The first preset value is greater than the second preset value.

[0104] In practical applications, the dynamic weight λ is set by the user or obtained through training the target decision model. When bandwidth utilization is high (e.g., bandwidth utilization exceeds a preset threshold), the dynamic weight λ is set to 0.7 to prioritize smaller candidate data block sizes, dividing the data to be sent into smaller blocks for transmission. When data transmission pressure is high (e.g., data transmission pressure exceeds a preset pressure threshold), λ is set to 0.3 to prioritize larger candidate data block sizes, dividing the data to be sent into larger blocks for transmission. If the current bandwidth utilization is high and no more bandwidth can be allocated, and a high-weight data packet is being transmitted, then no large data blocks are available, only small data blocks. In fixed scenarios, high-priority data packets have very short frames; providing large data blocks would result in low bandwidth utilization, so providing small data blocks improves resource utilization. When data transmission consistently involves fragmented packets, it indicates high transmission pressure; in this case, small data blocks are pieced together, prioritizing the use of large data blocks for transmission to improve bandwidth utilization.

[0105] The data transmission method provided in this embodiment inputs the fragmentation rate, the amount of data to be sent, and data block characteristics into a target decision model to obtain a set of data block sizes. Then, based on dynamic weights and a fragmentation penalty mechanism, the target data block size is determined. When bandwidth is limited, high-priority data is prioritized for transmission using small data blocks. When transmission pressure is high, small data blocks are merged for transmission, thereby effectively improving bandwidth utilization and transmission efficiency.

[0106] In some optional implementations, step d3 above, which involves writing the data to be sent into the shared cache space based on the target data block size to obtain the target address, includes:

[0107] Step d31: Locate the first free block in the shared cache space that meets the target data block size.

[0108] The first free block is a series of consecutive free blocks.

[0109] Step d32: If the number of first free blocks is greater than or equal to the number of data blocks corresponding to the target data block size, then write the data to be sent into the first free block of the shared cache space to obtain the target address.

[0110] Specifically, if the number of consecutive free blocks is greater than or equal to the ratio of the amount of data to be sent to the size of the target data block, then the data to be sent is written into the consecutive free blocks in the shared cache space to obtain the target address.

[0111] Step d33: If the number of first free blocks is less than the number of data blocks, then write the first data into the first free block of the shared cache space and write the second data into the second free block of the shared cache space to obtain the target address. The target address includes the addresses of the first data and the second data in the shared cache space. The first data and the second data are obtained by dividing the data to be sent.

[0112] The second free block includes free blocks in the shared cache space that do not meet the target data block size. The size of the second free block is smaller than the size of the first free block, and the second free block is a discrete free block.

[0113] Specifically, when the number of consecutive free blocks is less than the number of data blocks, a consecutive free block is searched in the shared cache space. The first data corresponding to the data to be sent is determined and written into the consecutive free block in the shared cache space. Then, the remaining unallocated data to be sent is allocated to discrete free blocks, and the second data is written into the discrete free blocks in the shared cache space to obtain the target address. The target address includes the addresses of the first data corresponding to the consecutive free block and the second data corresponding to the discrete free block in the shared cache space.

[0114] Optionally, when allocating the second data using discrete free blocks, a descriptor table is generated. The descriptor table is used to record the address of the first free block, the address of the second free block, the length of the first free block, and the length of the second free block.

[0115] The data transmission method provided in this embodiment dynamically matches continuous or discrete free blocks for data writing based on the target data block size. This can improve transmission efficiency by prioritizing the use of continuous space to reduce the number of transmissions when there is sufficient remaining space in the shared cache space, and by flexibly allocating discrete free blocks to ensure the storage of data to be sent when fragmentation is severe.

[0116] In some optional implementations, the data transmission method of this disclosure further includes: when the fragmentation rate of the shared cache space is greater than a preset fragmentation rate threshold, searching for a third free block in the shared cache space whose free block size is smaller than a preset size, and merging adjacent third free blocks.

[0117] Optionally, the preset fragmentation rate threshold is 60% and the preset size is 2KB, which can be adjusted according to the actual situation.

[0118] For example, with a preset fragmentation rate threshold of 60% and a preset size of 2KB, if the fragmentation rate of the shared cache space is greater than 60%, background fragment merging is triggered, merging two adjacent 1KB blocks to obtain a 2KB free block.

[0119] Furthermore, merging adjacent third free blocks includes: obtaining the access frequency of adjacent third free blocks; if the access frequency of adjacent third free blocks is less than or equal to a preset frequency threshold, then merging the adjacent third free blocks.

[0120] That is, the third free block is reserved if the access frequency is greater than a preset frequency threshold, in order to avoid the additional performance overhead caused by frequent merging.

[0121] Optionally, the preset frequency threshold is 100 times / second, which can be adjusted according to the actual situation.

[0122] In some optional implementations, the data transmission method of this disclosure further includes: adjusting the parameters and dynamic weights of the target decision model based on the set of data block sizes and the data block size of the data to be sent in the shared cache space, with the goal of minimizing data transmission latency and space waste rate of the shared cache space.

[0123] The data block size of the data to be sent in the shared cache space includes at least one of the first free block size and the second free block size.

[0124] In practical applications, for each preset number of data to be sent, the optimization goal is to minimize data transmission latency and the space waste rate of the shared cache space. For each set of data to be sent, the parameters and dynamic weights of the target decision model are adjusted based on the corresponding set of data block sizes and the size of the data block in the shared cache space.

[0125] For example, taking a preset number of 100 times as an example, after writing the data to be sent into the shared cache space every 100 times, the parameters and dynamic weights of the target decision model are adjusted according to the set of data block sizes and the data block sizes of these 100 data to be sent.

[0126] Furthermore, based on the corresponding set of data block sizes and the data block size of the data to be sent in the shared cache space, the parameters and dynamic weights of the target decision model are adjusted, including: if the number of data writes to the second free block in the shared cache space that does not meet the target data block size reaches a preset threshold, the dynamic weight is increased. If the data transmission delay of the determined target data channel is greater than a preset delay threshold, the dynamic weight is set to a preset minimum weight.

[0127] Optionally, the preset threshold for the number of attempts is 5, and the preset minimum weight is 0.1, which can be adjusted according to the actual situation.

[0128] Optionally, the preset delay threshold can be set by the user, and can be 100μs or 300μs, without limitation.

[0129] For example, taking a preset threshold of 5 times and a preset minimum weight of 0.1 as an example, when the target decision model is in the online adaptive phase, if it detects 5 consecutive discrete allocations of data to be sent in the shared cache space, it will automatically increase the dynamic weight to reduce the fragmentation of the shared cache space. If the data transmission delay of the target data channel with high scheduling priority is greater than the preset delay threshold, the dynamic weight will be temporarily set to 0.1 to prioritize the transmission of data to be sent using larger data block sizes, thereby reducing the number of data transmissions.

[0130] Specifically, the data transmission method disclosed herein further includes: when the host is offline, offline training of the target decision model is performed by acquiring the host's data transmission log, which records historical data written by the host to the shared cache space and related transmission information. The transmission information includes the set of data block sizes corresponding to the historical data, the data block size of the historical data in the shared cache space, the space waste rate of the shared cache space corresponding to the historical data, and the data transmission latency. With the optimization objective of minimizing data transmission latency and the space waste rate of the shared cache space, the parameters of the target decision model are adjusted using the data transmission log, and the dynamic weights are adjusted using a dynamic programming algorithm.

[0131] The aforementioned adjustment of dynamic weights using a dynamic programming algorithm includes: increasing the dynamic weights when the shared cache space waste rate exceeds a preset waste rate threshold to prioritize smaller data block sizes; and decreasing the dynamic weights when the data transmission delay exceeds a preset delay threshold to prioritize larger data block sizes.

[0132] Taking a specific application example, during the offline training phase, if the shared cache space wastage rate exceeds 30%, the dynamic weight of the target decision model is increased to 0.8 to prioritize smaller data block sizes. If the data transmission latency exceeds 100ns, the dynamic weight is decreased to 0.2 to prioritize larger data block sizes. During the online adaptive phase, the dynamic weight is updated every 100 allocations. For example, if five consecutive discrete allocations of data to be sent in the shared cache space are detected, the target decision model automatically increases the dynamic weight to reduce fragmentation of the shared cache space. If the data transmission latency of the high-priority target data channel exceeds 100μs, the dynamic weight is set to 0.1 to prioritize larger data block sizes and reduce the number of data transmissions.

[0133] The data transmission method provided in this embodiment employs a dual optimization mechanism of offline training and online adaptation. Its optimization objective is to minimize data transmission latency and the space waste rate of the shared cache space. When the space waste rate is high, the dynamic weight is increased; when the data transmission latency is high, the dynamic weight is decreased. Furthermore, when the number of writes to the second free block in the shared cache space that does not meet the target data block size reaches a preset threshold, the dynamic weight is increased to reduce the fragmentation rate. This achieves adaptive adjustment of the parameters and dynamic weights of the target decision model, while simultaneously reducing fragmentation and improving resource utilization.

[0134] In practical applications, it is necessary not only to save the input and output data of the target decision model, so that during both offline and online training phases, the parameters and dynamic weights of the target decision model can be adjusted with the goal of minimizing data transmission latency and shared cache space waste, but also to save the input data, output data, and relevant data of the target scheduling model. This allows for further optimization of the target scheduling model's parameters during both offline and online training phases, with the goal of minimizing data transmission latency and shared cache space waste.

[0135] This disclosure also provides an electronic device, see embodiments thereof. Figure 3 , Figure 3 This is a structural block diagram of an electronic device provided in an optional embodiment of this disclosure, such as... Figure 3 As shown, the electronic device includes one or more processors 301, a memory 302, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise as required. The processors can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 3 Take processor 301 as an example.

[0136] Processor 301 may be a central processing unit, a network processor, or a combination thereof. Processor 301 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0137] The memory 302 stores instructions executable by at least one processor 301 to cause at least one processor 301 to perform the method shown in the above embodiments.

[0138] The memory 302 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 302 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 302 may optionally include memory remotely located relative to the processor 301, and these remote memories can be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0139] Memory 302 may include volatile memory, such as random access memory; memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; memory 302 may also include combinations of the above types of memory.

[0140] This disclosure also provides a computer-readable storage medium in which the methods described in this disclosure can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium after being downloaded over a network. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium may also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implement the data transmission methods shown in the above embodiments.

[0141] A portion of this disclosure can be applied to computer program products, such as computer program instructions, which, when executed by a computer, can invoke or provide methods and / or technical solutions according to this disclosure through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, and installation package files. Accordingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions; the computer compiling the instructions and then executing the corresponding compiled program; the computer reading and executing the instructions; or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0142] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A data transmission method, characterized in that, Applicable to a host computer, wherein the host computer has multiple buffers deployed thereon, and multiple data channels are provided between the host computer and the graphics processor, wherein the buffers correspond to the data channels; the method includes: Acquire the data to be sent and the first communication data of the multiple data channels; the first communication data includes the current throughput, the current data flow, and the first service type. Based on the first communication data and the target scheduling model, the scheduling priority of the multiple data channels is determined; wherein, the target scheduling model is obtained by training a preset scheduling model based on the historical communication data and corresponding historical scheduling priorities of the multiple data channels. The target data channel is determined from the multiple data channels based on the scheduling priority. Write the data to be sent into the shared cache space to obtain the target address of the data to be sent in the shared cache space; The target address is written into the target buffer corresponding to the target data channel; wherein, the graphics processor is configured to read the target address in the target buffer through the target data channel, and read and process the data to be sent in the shared cache space according to the target address; The step of determining the scheduling priority of the multiple data channels based on the first communication data and the target scheduling model includes: The current throughput is compared with the historical throughput to obtain the throughput matching degree; Based on the comparison between the current data traffic and the preset traffic threshold, a traffic correction coefficient is determined; Based on the first service type and the pre-configured correspondence between service types and transmission delay sensitivity, the target transmission delay sensitivity of the multiple data channels is determined; The throughput matching degree, the traffic correction coefficient, and the target transmission delay sensitivity are input into the target scheduling model to obtain the scheduling priority of the multiple data channels.

2. The data transmission method according to claim 1, characterized in that, The step of inputting the throughput matching degree, the traffic correction coefficient, and the target transmission delay sensitivity into the target scheduling model to obtain the scheduling priority of the multiple data channels includes: For each data channel, the throughput matching degree, the traffic correction coefficient, and the target transmission delay sensitivity are input into the target scheduling model. The throughput matching degree, the traffic correction coefficient, and the target transmission delay sensitivity are weighted and summed according to the weighted round-robin algorithm to obtain the scheduling priority of the data channel.

3. The data transmission method according to claim 2, characterized in that, The method further includes: Acquire second communication data, which includes the host's transmission delay violation rate, throughput compliance rate, and channel switching count; the transmission delay violation rate is used to characterize the proportion of the host's transmission delay that does not meet the preset transmission delay requirements; Based on the target reward function and the second communication data, a target reward value is determined. The transmission delay violation rate and the number of channel switching are negatively correlated with the target reward value, while the throughput achievement rate is positively correlated with the target reward value. If the target reward value exceeds the preset reward value range, the parameters of the target scheduling model are adjusted with the goal of minimizing the throughput compliance rate and the transmission delay violation rate. The parameters of the target scheduling model include the weight of the throughput matching degree, the weight of the traffic correction coefficient, and the weight of the target transmission delay sensitivity.

4. The data transmission method according to claim 1, characterized in that, The method further includes: The time slice of the target data channel is configured based on the scheduling priority of the target data channel, and the duration of the time slice is positively correlated with the scheduling priority. If the time slice of the target data channel expires, the target data channel is redefined.

5. The data transmission method according to claim 1, characterized in that, The step of writing the data to be sent into the shared cache space to obtain the target address of the data to be sent in the shared cache space includes: The fragmentation rate of the shared cache space, the amount of data to be sent, and the data block characteristics corresponding to the second service type of the data to be sent are obtained. The data block characteristics are determined based on the historical data block size of the second service type. The target data block size is determined based on the target decision model, the fragmentation rate, the amount of data to be sent, and the data block characteristics; wherein, the target decision model is obtained by training a preset decision model based on the historical fragmentation rate of the shared cache space, the amount of data sent in the past, the data block characteristics of the service type corresponding to the past sent data, and the data block size corresponding to the past sent data. The target address is obtained by writing the data to be sent into the shared cache space based on the target data block size.

6. The data transmission method according to claim 5, characterized in that, The determination of the target data block size based on the target decision model, the fragmentation rate, the amount of data to be sent, and the data block characteristics includes: The fragmentation rate, the amount of data to be sent, and the data block characteristics are input into the target decision model to determine the data block size set, which includes multiple candidate data block sizes. The target data block size is determined from the set of data block sizes using the following formula: ； Where Size is the target data block size, argmin is the function used to select the minimum value, s is the candidate data block size, S1 is the set of data block sizes, S2 is the amount of data to be sent, c is the penalty value of the candidate data block size, λ is the dynamic weight, c is determined based on the comparison between the candidate data block size and the minimum free block size in the shared cache space, and λ is related to the host's bandwidth utilization and data transmission pressure.

7. The data transmission method according to claim 5, characterized in that, The step of writing the data to be sent into the shared cache space based on the target data block size to obtain the target address includes: Find the first free block in the shared cache space that meets the target data block size; If the number of the first free blocks is greater than or equal to the number of data blocks corresponding to the target data block size of the data to be sent, then the data to be sent is written into the first free block of the shared cache space to obtain the target address; If the number of the first free blocks is less than the number of data blocks, then first data is written into the first free block of the shared cache space, and second data is written into the second free block of the shared cache space to obtain the target address. The target address includes the addresses of the first data and the second data in the shared cache space. The first data and the second data are obtained by dividing the data to be sent.

8. The data transmission method according to claim 6, characterized in that, The method further includes: With the optimization objective of minimizing data transmission latency and the space wastage rate of the shared cache space, the parameters of the target decision model and the dynamic weights are adjusted based on the set of data block sizes and the data block size of the data to be sent in the shared cache space.

9. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the data transmission method of any one of claims 1 to 8.

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