Cache control device and control method based on context, and chip

Abstract

The invention provides a context-based Cache control device. The context-based Cache control device comprises an instruction management module and an instruction processing module. The instruction management module is configured to receive a Cache operation instruction and a context number corresponding to the Cache operation instruction; when the Cache operation instruction in processing does not exist or when the Cache operation instruction in processing exists and the context number corresponding to the Cache operation instruction in processing is different from the context number corresponding to the Cache operation instruction, allowing the Cache operation instruction to be issued; and when the Cache operation instruction in processing exists and the context number corresponding to the Cache operation instruction in processing is the same as the context number corresponding to the Cache operation instruction, blocking the Cache operation instruction. And the instruction processing module is configured to receive the Cache operation instructions issued by the instruction management module, and operate the Cache according to the Cache operation instructions and the context numbers corresponding to the Cache operation instructions. The invention further relates to a Cache control method based on the context and a chip comprising the Cache control device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of chips, in particular, to a context-based Cache control device and a Cache control method applicable to the Cache control device, and further to a chip comprising the Cache control device. BACKGROUND

[0002] A cache (i.e., Cache) is usually arranged between a chip core and a main memory (i.e., memory), which has a much higher access rate than the main memory, and thus can be used to store instructions and data frequently used by the chip core, so as to solve the problem of a large gap between the processing rate of the chip core and the access rate of the main memory.

[0003] At present, when performing operations such as flushing (i.e., flush operation) on the Cache, subsequent operation instructions for operating the Cache are blocked. Since there is a long processing time in the process of flushing data to the main memory, the Cache needs to wait for the processing to be completed before unblocking the subsequent operation instructions, which leads to the fact that hardware resources are not fully utilized. SUMMARY

[0004] According to a first aspect of the present disclosure, a context-based Cache control device is provided, which comprises an instruction management module and an instruction processing module. The instruction management module is configured to: receive a Cache operation instruction and a context number corresponding to the Cache operation instruction; allow the Cache operation instruction to be issued when there is no Cache operation instruction being processed or when there is a Cache operation instruction being processed and the context number corresponding to the Cache operation instruction is different from the context number corresponding to the Cache operation instruction; and block the Cache operation instruction when there is a Cache operation instruction being processed and the context number corresponding to the Cache operation instruction is the same as the context number corresponding to the Cache operation instruction. The instruction processing module is configured to: receive the Cache operation instruction issued from the instruction management module, and operate the Cache according to each Cache operation instruction and the context number corresponding to each Cache operation instruction.

[0005] According to some example embodiments, the instruction management module comprises a context management unit and an instruction issue logic judging unit. The context management unit is configured to store a context number corresponding to the Cache operation instruction in processing. The instruction issue logic judging unit is configured to compare the context number corresponding to the Cache operation instruction with the context number corresponding to the Cache operation instruction in processing obtained from the context management unit, and when the two are the same, block the Cache operation instruction, and when the two are different, allow the Cache operation instruction to be issued to the instruction processing module.

[0006] According to some example embodiments, the context management unit is further configured to delete the context number corresponding to the Cache operation instruction in processing in response to the Cache operation instruction in processing being processed by the instruction processing module.

[0007] According to some example embodiments, the instruction processing module is further configured to, when the received and processed Cache operation instruction is a data flush operation instruction indicating a data flush operation on the Cache, perform a data flush operation on all addresses in the Cache having the context number corresponding to the data flush operation instruction.

[0008] According to some example embodiments, the instruction processing module is further configured to, when the received and processed Cache operation instruction is a data synchronization operation instruction indicating a data synchronization on the Cache, count a number of Cache operation instructions having the same context number as the context number corresponding to the data synchronization operation instruction but not yet completed processing; in response to each of the Cache operation instructions not yet completed processing being processed, decrement the number by one; and when the number becomes zero, notify the instruction management module to unblock the Cache operation instruction having the context number corresponding to the data synchronization operation instruction.

[0009] According to some example embodiments, the instruction processing module further comprises a counter configured to count a number of Cache operation instructions having the same context number as the context number corresponding to the data synchronization operation instruction but not yet completed processing; in response to each of the Cache operation instructions not yet completed processing being processed, decrement the number by one.

[0010] According to a second aspect of the present disclosure, a context-based Cache control method is provided, which comprises: receiving a Cache operation instruction and a context number corresponding to the Cache operation instruction; when there is no Cache operation instruction under processing or when there is a Cache operation instruction under processing and the context number corresponding to the Cache operation instruction under processing is different from the context number corresponding to the Cache operation instruction, the Cache operation instruction is allowed to be issued; when there is a Cache operation instruction under processing and the context number corresponding to the Cache operation instruction under processing is the same as the context number corresponding to the Cache operation instruction, the Cache operation instruction is blocked.

[0011] According to some example embodiments, the context-based Cache control method further comprises: for the issued Cache operation instruction, operating the Cache according to each Cache operation instruction and the context number corresponding to each Cache operation instruction.

[0012] According to some example embodiments, the operating the Cache according to each Cache operation instruction and the context number corresponding to each Cache operation instruction for the issued Cache operation instruction comprises: when the issued Cache operation instruction is a data refresh operation instruction indicating a data refresh operation on the Cache, performing the data refresh operation on all addresses in the Cache having the context number corresponding to the data refresh operation instruction.

[0013] According to some example embodiments, the operating the Cache according to each Cache operation instruction and the context number corresponding to each Cache operation instruction for the issued Cache operation instruction comprises: when the issued Cache operation instruction is a data synchronization operation instruction indicating a data synchronization on the Cache, counting the number of Cache operation instructions corresponding to the context number corresponding to the data synchronization operation instruction which have been issued for processing but have not received a response signal; in response to receiving one response signal, decreasing the number by one; when the number becomes zero, unblocking the Cache operation instruction having the context number corresponding to the data synchronization operation instruction.

[0014] According to a third aspect of the present disclosure, a chip is provided, which comprises the context-based Cache control apparatus according to the first aspect of the present disclosure and example embodiments thereof.

[0015] According to some example embodiments, the chip is a GPU chip or an NPU chip. BRIEF DESCRIPTION OF DRAWINGS

[0016] The exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings:

[0017] Figure 1 An exemplary application scenario of the context-based Cache control apparatus according to an exemplary embodiment of the present disclosure is schematically shown;

[0018] Figure 2 According to an exemplary embodiment of the present disclosure, details of the structure of the context-based Cache control apparatus shown in Figure 1

[0019] Figure 3 According to an exemplary embodiment of the present disclosure, details of the structure of the context-based Cache control apparatus shown in Figure 2

[0020] Figure 4 A process when the context-based Cache control apparatus according to an exemplary embodiment of the present disclosure performs a data synchronization operation is schematically shown in the form of a state transition diagram;

[0021] Figure 5 A context-based Cache control method according to an exemplary embodiment of the present disclosure is schematically shown in the form of a flowchart;

[0022] Figure 6 A context-based Cache control method according to another exemplary embodiment of the present disclosure is schematically shown in the form of a flowchart;

[0023] Figure 7 A structure of a chip according to an exemplary embodiment of the present disclosure is schematically shown in the form of a block diagram.

[0024] It should be understood that the accompanying drawings are only schematic diagrams of the exemplary embodiments of the present disclosure, and are not intended to limit the present disclosure, nor need they be drawn according to scale. In addition, in the accompanying drawings, the same or similar features are indicated by the same or similar reference numerals. DETAILED DESCRIPTION

[0025] The exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings:

[0026] Referring to Figure 1 An exemplary application scenario of the context-based Cache control apparatus according to an exemplary embodiment of the present disclosure is schematically shown. As shown in Figure 1 ​​As shown, the application scenario 100 includes a chip core 110, a Cache 120 and a main memory 130. Among them, the instruction scheduling unit 111 in the chip core 110 can schedule instructions and manage addresses based on the granularity of the context (i.e. context), send Cache operation instructions to the Cache 120, so as to perform operations such as data refresh operation, data synchronization operation, etc. on the Cache 120. It should be understood that the chip core 110, the Cache 120 and the main memory 130 can have any suitable type. For example, the chip core 110 can be a kernel of a GPU chip, the Cache 120 can be a static random access memory (i.e. SRAM memory), and the main memory 130 can be a DDR memory. The present disclosure does not make any limitation on the specific types of the chip core 110, the Cache 120 and the main memory 130.

[0027] It should be understood that in the present disclosure, the term "context" refers to the overall of the resource environment configured for the task to be performed, which can include, for example, the values of variables, the storage addresses of data, the calling conditions of functions, the execution positions of programs, etc. Therefore, the context plays an important role in the operation of the chip, which can help to manage the state, control flow and instruction execution process. As mentioned above, the Cache control device according to the present disclosure operates with the context as the granularity, which also means that it takes the overall of one configured resource environment as a single object to perform the relevant Cache operation, and therefore, this way is more conducive to the full use of hardware resources.

[0028] Continuing to refer to Figure 1 , the instruction scheduling unit 111 can send the Cache operation command for operating the Cache 120 and the corresponding context number CTXT-ID to the Cache control device 121 in the Cache 120. The Cache control device 121 can perform the operation indicated by the Cache operation command on the Cache 120 according to the received context number CTXT-ID.

[0029] Taking the data refresh operation as an example, the Cache control device 121 can poll the addresses in the Cache 120 (for example, poll in the form of set, way), and then refresh the data in the addresses with the same context number CTXT-ID to the main memory 130. The main memory 130 performs the data refresh operation after receiving the request REQ, and returns the response signal ACK2 to the Cache control device 121 after processing is completed. Accordingly, the Cache control device 121 also returns the response signal ACK1 of the Cache operation command processing to the instruction scheduling unit 111.

[0030] From the time when the cache control device 121 receives the data refresh operation instruction until the time when the main memory 130 returns the response signal ACK2, cache operation commands with different context numbers (including data refresh operation instructions with different context numbers) can still be processed by the cache control device 121 without being affected by the data refresh operation instruction corresponding to the context number CTXT-ID that is currently being processed. That is, the processing of the data refresh operation instruction corresponding to the context number CTXT-ID does not block (i.e., STALL) the processing of subsequent cache operation commands corresponding to different context numbers. In this way, the context-based cache control device 121 according to the present disclosure can improve the system bandwidth when performing cache operations, thereby improving the overall performance of the chip.

[0031] Referring to Figure 2 , which schematically illustrates the structure of a context-based cache control device according to one exemplary embodiment of the present disclosure. Figure 1 As shown in Figure 2 , the cache control device 121 can include an instruction management module 121a and an instruction processing module 121b. The instruction management module 121a can be configured to: receive a cache operation instruction and a context number corresponding to the cache operation instruction; allow the cache operation instruction to be issued when there is no cache operation instruction being processed or when there is a cache operation instruction being processed and the context number corresponding to the cache operation instruction being processed is different from the context number corresponding to the cache operation instruction; and block the cache operation instruction when there is a cache operation instruction being processed and the context number corresponding to the cache operation instruction being processed is the same as the context number corresponding to the cache operation instruction. In addition, in the case where there is a cache operation instruction being processed and the context number corresponding to the cache operation instruction being processed is the same as the context number corresponding to the cache operation instruction, the instruction management module 121a will stop blocking the cache operation instruction when the cache operation instruction being processed has been processed. The instruction processing module 121b can be configured to: receive the cache operation instruction issued from the instruction management module 121a, and perform a cache operation according to the issued cache operation instruction and the context number corresponding thereto. The instruction processing module 121b can process cache operation instructions corresponding to all context numbers, that is, it can receive and process cache operation instructions corresponding to different context numbers. Thus, the instruction processing module 121b can improve the bandwidth of instruction processing.

[0032] Referring to Figure 3 , which schematically illustrates Figure 2 the details of the structure of the context-based Cache control apparatus according to one exemplary embodiment of the present disclosure. As Figure 3 shown, the instruction management module 121a can include a context management unit 121a-1 and an instruction issue logic judging unit 121a-2. The context management unit 121a-1 can be configured to store the context number corresponding to the Cache operation instruction in the process. That is, when the instruction management module 121a issues the Cache operation instruction to the instruction processing module 121b, the context number cur_CTXT-ID corresponding to the Cache operation instruction can be stored in the context management unit 121a-1, whereby it can be recorded that the address corresponding to the context number cur_CTXT-ID in the Cache 120 is being operated. Accordingly, when the Cache operation instruction corresponding to the context number cur_CTXT-ID is processed, the context management unit 121a-1 can delete the context number cur_CTXT-ID, so that other Cache operation instructions with the same context number can no longer be blocked. The instruction issue logic judging unit 121a-2 can be configured to compare the context number corresponding to the Cache operation instruction with the context number corresponding to the Cache operation instruction in the process obtained from the context management unit, and when the two are the same, block the Cache operation instruction, and when the two are different, allow the Cache operation instruction to be issued to the instruction processing module. As Figure 3 shown, when there is no context number cur_CTXT-ID (i.e., there is no operation instruction currently operating on the Cache 120 being processed), or when the context number CTXT-ID corresponding to the Cache operation instruction is not equal to the context number cur_CTXT-ID corresponding to the Cache operation instruction in the process obtained from the context management unit 121a-1 (i.e., Cache operation is being performed on the address corresponding to a different context number in the Cache 120), the Cache operation instruction and the corresponding context number CTXT-ID can be issued to the instruction processing module 121b for processing. And if the context number CTXT-ID corresponding to the Cache operation instruction is equal to the context number cur_CTXT-ID corresponding to the Cache operation instruction in the process obtained from the context management unit 121a-1, the instruction issue logic judging unit 121a-2 will block the Cache operation instruction (e.g., an instruction blocking signal STALL can be sent to the instruction scheduling unit 111).

[0033] In one example embodiment, the Cache operation instruction can be a data flush operation instruction indicating a data flush operation on the Cache 120. In this case, the instruction processing module 121b can perform the data flush operation on addresses with the same context number cur_CTXT-ID based on the context, while the context number cur_CTXT-ID can be stored in the context management unit 121a-1 to block subsequent Cache operation instructions corresponding to the same context number, but not to block Cache operation instructions corresponding to different context numbers. Thus, the instruction processing module 121b can process the data flush operation instruction and Cache operation instructions corresponding to different context numbers at the same time, so as to improve the processor bandwidth during the data flush operation.

[0034] In one example embodiment, the Cache operation instruction can be a data flush operation instruction indicating a data flush operation on the Cache. In this case, the instruction processing module 121b can further be configured to: when the received and processed Cache operation instruction is a data flush operation instruction indicating a data flush operation on the Cache, count the number of Cache operation instructions corresponding to the same context number as the data flush operation instruction but not yet completed processing; in response to each of the Cache operation instructions not yet completed processing being processed, decrement the number by one; and when the number becomes zero, inform the instruction management module to unblock the Cache operation instructions with the context number corresponding to the data flush operation instruction.

[0035] In one example embodiment, the instruction processing module 121b can further include a counter configured to: count the number of Cache operation instructions corresponding to the same context number as the data flush operation instruction but not yet completed processing; and in response to each of the Cache operation instructions not yet completed processing being processed, decrement the number by one.

[0036] Referring to Figure 4 which schematically shows a process of performing a data flush operation by the context-based Cache control apparatus according to an example embodiment of the present disclosure, the state transition shown in the state transition diagram can be applied to the context-based Cache control apparatus 121.

[0037] As Figure 4As shown, the state machine 300 includes a standby state 310, a running state 320 and a sending state 330. In the standby state 310, the Cache control device 121 has not received the data synchronization operation instruction and is in an idle state. In the running state 320, the Cache control device 121 processes the Cache operation instruction which has not been completed when the data synchronization operation instruction is received. In the sending state 330, the Cache control device 121 has completed the data synchronization operation and sends a response signal.

[0038] Specifically, the transition between each state can be as follows:

[0039] Transition from the standby state 310 to the running state 320: the condition for this state transition is receiving the data synchronization operation instruction. Accordingly, the Cache control device 121 will perform the following actions: determining that the data synchronization operation instruction can be issued and processed, counting the number of other Cache operation instructions which have been issued but not completed processing corresponding to the context number of the data synchronization operation instruction, and activating the blocking of any subsequent Cache operation instruction corresponding to the context number of the data synchronization operation instruction.

[0040] Transition from the running state 320 to the sending state 330: the condition for this state transition is that the counted number of instructions becomes zero. After starting to process the data synchronization operation instruction, the Cache control device 121 will continue to process the counted Cache operation instructions which have not been completed processing, and each time a response signal of a processed Cache operation instruction is received, the counted number of instructions is reduced by one. When the number of instructions becomes zero, it means that the counted Cache operation instructions have all been processed, so the data synchronization operation is completed. Accordingly, the Cache control device 121 will perform the following actions: generating a response signal of the context number and sending it to the response message queue for subsequent processing.

[0041] Transition from the sending state 330 to the standby state 310: the condition for this state transition is that the response signal of the context number is sent out through the corresponding interface (for example, to the instruction scheduling unit 111). The response signal being sent out through the corresponding interface means that the upstream chip kernel is reported that the data synchronization operation has been completed. Accordingly, the Cache control device 121 will perform the following actions: releasing the blocking of any subsequent Cache operation instruction corresponding to the context number of the data synchronization operation instruction.

[0042] It should be understood that, Figure 4The state transition shown is merely exemplary and is not restrictive. Therefore, any other suitable state transition procedure is possible as long as it can implement the data synchronization operation procedure described in the present disclosure, and the present disclosure does not limit this. In this way, the context-based Cache control apparatus 121 according to the present disclosure can improve the system bandwidth when performing data synchronization operations, thereby improving the overall performance of the chip.

[0043] Referring to Figure 5 which schematically shows a context-based Cache control method according to an exemplary embodiment of the present disclosure in the form of a flowchart, which can be applied to the Cache control apparatus according to the present disclosure. As Figure 5 shown, the Cache control method 500 includes the following steps:

[0044] At step 510, a Cache operation instruction and a context number corresponding to the Cache operation instruction are received;

[0045] At step 520, when there is no Cache operation instruction under processing or when there is a Cache operation instruction under processing and the context number corresponding to the Cache operation instruction under processing is different from the context number corresponding to the Cache operation instruction, the Cache operation instruction is allowed to be issued;

[0046] At step 530, when there is a Cache operation instruction under processing and the context number corresponding to the Cache operation instruction under processing is the same as the context number corresponding to the Cache operation instruction, the Cache operation instruction is blocked.

[0047] It should be understood that the above method steps do not necessarily have to be executed in the order described in the present disclosure, but can be executed in different orders, for example, they can be executed simultaneously, or in reverse order, or individual steps can not be executed, as long as they do not contradict the principles of the technical solution described in the present disclosure.

[0048] In this way, the context-based Cache control method 500 according to the present disclosure can improve the system bandwidth when performing Cache operations, thereby improving the overall performance of the chip.

[0049] Figure 6 which schematically shows a context-based Cache control method according to another exemplary embodiment of the present disclosure in the form of a flowchart. Compared with Figure 5 the Cache control method 500 shown in Figure 6The Cache control method 500a shown differs in that it further comprises a step 540 of, for a Cache operation instruction issued, operating the Cache according to the issued Cache operation instruction and its corresponding context number.

[0050] In some example embodiments, the issued Cache operation instruction can be a data refresh operation instruction indicating a data refresh operation on the Cache. In this case, the step 540 can further comprise a step of performing a data refresh operation on all addresses in the Cache having the context number corresponding to the data refresh operation instruction.

[0051] In other example embodiments, the issued Cache operation instruction can be a data synchronization operation instruction indicating a data synchronization on the Cache. In this case, the step 540 can further comprise the following steps: when the issued Cache operation instruction is the data synchronization operation instruction indicating a data synchronization on the Cache, counting the number of Cache operation instructions corresponding to the context number corresponding to the data synchronization operation instruction that have been issued for processing but no response signal has been received; in response to receiving each response signal, decreasing the number by one; and when the number becomes zero, unblocking the Cache operation instructions having the context number corresponding to the data synchronization operation instruction.

[0052] In this way, the context-based Cache control method according to the present disclosure can improve the system bandwidth when performing Cache operations (which can include data refresh operations or data synchronization operations), thereby improving the overall performance of the chip.

[0053] Referring to Figure 7 , a structure of a chip according to example embodiments of the present disclosure is schematically shown in the form of a block diagram. As shown in Figure 7 , the chip 700 can comprise a chip core 710 and a Cache 720. The chip core 710 and the Cache 720 can each be of any suitable type, which is not limited by the present disclosure. The Cache 720 can further comprise a context-based Cache control device 721, which can be implemented as any Cache control device described in the embodiments of the present disclosure. Thus, the chip 700 can improve the system bandwidth when performing Cache operations (which can include data refresh operations or data synchronization operations), make full use of hardware resources, and thereby improve the overall performance of the chip. In addition, in some example embodiments, the chip 700 can be implemented as a GPU chip or an NPU chip, etc. Figures 1 to 4 In this way, the context-based Cache control method according to the present disclosure can improve the system bandwidth when performing Cache operations (which can include data refresh operations or data synchronization operations), thereby improving the overall performance of the chip.

[0054] The terminology used in the present disclosure is only for the purpose of describing embodiments in the present disclosure and is not intended to limit the present disclosure. As used in the present disclosure, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and "comprising," when used in this specification, specify the presence of stated features, but do not preclude the presence or addition of one or more other features. As used in the present disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood that, although the terms "first," "second," "third," etc. can be used herein to describe various features, these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used in the present disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present specification, and will not be interpreted in an idealized or overly formal sense unless expressly so defined in the present disclosure.

[0056] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" or the like means that the specific feature, structure, material or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. Descriptive expressions of the above terms in the present specification do not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. Furthermore, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples, or can omit some technical features from the different embodiments or examples described in the present specification, and the embodiments or examples obtained based on such combination, combination or omission are also considered to fall within the scope of the present disclosure.

[0057] The methods described in the present disclosure include one or more steps or actions. The method steps and / or actions need not be performed in the order described in the present disclosure, but can be performed in different orders, for example, they can be performed simultaneously or in reverse order, as long as the principles of the technical solutions described in the present disclosure are not contradicted. In addition, according to actual needs, the steps or actions in the methods described in the present disclosure can be replaced by different steps or actions, or additional steps or actions can also be included.

[0058] Although the present disclosure has been described in detail in conjunction with some exemplary embodiments, it is not limited to the specific forms described in the present disclosure. Instead, the scope of the present disclosure is only limited by the appended claims.

Claims

1. A context-based cache control apparatus, characterized by comprising: The application comprises: an instruction management module configured to: receive a Cache operation instruction and a context number corresponding to the Cache operation instruction; when there is no Cache operation instruction under processing or when there is a Cache operation instruction under processing and the context number corresponding to the Cache operation instruction under processing is different from the context number corresponding to the Cache operation instruction, allow the Cache operation instruction to be issued; when there is a Cache operation instruction under processing and the context number corresponding to the Cache operation instruction under processing is the same as the context number corresponding to the Cache operation instruction, block the Cache operation instruction; an instruction processing module configured to: receive the Cache operation instruction issued from the instruction management module, and operate on the Cache according to the issued Cache operation instruction and the context number corresponding to the issued Cache operation instruction.

2. The context-based cache control apparatus of claim 1, wherein, The instruction management module comprises: a context management unit configured to: store the context number corresponding to the Cache operation instruction under processing; an instruction issuing logic judgment unit configured to: compare the context number corresponding to the Cache operation instruction with the context number corresponding to the Cache operation instruction under processing obtained from the context management unit, and when they are the same, block the Cache operation instruction, and when they are different, allow the Cache operation instruction to be issued to the instruction processing module.

3. The context-based cache control apparatus of claim 2, wherein, The context management unit is further configured to: in response to the Cache operation instruction under processing being processed by the instruction processing module, delete the context number corresponding to the Cache operation instruction under processing.

4. The context-based cache control apparatus according to any one of claims 1 to 3, wherein The instruction processing module is further configured to: when the received and processed Cache operation instruction is a data refresh operation instruction indicating a data refresh operation on the Cache, perform a data refresh operation on all addresses with the context number corresponding to the data refresh operation instruction in the Cache.

5. The context-based cache control apparatus of claim 1, wherein, The instruction processing module is further configured to: when the received and processed Cache operation instruction is a data synchronization operation instruction indicating a data synchronization on the Cache, count the number of Cache operation instructions with the same context number as the context number corresponding to the data synchronization operation instruction but not yet completed processing; in response to each of the Cache operation instructions not yet completed processing being processed, decrease the number by one; when the number becomes zero, notify the instruction management module to unblock the Cache operation instruction with the context number corresponding to the data synchronization operation instruction.

6. The context-based cache control apparatus of claim 5, wherein, The instruction processing module further comprises a counter configured to: count the number of Cache operation instructions with the same context number as the context number corresponding to the data synchronization operation instruction but not yet completed processing; in response to each of the Cache operation instructions that has not been completed being processed, decrementing the instruction number by one.

7. A context-based cache control method, characterized by, comprising: receiving a Cache operation instruction and a context number corresponding to the Cache operation instruction; when there is no Cache operation instruction being processed or when there is a Cache operation instruction being processed and the context number corresponding to the Cache operation instruction being processed is different from the context number corresponding to the Cache operation instruction, allowing the Cache operation instruction to be issued; when there is a Cache operation instruction being processed and the context number corresponding to the Cache operation instruction being processed is the same as the context number corresponding to the Cache operation instruction, blocking the Cache operation instruction.

8. The context-based cache control method of claim 7, wherein, further comprising: for the issued Cache operation instruction, operating on the Cache according to the issued Cache operation instruction and the context number corresponding to the issued Cache operation instruction.

9. The context-based cache control method of claim 8, wherein, the operating on the Cache according to each Cache operation instruction and the context number corresponding to each Cache operation instruction in sequence includes: when the issued Cache operation instruction is a data refresh operation instruction indicating a data refresh operation on the Cache, performing a data refresh operation on all addresses in the Cache having the context number corresponding to the data refresh operation instruction.

10. The context-based cache control method of claim 8, wherein, the operating on the Cache according to each Cache operation instruction and the context number corresponding to each Cache operation instruction in sequence includes: when the issued Cache operation instruction is a data synchronization operation instruction indicating a data synchronization on the Cache, counting the instruction number of Cache operation instructions corresponding to the context number corresponding to the data synchronization operation instruction that have been issued for processing but have not received a response signal; in response to receiving one response signal, decrementing the instruction number by one; when the instruction number becomes zero, unblocking the Cache operation instruction having the context number corresponding to the data synchronization operation instruction.

11. A chip comprising the context-based Cache control apparatus according to any one of claims 1 to 6.

12. The chip of claim 11, wherein, The chip is a GPU chip or an NPU chip.

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