Communication system, communication method and communication device

Abstract

The invention provides a communication system, a communication method and communication equipment, belongs to the technical field of communication, and can solve the problem that a plurality of host equipment cannot be connected and communicated with one slave equipment at the same time in the existing communication system. The communication system comprises a plurality of host devices and at least one slave device, wherein the host devices communicate with the slave device through an SPI bus; wherein the communication system further comprises at least one interconnection module which is configured to receive a communication instruction sent by the host device to be communicated and detect the port state of the chip selection signal receiving end of the slave device; and in response to the condition that the port state is an idle state, gating a chip selection signal receiving end of the slave equipment and a chip selection signal transmitting end of the to-be-communicated host equipment, so that the to-be-communicated host equipment communicates with the corresponding slave equipment through an SPI (Serial Peripheral Interface) bus. According to the invention, multiple host devices can be simultaneously connected and communicated with one slave device based on the SPI bus.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of communication, and particularly relates to a communication system, a communication method and a communication device. BACKGROUND

[0002] Serial Peripheral Interface (SPI) is a high-speed, full-duplex communication bus. Due to the simplicity, low component, and high speed of the SPI interface, it is widely used in various digital electronic devices, mainly for data transmission, network communication, and interface control between the master device and the peripheral device. The SPI host can be connected with multiple SPI slaves for communication, but due to the defects of the SPI protocol, it cannot realize the communication between multiple SPI hosts and the same SPI slave. However, in some use scenarios, there are multiple hosts that need to communicate with the same or multiple slaves, which limits the application of the SPI interface. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a communication system, a communication method, and a communication device for communication between multiple host devices and at least one slave device.

[0004] In a first aspect, a technical solution for solving the technical problems of the present disclosure is a communication system, including multiple host devices and at least one slave device, the host devices being in communication with the slave devices through an SPI bus; wherein,

[0005] The communication system further includes at least one interconnection module configured to receive a communication instruction sent by a host device to be communicated, and detect the port state of the chip select signal receiving end of the slave device.

[0006] The interconnection module is further configured to, in response to the port state being an idle state, gate the chip select signal receiving end of the slave device and the chip select signal sending end of the host device to be communicated, so that the host device to be communicated communicates with its corresponding slave device through the SPI bus.

[0007] In some embodiments, the communication system includes multiple interconnection modules corresponding one-to-one to the host devices, and the interconnection module includes at least one first control circuit, a second control circuit, and a third control circuit.

[0008] For the corresponding setting of the host device and the interconnection module, the chip selection signal sending end of the host device is connected with the input end of the first control circuit, the output end of the first control circuit is connected with the chip selection signal receiving end of the slave device through the SPI bus, and the chip selection signal receiving end of the host device is connected with the output end of the first control circuit; the second data sending end of the host device and the chip selection signal sending end of the host device are both connected with the input end of the second control circuit, the output end of the second control circuit is connected with the second data receiving end of the slave device through the SPI bus; the clock signal sending end of the host device and the chip selection signal sending end of the host device are both connected with the input end of the third control circuit, the output end of the third control circuit is connected with the clock signal receiving end of the slave device through the SPI bus;

[0009] The first control circuit is configured to detect the voltage of the chip selection signal receiving end of the host device to be communicated, determine the port state of the chip selection signal receiving end of the slave device as an idle state in response to the chip selection signal receiving end of the host device to be communicated being a first voltage, and send the port state to the host device to be communicated; and receive the second voltage sent by the chip selection signal sending end of the host device to be communicated, and control the chip selection signal sending end of the host device to be communicated and the chip selection signal receiving end of the slave device to be gated.

[0010] The second control circuit is configured to control the second data sending end of the host device to be communicated and the second data receiving end of the slave device to be gated in response to the chip selection signal sending end of the host device to be communicated being a second voltage.

[0011] The third control circuit is configured to control the clock signal sending end of the host device to be communicated and the clock signal receiving end of the slave device to be gated in response to the chip selection signal sending end of the host device to be communicated being a second voltage.

[0012] In some embodiments, the communication system includes a plurality of slave devices, for the corresponding setting of the host device and the interconnection module, the host device includes a plurality of chip selection signal sending ends, and the chip selection signal sending ends are one-to-one corresponding to the slave devices; the interconnection module includes a plurality of first control circuits, one chip selection signal sending end is connected with the input end of one first control circuit; the output ends of a plurality of first control circuits are connected with the chip selection signal receiving end of the host device through a first AND gate;

[0013] The chip selection signal receiving end of the host device is configured to be a first voltage in response to the plurality of chip selection signal sending ends of the host device being the first voltage.

[0014] The plurality of chip select signal transmitting ends of the host device are also connected with the input ends of the second control circuit and the third control circuit through a second AND gate respectively,

[0015] The second control circuit is specifically configured to control the second data transmitting end of the host device to be communicated and the second data receiving end of the slave device to be gated in response to the plurality of chip select signal transmitting ends of the host device being the second voltage.

[0016] The third control circuit is specifically configured to control the clock signal transmitting end of the host device to be communicated and the clock signal receiving end of the slave device to be gated in response to the plurality of chip select signal transmitting ends of the host device being the second voltage.

[0017] In some embodiments, the first control circuit is an open-drain output circuit, and for the corresponding setting of the host device and the interconnection module, the input end of the open-drain output circuit is connected with the chip select signal transmitting end of the host device, and the output end of the open-drain output circuit is connected with the chip select signal receiving end of the slave device and the chip select signal receiving end of the host device through the SPI bus.

[0018] In some embodiments, the second control circuit is a first tri-state output circuit, and for the corresponding setting of the host device and the interconnection module, the input end of the first tri-state output circuit is connected with the second data transmitting end of the host device, and the control end of the first tri-state output circuit is connected with the chip select signal transmitting end of the host device through a first inverter; the output end of the first tri-state output circuit is connected with the second data receiving end of the slave device through the SPI bus.

[0019] The control end of the first tri-state output circuit is configured to control the second data transmitting end of the host device to be communicated and the second data receiving end of the slave device to be gated in response to the chip select signal transmitting end of the host device to be communicated being the second voltage.

[0020] In some embodiments, the third control circuit is a second tri-state output circuit, and for the corresponding setting of the host device and the interconnection module, the input end of the second tri-state output circuit is connected with the clock signal transmitting end of the host device, the control end of the second tri-state output circuit is connected with the chip select signal transmitting end of the host device through a second inverter, and the output end of the second tri-state output circuit is connected with the clock signal receiving end of the slave device through the SPI bus.

[0021] The control end of the second tri-state output circuit is configured to control the clock signal sending end of the host device to be communicated and the clock signal receiving end of the slave device to be selected in response to the clock signal sending end of the host device to be communicated being at a second voltage.

[0022] In some embodiments, the communication system comprises an interconnection module, the interconnection module comprising a first multiplexer, a second multiplexer, a third multiplexer, at least one fourth multiplexer, and a sub-control module; wherein,

[0023] The input end of the first multiplexer is connected to the clock signal output end of each host device, the input end of the second multiplexer is connected to the second data sending end of each host device, the output end of the third multiplexer is connected to the first data receiving end of each host device, and the input end of the fourth multiplexer is connected to the chip select signal sending end of each host device, configured to select one host device from each host device as a host device to be communicated to communicate with a slave device.

[0024] The input end of the third multiplexer is connected to a plurality of state ends in the sub-control module corresponding to each host device, and the third multiplexer is configured to receive a communication instruction sent by the host device to be communicated and detect the plurality of state ends to determine the port state of the chip select signal receiving end of the slave device.

[0025] The selection end of the first multiplexer, the second multiplexer, the third multiplexer, and the fourth multiplexer is connected to the data selection communication signal end of the sub-control module, and the sub-control module is configured to control the chip select signal sending end of the host device to be communicated and the chip select signal receiving end of the corresponding slave device to be selected in response to the port state being an idle state, so that the host device to be communicated communicates with the corresponding slave device through the SPI bus.

[0026] In some embodiments, the communication system comprises a plurality of slave devices, each host device comprises a plurality of chip select signal sending ends, and the chip select signal sending ends are arranged one-to-one corresponding to the slave devices, and the interconnection module comprises a plurality of fourth multiplexers corresponding one-to-one to the chip select signal sending ends of one host device; wherein,

[0027] The input end of one fourth multiplexer is connected to each chip select signal sending end of each host device connected to the same slave device.

[0028] In a second aspect, the embodiments of the present disclosure further provide a communication method, the method being used in a communication system, and the method comprising:

[0029] The interconnection module receives a communication instruction sent by a host device to be communicated, detects a signal of a chip select signal receiving end of the host device to be communicated;

[0030] In response to the chip select signal receiving end being the first voltage, a chip select signal sending end of the host device to be communicated outputs a second voltage, and the interconnection module selects and enables the chip select signal sending end of the host device to be communicated and a chip select signal receiving end of a corresponding slave device, so that the host device to be communicated communicates with the corresponding slave device through an SPI bus.

[0031] In a third aspect, the embodiments of the present disclosure further provide another communication method, which is used in a communication system, and the method comprises:

[0032] The chip select signal sending end of the host device to be communicated outputs a second voltage;

[0033] The interconnection module receives the second voltage output by the chip select signal sending end of the host device, and detects a port state of the chip select signal receiving end of the slave device;

[0034] In response to the port state of the chip select signal receiving end of the slave device being an idle state, the interconnection module selects and enables the host device to be communicated and the slave device to communicate.

[0035] In a fourth aspect, the embodiments of the present disclosure further provide a communication device comprising the communication system in any one of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A schematic diagram of SPI single-host and multi-slave communication connection in the prior art;

[0037] Figure 2 A schematic diagram of a communication system provided by the embodiments of the present disclosure;

[0038] Figure 3 A schematic diagram of a connection between a host device Master and an interconnection module MUX provided by the embodiments of the present disclosure;

[0039] Figure 4 A schematic diagram of communication connection between two host devices Master and one slave device Slave provided by the embodiments of the present disclosure;

[0040] Figure 5 A schematic diagram of communication connection between two host devices Master and two slave devices Slave provided by the embodiments of the present disclosure;

[0041] Figure 6 A schematic diagram of another connection between a host device Master and an interconnection module MUX provided by the embodiments of the present disclosure;

[0042] Figures 7-9 Schematic diagrams of a first control circuit, a second control circuit and a third control circuit provided by embodiments of the present disclosure, respectively;

[0043] Figure 10 An interface schematic diagram of another interconnection module provided by embodiments of the present disclosure;

[0044] Figures 11-12 Circuit structure schematic diagrams of two interconnection modules provided by embodiments of the present disclosure;

[0045] Figures 13-14 Schematic diagrams of two host devices interconnected with slave devices through interconnection modules provided by embodiments of the present disclosure;

[0046] Figure 15 A communication method provided by embodiments of the present disclosure;

[0047] Figure 16 A communication method provided by embodiments of the present disclosure;

[0048] Figures 17-18 Interface signal timing schematic diagrams corresponding to each interface of two interconnection modules MUX provided by embodiments of the present disclosure, respectively. DETAILED DESCRIPTION

[0049] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below in conjunction with the drawings and specific embodiments.

[0050] Unless otherwise defined, technical or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second" and similar terms used in the present disclosure do not indicate any order, number or importance, but are only used to distinguish different components. Similarly, the terms "one", "an" or "the" and similar terms do not indicate a quantity limitation, but indicate the presence of at least one. The terms "include" or "contain" and similar terms mean that the elements or objects before the term encompass the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "up", "down", "left", "right" and the like only indicate relative positional relationships, which may change when the absolute positions of the described objects change.

[0051] The SPI bus is a synchronous serial interface technology. The SPI bus realizes communication between a master device and a slave device through four interface signals, including four bus signal lines, namely:

[0052] SCK (Serial Clock): a clock signal line, transmitted from the master device to the slave device, used for data synchronization; MOSI (Master Output Slave Input): a master device output signal and a slave device input signal, used for the SPI master device to transmit data; MISO (Master Input Slave Output): a master device input signal and a slave device output signal, used for the SPI master device to receive data; SS / CS (Slave Select / Chip Select): a slave device selection signal, a chip selection signal transmitted from the SPI master device.

[0053] In the prior art, the master device and the slave device each include four interface ends connected to the four bus signal lines. The four interface ends of the master device / slave device are used to output or receive interface signals, and the four interface signals are transmitted through the four bus signal lines to realize communication between the master device and the slave device. In addition, the master device can have multiple SS signal ends, and multiple SS signals are output through the SPI bus to realize communication with multiple SPI slave devices. Each SS signal corresponds to a slave device. Figure 1 A schematic diagram of communication connection between a single SPI master device and multiple slave devices in the prior art is shown in FIG. 1. Figure 1 As shown in FIG. 1, the master device Master communicates with the first slave device Slave1 and the second slave device Slave2 through the SPI bus (including SCK, MISO, MOSI, and two SS signal lines (SS_1 and SS_2)). When the SPI master device Master needs to communicate with a certain slave device Slave, the SS signal output by the chip selection signal transmission end of the master device Master is pulled low (the SS signal is usually at a high level by default). However, since the bus signal line of the SPI is unidirectional output, multiple master devices Master cannot be simultaneously connected to the same slave device Slave through the SPI bus.

[0054] Therefore, the embodiment of the present disclosure provides a communication system. Figure 2 A schematic diagram of a communication system provided by the embodiment of the present disclosure is shown in FIG. 2. Figure 2The communication system includes multiple master devices and at least one slave device. The master devices communicate with the slave devices via an SPI bus. The system also includes at least one interconnect module (MUX), configured to receive communication commands from the master devices and detect the port status of the chip select signal receiver (SS_IN) of the slave device. The MUX is further configured to, in response to an idle port status, enable communication between the slave device's chip select signal receiver (SS_IN) and the master device's chip select signal transmitter (SS_OUT), allowing the master device to communicate with its corresponding slave device via the SPI bus.

[0055] Specifically, such as Figure 2 As shown, each master device includes a clock signal transmitter SCK_OUT, a first data receiver MISO_IN, a second data transmitter MOSI_OUT, and at least one chip select signal transmitter SS_OUT. Each slave device includes a clock signal receiver SCK_IN, a first data transmitter MISO_OUT, a second data receiver MOSI_IN, and a chip select signal receiver SS_IN. Specifically, the clock signal transmitter SCK_OUT outputs a clock signal and sends it to the clock signal receiver SCK_IN via the SCK line of the SPI bus; the first data receiver MISO_IN receives the first signal output by the first data transmitter MISO_OUT via the MISO line of the SPI bus; the second data transmitter MOSI_OUT outputs a second signal and sends it to the second data receiver MOSI_IN via the MOSI line of the SPI bus; and the chip select signal transmitter SS_OUT outputs a chip select signal SS via the SS line of the SPI bus.

[0056] From the perspective of the SPI bus protocol, the master device can control its chip select signal transmitter SS_OUT to send a chip select signal to the slave device, thus enabling communication with the slave device. Since the SPI bus is unidirectional, the slave device only has one chip select signal receiver SS_IN, and can only communicate with one master device at a time. Therefore, existing communication systems cannot connect multiple master devices to the same slave device via the SPI bus.

[0057] The communication system provided by the embodiments of the present disclosure can detect the port state of the chip select signal receiving end SS IN of the slave device through the interconnection module MUX, so that the master device to be communicated can determine whether it can communicate with the slave device based on the port state of the chip select signal receiving end SS IN of the slave device. When the chip select signal receiving end SS IN of the slave device is occupied, the slave device cannot communicate with other master devices. Based on this, the interconnection module MUX determines whether to select the chip select signal receiving end SS IN of the slave device and the chip select signal sending end SS OUT of the master device to be communicated, so that the master device to be communicated can communicate with the corresponding slave device through the SPI bus. In this way, multiple master devices can be connected to the same slave device.

[0058] In the communication system provided by the embodiments of the present disclosure, the interconnection module MUX can be configured in different ways. The specific structure of the interconnection module MUX will be described below with respect to embodiments 1 and 2.

[0059] Embodiment 1,

[0060] The embodiments of the present disclosure provide a communication system, which includes multiple master devices Master, at least one slave device Slave, and multiple interconnection modules MUX corresponding to the master devices Master. The master devices Master communicate with the slave device Slave through the SPI bus. Each interconnection module MUX is configured to detect the port state of the chip select signal receiving end SS IN of the slave device Slave and control the corresponding master device Master to communicate with the slave device Slave.

[0061] Figure 3 A schematic diagram of a master device Master connected to an interconnection module MUX is provided for the embodiments of the present disclosure; wherein, Figure 3 Only a master device Master including one chip select signal sending end SS OUT is taken as an example for description. Figure 4 A schematic diagram of two master devices Master and one slave device Slave in communication is provided for the embodiments of the present disclosure. Figure 5 A schematic diagram of two master devices Master and two slave devices Slave in communication is provided for the embodiments of the present disclosure. Figure 6 A schematic diagram of a master device Master connected to an interconnection module MUX is provided for the embodiments of the present disclosure; wherein, Figure 6The explanation will focus on the host device, which includes two chip select signal transmitters, SS_OUT.

[0062] like Figure 3 As shown, the interconnect module MUX includes a first control circuit 1, a second control circuit 2, and a third control circuit 3. For the corresponding master device Master and interconnect module MUX, the chip select signal transmitting terminal SS_OUT of the master device Master is connected to the input terminal of the first control circuit 1, and the output terminal of the first control circuit 1 is connected to the chip select signal receiving terminal SS_IN of the slave device Slave via the SPI bus (specifically the SS line of the SPI bus). The chip select signal receiving terminal SS_IN of the master device Master is connected to the output terminal of the first control circuit 1. The second data transmitter MOSI_OUT and the chip select signal transmitter SS_OUT of the master device are both connected to the input of the second control circuit 2. The output of the second control circuit 2 is connected to the second data receiver MOSI_IN of the slave device via the SPI bus (specifically, the MOSI line in the SPI bus). The clock signal transmitter SCK_OUT and the chip select signal transmitter SS_OUT of the master device are both connected to the input of the third control circuit 3. The output of the third control circuit 3 is connected to the clock signal receiver SCK_IN of the slave device via the SPI bus (specifically, the SCK line in the SPI bus).

[0063] The first control circuit 1 is configured to detect the voltage of the chip select signal receiving terminal SS_IN of the master device to be communicated with; in response to the first voltage of the chip select signal receiving terminal SS_IN of the master device to be communicated with, determine that the port state of the chip select signal receiving terminal SS_IN of the slave device is idle, and send the port state to the master device to be communicated with; and receive the second voltage sent by the chip select signal transmitting terminal SS_OUT of the master device to be communicated with, and control the chip select signal transmitting terminal SS_OUT of the master device to be communicated with to be connected to the chip select signal receiving terminal SS_IN of the slave device.

[0064] The second control circuit 2 is configured to control the second data transmission terminal MOSI_OUT of the master device to be communicated to be selected and the second data reception terminal MOSI_IN of the slave device when the chip select signal transmission terminal SS_OUT of the master device to be communicated is a second voltage.

[0065] The third control circuit 3 is configured to control the clock signal sending end SCK_OUT of the host device Master to be communicated and the clock signal receiving end SCK_IN of the slave device Slave to be gated in response to the chip select signal sending end SS_OUT of the host device Master to be communicated being the second voltage.

[0066] Specifically, when multiple host devices Master are connected to the same slave device Slave through the SPI bus, the multiple host devices Master are connected to the same SPI bus through the corresponding interconnection module MUX of each host device Master, so as to realize communication with the slave device Slave. When any host device Master among the multiple host devices Master connected to the slave device Slave is ready for communication, that is, the interconnection module MUX corresponding to the host device Master receives a communication instruction, the first control circuit 1 needs to detect whether the chip select signal sending end SS_OUT of the slave device Slave is in an idle state. Only when the chip select signal sending end SS_OUT of the slave device Slave is in the idle state, the host device Master ready for communication can communicate with the slave device Slave. Since the chip select signal receiving end SS_IN of the host device Master and the chip select signal receiving end SS_IN of the slave device Slave are connected to the same signal end (that is, both are connected to the output end of the first control circuit 1), the chip select signal receiving end SS_IN of the host device Master and the chip select signal receiving end SS_IN of the slave device Slave receive the same signal. Therefore, the first control circuit 1 can determine whether the chip select signal receiving end SS_IN of the slave device Slave is in the idle state by detecting the chip select signal receiving end SS_IN of the host device Master.

[0067] The first voltage can be a high-level voltage, and the second voltage can be a low-level voltage. Generally, the chip select signal ss is high level. When the chip select signal ss is low level, the host device Master can communicate with the slave device Slave. When the first control circuit 1 detects that the chip select signal receiving end SS_IN of the host device Master is a high-level voltage, it indicates that the chip select signal receiving end SS_IN of the slave device Slave is in an idle state. The first control circuit 1 sends the idle state to the host device Master. After the host device Master receives the idle state, the chip select signal sending end SS_OUT of the host device Master sends a low-level voltage chip select signal ss. After the first control circuit 1 receives the low-level voltage chip select signal ss, the chip select signal sending end SS_OUT of the host device Master and the chip select signal receiving end SS_IN of the slave device Slave are gated.

[0068] Meanwhile, the second control circuit 2 receives the low voltage of the chip selection signal sending end SS_OUT of the host device Master, controls the second data sending end MOSI_OUT of the host device Master to be communicated and the second data receiving end MOSI_IN of the slave device Slave, so that the host device Master sends the second data to the slave device Slave; the third control circuit 1 receives the low voltage of the chip selection signal sending end SS_OUT of the host device Master, controls the clock signal sending end SCK_OUT of the host device Master to be communicated and the clock signal receiving end SCK_IN of the slave device Slave, so that the host device Master sends the clock signal to the slave device Slave, thereby realizing the communication between the host device Master and the slave device Slave.

[0069] In addition, according to the SPI protocol, one host device Master can communicate with only one slave device Slave (as shown in Figure 3 ), and one host device Master can also communicate with multiple slave devices Slave (as shown in Figure 4 ). In other words, the number of the chip selection signal sending end SS_OUT in the host device Master can be one or multiple, and the number of the chip selection signal sending end SS_OUT in the host device Master can be set according to the number of the slave devices Slave corresponding to the communication of the host device Master. As shown in Figures 4-5 , and in Figure 4 and Figure 5 , each slave device Slave is connected with multiple (both Figure 4 and Figure 5 take 2 as an example for description) host devices Master.

[0070] In the case that one host device Master is connected with only one slave device Slave, and multiple host devices Master are connected with the same slave device Slave, the interconnection module MUX includes a first control circuit 1, each host device Master includes a chip selection signal sending end SS_OUT, and the chip selection signal sending end SS_OUT is connected with the input end of the first control circuit 1.

[0071] In a case where one master device Master is connected with multiple slave devices Slave, and multiple master devices Master are connected with the same slave device Slave. In some embodiments, the communication system includes multiple slave devices Slave, for the corresponding set of master devices Master and interconnection module MUX, the master device Master includes multiple chip select signal sending ends SS_OUT, and the chip select signal sending ends SS_OUT are one-to-one set with the slave devices Slave; the interconnection module MUX includes multiple first control circuits 1, one chip select signal sending end SS_OUT is connected with the input end of one first control circuit 1; the output ends of the multiple first control circuits 1 are connected with the chip select signal receiving end SS_IN of the master device Master through a first AND gate. The chip select signal receiving end SS_IN of the master device Master is configured to be the first voltage in response to the multiple chip select signal sending ends SS_OUT of the master device Master being the first voltage.

[0072] Among them, the multiple chip select signal sending ends SS_OUT of the master device Master are also connected with the input ends of the second control circuit 2 and the third control circuit 3 through a second AND gate respectively. The second control circuit 2 is specifically configured to control the second data sending end MOSI_OUT of the master device Master to be communicated and the second data receiving end MOSI_IN of the slave device Slave to be gated in response to the multiple chip select signal sending ends SS_OUT of the master device Master being the second voltage; the third control circuit 3 is specifically configured to control the clock signal sending end SCK_OUT of the master device Master to be communicated and the clock signal receiving end SCK_IN of the slave device Slave to be gated in response to the multiple chip select signal sending ends SS_OUT of the master device Master being the second voltage.

[0073] Specifically, for the corresponding set of host device Master and interconnection module MUX, the chip select signal sending end SS_OUT of the host device Master and the first control circuit 1 of the interconnection module MUX are one-to-one corresponding, and one first control circuit 1 controls the selection of the chip select signal receiving end SS_IN of the corresponding slave device Slave of the chip select signal sending end SS_OUT of the host device Master. Before the host device Master to be communicated performs SPI communication, the host device Master to be communicated needs to query the port state of the chip select signal receiving end SS_IN of the corresponding plurality of slave devices Slave at the same time, and if the port state of the chip select signal receiving end SS_IN of the plurality of slave devices Slave corresponding to the host device Master is all the first voltage (high level), the SPI bus is in an idle state. At this time, the second voltage (low level) sent by the chip select signal sending end SS_OUT (for example Figure 6 SS_1_OUT and SS_2_OUT) of the host device Master to be communicated, the first control circuit 1 controls the selection of the chip select signal receiving end SS_IN of the corresponding slave device Slave of the chip select signal sending end SS_OUT of the host device Master to be communicated; at the same time, the second control circuit 2 controls the selection of the second data receiving end MOSI_IN of the corresponding slave device Slave of the second data sending end MOSI_OUT of the host device Master to be communicated in response to the second voltage (low level) of all chip select signal sending ends SS_OUT (for example Figure 6 SS_1_OUT and SS_2_OUT) of the host device Master to be communicated; the third control circuit 3 controls the selection of the clock signal receiving end SCK_IN of the corresponding slave device Slave of the clock signal sending end SCK_OUT of the host device Master to be communicated in response to the second voltage (low level) of all chip select signal sending ends SS_OUT (for example Figure 6 SS_1_OUT and SS_2_OUT) of the host device Master to be communicated, so that the host device Master and the corresponding slave device Slave can communicate. If the port state of the chip select signal receiving end SS_IN of one slave device Slave is the second voltage, the SPI bus is in an occupied state, and the host device Master to be communicated needs to wait.

[0074] Figures 7-9 The schematic diagrams of a first control circuit, a second control circuit and a third control circuit provided by the embodiments of the present disclosure are shown in FIGS. 1 to 3, respectively.

[0075] As shown in FIG. 4, the first control circuit 1, the second control circuit 2 and the third control circuit 3 are connected to the chip select signal sending end SS_OUT of the host device Master, and the chip select signal receiving end SS_IN of the corresponding slave device Slave. Figure 3 , Figure 6 and Figure 7As shown, in some embodiments, the first control circuit 1 is an open drain output circuit, and the input end of the open drain output circuit is connected with the chip selection signal sending end SS OUT of the host device Master corresponding to the set interconnection module MUX, and the output end of the open drain output circuit is connected with the chip selection signal receiving end SS IN of the slave device Slave and the chip selection signal receiving end SS IN of the host device Master through the SPI bus.

[0076] Specifically, the working principle of the open drain output circuit is that when the control output is low, the pin is grounded, and when the control output is high, the pin neither outputs high nor low, and is in a high resistance state. The first control circuit 1 in the embodiment of the present disclosure adopts the open drain output circuit. When the chip selection signal sending end SS OUT of the host device Master outputs a second voltage (low level), the corresponding chip selection signal SS is a second voltage (low level); when the chip selection signal sending end SS OUT of the host device Master outputs a first voltage (high level), the corresponding chip selection signal SS signal is in a high resistance state. In addition, the output pin of the chip selection signal SS is generally externally connected with a pull-up resistor. When a plurality of host devices Master are connected with the same slave device Slave, that is, when a plurality of chip selection signals SS are connected, if the chip selection signal sending ends SS OUT of the plurality of host devices Master all output the first voltage (high level), the SS signal is high (idle state); if the chip selection signal sending end SS OUT of any host device Master outputs the second voltage (low level), the chip selection signal SS is low (occupied state). Optionally, the chip selection signal receiving end SS IN of the host device Master is connected with the output end of the first control circuit 1 through an input buffer. When the host device Master is ready to perform SPI communication, the chip selection signal receiving end SS IN is queried. If the chip selection signal receiving end SS IN is the second voltage (low level), it indicates that other host devices Master are occupying the SPI bus for communication, and the host waits at this time. When the chip selection signal receiving end SS IN is the first voltage (high level) in the idle state, the chip selection signal sending end SS OUT of the host device Master to be communicated outputs the second voltage (low level), and the open drain output circuit is turned on, so that the host device Master and the slave device Slave perform communication.

[0077] As Figure 3 , Figure 6 and Figure 8As shown, in some embodiments, the second control circuit 2 is a first tri-state output circuit, for a corresponding set of host device Master and interconnection module MUX, the input end of the first tri-state output circuit is connected with the second data sending end MOSI_OUT of the host device Master, the control end of the first tri-state output circuit is connected with the chip selection signal sending end SS_OUT of the host device Master through the first inverter, and the output end of the first tri-state output circuit is connected with the second data receiving end MOSI_IN of the slave device Slave through the SPI bus.

[0078] The control end of the first tri-state output circuit is configured to select the second data sending end MOSI_OUT of the host device Master to be communicated and the second data receiving end MOSI_IN of the slave device Master in response to the chip selection signal sending end SS_IN of the host device Master to be communicated being the second voltage.

[0079] Specifically, the tri-state output circuit includes an input end, a control end and an output end, and can provide three different output values: logic "0", logic "1" and high impedance state. The working principle of the tri-state output circuit is that the output is controlled by the control end. When the control end is at a high level, the function of the tri-state output circuit is a normal buffer driver, and the output is determined by the input, that is, when the input is at a low level or a high level, the output is also at a low level or a high level. When the control end is at a low level, regardless of the level of the input, the output is in a high impedance state at this time.

[0080] The second control circuit 2 in the embodiment of the present disclosure adopts the first tri-state output circuit, and the control end of the first tri-state output circuit is connected with the chip selection signal sending end SS_OUT of the host device Master through the inverter. In this way, when the host device Master performs SPI communication, the chip selection signal sending end SS_OUT of the host device Master is pulled low, the control end of the first inverter is at a high level, and the corresponding tri-state gate output is in an enabled state. At this time, the MOSI line output signal of the SPI bus is consistent with the second data sending end MOSI_OUT output signal of the host device Master. When the host Master does not perform SPI communication, the chip selection signal sending end SS_OUT of the host device Master is at a high level, the control end of the first inverter is at a low level, and the MOSI line output signal of the SPI bus is in a high impedance state, which does not affect the communication between other SPI host devices Master and slave devices Slave.

[0081] As Figure 3 , Figure 6 and Figure 9As shown, in some embodiments, the third control circuit 3 is a second tri-state output circuit, for the corresponding set of host device Master and interconnection module MUX, the input end of the second tri-state output circuit is connected with the clock signal sending end SCK_OUT of the host device Master, the control end of the second tri-state output circuit is connected with the chip selection signal sending end SS_OUT of the host device Master through the second inverter, and the output end of the second tri-state output circuit is connected with the clock signal receiving end SCK_IN of the slave device Master through the SPI bus.

[0082] The control end of the second tri-state output circuit is configured to select the clock signal sending end SCK_OUT of the host device Master to be communicated and the clock signal receiving end SCK_IN of the slave device Slave in response to the chip selection signal sending end SS_OUT of the host device Master to be communicated being the second voltage.

[0083] It should be noted that the working principle of the second tri-state output circuit is exactly the same as that of the first tri-state output circuit, and the only difference is that the signal ends of the host device Master connected by the two are different, and the working principle and working process of the second tri-state output circuit will not be repeated here.

[0084] It should be further noted that the first control circuit 1 in the embodiment of the present disclosure is not limited to the open drain output circuit described above, the second control circuit 2 is not limited to the first tri-state output circuit described above, and the third control circuit 3 is not limited to the second tri-state output circuit described above, and can also be other circuit structures as long as the corresponding functions can be realized, and the present disclosure does not limit this.

[0085] The interconnection module MUX provided by the embodiment of the present disclosure communicates with the SPI host device Master through the first control circuit 1, the second control circuit 2 and the third control circuit 3, and the chip selection signal receiving end SS_IN is added in the host device Master, and the chip selection signal SS output by the third control circuit 3 is connected through the input buffer. When the host device Master is ready for SPI communication, the chip selection signal receiving end SS_IN added in the host device Master is queried to determine whether other host devices Master are occupying the SPI bus for communication, so that conflict-free communication of multiple host devices Master and the same slave device Slave can be realized.

[0086] Embodiment 2,

[0087] The embodiment of the present disclosure provides a communication system, which comprises a plurality of master devices Master, at least one slave device Slave and a interconnection module MUX. Wherein, the master device Master communicates with the slave device Slave through the SPI bus. The interconnection module MUX is configured to detect the port state of the chip selection signal receiving end SS_IN of the slave device Slave, and control the corresponding master device Master to communicate with the slave device Slave.

[0088] Figure 10 The interface schematic diagram of another interconnection module provided by the embodiment of the present disclosure. Figures 11-12 The circuit structure schematic diagram of two interconnection modules provided by the embodiment of the present disclosure. Wherein, Figure 11 The interconnection module in the embodiment of the present disclosure comprises a fourth multiplexer, Figure 12 The interconnection module in the embodiment of the present disclosure comprises two fourth multiplexers. Figures 13-14 The schematic diagram of two master devices provided by the embodiment of the present disclosure interconnecting with the slave device through the interconnection module, wherein, Figure 13 The schematic diagram of two master devices interconnecting with one slave device through the interconnection module; Figure 14 The schematic diagram of two master devices interconnecting with a plurality of slave devices through the interconnection module.

[0089] As shown in Figures 10-12 The interconnection module MUX comprises a first multiplexer 10, a second multiplexer 20, a third multiplexer 30, at least one fourth multiplexer 40 and a sub-control module 50.

[0090] Wherein, the input end of the first multiplexer 10 is connected with the clock signal output end SCK_OUT of each master device Master, the input end of the second multiplexer 20 is connected with the second data sending end MOSI_OUT of each master device Master, the output end of the third multiplexer 30 is connected with the first data receiving end MISO_IN of each master device Master, and the input end of the fourth multiplexer 40 is connected with the chip selection signal sending end SS_OUT of each master device Master, which is configured to select one master device Master from each master device Master as the master device Master to be communicated to communicate with the slave device Slave.

[0091] The input end of the third multiplexer 30 is connected with a plurality of state ends RES( Figure 11 and Figure 12The connection includes RES1 and RES2. The third multiplexer 30 is configured to receive communication commands sent by the master device to be communicated and detect multiple status terminals RES to determine the port status of the chip select signal receiver SS_IN of the slave device.

[0092] The selection terminals of the first multiplexer 10, the second multiplexer 20, the third multiplexer 30, and the fourth multiplexer 40 are all connected to the data strobe signal terminal SEL of the sub-control module 50. The sub-control module 50 is configured to, in response to the port being in an idle state, control the chip select signal transmitting terminal SS_OUT of the master device to be communicated to be strobe the chip select signal receiving terminal SS_IN of the corresponding slave device, so that the master device to be communicated can communicate with its corresponding slave device via the SPI bus.

[0093] Specifically, a multiplexer, also called a data selector, is used to multiplex data from multiple input channels onto one output channel. Its working principle is as follows: the control signal at the selection terminal selects one data from multiple data channels and sends it to the output terminal for output.

[0094] In this embodiment of the disclosure, the multiple inputs of the multiplexer are respectively connected to different master devices. Taking two master devices connected to the same slave device as an example, Figure 11 and Figure 12 The multiplexers in the system all include two input data channels, and these two input data channels come from two different master devices connected to the same slave device.

[0095] It should be noted that, in Figures 13-14 The code only shows the bus signal lines (SCK line, MISO line, MOSI line, SS line (including SS_1 and SS_2)) corresponding to the ports of the master devices (Master1, Master2) and slave devices, without showing the specific ports of the master and slave devices. For example... Figures 10-14As shown, the SCK_M_1, MISO_M_1, MOSI_M_1, SS_M_1 signal interfaces of the interconnection module MUX are respectively used for connecting the port corresponding bus signals of the first host device Master1; the SCK_M_2, MISO_M_2, MOSI_M_2, SS_M_2 signal interfaces of the interconnection module MUX are respectively used for connecting the port corresponding bus signals of the second host device Master2; the SCK_S, MISO_S, MOSI_S, SS_S signal interfaces of the interconnection module MUX are respectively used for connecting the port corresponding bus signals of the slave device Slave. And SCK_M_1, SCK_M_2 are the input terminals of the first multiplexer 10, MOSI_M_1, MOSI_M_2 are the input terminals of the second multiplexer 20, MISO_M_1, MISO_M_2 are the output terminals of the third multiplexer 30, SS_M_1, SS_M_2 are the input terminals of the fourth multiplexer 40.

[0096] As Figures 11-12As shown, the interconnection module MUX mainly consists of a plurality of multiplexers and a sub-control module 50. The sub-control module 50 controls the data gating of the master device Master and the slave device Slave to communicate according to the port state of the chip select signal receiving end of the slave device Slave (i.e. the current SPI bus occupation state) and the signal change of the chip select signal sending ends (SS_1, SS_2) of the two master devices, and negotiates communication with the master device Master according to the current SPI bus state. The SEL signal of the sub-control module 50 is a data gating signal, and RES1 and RES2 are used to respond to the current SPI bus state of the first master device Master1 and the second master device Master2, respectively. Specifically, the fourth multiplexer 40 is configured to select the chip select signal sending end SS_OUT of the master device Master to be communicated and the corresponding chip select signal receiving end SS_IN of the slave device Slave to be gated in response to the data gating signal of the sub-control module 50; the third multiplexer 30 is configured to select the first data receiving end MISO_IN of the master device Master to be communicated and the first data sending end MISO_OUT of the slave device Slave to be gated in response to the data gating signal of the sub-control module 50; the second multiplexer 20 is configured to select the second data sending end MOSI_OUT of the master device Master to be communicated and the second data receiving end MOSI_IN of the slave device Slave to be gated in response to the data gating signal of the sub-control module 50; and the first multiplexer 10 is configured to select the clock signal sending end SCK_OUT of the master device Master to be communicated and the clock signal receiving end SCK_IN of the slave device Slave to be gated in response to the data gating signal of the sub-control module 50, so as to select one master device Master from the master devices Master to communicate with the corresponding slave device Slave.

[0097] In addition, according to the SPI protocol, one master device Master can communicate with only one slave device Slave (as shown in Figure 13 ), and one master device Master can also communicate with a plurality of slave devices Slave (as shown in Figure 14 ). In other words, the number of chip select signal sending ends SS_OUT in the master device Master can be one or multiple, and the number of chip select signal sending ends SS_OUT in the master device Master can be set according to the number of slave devices Slave corresponding to the communication of the master device Master. As shown in Figures 13-14 , and in Figure 13 and Figure 14 , each slave device Slave communicates with multiple (Figure 13 and Figure 14 each with 2 as an example) host device Master is connected.

[0098] As shown in Figure 11 and Figure 13 , in the case where one host device Master is connected with one slave device Slave, and multiple host devices Master are connected with the same slave device Slave, the interconnection module MUX includes a fourth multiplexer 40, each host device Master includes a chip selection signal sending end SS_OUT, and the chip selection signal sending end SS_OUT of each host device Master is connected with the input end of the fourth multiplexer 40.

[0099] In the case where one host device Master is connected with multiple slave devices Slave, and multiple host devices Master are connected with the same slave device Slave. In some embodiments, the communication system includes multiple slave devices Slave, each host device Master includes multiple chip selection signal sending ends SS_OUT, and the chip selection signal sending ends SS_OUT are arranged one-to-one with the slave devices Slave, and the interconnection module MUX includes multiple fourth multiplexers 40 corresponding to the chip selection signal sending ends SS_OUT of one host device Master; wherein the input end of one fourth multiplexer 40 is connected with the chip selection signal sending ends SS_OUT of each host device Master connected with the same slave device Slave.

[0100] Specifically, as shown in Figure 12 and Figure 14 , each host device Master includes two chip selection signal output ends SS_OUT, which are respectively used for selecting communication with the first slave device Slave1 and the second slave device Slave2. Among them, the two chip selection signal output ends SS_OUT of the first host device Master1 and the second host device Master2 connected with the first slave device Slave1 are connected with the same fourth multiplexer 40, and the two chip selection signal output ends SS_OUT of the first host device Master1 and the second host device Master2 connected with the second slave device Slave2 are connected with another fourth multiplexer 40, so that the interconnection of multiple host devices Master and multiple slave devices Slave can be realized without conflict communication.

[0101] It should be noted that the interconnection module MUX disclosed in Embodiment 1 and Embodiment 2 can realize multiple host devices Master and the same (or multiple) slave devices Slave to interconnect conflict-free communication. The interconnection module MUX proposed in Embodiment 2 has the advantage of not needing to modify the original circuit structure of the SPI host device Master, but only needs to modify the control program of the SPI host device Master, and has high compatibility with the original SPI host device Master and SPI slave device Slave.

[0102] Based on the same invention, the embodiment of the present disclosure also provides a communication method which can be applied to any communication system in Embodiment 1. Figure 15 A communication method provided by the embodiment of the present disclosure, as shown in the figure, comprises: Figure 15

[0103] 1501, the interconnection module MUX receives the communication instruction sent by the host device Master to be communicated.

[0104] 1502, the interconnection module MUX detects the signal of the chip select signal receiving end SS_IN of the host device Master to be communicated.

[0105] 1503, the interconnection module MUX judges whether the chip select signal receiving end SS_IN of the host device Master to be communicated is the first voltage. If the chip select signal receiving end SS_IN of the host device Master is the first voltage, steps 1504-1506 are executed, otherwise step 1507 is executed: waiting and re-executing step 1502.

[0106] 1504, the chip select signal sending end SS_OUT of the host device Master to be communicated outputs the second voltage, and the interconnection module MUX selects the chip select signal sending end SS_OUT of the host device Master to be communicated and the chip select signal receiving end SS_IN of the corresponding slave device Slave, so that the host device Master to be communicated communicates with the corresponding slave device Slave through the SPI bus.

[0107] 1505, the chip select signal sending end SS_OUT of the host device Master to be communicated outputs the first voltage, so that the chip select signal receiving end SS_IN of the slave device Slave is the first voltage.

[0108] 1506, end communication.

[0109] ​Specifically, when the host device Master to be communicated is ready to perform SPI communication, the interconnection module MUX in the communication system needs to query the chip select signal receiving end SS_IN of the host device Master, and if the chip select signal receiving end SS_IN is not the first voltage (high level) but the second voltage (low level), it indicates that another host device Master is occupying the SPI bus to perform communication. At this time, the host waits until the chip select signal receiving end SS_IN of the host device Master is the first voltage (high level) in an idle state. Then, the chip select signal sending end SS_OUT of the host device Master to be communicated outputs the second voltage (low level), the first control circuit 1 of the interconnection module MUX controls the chip select signal sending end SS_OUT of the host device Master to be communicated and the chip select signal receiving end SS_IN of the slave device Slave to be selected. At the same time, the second control circuit 2 receives the low voltage of the chip select signal sending end SS_OUT of the host device Master, controls the second data sending end MOSI_OUT of the host device Master to be communicated and the second data receiving end MOSI_IN of the slave device Slave to be selected, so that the host device Master sends the second data to the slave device Slave. The third control circuit 1 receives the low voltage of the chip select signal sending end SS_OUT of the host device Master, controls the clock signal sending end SCK_OUT of the host device Master to be communicated and the clock signal receiving end SCK_IN of the slave device Slave to be selected, so that the host device Master sends the clock signal to the slave device Slave, thereby realizing the communication between the host device Master and the slave device Slave. When the communication between the host device Master to be communicated and the slave device Slave is completed, the chip select signal sending end SS_OUT of the host device Master to be communicated outputs the first voltage (high level), and the chip select signal receiving end SS_IN of the corresponding slave device Slave also corresponds to the first voltage (high level). At this time, the communication between the host device Master to be communicated and the slave device Slave ends.

[0110] For other details in the communication method, refer to the content in Embodiment 1 above, which will not be described in detail here.

[0111] Based on the same invention, the embodiment of the disclosure also provides another communication method which can be applied to any communication system in Embodiment 2. Figure 16 A communication method provided by the embodiment of the disclosure, as shown in Figure 16 The communication method comprises:

[0112] 1601、The chip select signal sending end SS_OUT of the host device Master to be communicated outputs the second voltage (low level).

[0113] 1602、The interconnection module MUX receives the second voltage (low level) output by the chip select signal sending end SS_OUT of the host device Master.

[0114] 1603、The interconnection module MUX detects the port state of the chip select signal receiving end SS_IN of the slave device Slave and judges whether the chip select signal receiving end SS_IN of the slave device Slave is the first voltage (high level).

[0115] If the port state of the chip select signal receiving end SS_IN of the slave device Slave is the first voltage (high level), indicating that the SPI bus is in an idle state, steps 1604-1606 are executed, otherwise step 1607 is executed: waiting and re-executing step 1602.

[0116] 1604、The interconnection module MUX controls the chip select signal sending end SS_OUT of the host device Master to be communicated and the chip select signal receiving end SS_IN of the slave device Slave to be gated, so that the host device Master to be communicated communicates with the corresponding slave device Slave through the SPI bus.

[0117] 1605、The chip select signal sending end SS_OUT of the host device Master to be communicated outputs the first voltage, so that the chip select signal receiving end SS_IN of the slave device Slave is the first voltage.

[0118] 1606、End communication.

[0119] Specifically, Figures 17-18 The interface signal timing diagrams corresponding to the interfaces of the two interconnection modules MUX provided by the embodiments of the present disclosure are shown. Among them, Figure 17 The interface signal timing diagram corresponding to the idle time of the SPI bus, Figure 18 The interface signal timing diagram corresponding to the occupied time of the SPI bus.

[0120] As Figures 16-18As shown, when the master device to be communicated is ready to communicate, the chip select signal output terminal SS_OUT of the master device sends a second voltage (low level) to the interconnect module MUX. The third multiplexer 30 of the interconnect module MUX queries multiple status terminals in the sub-control module 50. These multiple status terminals correspond to the port status of the chip select signal receiving terminal SS_IN of each slave device corresponding to the master device, to determine whether the SPI bus is occupied. The control sub-module 50 controls the data selection between the master device and the slave device based on the port status of the chip select signal receiving terminal of the slave device (i.e., the current SPI bus occupancy status) and the signal changes of the chip select signal transmitting terminals (SS_1, SS_2) of the two master devices to enable communication, and negotiates communication with the master device regarding the current SPI bus status.

[0121] like Figures 17-18 As shown, ACK indicates that the SPI bus is currently idle and communication is possible; NACK indicates that the SPI bus is currently occupied and SPI master communication is terminated. ACK and NACK can be represented by signals with specific timing sequences. Typically, ACK is represented by transmitting bit 1 and bit 0 sequentially over two consecutive timing cycles; NACK is represented by transmitting bit 0 and bit 1 sequentially over two consecutive timing cycles.

[0122] Specifically, when the third multiplexer 30 receives ACKs from all the status terminals of the sub control module 50, it indicates that the current SPI bus is idle, and the fourth multiplexer 40 is configured to select the chip select signal sending terminal SS_OUT of the host device Master to be communicated and the chip select signal receiving terminal SS_IN of the corresponding slave device Slave to be gated in response to the data enable signal of the sub control module 50; the third multiplexer 30 is configured to select the first data receiving terminal MISO_IN of the host device Master to be communicated and the first data sending terminal MISO_OUT of the corresponding slave device Slave to be gated in response to the data enable signal of the sub control module 50; the second multiplexer 20 is configured to select the second data sending terminal MOSI_OUT of the host device Master to be communicated and the second data receiving terminal MOSI_IN of the corresponding slave device Slave to be gated in response to the data enable signal of the sub control module 50; and the first multiplexer 10 is configured to select the clock signal sending terminal SCK_OUT of the host device Master to be communicated and the clock signal receiving terminal SCK_IN of the corresponding slave device Slave to be gated in response to the data enable signal of the sub control module 50, so as to select one host device Master from the host devices Master to be communicated to communicate with the corresponding slave device Slave. After the communication between the host device Master to be communicated and the slave device Slave is completed, the host device Master to be communicated outputs a first voltage (high level) to end the communication with the slave device Slave.

[0123] When the third multiplexer 30 receives NACKs from any status terminal of the sub control module 50, it indicates that the current SPI bus is occupied, and is sent to the corresponding host device Master to be communicated, which waits until the SPI bus is idle to communicate.

[0124] For other details in the communication method provided in the embodiments of the present disclosure, reference can be made to the corresponding contents in Embodiment 2 described above, which will not be repeated here.

[0125] The embodiments of the present disclosure also provide a communication device comprising any one of the communication systems in the above embodiments.

[0126] It can be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the protection scope of the present application.

Claims

1. A communication system, characterized in that, It includes multiple master devices and at least one slave device, wherein the master devices communicate with the slave devices via an SPI bus; wherein, The communication system further includes at least one interconnect module configured to receive communication commands sent by the host device to be communicated with, and to detect the port status of the chip select signal receiving end of the slave device; The interconnect module is also configured to, in response to the port being in an idle state, select the chip select signal receiving end of the slave device and the chip select signal transmitting end of the master device to be communicated, so that the master device to be communicated can communicate with its corresponding slave device through the SPI bus.

2. The communication system according to claim 1, characterized in that, The communication system includes multiple interconnect modules that correspond one-to-one with the host device. Each interconnect module includes at least one first control circuit, a second control circuit, and a third control circuit. For the corresponding host device and interconnect module, the chip select signal transmitting terminal of the host device is connected to the input terminal of the first control circuit, and the output terminal of the first control circuit is connected to the chip select signal receiving terminal of the slave device via an SPI bus. The chip select signal receiving terminal of the host device is also connected to the output terminal of the first control circuit. The second data transmitting terminal and the chip select signal transmitting terminal of the host device are both connected to the input terminal of the second control circuit, and the output terminal of the second control circuit is connected to the second data receiving terminal of the slave device via an SPI bus. The clock signal transmitting terminal and the chip select signal transmitting terminal of the host device are both connected to the input terminal of the third control circuit, and the output terminal of the third control circuit is connected to the clock signal receiving terminal of the slave device via an SPI bus. The first control circuit is configured to detect the voltage of the chip select signal receiving terminal of the host device to be communicated with, and in response to the chip select signal receiving terminal of the host device to be communicated with being at a first voltage, determine that the port state of the chip select signal receiving terminal of the slave device is idle, and send the port state to the host device to be communicated with. And receive the second voltage sent by the chip select signal transmitter of the host device to be communicated, and control the chip select signal transmitter of the host device to be communicated to be connected to the chip select signal receiver of the slave device; The second control circuit is configured to control the second data transmission terminal of the host device to be communicated to select the second data reception terminal of the slave device when the chip select signal transmission terminal of the host device to be communicated is at the second voltage; The third control circuit is configured to control the clock signal transmitter of the host device to be communicated to select the clock signal receiver of the slave device when the chip select signal transmitter of the host device to be communicated is at the second voltage.

3. The communication system according to claim 2, characterized in that, The communication system includes multiple slave devices. For the corresponding master device and interconnect module, the master device includes multiple chip select signal transmitters, and each chip select signal transmitter corresponds to one of the slave devices. The interconnect module includes multiple first control circuits, and one chip select signal transmitter is connected to the input of one of the first control circuits. The outputs of the multiple first control circuits are connected to the chip select signal receiver of the master device through a first AND gate. The chip select signal receiving end of the host device is configured to respond to the first voltage being applied to the chip select signal receiving end of the host device when all of the multiple chip select signal transmitting ends of the host device are at the first voltage. The multiple chip select signal transmitters of the host device are also connected to the inputs of the second control circuit and the third control circuit respectively via a second AND gate. The second control circuit is specifically configured to control the second data transmission terminal of the host device to be communicated to be selected with the second data reception terminal of the slave device in response to the fact that multiple chip select signal transmission terminals of the host device are all at the second voltage; The third control circuit is specifically configured to control the clock signal transmitting end of the host device to be communicated and the clock signal receiving end of the slave device to be communicated in response to the fact that multiple chip select signal transmitting ends of the host device are all at the second voltage.

4. The communication system according to claim 2, characterized in that, The first control circuit is an open-drain output circuit. For the corresponding host device and the interconnection module, the input terminal of the open-drain output circuit is connected to the chip select signal transmitting terminal of the host device, and the output terminal of the open-drain output circuit is connected to the chip select signal receiving terminal of the slave device and the chip select signal receiving terminal of the host device through the SPI bus.

5. The communication system according to claim 2, characterized in that, The second control circuit is a first tri-state output circuit. For the corresponding host device and the interconnection module, the input terminal of the first tri-state output circuit is connected to the second data transmission terminal of the host device, and the control terminal of the first tri-state output circuit is connected to the chip select signal transmission terminal of the host device through a first inverter. The output terminal of the first tri-state output circuit is connected to the second data receiving terminal of the slave device through an SPI bus. The control terminal of the first tri-state output circuit is configured to control the second data transmission terminal of the host device to be communicated and the second data reception terminal of the slave device to be communicated to be selected in response to the chip select signal transmission terminal of the host device to be communicated being the second voltage.

6. The communication system according to claim 2, characterized in that, The third control circuit is a second tri-state output circuit. For the corresponding host device and the interconnection module, the input terminal of the second tri-state output circuit is connected to the clock signal transmitting terminal of the host device, the control terminal of the second tri-state output circuit is connected to the chip select signal transmitting terminal of the host device through the second inverter, and the output terminal of the second tri-state output circuit is connected to the clock signal receiving terminal of the slave device through the SPI bus. The control terminal of the second tri-state output circuit is configured to control the clock signal transmitting terminal of the host device to be communicated and the clock signal receiving terminal of the slave device to be communicated to be selected in response to the second voltage of the clock signal transmitting terminal of the host device to be communicated.

7. The communication system according to claim 1, characterized in that, The communication system includes an interconnection module, which comprises a first multiplexer, a second multiplexer, a third multiplexer, at least one fourth multiplexer, and a sub-control module; wherein, The input of the first multiplexer is connected to the clock signal output of each of the host devices, the input of the second multiplexer is connected to the second data transmission end of each of the host devices, the output of the third multiplexer is connected to the first data reception end of each of the host devices, and the input of the fourth multiplexer is connected to the chip select signal transmission end of each of the host devices. The multiplexer is configured to select one of the host devices as the host device to communicate with the slave device. The input terminal of the third multiplexer is connected to multiple status terminals in the sub-control module that correspond one-to-one with each of the host devices. The third multiplexer is configured to receive communication commands sent by the host device to be communicated and to detect the multiple status terminals to determine the port status of the chip select signal receiving terminal of the slave device. The selection terminals of the first, second, third, and fourth multiplexers are all connected to the data strobe signal terminal of the sub-control module; the sub-control module is configured to, in response to the port being in an idle state, control the chip select signal transmitting terminal of the host device to be communicated to be selected with the chip select signal receiving terminal of the corresponding slave device, so that the host device to be communicated can communicate with its corresponding slave device through the SPI bus.

8. The communication system according to claim 7, characterized in that, The communication system includes multiple slave devices, and each master device includes multiple chip select signal transmitters, with each chip select signal transmitter corresponding to one of the slave devices. The interconnection module includes multiple fourth multiplexers, each corresponding to one of the chip select signal transmitters of a master device. The input of a fourth multiplexer is connected to the chip select signal transmitters of each slave device in each master device.

9. A communication method, characterized in that, The method is used in the communication system as described in any one of claims 2-6, the method comprising: The interconnect module receives communication commands sent by the host device to be communicated with, and detects the signal at the chip select signal receiver of the host device to be communicated with; In response to the chip select signal receiving terminal being at a first voltage, the chip select signal transmitting terminal of the host device to be communicated outputs a second voltage, and the interconnect module selects the chip select signal transmitting terminal of the host device to be communicated with the chip select signal receiving terminal of the corresponding slave device, so that the host device to be communicated can communicate with its corresponding slave device through the SPI bus.

10. A communication method, characterized in that, The method is used in the communication system as described in any one of claims 7-8, the method comprising: The chip select signal transmitter of the host device to be communicated outputs a second voltage; The interconnect module receives the second voltage output from the chip select signal transmitter of the host device and detects the port status of the chip select signal receiver of the slave device; In response to the idle state of the port of the slave device chip select signal receiver, the interconnection module selects the master device to be communicated with the slave device to communicate.

11. A communication device, characterized in that, Includes the communication system as described in any one of claims 1-8.

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