Digital-analog hybrid simulation verification method, device, equipment and medium

Abstract

The invention relates to a digital-analog hybrid simulation verification method and device, equipment and a medium. The digital-analog hybrid simulation verification method comprises the steps of obtaining a to-be-verified target program corresponding to a digital unit; compiling the target program into a hexadecimal file through a preset compiler; based on a preset mapping rule, performing data mapping processing on data in the hexadecimal file to obtain a bit stream file corresponding to the physical unit; and carrying out digital-analog hybrid simulation verification on the digital unit and the physical unit based on the bit stream file. According to the embodiment of the invention, the verification efficiency and accuracy can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of storage array circuit mixed simulation verification technology, and particularly relates to a digital-analog mixed simulation verification method and device, equipment and medium. BACKGROUND

[0002] With the increasing complexity of integrated circuit design, the verification work of digital circuits becomes increasingly difficult. In particular, in the design of flash memory (Flash), how to effectively verify the correctness of the storage unit, the integrity of the digital controller, and ensure consistency in circuit design and physical implementation has become a technical problem. Traditional verification methods usually rely on simulation and testing, but in large-scale integrated circuits (such as Flash memory), the verification process is tedious and inefficient. SUMMARY

[0003] In order to solve the above technical problems, the present disclosure provides a digital-analog mixed simulation verification method, device, equipment and medium.

[0004] In a first aspect, the present disclosure provides a digital-analog mixed simulation verification method, comprising:

[0005] Obtaining a target program to be verified corresponding to a digital unit;

[0006] Compiling the target program into a hexadecimal file through a preset compiler;

[0007] Based on a preset mapping rule, data mapping processing is performed on the data in the hexadecimal file to obtain a bitstream file corresponding to a physical unit;

[0008] Based on the bitstream file, digital-analog mixed simulation verification is performed on the digital unit and the physical unit.

[0009] In some embodiments, the hexadecimal file and the bitstream file are used to store instruction data in the digital-analog mixed simulation verification process.

[0010] In some embodiments, the data mapping processing based on the preset mapping rule on the data in the hexadecimal file to obtain a bitstream file corresponding to a physical unit comprises:

[0011] Arranging and padding the data in the hexadecimal file to obtain a target page;

[0012] Reversing the target page to obtain a bitstream file corresponding to a physical unit, the bitstream file being a binary file.

[0013] In some embodiments, the arranging and padding the data in the hexadecimal file to obtain a target page comprises:

[0014] arranging and padding the data in the hexadecimal file according to a preset page size, and determining whether the target page is filled up;

[0015] if the target page is not filled up, filling the target page with preset data.

[0016] In some embodiments, the reversing the target page to obtain a bitstream file corresponding to a physical unit comprises:

[0017] storing the target page to a backup unit, and reversing the target page according to a preset number of reversals to obtain a bitstream file corresponding to a physical unit, the preset number of reversals being determined according to a minimum bitstream.

[0018] In a second aspect, the present disclosure provides a digital-analog hybrid simulation verification device, comprising:

[0019] a program acquisition module configured to acquire a target program to be verified corresponding to a digital unit;

[0020] a file compilation module configured to compile the target program into a hexadecimal file by using a preset compiler;

[0021] a mapping processing module configured to perform data mapping processing on data in the hexadecimal file based on a preset mapping rule to obtain a bitstream file corresponding to a physical unit;

[0022] a simulation verification module configured to perform digital-analog hybrid simulation verification on the digital unit and the physical unit based on the bitstream file.

[0023] In some embodiments, the mapping processing module comprises:

[0024] a first processing unit configured to perform arranging and padding processing on the data in the hexadecimal file to obtain a target page;

[0025] a second processing unit configured to perform reversing processing on the target page to obtain a bitstream file corresponding to a physical unit, the bitstream file being a binary file.

[0026] In some embodiments, the mapping processing module comprises:

[0027] a first padding unit configured to arrange and pad the data in the hexadecimal file according to a preset page size, and determine whether the target page is filled up;

[0028] A second filling unit is configured to fill the target page with preset data if the target page is not filled.

[0029] In a third aspect, the present disclosure provides a digital-analog mixed simulation verification device, comprising:

[0030] a processor;

[0031] a memory configured to store executable instructions;

[0032] The processor is configured to read the executable instructions from the memory and execute the executable instructions to implement the digital-analog mixed simulation verification method of the first aspect.

[0033] In a fourth aspect, the present disclosure provides a computer-readable storage medium storing a computer program, when the computer program is executed by a processor, the processor implements the digital-analog mixed simulation verification method of the first aspect.

[0034] The technical solution provided by the embodiments of the present disclosure has the following advantages compared with the prior art:

[0035] The digital-analog mixed simulation verification method, device, equipment and medium provided by the embodiments of the present disclosure can obtain a target program to be verified corresponding to a digital unit, then compile the target program into a hexadecimal file through a preset compiler, then perform data mapping processing on the data in the hexadecimal file based on a preset mapping rule, obtain a bitstream file corresponding to a physical unit, and finally perform digital-analog mixed simulation verification on the digital unit and the physical unit based on the bitstream file. Therefore, the hexadecimal file generated by compiling the target program corresponding to the digital unit is mapped into the bitstream file corresponding to the physical unit, and digital-analog mixed simulation verification is performed based on the bitstream file. Since the mapped bitstream file can truly reflect the characteristics of the physical unit, the transmission and operation of the mapped bitstream file can truly reflect the behavior of the physical unit in hardware implementation, thereby improving the efficiency and accuracy of verification. BRIEF DESCRIPTION OF DRAWINGS

[0036] The above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the original and elements are not necessarily drawn according to the scale.

[0037] Figure 1 A flowchart of a digital-analog mixed simulation verification method provided by an embodiment of the present disclosure;

[0038] Figure 2 A schematic diagram of a digital-analog mixed simulation verification environment provided by an embodiment of the present disclosure;

[0039] Figure 3 A flowchart of another method for mixed-signal simulation verification provided by an embodiment of the present disclosure is shown in FIG. 3.

[0040] Figure 4 A structural diagram of a device for mixed-signal simulation verification provided by an embodiment of the present disclosure is shown in FIG. 4.

[0041] Figure 5 A structural diagram of an apparatus for mixed-signal simulation verification provided by an embodiment of the present disclosure is shown in FIG. 5. DETAILED DESCRIPTION

[0042] Embodiments of the present disclosure will be described in more detail with reference to the drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein, but rather the embodiments are provided so that the present disclosure can be more thoroughly and completely understood. It should be understood that the drawings and embodiments of the present disclosure are only for illustrative purposes and are not intended to limit the scope of protection of the present disclosure.

[0043] It should be understood that each step described in the method embodiments of the present disclosure can be executed in different orders and / or in parallel. In addition, the method embodiments can include additional steps and / or omit the execution of the steps shown. The scope of the present disclosure is not limited in this respect.

[0044] The term “comprising” and variations thereof as used in the present disclosure are open-ended, that is, “including but not limited to”. The term “based on” is “based, at least in part, on”. The term “one embodiment” means “at least one embodiment”; the term “another embodiment” means “at least one additional embodiment”; the term “some embodiments” means “at least some embodiments”. Related definitions are given throughout the description.

[0045] It should be noted that the terms “first”, “second”, and the like mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not intended to limit the order or interdependence of the functions performed by these devices, modules or units.

[0046] It should be noted that the terms “one”, “multiple” in the present disclosure are illustrative and not limiting, and those skilled in the art should understand that, unless otherwise explicitly stated in the context, it should be understood as “one or more”.

[0047] The names of the messages or information exchanged between the devices in the embodiments of the present disclosure are only for illustrative purposes, and are not intended to limit the scope of the messages or information.

[0048] To solve the above problems, the embodiment of the disclosure provides a digital-analog mixed simulation verification method, device, equipment and medium. The following will be described in detail Figures 1-3 The digital-analog mixed simulation verification method provided by the embodiment of the disclosure is described in detail.

[0049] Figure 1 The flowchart of the digital-analog mixed simulation verification method provided by the embodiment of the disclosure is shown.

[0050] In the embodiment of the disclosure, the digital-analog mixed simulation verification method can be executed by an electronic device. The electronic device can include but is not limited to devices such as computer devices, cloud servers or cloud server clusters.

[0051] As shown in the embodiment of the disclosure, the digital-analog mixed simulation verification method can include the following steps. Figure 1

[0052] S110, obtaining a target program to be verified corresponding to a digital unit.

[0053] In the embodiment of the disclosure, the electronic device can obtain the target program to be verified corresponding to the digital unit.

[0054] Optionally, the digital unit can be used to store the virtual digital circuit design logic.

[0055] Optionally, the target program to be verified can be a program for implementing the corresponding physical circuit function that needs to be verified.

[0056] Specifically, the user can input the designed target program into the electronic device, and the electronic device can obtain the target program to be verified corresponding to the digital unit, or the electronic device can obtain the target program to be verified corresponding to the digital unit from the local storage, which is not limited here.

[0057] S120, compiling the target program into a hexadecimal file through a preset compiler.

[0058] In the embodiment of the disclosure, the electronic device can compile the target program into a hexadecimal file through a preset compiler.

[0059] Optionally, the preset compiler (GNU Compiler Collection, GCC) can be used for program compilation.

[0060] Optionally, the hexadecimal file can be a Read-Only Memory (ROM) file. The hexadecimal file can be used to store instruction data in the digital-analog mixed simulation verification process, that is, the hexadecimal file stores various instruction data that need to be executed and verified in the digital-analog mixed simulation verification process. ​

[0061] Specifically, the electronic device can compile the target program into a hexadecimal ROM file through a preset compiler (GCC).

[0062] In the embodiment of the present disclosure, the electronic device can perform data mapping processing on the data in the hexadecimal file based on a preset mapping rule to obtain a bitstream file corresponding to the physical unit.

[0063] In the embodiment of the present disclosure, the electronic device can perform data mapping processing on the data in the hexadecimal file based on a preset mapping rule to obtain a bitstream file corresponding to the physical unit.

[0064] Optionally, the preset mapping rule can be a rule preset for mapping the virtual digital circuit design logic to the physical unit, and the preset mapping rule includes the physical characteristics of the physical unit.

[0065] Optionally, the bitstream file can be a real behavior file for simulating the physical unit. The physical unit can be a Flash storage unit. The bitstream file can be used to store instruction data in the mixed-signal simulation and verification process, that is, the bitstream file stores various instruction data that need to be executed and verified in the mixed-signal simulation and verification process.

[0066] Specifically, after obtaining the hexadecimal file, the electronic device can perform data mapping processing on the data in the hexadecimal file according to the preset mapping rule, that is, convert the hexadecimal file into a bitstream file corresponding to the physical unit.

[0067] S140, based on the bitstream file, performing mixed-signal simulation and verification on the digital unit and the physical unit.

[0068] In the embodiment of the present disclosure, the electronic device can perform mixed-signal simulation and verification on the digital unit and the physical unit based on the bitstream file.

[0069] Specifically, after obtaining the bitstream file, since the bitstream file is used to simulate the real behavior of the physical unit, the electronic device can perform mixed-signal simulation and verification on the digital unit and the physical unit according to the bitstream file, that is, simulate the real circuit behavior through the bitstream file for verification.

[0070] Thus, in the embodiments of the present disclosure, the target program corresponding to the digital unit can be obtained, and then the target program is compiled into a hexadecimal file by using a preset compiler, and then data in the hexadecimal file is processed by data mapping based on a preset mapping rule to obtain a bitstream file corresponding to the physical unit, and finally the digital unit and the physical unit are verified by mixed simulation based on the bitstream file. Thus, the hexadecimal file generated by compiling the target program corresponding to the digital unit is mapped into the bitstream file corresponding to the physical unit, and the mixed simulation verification is performed based on the bitstream file. Since the mapped bitstream file can truly reflect the characteristics of the physical unit, the transmission and operation of the mapped bitstream file can truly reflect the behavior of the physical unit in hardware implementation, thereby improving the efficiency and accuracy of verification.

[0071] Figure 2 A schematic diagram of a mixed simulation verification environment provided by an embodiment of the present disclosure is shown.

[0072] As shown in Figure 2 In the process of mixed simulation verification, the electronic device can first obtain a target program corresponding to a digital unit, and then compile the target program into a hexadecimal file by using a preset compiler, and then perform data mapping on the hexadecimal file according to a preset mapping rule to obtain a bitstream file corresponding to a physical unit, and finally load the bitstream file into the physical unit (Flash storage unit) through a backdoor to implement mixed simulation verification of the digital unit and the physical unit.

[0073] Optionally, S130 can specifically include: performing arrangement and padding processing on data in the hexadecimal file to obtain a target page; and performing reverse processing on the target page to obtain a bitstream file corresponding to the physical unit, the bitstream file being a binary file.

[0074] In the embodiments of the present disclosure, the electronic device can perform arrangement and padding processing on data in the hexadecimal file to obtain a target page.

[0075] Specifically, the electronic device performs arrangement and padding processing on data in the hexadecimal file, such as arranging and padding the data in the hexadecimal file according to the same structure as the physical unit (Flash storage unit), so as to obtain a corresponding target page.

[0076] Further, the electronic device can perform reverse processing on the target page to obtain a bitstream file corresponding to the physical unit.

[0077] Specifically, the electronic device can perform reverse processing on the target page, i.e., performing reverse processing on the target page in binary to obtain a bitstream file corresponding to a physical unit, i.e., a binary file.

[0078] Optionally, the data in the hexadecimal file is arranged and padded to obtain a target page, including: arranging and padding the data in the hexadecimal file according to a preset page size, and determining whether the target page is full; if the target page is not full, the target page is padded with preset data.

[0079] In the embodiments of the present disclosure, the electronic device arranges and pads the data in the hexadecimal file according to a preset page size, and determines whether the target page is full.

[0080] Specifically, the electronic device can arrange and pad the data in the hexadecimal file according to a preset page size, for example, the preset page size (in lines) can be determined, the hexadecimal file is divided by the preset page size in the page, and the data is arranged according to the page, and it is determined whether the target page is full of data.

[0081] Further, if the target page is not full, the target page is padded with preset data. Specifically, after the electronic device determines that the target page is not full, the electronic device can fill the remaining positions of the target page with preset data, so that the target page is full.

[0082] Optionally, the target page is reverse processed to obtain a bitstream file corresponding to a physical unit, including: storing the target page to a backup unit, and reverse processing the target page according to a preset reverse number to obtain a bitstream file corresponding to a physical unit, the preset reverse number being determined according to a minimum bitstream.

[0083] In the embodiments of the present disclosure, the electronic device can store the target page to a backup unit, and reverse process the target page according to a preset reverse number to obtain a bitstream file corresponding to a physical unit.

[0084] Specifically, after obtaining the full target page, the electronic device can reverse process the target page according to a preset reverse number, and the preset reverse number is determined according to a minimum bitstream. The electronic device can reverse the target page multiple times according to the preset reverse number, so as to obtain a bitstream file (binary file) corresponding to a physical unit.

[0085] Therefore, the virtual digital storage unit is bound with the actual physical unit by using the physical unit mapping module to simulate the real circuit behavior. The design ensures that the transmission and operation of the simulation data can truly reflect the behavior of the Flash memory in the hardware implementation in the mixed simulation process, effectively improving the verification efficiency of the storage unit.

[0086] Figure 3 A flowchart of another mixed simulation verification method provided by an embodiment of the present disclosure is shown.

[0087] As shown in Figure 3 , the electronic device can obtain a target program to be verified corresponding to a digital unit, compile the target program into a hexadecimal file through a preset compiler, then arrange and fill data according to the input hexadecimal file according to a preset page size, and determine whether the target page is filled. If the target page is not filled, fill the target page with preset data; if the target page is filled, store the target page to a backup unit, and perform reverse processing on the target page according to a preset reverse number of times to obtain a bitstream file corresponding to a physical unit, the preset reverse number of times is determined according to the minimum bitstream, and finally output the bitstream file.

[0088] Therefore, the performance of the storage unit can be verified in real time, avoiding redundant operations and inefficient links in the traditional verification method. Not only can the accuracy and speed of verification be greatly improved, but also the risk of errors that may exist in the design process can be reduced.

[0089] Figure 4 A structural diagram of a mixed simulation verification device provided by an embodiment of the present disclosure is shown.

[0090] As shown in Figure 4 , the mixed simulation verification device 400 can include a program acquisition module 410, a file compilation module 420, a mapping processing module 430, and a simulation verification module 440.

[0091] The program acquisition module 410 can be configured to obtain a target program to be verified corresponding to a digital unit.

[0092] The file compilation module 420 can be configured to compile the target program into a hexadecimal file through a preset compiler.

[0093] The mapping processing module 430 can be configured to perform data mapping processing on the data in the hexadecimal file based on a preset mapping rule to obtain a bitstream file corresponding to a physical unit.

[0094] The simulation verification module 440 can be configured to perform mixed simulation verification on the digital unit and the physical unit based on the bitstream file.

[0095] Therefore, in the embodiments of the present disclosure, the target program corresponding to the digital unit can be obtained, then the target program is compiled into a hexadecimal file by using a preset compiler, then data in the hexadecimal file is processed by data mapping based on a preset mapping rule, a bitstream file corresponding to the physical unit is obtained, and finally the digital unit and the physical unit are verified by mixed simulation based on the bitstream file. Therefore, the hexadecimal file generated by compiling the target program corresponding to the digital unit is mapped into the bitstream file corresponding to the physical unit, and the mixed simulation verification is performed based on the bitstream file. Since the mapped bitstream file can truly reflect the characteristics of the physical unit, the behavior of the physical unit in hardware implementation can be truly reflected through the transmission and operation of the mapped bitstream file, and the efficiency and accuracy of the verification are improved.

[0096] In some embodiments of the present disclosure, the hexadecimal file and the bitstream file are used to store instruction data in the mixed simulation verification process.

[0097] In some embodiments of the present disclosure, the mapping processing module 430 can specifically include a first processing unit and a second processing unit.

[0098] The first processing unit can be used to arrange and fill data in the hexadecimal file to obtain a target page.

[0099] The second processing unit can be used to reverse the target page to obtain a bitstream file corresponding to the physical unit, and the bitstream file is a binary file.

[0100] In some embodiments of the present disclosure, the mapping processing module 430 can further specifically include a first filling unit and a second filling unit.

[0101] The first filling unit can be used to arrange and fill data in the hexadecimal file according to a preset page size, and determine whether the target page is filled.

[0102] The second filling unit can be used to fill the target page with preset data if the target page is not filled.

[0103] In some embodiments of the present disclosure, the mapping processing module 430 can further specifically include a reverse processing unit.

[0104] The reverse processing unit can be used to store the target page to a backup unit, and reverse the target page according to a preset reverse number of times to obtain a bitstream file corresponding to the physical unit, and the preset reverse number of times is determined according to the minimum bitstream.

[0105] It should be noted that,Figure 4 The digital-analog hybrid simulation verification apparatus 400 shown can perform Figures 1-3 The various steps in the method embodiments shown, and achieve Figures 1-3 The various processes and effects in the method embodiments shown, and achieve

[0106] Figure 5 A structure diagram of a digital-analog hybrid simulation verification device provided by an embodiment of the present disclosure is shown.

[0107] In some embodiments of the present disclosure, Figure 5 The digital-analog hybrid simulation verification device shown can be an electronic device. Specifically, the electronic device can include but is not limited to devices such as computer devices, cloud servers or cloud server clusters, etc.

[0108] As Figure 5 The digital-analog hybrid simulation verification device shown can include a processor 501 and a memory 502 storing computer program instructions.

[0109] Specifically, the processor 501 described above can include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or can be configured to implement one or more integrated circuits of the embodiments of the present disclosure.

[0110] The memory 502 can include a mass storage for information or instructions. By way of example and not limitation, the memory 502 can include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. Where appropriate, the memory 502 can include removable or non-removable (or fixed) media. Where appropriate, the memory 502 can be internal or external to the integrated gateway device. In certain embodiments, the memory 502 is a non-volatile solid-state memory. In certain embodiments, the memory 502 includes read-only memory (ROM). Where appropriate, this ROM can be mask-programmed ROM, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), electrically alterable ROM (EAROM), or flash memory, or a combination of two or more of these.

[0111] The processor 501 executes the computer program instructions stored in the memory 502 to perform the steps of the hybrid simulation verification method provided by the embodiments of the present disclosure.

[0112] In one example, the hybrid simulation verification device can further include a transceiver 503 and a bus 504. As shown, the processor 501, the memory 502 and the transceiver 503 are connected through the bus 504 and complete communication with each other. Figure 5

[0113] The bus 504 includes hardware, software or both. By way of example and not limitation, the bus can include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or another suitable bus or a combination of two or more of these. Where appropriate, the bus 504 can include one or more buses. Although the present embodiments describe and show a particular bus, the present disclosure contemplates any suitable bus or interconnect.

[0114] The embodiments of the present disclosure further provide a computer readable storage medium, which can store a computer program. When the computer program is executed by a processor, the processor implements the hybrid simulation verification method provided by the embodiments of the present disclosure.

[0115] ​The storage medium described above may, for example, include a memory 502 of computer program instructions, which may be executed by a processor 501 of the mixed-signal simulation verification device to complete the mixed-signal simulation verification method provided by the embodiments of the present disclosure. Alternatively, the storage medium may be a non-transitory computer readable storage medium, for example, the non-transitory computer readable storage medium may be a ROM, a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0116] It should be noted that, in this document, relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", "includes", "including", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0117] The above description is merely one specific implementation of the present disclosure, which enables a person skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A hybrid numerical simulation verification method, characterized in that, include: Obtain the target program to be verified corresponding to the digital unit; The target program is compiled into a hexadecimal file using a preset compiler; Based on preset mapping rules, the data in the hexadecimal file is processed by data mapping to obtain a bitstream file corresponding to the physical unit; Based on the bitstream file, a mixed-signal simulation verification was performed on the digital unit and the physical unit.

2. The method according to claim 1, characterized in that, The hexadecimal file and the bitstream file are used to store instruction data during the mixed-signal simulation verification process.

3. The method according to claim 1, characterized in that, The process of performing data mapping processing on the data in the hexadecimal file based on preset mapping rules to obtain a bitstream file corresponding to the physical unit includes: The data in the hexadecimal file is arranged and filled to obtain the target page; The target page is reversed to obtain a bitstream file corresponding to the physical unit, and the bitstream file is a binary file.

4. The method according to claim 3, characterized in that, The step of arranging and filling the data in the hexadecimal file to obtain the target page includes: The data in the hexadecimal file is arranged and filled according to a preset page size, and it is determined whether the target page is full. If the target page is not full, then fill the target page with preset data.

5. The method according to claim 3, characterized in that, The step of reversing the target page to obtain a bitstream file corresponding to the physical unit includes: The target page is stored in the backup unit, and the target page is reversed according to a preset number of reversals to obtain a bitstream file corresponding to the physical unit. The preset number of reversals is determined based on the minimum bitstream.

6. A mixed-signal simulation verification device, characterized in that, include: The program acquisition module is used to acquire the target program to be verified corresponding to the digital unit; The file compilation module is used to compile the target program into a hexadecimal file using a preset compiler; The mapping processing module is used to perform data mapping processing on the data in the hexadecimal file based on preset mapping rules to obtain a bitstream file corresponding to the physical unit; The simulation verification module is used to perform mixed-signal simulation verification on the digital unit and the physical unit based on the bitstream file.

7. The apparatus according to claim 6, characterized in that, The mapping processing module includes: The first processing unit is used to arrange and fill the data in the hexadecimal file to obtain the target page; The second processing unit is used to reverse the target page to obtain a bitstream file corresponding to the physical unit, wherein the bitstream file is a binary file.

8. The apparatus according to claim 6, characterized in that, The mapping processing module includes: The first filling unit is used to fill the data in the hexadecimal file according to the preset page size, and to determine whether the target page is filled. The second filling unit is used to fill the target page with preset data if the target page is not full.

9. A mixed-signal simulation verification device, characterized in that, include: processor; Memory, used to store executable instructions; The processor is configured to read the executable instructions from the memory and execute the executable instructions to implement the mixed-signal simulation verification method according to any one of claims 1-5.

10. A non-volatile computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, causes the processor to implement the mixed-signal simulation verification method according to any one of claims 1-5.

Images