Element grouping and sorting method and device, storage medium and computer equipment
By obtaining the delay time and total waiting time of component groups in the FPGA, a greedy algorithm is used to optimize the component sorting and construct multiple groups, which solves the problem that the parallel computing capability of FPGA is not fully utilized in the existing technology and improves the efficiency of electromagnetic transient simulation.
Patent Information
- Application Number
- CN202511102934.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-07
- Publication Date
- 2025-11-18
AI Technical Summary
In existing technologies, when using floating-point node analysis in FPGAs, the simple component grouping and sorting methods result in the FPGA's parallel computing capabilities not being fully utilized, thus reducing the efficiency of electromagnetic transient simulation.
By obtaining the initial component group and its parameters from the component update module, the delay time and total waiting time of each component are determined. A greedy algorithm is used to optimize the sorting of the component group, construct multiple component groups, and update the components to the corresponding groups according to the optimal sorting, so as to reduce the waiting time of each component group.
By fully utilizing the parallel computing capabilities of FPGAs, the waiting time between components can be reduced, thereby improving the efficiency of electromagnetic transient simulation.
Smart Images
Figure CN120975010A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of power system simulation, and particularly relates to a component grouping and sequencing method and device, a storage medium and a computer device. BACKGROUND
[0002] In recent years, field programmable gate array (FPGA) has been widely concerned in the field of electromagnetic transient simulation due to its powerful parallel computing capability and flexible programmability. In electromagnetic transient simulation, the node analysis method can simulate the electromagnetic transient process of the circuit by analyzing the voltage and current of each node in the circuit, and FPGA can simultaneously process multiple computing tasks in the node analysis process, thereby significantly improving the simulation efficiency.
[0003] However, when the node analysis method using floating-point numbers is adopted in FPGA, the parallel computing characteristics of FPGA itself will accelerate the calculation of each module of the power system, but at the same time, the time sequence complexity in the calculation of each component node and the merging of historical currents will be increased. In the node analysis process, the existing technology usually adopts simple component grouping and fixed sequencing, so that the parallel computing capability of FPGA cannot be fully utilized, thereby greatly reducing the simulation efficiency. SUMMARY
[0004] The present application aims to at least solve one of the above technical defects, in particular, the technical defect that the node analysis in the prior art usually adopts simple component grouping and fixed sequencing, so that the parallel computing capability of FPGA cannot be fully utilized, thereby greatly reducing the simulation efficiency.
[0005] The present application provides a component grouping and sequencing method, which comprises:
[0006] obtaining an initial component group in a component update module, and determining the component parameters and the number of components of the initial component group;
[0007] determining the delay time of each component in the initial component group based on the component parameters, and determining the total waiting time of the initial component group based on the delay times;
[0008] performing component sequencing optimization on the initial component group by using a greedy algorithm according to the total waiting time, to obtain an optimal component group with the shortest total waiting time;
[0009] constructing multiple component groups according to the number of components, and sequentially updating each component into the corresponding component group by using the greedy algorithm according to the component sequencing of the optimal component group, so that the waiting time of each component group is the shortest.
[0010] Optionally, the component parameters comprise the head end number and the node number of each component.
[0011] determining the delay time of each element in the initial element group based on the element parameters comprises:
[0012] dividing the initial element group into a plurality of parallel element groups according to the first end number of each of the element parameters, the first end number of each element in each parallel element group being consistent;
[0013] for each parallel element group, sequentially subtracting the node numbers of two adjacent elements to obtain an index difference value, and determining the delay time of a first element of the two adjacent elements based on the index difference value.
[0014] Optionally, the determining of the delay time of the first element of the two adjacent elements based on the index difference value comprises:
[0015] determining the signal delay time of the adder and the multiplier in the element updating module, and calculating the delay time of the first element of the two adjacent elements based on the signal delay time and the index difference value.
[0016] Optionally, the determining of the total waiting time of the initial element group based on each delay time comprises:
[0017] if the number of elements in a parallel element group is greater than 2, starting from a second element in the parallel element group, sequentially marking the element as a current element, marking a previous element of the current element in the parallel element group as a first element, and marking a previous element and a previous two elements of the current element in the initial element group as a second element and a third element respectively;
[0018] obtaining an index difference value between the current element and the first element;
[0019] when the index difference value is not less than 2, subtracting the delay times of the first element and the third element from the delay time of the second element to obtain an additional waiting time, and determining whether the additional waiting time is less than 0;
[0020] if yes, keeping the delay time of the second element unchanged;
[0021] if no, updating the delay time of the second element according to the additional waiting time;
[0022] adding the delay times of each element in the initial element group to obtain the total waiting time of the initial element group.
[0023] Optionally, the step of optimizing the initial component group using a greedy algorithm based on the total waiting time to obtain the optimal component group with the shortest total waiting time includes:
[0024] The components in the initial component group are swapped according to the order swapping rules to obtain the optimized component group, and the total waiting time of the optimized component group is calculated.
[0025] The total waiting time of the initial component group and the optimized component group is compared, and the component group with the smaller total waiting time in the comparison result is marked as the new initial component group;
[0026] Return to the previous step and perform the step of swapping the order of the components in the initial component group according to the order swapping rules to obtain the optimized component group and subsequent steps, until the optimized component group meets the sorting end condition of the order swapping rules, and the last marked initial component group is taken as the optimal component group.
[0027] Optionally, the step of updating each element to its corresponding element group according to the element sorting of the optimal element group and sequentially using the greedy algorithm to minimize the waiting time of each element group includes:
[0028] According to the element sorting of the optimal element group, each element is marked as the current element in turn;
[0029] The greedy algorithm is used to determine the optimal order of each group of elements connected in series with the current element and its waiting time.
[0030] The component group with the shortest waiting time is selected as the target group for the current component, and the current component is updated to the target group according to the optimal sorting of the target group.
[0031] This application also provides a component grouping and sorting device, including:
[0032] The data initialization module is used to obtain the initial component group from the component update module, and to determine the component parameters and the number of components in the initial component group;
[0033] A waiting time calculation module is used to determine the delay time of each element in the initial element group based on the element parameters, and to determine the total waiting time of the initial element group based on each delay time;
[0034] The sorting optimization module is used to optimize the sorting of the initial component group based on the total waiting time using a greedy algorithm, so as to obtain the optimal component group with the shortest total waiting time.
[0035] The component grouping module is used to construct multiple component groups according to the number of components, and to update each component to the corresponding component group in turn using the greedy algorithm according to the component sorting of the optimal component group, so as to minimize the waiting time of each component group.
[0036] Optionally, the waiting time calculation module includes:
[0037] The parallel element division submodule is used to divide the initial element group into multiple parallel element groups according to the starting end number in the element parameters, wherein the starting end number of each element in each parallel element group is consistent.
[0038] The delay time calculation submodule is used to obtain the node numbers of two adjacent elements in each parallel element group in sequence, subtract them to obtain the index difference, and determine the delay time of the first element among the two adjacent elements based on the index difference.
[0039] This application also provides a storage medium storing computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform the steps of the element grouping and sorting method as described in any of the above embodiments.
[0040] This application also provides a computer device, including: one or more processors, and memory;
[0041] The memory stores computer-readable instructions that, when executed by the one or more processors, perform the steps of the element grouping and sorting method as described in any of the above embodiments.
[0042] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:
[0043] The component grouping and sorting method, apparatus, storage medium, and computer equipment provided in this application, when performing node analysis in electromagnetic transient simulation, can first obtain the initial component group in the component update module, and determine the component parameters and number of components in the initial component group, providing basic data for component characteristic analysis; then, based on the component parameters, the delay time of each component in the initial component group can be determined, and based on each delay time, the total waiting time of the initial component group can be determined, so as to quantify the time loss of the entire component group in the calculation process by the number of clock cycles required for different components in the current sort; next, based on the total waiting time, a greedy algorithm is used to optimize the component sorting of the initial component group to obtain the optimal component group with the shortest total waiting time, thereby fully considering the differences in calculation time between components in combination with component characteristics, and minimizing the waiting time between components; finally, multiple component groups can be constructed according to the number of components, and according to the component sorting of the optimal component group, the greedy algorithm is used to update each component to the corresponding component group in turn, so as to minimize the waiting time of each component group, thereby making full use of the parallel computing capability of FPGA, adaptively optimizing component grouping, and further improving simulation efficiency. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0045] Figure 1 A flowchart illustrating a component grouping and sorting method provided in an embodiment of this application;
[0046] Figure 2 A flowchart illustrating an optimal component sorting process provided in an embodiment of this application;
[0047] Figure 3 A flowchart illustrating an optimal component grouping process provided in this application embodiment;
[0048] Figure 4 This is a schematic diagram of the structure of a component grouping and sorting device provided in an embodiment of this application;
[0049] Figure 5 This is a schematic diagram of the internal structure of a computer device provided in an embodiment of this application. Detailed Implementation
[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0051] When using floating-point node analysis in FPGA, the parallel computing characteristics of FPGA itself will accelerate the calculation of various modules of the power system. However, it will also increase the timing complexity of the calculation of each component node and the historical current merging process. In the node analysis process, the existing technology usually adopts simple component grouping and fixed sorting, which makes it impossible to fully utilize the parallel computing capabilities of FPGA and greatly reduces the simulation efficiency.
[0052] Based on this, this application proposes the following technical solution, as detailed below:
[0053] In one embodiment, such as Figure 1 As shown, Figure 1 This is a flowchart illustrating a component grouping and sorting method provided in an embodiment of this application. The application provides a component grouping and sorting method, specifically including the following:
[0054] S110: Obtain the initial component group in the component update module, and determine the component parameters and number of components in the initial component group.
[0055] In this embodiment, when performing node analysis in electromagnetic transient simulation, the computer device can first obtain the initial component group in the component update module, and determine the component parameters and number of components in the initial component group, providing basic data for component characteristic analysis.
[0056] The component update module is mainly responsible for calculating the historical current of components. It performs simulation calculations on a group basis. The floating-point data type has high accuracy, but the calculation is relatively complex and usually requires multiple clock cycles to obtain the result. Since the calculation formula for each component is different, the number of clock cycles required for calculation of different components is different.
[0057] Specifically, the computer device can obtain the components to be simulated and updated during the current electromagnetic transient simulation, as well as the update order of each component, from the component update module. It then generates an initial component group and obtains the component parameters and number of components in this initial component group to characterize its characteristics. The component parameters refer to the set of parameters for all components. The parameters for each component can include basic information such as component type, port information, node number, and initial state.
[0058] S120: Determine the delay time of each element in the initial element group based on the element parameters, and determine the total waiting time of the initial element group based on each delay time.
[0059] In this step, after obtaining the component parameters of the initial component group through step S110, the computer device can determine the delay time of each component in the initial component group based on the component parameters, and determine the total waiting time of the initial component group based on each delay time, so as to quantify the time loss of the entire component group in the calculation process by calculating the number of clocks required by different components in the current sort.
[0060] Understandably, delay time refers to the length of time that a component's computation needs to be postponed in the current order to avoid conflicts with subsequent components in node access. For example, when multiple components are connected to the same circuit node, to avoid resource contention caused by these parallel components accessing the node simultaneously within the same clock cycle, a scheduling delay must be introduced during computation. In this case, the delay time of the preceding component determines how many clock cycles its computation should be delayed, thus ensuring that the following component begins execution only after it has completed its computation.
[0061] Specifically, the computer device can determine the connection relationships between components based on the node number and port information of each component in the component parameters. Then, it can determine the delay time of each component under the current component sorting based on these connection relationships. By statistically analyzing the delay times of all components, the computer device can further determine the total waiting time of the entire initial component group under the current component sorting. This comprehensively quantifies the time consumption of this sorting in FPGA parallel simulation, enabling efficiency evaluation of the current scheduling strategy and providing a basis for subsequent grouping and sorting.
[0062] S130: Based on the total waiting time, a greedy algorithm is used to optimize the component sorting of the initial component group to obtain the optimal component group with the shortest total waiting time.
[0063] In this step, after calculating the total waiting time of the initial component group in step S120, the computer device can use a greedy algorithm to optimize the component sorting of the initial component group based on the total waiting time, and obtain the optimal component group with the shortest total waiting time. This allows for full consideration of the differences in computation time between components based on their characteristics, thereby minimizing the waiting time between components.
[0064] Greedy algorithms, in this context, refer to an optimization strategy that selects the optimal decision at each step during problem-solving, without backtracking or considering future global impact, focusing only on local optima. Therefore, this application can employ a greedy algorithm to optimize component sorting, approximating the global optimum through each local optimum.
[0065] It is understandable that computer equipment can use a greedy algorithm to optimize the initial component group and select the component group with the shortest total waiting time from the pre- and post-optimization component groups. This component group is the local optimum and can participate in the next round of optimal judgment as a computational object until the optimized component group is the final sorting result. The local optimum selected in this round is the global optimum. Through the sorting optimization of the greedy algorithm, this application can fully consider the differences in computation time among different components under the premise of reasonably controlling computing resources and optimization strategy complexity, thereby dynamically adjusting their execution order, minimizing node conflicts, making resource scheduling more efficient, and thus minimizing the waiting time between components.
[0066] S140: Construct multiple component groups based on the number of components, and sort the components according to the optimal component group. Then, use a greedy algorithm to update each component to the corresponding component group in turn, so as to minimize the waiting time of each component group.
[0067] In this step, after determining the optimal component group in step S130, the computer device can construct multiple component groups according to the number of components, and update each component to the corresponding component group in turn using a greedy algorithm according to the component sorting of the optimal component group, so as to minimize the waiting time of each component group, thereby making full use of the parallel computing capability of the FPGA, adaptively optimizing the component grouping, and further improving the simulation efficiency.
[0068] Specifically, the computer device can construct multiple component groups for parallel processing based on the number of components and a certain partitioning strategy. Then, it sequentially allocates and updates each component to the most suitable component group according to its position in the sorting and its computational characteristics. During each allocation process, the computer device can dynamically select each component to be added to a group using a greedy algorithm, with the principle of minimizing the current waiting time of the component group. This minimizes the waiting time of the component group after receiving and updating the corresponding position of the component value, thereby achieving an optimal balance between the computational order and resource utilization within each component group.
[0069] It is understood that by using the component grouping and sorting method of this application, not only can local bottleneck problems caused by uneven component distribution or node conflicts be fully avoided, but the component sorting of each group can also be adaptively adjusted according to the component characteristics to minimize resource contention and waiting redundancy. This allows electromagnetic transient simulation to fully utilize the multi-channel parallel processing capabilities of the FPGA architecture, thereby improving the overall execution efficiency of the simulation system.
[0070] In the above embodiments, when performing node analysis in electromagnetic transient simulation, the initial component group in the component update module can be obtained first, and the component parameters and number of components in the initial component group can be determined to provide basic data for component characteristic analysis. Then, the delay time of each component in the initial component group can be determined based on the component parameters, and the total waiting time of the initial component group can be determined based on each delay time. This allows the time consumption of the entire component group during the calculation process to be quantified by the number of clock cycles required for different components in the current order. Next, based on the total waiting time, a greedy algorithm can be used to optimize the component sorting of the initial component group to obtain the optimal component group with the shortest total waiting time. This allows for a full consideration of the differences in calculation time between components, taking into account component characteristics, and minimizing the waiting time between components. Finally, multiple component groups can be constructed based on the number of components, and each component can be updated to the corresponding component group in sequence according to the component sorting of the optimal component group, using a greedy algorithm to minimize the waiting time of each component group. This fully utilizes the parallel computing capabilities of the FPGA, adaptively optimizes the component grouping, and further improves simulation efficiency.
[0071] In one embodiment, the component parameters in step S120 may include the start-end number and node number of each component; wherein, the process of determining the delay time of each component in the initial component group based on the component parameters may include:
[0072] S121: Divide the initial component group into multiple parallel component groups according to the starting end numbers in the component parameters, and the starting end numbers of each component in each parallel component group are consistent.
[0073] S122: For each group of parallel elements, obtain the node numbers of two adjacent elements in sequence, subtract them to get the index difference, and determine the delay time of the first element among the two adjacent elements based on the index difference.
[0074] In this embodiment, the component parameters may include the start-end number and node number of each component. Therefore, when determining the delay time of each component in the initial component group based on the component parameters, the computer device can divide the initial component group into multiple parallel component groups according to the start-end numbers in the component parameters, with the start-end numbers of each component in each parallel component group being consistent; for each parallel component group, the computer device can sequentially obtain the node numbers of two adjacent components, subtract them to obtain the index difference, and determine the delay time of the first component among the two adjacent components based on the index difference.
[0075] Understandably, the start-end number refers to the number corresponding to the first port to which a component is connected. It indicates which node the component is connected to. In a circuit, a component typically has two ports: the start-end (F terminal) and the end-end (T terminal). Of course, besides the F terminal, the start-end of a component can also come from other ports, and each port contains multiple connection nodes. Therefore, components connected to the same port may have different port numbers; for example, resistor R1 has a start-end number of F1, which is the first node of the F terminal, while resistor R2 has a start-end number of F3, which is the third node of the F terminal. In a circuit, components connected to the same port and the same node are connected in parallel; conversely, components with different start-end numbers are connected in series.
[0076] In addition, the node number refers to the position number of the element in the current sequence in the element parameter matrix, that is, the sorting position of the element in the initial element group. This number does not represent the electrical node in the circuit, but rather the sequential position when the elements are sorted and scheduled in the program.
[0077] Specifically, the component parameters after initialization of the initial component group can be expressed as including: The first column represents the starter number, primarily connected to port F; the second column represents the end number, primarily connected to port T; and the third column represents the node number, with N components. Using these starter numbers, the computer can divide the initial component group into multiple parallel component groups, such as component group F1, component group F2, etc. The order of components in each parallel component group is consistent with the initial component group. For each parallel component group, the computer can sequentially acquire two adjacent components, such as the first and second components, the second and third components, and so on. Between two adjacent components, the computer can calculate the difference between their node numbers to obtain the interval distance between them in the calculation order, i.e., the index difference. This index difference reflects the queuing interval required between the two parallel components during the calculation process. Based on this, the computer can calculate the delay time of the preceding component, thus clarifying the waiting time required for the following component before calculation, avoiding resource conflicts caused by two parallel components accessing the same node simultaneously in the same clock cycle.
[0078] It should be noted that the delay time is set to prevent resource conflicts between the preceding and following elements in a parallel element group during calculation. Since the last element itself has no other elements following it that need to coordinate or wait, the last element in each parallel element group will not affect any subsequent calculations, and its delay time can be regarded as 0.
[0079] In one embodiment, the process of determining the delay time of the first element among two adjacent elements based on the index difference in step S122 may include:
[0080] S1221: Determine the signal delay time of the adder and multiplier in the component update module, and calculate the delay time of the first component among two adjacent components based on the signal delay time and index difference.
[0081] In this embodiment, when calculating the delay time of an element, the computer device can determine the signal delay time of the adder and multiplier in the element update module, that is, the number of clock cycles required for each addition or multiplication operation to complete one operation in the FPGA. Then, based on the signal delay time and the index difference, the delay time of the first element among two adjacent elements can be calculated.
[0082] Understandably, since adders and multipliers require a certain number of logic levels and clock cycles to complete data propagation, processing, and output when performing operations, in order to further improve the accuracy of delay time, computer equipment can combine signal delay time and index difference to further deduce the scheduling interval requirement between the two parallel elements, thereby calculating the delay time of the previous element.
[0083] Specifically, the expression for calculating the delay time can be as follows:
[0084]
[0085] In the formula, Indicates the delay time; Indicates the signal delay time; This represents the index difference.
[0086] In one embodiment, the process of determining the total waiting time of the initial component group based on each delay time in step S120 may include:
[0087] S123: If there are more than 2 elements in the parallel element group, then starting from the second element in the parallel element group, mark them sequentially as the current element, and mark the element before the current element in the parallel element group as the first element, and mark the element before the current element and the two elements before the current element in the initial element group as the second element and the third element, respectively.
[0088] S124: Get the index difference between the current element and the first element.
[0089] S125: When the index difference is not less than 2, subtract the delay times of the first and third elements from the delay time of the second element to obtain the extra waiting time, and determine whether the extra waiting time is less than 0.
[0090] S126: If so, then keep the delay time of the second element unchanged.
[0091] S127: If not, update the delay time of the second element based on the additional waiting time.
[0092] S128: Add the delay times of each element in the initial element group to obtain the total waiting time of the initial element group.
[0093] In this embodiment, if the number of elements in a parallel element group is greater than 2, the computer device can start from the second element in the parallel element group and sequentially mark it as the current element. The element preceding the current element in the parallel element group is marked as the first element, and the element preceding and the two preceding elements in the initial element group are marked as the second and third elements, respectively. Then, the index difference between the current element and the first element is obtained. When the index difference is not less than 2, the delay time of the second element is subtracted from the delay times of the first and third elements to obtain the extra waiting time. The delay time of the first element can then be optimized based on this extra waiting time. Finally, the computer device can add the optimized delay times of each element in the initial element group to obtain the total waiting time of the initial element group.
[0094] Specifically, when a computer device detects that a parallel element group contains more than two elements, it indicates that there may be unreasonable delay allocation or local scheduling redundancy in the parallel structure, thus leaving room for further optimization. Based on this, the computer device can start from the second element in the parallel element group and sequentially mark each element as the current element, traversing each element and using it as the current analysis object. Then, it can mark the element preceding it in the parallel element group as the first element to record the connection order relationship with the same node, and mark the element preceding it and the two preceding elements in the initial element group as the second and third elements respectively to capture contextual information in the context of global scheduling. Subsequently, the computer device can obtain the index difference between the current element and the first element to measure the interval between the current element and the preceding element in the same group in terms of execution order. If the index difference is not less than 2, it indicates that there may be redundant waiting space between elements. In this case, the computer device can subtract the sum of the delay times of the first and third elements from the current delay time of the second element to obtain an adjustable additional waiting time to reflect the potential time redundancy in the current scheduling structure. Therefore, after obtaining the extra waiting time, the computer device can optimize the delay time of the second element based on that extra waiting time.
[0095] More specifically, if the extra waiting time is less than 0, it means that the delay time of the second component is already the minimum allowed for safe system operation. Further reduction would lead to resource conflicts or scheduling errors between components, so no further adjustment to the delay time of the second component is needed. If the extra waiting time is greater than 0, it means that the delay time of the second component is excessive, i.e., there is redundant waiting time. In this case, the extra waiting time can be used to update the delay time of the second component, that is, to subtract the extra waiting time from its original delay time, thereby compressing the scheduling cycle and improving the overall scheduling efficiency.
[0096] In one embodiment, step S130, which optimizes the initial component group by using a greedy algorithm based on the total waiting time to obtain the optimal component group with the shortest total waiting time, may include:
[0097] S131: Exchange the order of components in the initial component group according to the order exchange rules to obtain the optimized component group, and calculate the total waiting time of the optimized component group.
[0098] S132: Compare the total waiting time of the initial component group with that of the optimized component group, and mark the component group with the smaller total waiting time in the comparison result as the new initial component group.
[0099] S133: Return to execute the process of swapping the order of components in the initial component group according to the order swapping rules to obtain the optimized component group and its subsequent steps, until the optimized component group meets the sorting end condition of the order swapping rules, and the last marked initial component group is taken as the optimal component group.
[0100] In this embodiment, when the computer device optimizes the sorting of the initial component group, it can first exchange the component order in the initial component group according to the order exchange rule to obtain the optimized component group, and calculate the total waiting time of the optimized component group. Then, it compares the total waiting time of the initial component group with that of the optimized component group, and marks the component group with the smaller total waiting time in the comparison result as the new initial component group, thereby selecting the local optimum of the optimization in this round. Then, the computer device can exchange the component order in the initial component group according to the order exchange rule and select the local optimum of the next round until the optimized component group meets the sorting end condition of the order exchange rule, and the last marked initial component group is taken as the optimal component group.
[0101] The sequence swap rule refers to a criterion used to guide the interchange of component positions when optimizing component sorting. For an initial component group of N components, the sequence swap rule can guide it to perform N*N sequence swaps.
[0102] Specifically, the computer device can adjust the order of adjacent or specific components in the initial component group based on a preset sequence exchange rule, forming a new optimized component group. This new optimized component group differs from the original component group in its sorting structure. Next, the computer device can recalculate and accumulate the delay time of each component in the optimized component group to obtain the total waiting time. Then, it can compare the total waiting time of the optimized component group with the total waiting time of the original initial component group, selecting the component group with the smaller total waiting time as the updated result of this round of optimization. This selected component group is marked as the new initial component group, representing the current locally optimal sorting structure. Based on this, the computer device can continue to repeat the above exchange, calculation, and comparison process for the new initial component group based on the sequence exchange rule, iteratively searching for a new locally optimal solution round by round until the current optimized component group no longer meets the further optimization conditions set by the sequence exchange rule. The finally marked initial component group is then taken as the globally optimal component group obtained in this optimization process.
[0103] For example, such as Figure 3 As shown, Figure 3 A flowchart illustrating an optimal component grouping process provided in this application embodiment; Figure 3 In the initial component group of the example, the component group data is 'data', and the number of components is N. After optimization and sorting using a greedy algorithm, the globally optimal component sorting 'newdata' is obtained, forming the optimal component group, i.e., the parameter list 'waitlist' and the shortest total waiting time 'total_time'. In the optimization and sorting of the greedy algorithm, the total waiting time 'ttm1' required for the component data 'data' in the initial component group can be calculated first. Each component is traversed, and the component order is swapped, recorded as 'data2'. The total waiting time 'ttm2' required for 'data2' after the component swap is 'data2'. 'ttm2' is compared with 'ttm1'. If 'ttm2' is less than 'ttm1', it means that the total waiting time under the component group order of 'data2' is locally optimal. Then, after N iterations, the component order is swapped N*N times to find the local optimum each time. Finally, the obtained 'newdata' is the globally optimal component sorting, thus ensuring that the total waiting time required for FPGA calculation is minimized.
[0104] In one embodiment, step S140, which involves sorting components according to the optimal component group and sequentially updating each component to its corresponding component group using a greedy algorithm to minimize the waiting time for each component group, may include:
[0105] S141: According to the component sorting of the optimal component group, mark each component as the current component in turn.
[0106] S142: Use a greedy algorithm to determine the optimal order of the grouping of elements after each current element and its waiting time.
[0107] S143: Take the group of components with the shortest waiting time as the target group of the current component, and update the current component to the target group according to the optimal sorting of the target group.
[0108] In this embodiment, when the computer device optimizes the grouping of the optimal component group, it can mark each component as the current component according to the component sorting of the optimal component group, and then use a greedy algorithm to determine the optimal sorting and waiting time of each component group after the current component is connected in series. The component group with the shortest waiting time is taken as the target group of the current component, and the current component is updated to the target group according to the optimal sorting of the target group.
[0109] Specifically, the computer device can sequentially traverse each element according to the element order of the optimal element group, and mark the currently processed element as the current element. When processing the current element, the computer device can use a greedy algorithm to make grouping decisions for the current element, that is, try to add the current element in series to multiple existing element groups, and calculate the optimal sorting structure of each element group after its addition and the resulting waiting time. Then, it can select the element group with the shortest waiting time from all attempts as the target group for the current element. Based on this, the computer device can officially update the current element to the corresponding group according to the optimal sorting result of the target group, ensuring that the scheduling efficiency remains optimal within the element group.
[0110] Indicatively, such as Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of a component grouping and sorting device provided in an embodiment of this application; Figure 4 Taking two component groups A and B as an example, before grouping the components, the parameters can be initialized first to obtain the optimal component group data and the number of components N. Two empty matrices A and B with N rows are constructed. Then, the components in data are searched sequentially, and the current components are concatenated into groups A and B. A greedy algorithm is used to calculate the optimal sorting of groups A and B to obtain the optimized component sorting newdataA and newdataB of groups A and B. The maximum waiting time ttmA and ttmB required for newdataA and newdataB are calculated respectively. Then, the size of ttmA and ttmB can be judged. If ttmA is less than ttmB, the optimal sorted newdataA is updated to group A, and otherwise the optimal sorted newdataB is updated to group B. This component update process is repeated until all the components in the optimal component group data are updated to groups A and B.
[0111] The component grouping and sorting apparatus provided in the embodiments of this application is described below. The component grouping and sorting apparatus described below can be referred to in correspondence with the component grouping and sorting method described above.
[0112] In one embodiment, such as Figure 4 As shown, Figure 4 This application provides a schematic diagram of a component grouping and sorting device according to an embodiment of the present application; the present application also provides a schematic diagram of a component grouping and sorting device, including a data initialization module 210, a waiting time calculation module 220, a sorting optimization module 230, and a component grouping module 240, specifically including the following:
[0113] The data initialization module 210 is used to obtain the initial component group in the component update module, and to determine the component parameters and the number of components in the initial component group.
[0114] The waiting time calculation module 220 is used to determine the delay time of each element in the initial element group based on the element parameters, and to determine the total waiting time of the initial element group based on each delay time.
[0115] The sorting optimization module 230 is used to optimize the sorting of the initial component group based on the total waiting time using a greedy algorithm, so as to obtain the optimal component group with the shortest total waiting time.
[0116] The component grouping module 240 is used to construct multiple component groups according to the number of components, and to update each component to the corresponding component group in turn using a greedy algorithm according to the component sorting of the optimal component group, so as to minimize the waiting time of each component group.
[0117] In the above embodiments, when performing node analysis in electromagnetic transient simulation, the initial component group in the component update module can be obtained first, and the component parameters and number of components in the initial component group can be determined to provide basic data for component characteristic analysis. Then, the delay time of each component in the initial component group can be determined based on the component parameters, and the total waiting time of the initial component group can be determined based on each delay time. This allows the time consumption of the entire component group during the calculation process to be quantified by the number of clock cycles required for different components in the current order. Next, based on the total waiting time, a greedy algorithm can be used to optimize the component sorting of the initial component group to obtain the optimal component group with the shortest total waiting time. This allows for a full consideration of the differences in calculation time between components, taking into account component characteristics, and minimizing the waiting time between components. Finally, multiple component groups can be constructed based on the number of components, and each component can be updated to the corresponding component group in sequence according to the component sorting of the optimal component group, using a greedy algorithm to minimize the waiting time of each component group. This fully utilizes the parallel computing capabilities of the FPGA, adaptively optimizes the component grouping, and further improves simulation efficiency.
[0118] In one embodiment, the component parameters in the waiting time calculation module 220 may include the start-end number and node number of each component; the waiting time calculation module 220 may also include:
[0119] The parallel element division submodule is used to divide the initial element group into multiple parallel element groups according to the starting end number in the element parameters. The starting end number of each element in each parallel element group is consistent.
[0120] The delay time calculation submodule is used to obtain the node numbers of two adjacent elements in each parallel element group in sequence, subtract them to obtain the index difference, and determine the delay time of the first element in the two adjacent elements based on the index difference.
[0121] In one embodiment, the delay time calculation submodule may include:
[0122] The delay calculation unit is used to determine the signal delay time of the adder and multiplier in the element update module, and calculate the delay time of the first element among two adjacent elements based on the signal delay time and the index difference.
[0123] In one embodiment, the waiting time calculation module 220 may further include:
[0124] The component determination submodule is used to, if there are more than 2 components in a parallel component group, mark the current component starting from the second component in the parallel component group, mark the component preceding the current component in the parallel component group as the first component, and mark the component preceding the current component in the initial component group and the component preceding the current component as the second component and the component preceding the first two components as the third component, respectively.
[0125] The difference acquisition submodule is used to obtain the index difference between the current element and the first element.
[0126] The extra waiting time calculation submodule is used to subtract the delay times of the first and third elements from the delay time of the second element when the index difference is not less than 2, to obtain the extra waiting time, and to determine whether the extra waiting time is less than 0.
[0127] The first update submodule is used to keep the delay time of the second element unchanged when it is less than 0.
[0128] The second update submodule is used to update the delay time of the second element based on the additional waiting time when it is not less than 0.
[0129] The time summation submodule is used to sum the delay times of each element in the initial element group to obtain the total waiting time of the initial element group.
[0130] In one embodiment, the sorting optimization module 230 may include:
[0131] The sequence swapping submodule is used to swap the order of components in the initial component group according to the sequence swapping rules to obtain the optimized component group, and to calculate the total waiting time of the optimized component group.
[0132] The time comparison submodule is used to compare the total waiting time of the initial component group with that of the optimized component group, and to mark the component group with the smaller total waiting time in the comparison result as the new initial component group.
[0133] The loop optimization submodule is used to return to the execution of swapping the order of components in the initial component group according to the order swapping rules, to obtain the optimized component group and its subsequent steps, until the optimized component group meets the sorting end condition of the order swapping rules, and the last marked initial component group is taken as the optimal component group.
[0134] In one embodiment, the component grouping module 240 may include:
[0135] The component tagging submodule is used to sort components according to the optimal component group and mark each component as the current component in turn.
[0136] The component serialization submodule is used to determine the optimal order of component groups after serializing each current component and its waiting time using a greedy algorithm.
[0137] The component update submodule is used to select the component group with the shortest waiting time as the target group for the current component, and update the current component into the target group according to the optimal sorting of the target group.
[0138] In one embodiment, this application also provides a storage medium storing computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform the steps of the element grouping and sorting method as described in any of the above embodiments.
[0139] In one embodiment, this application also provides a computer device storing computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform the steps of the element grouping and sorting method as described in any of the above embodiments.
[0140] Indicatively, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the internal structure of a computer device 300 provided in an embodiment of this application. The computer device 300 can be provided as a server. (Refer to...) Figure 5The computer device 300 includes a processing component 302, which further includes one or more processors, and memory resources represented by memory 301 for storing instructions, such as application programs, that can be executed by the processing component 302. The application programs stored in memory 301 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 302 is configured to execute instructions to perform the element grouping and sorting method of any of the above embodiments.
[0141] The computer device 300 may also include a power supply component 303 configured to perform power management of the computer device 300, a wired or wireless network interface 304 configured to connect the computer device 300 to a network, and an input / output (I / O) interface 305. The computer device 300 may operate on an operating system stored in memory 301, such as Windows Server™, Mac OS X™, Unix™, Linux™, Free BSD™, or similar.
[0142] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0143] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0144] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can be referred to each other.
[0145] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for grouping and sorting components, characterized in that, The method includes: Obtain the initial component group from the component update module, and determine the component parameters and number of components in the initial component group; The delay time of each element in the initial element group is determined based on the element parameters, and the total waiting time of the initial element group is determined based on each delay time. Based on the total waiting time, a greedy algorithm is used to optimize the component sorting of the initial component group to obtain the optimal component group with the shortest total waiting time. Multiple component groups are constructed based on the number of components, and each component is updated to its corresponding component group in turn using the greedy algorithm according to the component sorting of the optimal component group, so as to minimize the waiting time of each component group.
2. The component grouping and sorting method according to claim 1, characterized in that, The component parameters include the start number and node number of each component; The step of determining the delay time of each element in the initial element group based on the element parameters includes: The initial element group is divided into multiple parallel element groups according to the starting end numbers in the element parameters, and the starting end numbers of each element in each parallel element group are consistent. For each group of parallel elements, the node numbers of two adjacent elements are obtained sequentially and subtracted to obtain an index difference. Based on the index difference, the delay time of the first element among the two adjacent elements is determined.
3. The component grouping and sorting method according to claim 2, characterized in that, Determining the delay time of the first element among two adjacent elements based on the index difference includes: The signal delay times of the adder and multiplier in the element update module are determined, and the delay time of the first element among the two adjacent elements is calculated based on the signal delay time and the index difference.
4. The component grouping and sorting method according to claim 2, characterized in that, The determination of the total waiting time of the initial component group based on each delay time includes: If there is a parallel element group with more than 2 elements, then starting from the second element in the parallel element group, each element is sequentially marked as the current element, and the element preceding the current element in the parallel element group is marked as the first element, and the element preceding the current element and the two elements preceding it in the initial element group are marked as the second element and the third element, respectively. Obtain the index difference between the current element and the first element; When the index difference is not less than 2, the delay time of the second element is subtracted from the delay time of the first element and the third element to obtain the additional waiting time, and it is determined whether the additional waiting time is less than 0. If so, then keep the delay time of the second element unchanged; If not, the delay time of the second element is updated based on the additional waiting time; The delay times of each element in the initial element group are added together to obtain the total waiting time of the initial element group.
5. The component grouping and sorting method according to claim 1, characterized in that, The step of optimizing the initial component group using a greedy algorithm based on the total waiting time to obtain the optimal component group with the shortest total waiting time includes: The components in the initial component group are swapped according to the order swapping rules to obtain the optimized component group, and the total waiting time of the optimized component group is calculated. The total waiting time of the initial component group and the optimized component group is compared, and the component group with the smaller total waiting time in the comparison result is marked as the new initial component group; Return to the previous step and perform the step of swapping the order of the components in the initial component group according to the order swapping rules to obtain the optimized component group and subsequent steps, until the optimized component group meets the sorting end condition of the order swapping rules, and the last marked initial component group is taken as the optimal component group.
6. The component grouping and sorting method according to claim 1, characterized in that, The step of sorting components according to the optimal component group and sequentially updating each component to its corresponding component group using the greedy algorithm to minimize the waiting time for each component group includes: According to the element sorting of the optimal element group, each element is marked as the current element in turn; The greedy algorithm is used to determine the optimal order of each group of elements connected in series with the current element and its waiting time. The component group with the shortest waiting time is selected as the target group for the current component, and the current component is updated to the target group according to the optimal sorting of the target group.
7. A component grouping and sorting device, characterized in that, include: The data initialization module is used to obtain the initial component group from the component update module, and to determine the component parameters and the number of components in the initial component group; A waiting time calculation module is used to determine the delay time of each element in the initial element group based on the element parameters, and to determine the total waiting time of the initial element group based on each delay time; The sorting optimization module is used to optimize the sorting of the initial component group based on the total waiting time using a greedy algorithm, so as to obtain the optimal component group with the shortest total waiting time. The component grouping module is used to construct multiple component groups according to the number of components, and to update each component to the corresponding component group in turn using the greedy algorithm according to the component sorting of the optimal component group, so as to minimize the waiting time of each component group.
8. The component grouping and sorting device according to claim 7, characterized in that, The waiting time calculation module includes: The parallel element division submodule is used to divide the initial element group into multiple parallel element groups according to the starting end number in the element parameters, wherein the starting end number of each element in each parallel element group is consistent. The delay time calculation submodule is used to obtain the node numbers of two adjacent elements in each parallel element group in sequence, subtract them to obtain the index difference, and determine the delay time of the first element among the two adjacent elements based on the index difference.
9. A storage medium, characterized in that: The storage medium stores computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform the steps of the element grouping and sorting method as described in any one of claims 1 to 6.
10. A computer device, characterized in that, include: One or more processors, and memory; The memory stores computer-readable instructions that, when executed by the one or more processors, perform the steps of the element grouping and sorting method as described in any one of claims 1 to 6.