Method, device and equipment for generating schematic diagram based on DDR PHY layout and readable medium

Abstract

The application discloses a method and device for generating a schematic diagram based on a DDRPHY layout, equipment and a readable medium, the method comprising: sorting a plurality of modules in the DDRPHY layout according to the arrangement direction and module coordinates of the modules to obtain a module sequence list; setting a schematic diagram symbol corresponding to the modules according to the module type in the module sequence list and the arrangement direction; determining a signal line direction according to the pin direction of the schematic diagram symbol; and connecting the schematic diagram symbol according to the signal line direction and signal line type to generate a schematic diagram corresponding to the DDRPHY layout. The technical scheme can obtain a module sequence list according to the arrangement direction and coordinates of the modules in the DDRPHY layout, realize reverse generation from a layout to a schematic diagram, and be used for layout and schematic diagram consistency verification, thereby improving verification efficiency and pass rate.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit design technology, specifically relating to a method, apparatus, device, and readable medium for generating schematic diagrams based on DDRPHY layout. Background Technology

[0002] In the design flow of DDRPHY (Double Data Rate Physical Layer Layout), after the layout design is completed, a corresponding schematic needs to be generated for use in LVS (Layout and Schematic). Figure 1 Key verification steps, such as consistency verification, are necessary to ensure that the chip's electrical connections and functions conform to design specifications. However, in existing technologies, the generation of the schematic diagram for the DDRPHY simulation part requires simulation design engineers to manually place the corresponding schematic symbols one by one according to the actual arrangement direction of each module in the layout. This method is not only inefficient, but also prone to problems such as misjudgment of signal line direction and confusion of connection rules, resulting in a mismatch between the generated schematic diagram and the layout, making it difficult to pass subsequent LVS verification. Summary of the Invention

[0003] The purpose of this application is to provide a method, system, and computer program product for generating schematic diagrams based on DDRPHY layout, so as to improve the generation of schematic diagrams from layouts and schematics. Figure 1 Efficiency and pass rate of consistency verification.

[0004] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part by practice of this application.

[0005] According to one aspect of the embodiments of this application, a method for generating a schematic diagram based on a DDRPHY layout is provided, comprising:

[0006] The modules are sorted according to their arrangement direction and coordinates in the DDRPHY layout to obtain a module order list;

[0007] Set the schematic symbol corresponding to the module according to the module type in the module sequence list and the arrangement direction;

[0008] The signal line direction is determined according to the pin direction of the schematic symbols; wherein, the signal line includes wires connecting the various schematic symbols;

[0009] The schematic symbols are connected according to the signal line direction and signal line type to generate the schematic corresponding to the DDRPHY layout; wherein, different signal line types correspond to different schematic symbol connection methods.

[0010] According to one aspect of the embodiments of this application, a method for generating a schematic diagram based on a DDRPHY layout is provided, comprising:

[0011] In response to a trigger operation that enters the first parameter configuration interface, the configuration options for the first parameter are displayed in the first parameter configuration interface; the first parameter includes at least the arrangement direction of the modules.

[0012] According to one aspect of the embodiments of this application, a method for generating a schematic diagram based on a DDRPHY layout is provided, comprising:

[0013] Obtain the boundary parameters of the module in the DDRPHY layout, the boundary parameters including the coordinates of the lower left corner and the upper right corner of the module;

[0014] Calculate the coordinates of the center point of the module based on the boundary parameters of the module;

[0015] The coordinates of the center points of the multiple modules are sorted according to the arrangement direction to obtain a coordinate order list;

[0016] The module order list is generated based on the coordinate order list.

[0017] According to one aspect of the embodiments of this application, a method for generating a schematic diagram based on a DDRPHY layout is provided, comprising:

[0018] If the arrangement direction is the first direction, then the first preset coordinate values ​​of the center point coordinates of the multiple modules are sorted according to preset rules to obtain the coordinate order list; the coordinate axis direction corresponding to the first preset coordinate value is perpendicular to the first direction;

[0019] If the arrangement direction is the second direction, then the second preset coordinate values ​​of the center point coordinates of the multiple modules are sorted according to preset rules to obtain the coordinate order list; the coordinate axis direction corresponding to the second preset coordinate value is perpendicular to the second direction;

[0020] If the arrangement direction includes a first direction and a second direction, then the first preset coordinate values ​​among the coordinates of the center points of multiple modules arranged in the first direction are sorted according to preset rules to obtain a coordinate order list for the first direction; and the second preset coordinate values ​​among the coordinates of the center points of multiple modules arranged in the second direction are sorted according to preset rules to obtain a coordinate order list for the second direction; the coordinate order list for the first direction and the coordinate order list for the second direction are concatenated according to a preset format to obtain the coordinate order list; wherein, the first direction is perpendicular to the second direction, the first direction is perpendicular to the first preset coordinate axis direction, and the second direction is perpendicular to the second preset coordinate axis direction.

[0021] According to one aspect of the embodiments of this application, a method for generating a schematic diagram based on a DDRPHY layout is provided, comprising:

[0022] Traverse the coordinate order list to obtain the current center point coordinates from the coordinate order list;

[0023] For the current center point coordinates, iterate through the center point coordinates of each module in the DDRPHY layout. If the center point coordinates of a module match the current center point coordinates, add the name of that module to the module order list.

[0024] According to one aspect of the embodiments of this application, a method for generating a schematic diagram based on a DDRPHY layout is provided, comprising:

[0025] In response to a trigger operation that enters the second parameter configuration interface, the configuration options for the second parameter are displayed in the second parameter configuration interface; the second parameter includes at least a parameter for determining the signal line type.

[0026] According to one aspect of the embodiments of this application, a method for generating a schematic diagram based on a DDRPHY layout is provided, comprising:

[0027] Traverse the module names in the ordered list and divide the modules into a first module and a second module according to the module names; wherein the module name of the first module does not include the specified string, and the module name of the second module includes the specified string;

[0028] Pair the module name of the first module with the name of the first schematic symbol library to generate a first pairing list; pair the module name of the second module with the name of the second schematic symbol library to generate a second pairing list;

[0029] According to the first pairing list, the schematic symbol corresponding to the first module is obtained from the first schematic symbol library corresponding to the first schematic symbol library name; and according to the second pairing list, the schematic symbol corresponding to the second module is obtained from the second schematic symbol library corresponding to the second schematic symbol library name.

[0030] The schematic symbols corresponding to the first module and the second module are set according to the arrangement direction.

[0031] According to one aspect of the embodiments of this application, a method for generating a schematic diagram based on a DDRPHY layout is provided, comprising:

[0032] If the arrangement direction is the first direction, then starting from the first preset coordinate, multiple schematic symbols corresponding to the modules are set sequentially according to the preset interval value.

[0033] If the arrangement direction is the second direction, then starting from the second preset coordinates, multiple schematic symbols corresponding to the modules are sequentially set according to preset interval values.

[0034] If the arrangement direction includes a first direction and a second direction, then starting from the first preset coordinate, the schematic symbols corresponding to the multiple modules with the first direction are set sequentially according to a preset interval value; and starting from the second preset coordinate, the schematic symbols corresponding to the multiple modules with the second direction are set sequentially according to a preset interval value.

[0035] According to one aspect of the embodiments of this application, a method for generating a schematic diagram based on a DDRPHY layout is provided, comprising:

[0036] Obtain the boundary parameters of the schematic symbol and the pin coordinates of each pin in the schematic symbol; the boundary parameters of the schematic symbol include the coordinates of the lower left corner and the upper right corner of the schematic symbol;

[0037] The pin orientation is determined based on the boundary parameters and the pin coordinates; wherein the pin orientation represents the arrangement direction of the pins in the schematic symbol.

[0038] The direction of the signal line is determined based on the direction of the pin.

[0039] According to one aspect of the embodiments of this application, a method for generating a schematic diagram based on a DDRPHY layout is provided, comprising:

[0040] The signal lines are classified according to the parameters configured in the second parameter configuration interface to determine the signal line type, and the corresponding signal line types are obtained.

[0041] Obtain the corresponding signal line connection rules according to the signal line type; the signal line connection rules include the connection method between the signal line and the schematic symbol, and different signal line types correspond to different signal line connection rules;

[0042] The schematic symbols are connected according to the signal line direction and the signal line connection rules to generate the schematic corresponding to the DDRPHY layout.

[0043] According to one aspect of the embodiments of this application, a schematic diagram generation control device based on DDRPHY layout is provided, the control device comprising:

[0044] The list generation module is used to sort multiple modules according to the arrangement direction and coordinates of the modules in the DDRPHY layout to obtain a module order list;

[0045] The symbol setting module is used to set the corresponding schematic symbols according to the module type and the arrangement direction in the module order list;

[0046] A direction determination module is used to determine the direction of signal lines based on the pin directions of the schematic symbols; wherein, the signal lines include wires connecting the various schematic symbols;

[0047] The schematic generation module is used to connect the schematic symbols according to the signal line direction and signal line type to generate the schematic corresponding to the DDRPHY layout; wherein, different signal line types correspond to different schematic symbol connection methods.

[0048] According to one aspect of the embodiments of this application, an electronic device is provided, the electronic device comprising:

[0049] Processor; and

[0050] A memory for storing executable instructions of a processor; wherein the processor executes the executable instructions to cause an electronic device to perform the method for generating a schematic diagram based on a DDRPHY layout in any embodiment of this application.

[0051] According to one aspect of the embodiments of this application, a computer-readable medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method for generating schematic diagrams based on DDRPHY layout in any embodiment of this application.

[0052] In the technical solution provided in this application embodiment, firstly, multiple modules are sorted according to the arrangement direction and coordinates of the modules in the DDRPHY layout to obtain a module order list; then, corresponding schematic symbols are set according to the module type and arrangement direction in the module order list; next, the signal line direction is determined according to the pin direction of the schematic symbols; wherein, the signal line includes wires connecting each schematic symbol; finally, the schematic symbols are connected according to the signal line direction and signal line type to generate the schematic corresponding to the DDRPHY layout; wherein, different signal line types correspond to different schematic symbol connection methods. In this way, a module order list can be obtained according to the arrangement direction and coordinates of the modules in the DDRPHY layout, realizing automatic reverse generation from the layout to the corresponding schematic, eliminating the need for manual verification and connection of schematic symbols, thereby avoiding problems such as misalignment, missing connections, and layout errors that are prone to occur during manual operation, ensuring that the generated schematic and layout are highly consistent in module order, signal connection, and layout logic, thus improving the consistency between the layout and the schematic. Figure 1 The accuracy and pass rate of consistency verification.

[0053] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0054] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0055] Figure 1 A schematic diagram of the system architecture applying the technical solution of this application is shown.

[0056] Figure 2 A flowchart illustrating a method for generating schematic diagrams based on DDRPHY layout provided in one embodiment of this application is shown.

[0057] Figure 3 A schematic diagram of the layout structure provided in one embodiment of this application is shown.

[0058] Figure 4 The first parameter configuration interface provided in one embodiment of this application is illustrated schematically.

[0059] Figure 5 A flowchart illustrating one embodiment of this application is shown schematically.

[0060] Figure 6A The second parameter configuration interface provided in one embodiment of this application is illustrated schematically.

[0061] Figure 6B A pin diagram of one embodiment of this application is shown schematically.

[0062] Figure 6C A schematic diagram of a module provided in one embodiment of this application is shown.

[0063] Figure 7A A schematic diagram of schematic symbols provided in one embodiment of this application is shown.

[0064] Figure 7B A pin diagram of one embodiment of this application is shown schematically.

[0065] Figure 8A A flowchart illustrating the generation of a schematic diagram according to an embodiment of this application is shown schematically.

[0066] Figure 8B A flowchart illustrating the generation of a schematic diagram according to an embodiment of this application is shown schematically.

[0067] Figure 9A schematic block diagram of the control device structure provided in an embodiment of this application is shown.

[0068] Figure 10 A schematic diagram of the computer system architecture used to implement the technical solution of this application is shown. Detailed Implementation

[0069] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0070] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0071] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0072] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0073] Figure 1 A schematic diagram of the system architecture applying the technical solution of this application is shown.

[0074] like Figure 1As shown, the system architecture 100 may include terminal devices 110, a network 120, and a server 130. Terminal devices 110 may include smartphones, tablets, laptops, smart voice interaction devices, etc. Server 130 may be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. Network 120 may be a communication medium of various connection types capable of providing a communication link between terminal devices 110 and server 130, such as a wired communication link or a wireless communication link. Depending on the implementation requirements, the system architecture in this embodiment may have any number of terminal devices, networks, and servers.

[0075] The technical solutions provided in this application can be applied to terminal device 110, server 130, or jointly implemented by terminal device 110 and server 130. This application does not impose any special limitations on this.

[0076] The method for generating schematic diagrams based on DDRPHY layout provided in this application will be described in detail below with reference to specific implementation methods.

[0077] Figure 2 A flowchart illustrating a method for generating a schematic diagram based on a DDRPHY layout according to an embodiment of this application is shown. The implementation process of the technical solution of this application will be described below using a terminal device as the execution subject. Figure 2 As shown, the method for generating a schematic diagram based on a DDRPHY layout provided in this embodiment includes steps 210 to 240, as detailed below:

[0078] Step 210: Sort multiple modules according to the arrangement direction and coordinates of the modules in the DDRPHY layout to obtain a module order list.

[0079] Specifically, the DDRPHY layout (Double Data Rate Physical Layer Layout) is the physical implementation of the Double Data Rate memory interface physical layer in integrated circuit design. It serves as a crucial bridge connecting the chip's digital logic section with external DDR (Double Data Rate) memory. The DDRPHY layout mainly comprises three parts: input / output (IO) modules, phase-locked loop (PLL) modules, and digital standard cells designed by analog layout engineers. The IO and PLL modules are arranged in a predetermined order by analog layout engineers for use in DRC (Design Rule Check) and LVS (Layout vs. Schematic Check). Figure 1Key verification steps, such as conformity checks, ANT (Antenna Effect Check), and ESD (Electrostatic Discharge), are implemented to ensure physical compliance.

[0080] A module refers to a reusable unit or component with independent function and clear boundaries, divided to achieve a specific function and simplify the construction and management of complex systems. In the DDRPHY layout of this application, modules may include I / O modules and phase-locked loop (PLL) modules. Furthermore, the module arrangement direction refers to the spatial orientation or layout direction determined when physically laying out modules with independent functions based on functional requirements, physical space constraints, signal transmission characteristics, and process rules. The module order list includes the arrangement order of all modules in the DDRPHY layout, which can be used to generate the schematic diagram subsequently.

[0081] In one embodiment of this application, the process of obtaining the module order list may include: obtaining the boundary parameters of the modules in the DDRPHY layout; calculating the center point coordinates of the modules based on the boundary parameters of the modules; sorting the center point coordinates of multiple modules according to the arrangement direction to obtain a coordinate order list; and generating a module order list based on the coordinate order list.

[0082] Specifically, in DDRPHY layout design, module boundary parameters are a set of parameters used to precisely define the physical space range, electrical interaction boundaries, and functional partition boundaries of each module. These parameters can be directly accessed and obtained through the Skill language's API (Application Programming Interface), specifically including the coordinates of the module's lower left and upper right corners. The module's center point coordinates refer to the geometric center point coordinates of the module, and the coordinate order list refers to the ordered set of coordinates formed after sorting the module center point coordinates according to preset rules. The module's arrangement direction includes at least one of a first direction and a second direction, wherein the first and second directions are perpendicular to each other.

[0083] For example, the process of calculating the center point coordinates of a module can be as follows: first, obtain the coordinates of the lower left corner and the upper right corner of each module in the DDRPHY layout; then, determine a rectangular area based on the coordinates of the lower left corner and the upper right corner; and finally, directly calculate the center point coordinates of the rectangular area by calling the centerBox API of the layout tool.

[0084] Figure 3 A schematic diagram illustrating a layout structure provided in one embodiment of this application is shown. Figure 3As shown, the layout mainly includes three parts: Region 310, Region 320, and Region 330. Regions 310 and 320 contain multiple modules. Modules in Region 310 are arranged in an east-west (EW) direction, while modules in the green area of ​​Region 320 are arranged in a north-south (NS) direction. Each module in both regions has a name, such as DDRIO_A_EW in Region 310 and DDRIO_A_NS in Region 320. Region 330 includes the digital portion of the DDRPHY layout. This portion is mainly responsible for implementing digital signal processing, timing control, data transmission and reception coordination, and communication with the upper-level controller for the memory interface. Through cooperation with the analog portion (such as I / O modules and PLL modules), it ensures the accuracy and stability of high-speed data transmission.

[0085] In one embodiment of this application, the process of sorting the center point coordinates of multiple modules according to the arrangement direction to obtain a coordinate order list may include: if the arrangement direction is a first direction, sorting the first preset coordinate values ​​of the center point coordinates of multiple modules according to preset rules to obtain a coordinate order list.

[0086] Specifically, "arrangement direction is the first direction" indicates that all modules in the DDRPHY layout are arranged according to the first direction. The coordinate axis corresponding to the first preset coordinate value is perpendicular to the first direction. The first preset coordinate value refers to the coordinate axis value of the module's center point, which can be either the X-axis value or the Y-axis value. The preset rules include the sorting rules for the first preset coordinate values, which can be rules such as descending from largest to smallest or ascending from smallest to largest.

[0087] For example, the first direction can be the east-west (EW) direction, and the first preset coordinate value can be the Y-axis value of the center point coordinate. Then, the process of sorting the center point coordinates of the modules in the first direction can include: firstly, obtaining the boundary parameters of multiple modules arranged in the first direction, and using the algorithm in the API interface to calculate the center point coordinates of each module; then sorting the Y-axis values ​​of the center point coordinates according to the preset rules from smallest to largest to obtain the coordinate order list.

[0088] In one embodiment of this application, the process of obtaining the coordinate order list may further include: if the arrangement direction is the second direction, sorting the second preset coordinate values ​​of the center point coordinates of multiple modules according to preset rules to obtain the coordinate order list.

[0089] Specifically, the coordinate axis corresponding to the second preset coordinate value is perpendicular to the second direction.

[0090] For example, the second direction can be the north-south (NS) direction, and the second preset coordinate value can be the X-axis value of the center point coordinate. Then, the process of sorting the center point coordinates of the second direction module can include: first, obtaining the boundary parameters of multiple modules arranged in the second direction, and using the algorithm in the API interface to calculate the center point coordinates of each module; then, sorting the X-axis values ​​of the center point coordinates according to the preset rules from smallest to largest to obtain the coordinate order list.

[0091] In one embodiment of this application, the process of obtaining the coordinate order list may further include: if the arrangement direction includes a first direction and a second direction, sorting the first preset coordinate values ​​among the coordinates of the center points of multiple modules arranged in the first direction according to preset rules to obtain a coordinate order list for the first direction; and sorting the second preset coordinate values ​​among the coordinates of the center points of multiple modules arranged in the second direction according to preset rules to obtain a coordinate order list for the second direction; and concatenating the coordinate order list for the first direction and the coordinate order list for the second direction according to a preset format to obtain a coordinate order list.

[0092] Specifically, the first preset coordinate axis direction is the coordinate axis direction corresponding to the first preset coordinate value, and the second preset coordinate axis direction is the coordinate axis direction corresponding to the second preset coordinate value. The preset format includes a method of concatenating the coordinate order lists of the first and second directions, which can be vertical or horizontal concatenation. For example, concatenating the coordinate order lists of the first and second directions according to the preset format of vertical concatenation yields the following result: Figure 3 The portion formed by the first region 310 and the second region 320 shown.

[0093] In one embodiment of this application, generating a module order list based on a coordinate order list includes: traversing each center point coordinate in the coordinate order list to obtain the current center point coordinate; then embedding a traversal to traverse the center point coordinates of each module in the DDRPHY layout; next, matching the current center point coordinate with the traversed center point coordinate to verify whether they are consistent; if the current center point coordinate matches a certain traversed center point coordinate, adding the module name corresponding to that center point coordinate to the module order list; then, continuing the traversal and matching until all center point coordinates in the coordinate order list are successfully matched, thereby obtaining a module order list including multiple module names.

[0094] Specifically, the current center point coordinates refer to the center point coordinates corresponding to the current iteration position during the traversal of the coordinate order list. Matching the current center point coordinates with the center point coordinates obtained from the traversal is to associate the center point coordinates in the coordinate order list with the corresponding module names, so as to obtain a module order list that includes an ordered set of module names.

[0095] For example, if the arrangement direction of the modules in the layout is the first direction, then the final module order list can be as described above. Figure 3 The first region 310 in the layout displays an ordered list of module names; if the module arrangement direction in the layout is the second direction, the final module order list can be as described above. Figure 3 The second region 320 in the layout displays an ordered list of module names; if the module arrangement direction in the layout includes both the first and second directions, then the final module order list includes the aforementioned... Figure 3 The first region 310 and the second region 320 in the image display an ordered list of module names.

[0096] In one embodiment of this application, before sorting multiple modules according to the arrangement direction and coordinates of the modules in the DDRPHY layout, the method further includes: in response to a trigger operation of entering the first parameter configuration interface, displaying the configuration options of the first parameter in the first parameter configuration interface.

[0097] Specifically, the first parameter includes at least the arrangement direction of the modules, and its configuration options are used to configure the first parameter. The configuration method can be keyboard input, checking boxes, double-clicking, etc.

[0098] Figure 4 The first parameter configuration interface provided in one embodiment of this application is illustrated schematically.

[0099] like Figure 4 As shown, the first parameter configuration interface may include a key step area 410 for obtaining the sequence list and configuration options 420 for the first parameter. The first parameter configuration option 420 configures the first parameter, including the sequence list export path `pinlist outfile` and the module arrangement direction `IOdirection`. The sequence list export path `pinlistoutfile` can be entered directly by the user via the keyboard or selected from the terminal device file path; the module arrangement direction `IOdirection` can be configured by clicking or checking the selection boxes before each direction character. Here, `EW` indicates that the module arrangement direction `IOdirection` is east-west, `NS` indicates that the module arrangement direction `IOdirection` is north-south, and `EW / NS` indicates that in this DDRPHY layout, there are both east-west and north-south oriented modules. Figure 4 As shown, the current selected direction is EW, meaning the current module's IOdirection is east-west.

[0100] Step 220: Set the corresponding schematic symbols according to the module type and arrangement direction in the module order list.

[0101] Specifically, module types are derived from the functional attributes and naming characteristics of modules, and can include first modules and second modules. In the DDRPHY layout, module types can include input / output (IO) modules and phase-locked loop (PLL) modules. Schematic symbols are graphical abstract identifiers used in schematics to represent module functions and pin attributes; their shape and pin definitions strictly match the electrical characteristics of the corresponding module.

[0102] In one embodiment of this application, the process of setting schematic symbols may be as follows: traversing the module names in the sequential list and dividing the modules into a first module and a second module according to the module names; pairing the module name of the first module with the name of the first schematic symbol library to generate a first pairing list; pairing the module name of the second module with the name of the second schematic symbol library to generate a second pairing list; obtaining the schematic symbol corresponding to the first module from the first schematic symbol library corresponding to the first schematic symbol library name according to the first pairing list; obtaining the schematic symbol corresponding to the second module from the second schematic symbol library corresponding to the second schematic symbol library name according to the second pairing list; and setting the schematic symbols corresponding to the first module and the second module according to the arrangement direction.

[0103] Specifically, the module name of the first module does not include a specified string, while the module name of the second module does. This specified string is a specific identifier used to classify module types. Classifying module types is primarily for matching corresponding schematic symbol libraries to different module types; different module types correspond to different schematic symbol libraries. The first schematic symbol library refers to the resource set storing the schematic symbols corresponding to the first module. These schematic symbols are used in the schematic to indicate the corresponding first module, and the name of the first schematic symbol library is its library identifier string. The second schematic symbol library is the resource set storing the schematic symbols corresponding to the second module. These schematic symbols are used in the schematic to indicate the corresponding second module, and the name of the second schematic symbol library is also its library identifier string.

[0104] The first pairing list includes the mapping relationship between each module name and the corresponding first schematic symbol library name. Its list format can be "[(first module name 1, first schematic symbol library name 1), (first module name 2, first schematic symbol library name 2), ... (first module name n, first schematic symbol library name n)]". The second pairing list includes the mapping relationship between each module name and the corresponding second schematic symbol library name. Its list format can be "[(second module name 1, second schematic symbol library name 1), (second module name 2, second schematic symbol library name 2), ... (second module name n, second schematic symbol library name n)]".

[0105] Figure 5 A flowchart illustrating one embodiment of this application is shown schematically. For example... Figure 5 As shown, the specified string used to distinguish module types can be "PLL". Therefore, the first module can be an IO module whose module name does not contain "PLL", and the second module can be a PLL module that contains "PLL".

[0106] For example, if the DDRPHY layout contains modules DDRIO_A_EW, DDRIO_B_EW, DDRIO_C_EW, PLL_A_EW, and PLL_B_EW, the schematic symbol library name pairing process includes: first, creating a text reading interface and adding the module names in the sequential list to the variable NameList one by one, thereby traversing the variable NameList; then, determining whether the module names in the variable NameList contain "PLL", obtaining the IO modules (i.e., the first module): DDRIO_A_EW, DDRIO_B_EW, and DDRIO_C_EW, and the PLL modules (i.e., the second module): PLL_A_EW and PLL_B_EW; next, pairing the IO modules with the corresponding first schematic symbol library names, obtaining the first pairing list "[(DDRIO_A_EW, DDRIO_A_EW symbol library name), (DDRIO_B_EW, DDRIO_B_EW symbol library name), (DD The first pairing list "[(PLL_A_EW, PLL_A_EW symbol library name)]" is used to pair the PLL modules with the corresponding second schematic symbol library names. The second pairing list "[(PLL_A_EW, PLL_A_EW symbol library name), PLL_B_EW, PLL_B_EW symbol library name)]" is then added. Finally, the elements from the first and second pairing lists are added to the pairing list "namelist". This "namelist" includes the mapping relationship between the module names and corresponding schematic symbol library names of all modules in the DDRPHY layout. Specifically, the list format is "[(DDRIO_A_EW, DDRIO_A_EW symbol library name), (DDRIO_B_EW, DDRIO_B_EW symbol library name), (DDRIO_C_EW, DDRIO_C_EW symbol library name), (PLL_A_EW, PLL_A_EW symbol library name), PLL_B_EW, PLL_B_EW symbol library name)]".

[0107] In one embodiment of this application, the process of setting schematic symbols according to the arrangement direction can be as follows: if the arrangement direction is the first direction, then starting from the first preset coordinate, set the schematic symbols corresponding to multiple modules sequentially according to the preset interval value.

[0108] Specifically, the first preset coordinate is the initial reference coordinate, such as (0, 0), set beforehand when placing the schematic symbol corresponding to the first direction module. This coordinate is the starting position of the schematic symbol layout. Subsequent schematic symbols will be arranged sequentially according to the preset interval value, based on this coordinate, to ensure that the symbols form an orderly initial arrangement. The preset interval value is a fixed distance parameter between two adjacent schematic symbols when placing multiple schematic symbols (e.g., 15 units, the unit can be adapted to the coordinate system of the design tool). Setting the preset interval value is to ensure that the schematic symbols maintain a uniform spacing, avoid overlap or chaotic arrangement, thereby improving the standardization and readability of the schematic layout.

[0109] In one embodiment of this application, the process of setting schematic symbols according to the arrangement direction can also be as follows: if the arrangement direction is the second direction, then starting from the second preset coordinates, set the schematic symbols corresponding to multiple modules sequentially according to the preset interval value.

[0110] Specifically, the second preset coordinates are the initial reference coordinates set in advance when placing the schematic symbols corresponding to the first orientation module, such as coordinates (0, -15) or (0, 15). The first preset coordinates and the second preset coordinates are located at different positions on the coordinate system, and there can be a fixed vertical or horizontal offset between them to avoid overlap of schematic symbols corresponding to modules with different orientations.

[0111] In one embodiment of this application, the process of setting schematic symbols according to the arrangement direction may further include: if the arrangement direction includes a first direction and a second direction, then starting from a first preset coordinate, setting schematic symbols corresponding to multiple modules with the first direction in sequence according to a preset interval value; and starting from a second preset coordinate, setting schematic symbols corresponding to multiple modules with the second direction in sequence according to a preset interval value.

[0112] Specifically, since the first and second preset coordinates are located at different positions in the coordinate system, a fixed interval is maintained between the schematic symbols corresponding to multiple modules arranged in the first direction (starting from the first preset coordinate) and the schematic symbols corresponding to multiple modules arranged in the second direction (starting from the second preset coordinate). This allows users or designers to clearly observe the setting of schematic symbols corresponding to modules arranged in different directions.

[0113] In one embodiment of this application, before connecting schematic symbols according to signal line direction and signal line type, the method further includes: in response to a trigger operation of entering a second parameter configuration interface, displaying configuration options for the second parameter in the second parameter configuration interface.

[0114] Specifically, signal lines include wires connecting various schematic symbols. Signal line types include power signal lines, ground signal lines, pad signal lines, common signal lines, and bus signal lines. Power signal lines are dedicated lines that provide stable operating voltage to circuit modules. These can include MVDDQ (Memory Voltage supplied to the output buffers) for data signals and MVDD (Memory Core Voltage) for main circuit power. They must be uniformly labeled to ensure electrical connection between all module pins on the same power network and must be strictly isolated from ground signal lines to avoid short circuits. Ground signal lines are zero-potential reference lines in the circuit, used to establish a stable potential reference and discharge circuit noise and abnormal currents, such as the MVSS (Memory Voltage Source Supply) ground signal line. Pad signal lines are dedicated lines that enable physical and electrical connections between chips and external devices such as DDR memory. They include basic PAD signals and differential signals such as PADP (Pad Positive) and PADN (Pad Negative). Each pad signal line is uniquely identified by a "PAD_serial number" (e.g., "PAD_1", "PAD_2"). One end connects to an internal module pin, and the other end serves as an external connection interface. Each pad signal line is independently separated to avoid signal confusion. Bus signal lines are parallel transmission lines composed of a group of signal lines of the same type and function, such as a 3-bit wide H_ODT_PD<2:0>. The second parameter must include at least the parameter used to determine the signal line type.

[0115] Figure 6A The second parameter configuration interface provided in one embodiment of this application is illustrated schematically. Figure 6A As shown, the second parameter configuration interface can include a key step area 610 for generating the schematic and configuration options 620 for the second parameters. The second parameters configured in the second parameter configuration interface can include the library name LayoutLibName of the DDRPHY layout, the cell name LayoutCellName, the signal line name list PathNetList, and the power / ground line name list PgNetList. The signal line name list PathNetList includes the names of pad signal lines, common signal lines, and bus signal lines; the power / ground line name list PgNetList includes the names of power signal lines and ground signal lines. The power / ground line name list PgNetList is used to generate pins connecting power or ground signals, and these pins can be represented by red arrows, such as... Figure 6BAs shown, it includes the power supply pin MVDDQ, the power supply pin MVDD, and the ground pin MVSS.

[0116] Figure 6C The schematic diagram illustrates a module diagram provided in one embodiment of this application, such as... Figure 6C As shown, the module is named DDRIO_A_NS and is arranged in a north-south direction. Power lines, ground lines, and various signal lines are distributed on the DDRIO_A_NS module. Specifically, the upper area of ​​the DDRIO_A_NS module contains lines connecting to the digital section, used for signal interaction with the digital section; the middle area contains power lines, ground lines, and common signal lines, arranged vertically in layers. The power lines provide power to the module, the ground lines are used for signal grounding and ensuring circuit stability, and the common signal lines are used for transmitting specific signals; the lower area contains PAD (pad) signal lines for external connections. Thus, the power lines, ground lines, and various signal lines are arranged in a clear hierarchy and work together to ensure the signal transmission and power supply functions of the DDRIO_A_NS module in the NS direction.

[0117] For example, the second parameter may also include a bus cut-out module list (BusCutCellList), a sequential list storage path (InfilePath), a first schematic symbol library name list (DDRIOschLib), a first module name list (DDRIO_cellname), a second schematic symbol library name list (PLLschLib), and the module arrangement direction (IOdirection). The bus cut-out module list (BusCutCellList) refers to a set of specific module names preset in the second parameter configuration interface. It identifies specific module names whose bus signal line (Bus line) connections need to be disconnected, enabling automated segmentation and renaming of bus signal line connections. For instance, if the module DDRIO_A_EW is found in the bus cut-out module list (BusCutCellList), the bus signal lines at both ends of module DDRIO_A_EW need to be disconnected, and subsequent signal lines with the same name need to be renamed to avoid misconnection of bus signals from different functional areas.

[0118] The first schematic symbol library name list DDRIOschLib includes a set of schematic symbol library names storing the schematic symbols corresponding to the first module, and the second schematic symbol library name list PLLschLib includes a set of schematic symbol library names storing the schematic symbols corresponding to the second module. Furthermore, the module arrangement direction IOdirection configured in the second configuration interface should be the same as the arrangement direction IOdirection configured in the first configuration interface.

[0119] Step 230: Determine the signal line direction based on the pin direction of the schematic symbol.

[0120] Specifically, pin orientation indicates the arrangement direction of pins in a schematic symbol. A schematic symbol may have multiple pins, each arranged in a different position on the schematic symbol.

[0121] In one embodiment of this application, the process of determining the signal line direction based on the pin direction of the schematic symbol may include: obtaining the boundary parameters of the schematic symbol and the pin coordinates of each pin in the schematic symbol; determining the pin direction of the pin based on the boundary parameters and the pin coordinates; and determining the signal line direction based on the pin direction.

[0122] Specifically, the boundary parameters of a schematic symbol include the coordinates of the lower left and upper right corners of the schematic symbol, and the pin coordinates refer to the coordinates of the geometric center point of the pin. Figure 7A A schematic diagram of a schematic symbol provided in one embodiment of this application is illustrated. The boundary parameters of the schematic symbol are obtained through a layout tool API, yielding the coordinates of the lower left corner (lx, ly) and the upper right corner (rx, ry), as shown below. Figure 7A As shown, the schematic symbol includes pins 1, 2, 3 and 4 distributed in different positions.

[0123] Figure 7B A pin diagram illustrating one embodiment of this application is shown schematically. Figure 7B As shown, for example, first obtain the coordinates of the lower left corner (Lx0, Ly0) and the upper right corner (Rx0, Ry0) of pin 1, and then call the centerBox API in the layout tool to directly calculate the pin coordinates of pin 1. Similarly, the pin coordinates of pin 2 are calculated.

[0124] In one embodiment of this application, the process of determining the pin direction can also be: comparing the pin coordinates of the pin with the boundary parameters of the schematic symbol, and determining the pin direction based on the magnitude relationship.

[0125] For example, if the X-axis coordinate of a pin is less than the X-axis coordinate of the lower left corner of the schematic symbol boundary parameter, the pin is located on the left side of the schematic symbol; if the X-axis coordinate of a pin is greater than the X-axis coordinate of the upper right corner of the schematic symbol boundary parameter, the pin is located on the right side of the schematic symbol; if the Y-axis coordinate of a pin is greater than the Y-axis coordinate of the upper right corner of the schematic symbol boundary parameter, the pin is located on the top side of the schematic symbol; if the Y-axis coordinate of a pin is less than the Y-axis coordinate of the lower left corner of the schematic symbol boundary parameter, the pin is located on the bottom side of the schematic symbol.

[0126] In another embodiment of this application, the process of determining the pin direction can also be: introducing a preset threshold, first comparing the pin coordinates of the pin with the boundary parameters of the schematic symbol according to the preset threshold, and then determining the pin direction according to the relationship between the two.

[0127] Specifically, the preset threshold can be adjusted according to the schematic symbol size to avoid misjudgment of the final pin direction due to coordinate calculation errors.

[0128] For example, if the X-axis coordinate of a pin is less than or equal to the sum of the X-axis coordinate of the lower left corner of the schematic symbol boundary parameter and a preset threshold, the pin is located on the left side of the schematic symbol; if the X-axis coordinate of a pin is greater than or equal to the difference between the X-axis coordinate of the upper right corner of the schematic symbol boundary parameter and the preset threshold, the pin is located on the right side of the schematic symbol; if the Y-axis coordinate of a pin is greater than or equal to the difference between the Y-axis coordinate of the upper right corner of the schematic symbol boundary parameter and the preset threshold, the pin is located on the upper side of the schematic symbol; if the Y-axis coordinate of a pin is less than or equal to the sum of the Y-axis coordinate of the lower left corner of the schematic symbol boundary parameter and the preset threshold, the pin is located on the lower side of the schematic symbol.

[0129] Specifically, in this process, the schematic symbol and a preset threshold are compared as a whole with the pin coordinates. That is, by constructing a "determination interval" outside or inside the boundary of the schematic symbol, the coordinate range for determining which side the pin belongs to is indirectly expanded or narrowed. In this way, it can accommodate practical scenarios such as coordinate calculation errors and pin size offsets, avoiding misjudgments due to minor deviations.

[0130] The pin direction is consistent with the signal line direction. That is, if the pin direction is to the left, the generated signal line will be to the left; if the pin direction is to the right, the generated signal line will also be to the right; if the pin direction is to the top, the generated signal line will be upward; if the pin direction is to the bottom, the generated signal line will be downward.

[0131] In another embodiment of this application, it is assumed that the schematic symbol boundary parameters include Lx=10, Rx=50, Ly=5, Ry=35, the preset threshold is set to 3, the coordinates of pin 1 are (12, 20), the coordinates of pin 2 are (30, 33), the coordinates of pin 3 are (48, 20), and the coordinates of pin 4 are (48, 20). Therefore, the pin direction of pin 1 should be to the left [X-axis coordinate value of pin 1 ≤ sum of schematic symbol X-axis coordinate value and preset threshold (10+3=13)], that is, a signal line of a specified length can be created from the geometric center point of pin 1 to the left; the pin direction of pin 2 should be to the top [Y-axis coordinate value of pin 2 ≥ difference between schematic symbol Y-axis coordinate value and preset threshold (35-3=32)], that is, a signal line of a specified length can be created from the geometric center point of pin 2 upwards; the pin direction of pin 3 should be to the right [X-axis coordinate value of pin 3 ≥ difference between schematic symbol X-axis coordinate value and preset threshold (50-3=47)], that is, a signal line of a specified length can be created from the geometric center point of pin 3 to the right; the pin direction of pin 4 should be to the bottom [Y-axis coordinate value of pin 4 ≤ sum of schematic symbol X-axis coordinate value and preset threshold (5+3=8)], that is, a signal line of a specified length can be created from the geometric center point of pin 4 downwards.

[0132] Step 240: Connect schematic symbols according to signal line direction and signal line type to generate the schematic corresponding to the DDRPHY layout.

[0133] Specifically, signal line connection rules include the connection method between signal lines and schematic symbols, and different signal line types correspond to different signal line connection rules.

[0134] In one embodiment of this application, the process of generating a schematic diagram may be as follows: first, classify the signal lines according to the parameters configured in the second parameter configuration interface for determining the signal line type to obtain the corresponding signal line type; then, obtain the corresponding signal line connection rules according to the signal line type; finally, connect the schematic diagram symbols according to the signal line direction and the signal line connection rules to generate the schematic diagram corresponding to the DDRPHY layout.

[0135] Specifically, the parameters used to determine the signal line type include a list of signal line names and a list of power and ground line names. Signal line types include power signal lines, ground signal lines, pad signal lines, common signal lines, and bus signal lines. The signal line connection rules can include: all power signal lines with the same name must be connected as a continuous conductor to form a unified power network; all ground signal lines with the same name must be connected as a continuous conductor to form a unified ground network; each pad signal line is independently connected to its corresponding schematic symbol pin, generating a unique external interface; common signal lines are single, independent lines that can transmit signals with a single function (such as reset or enable signals), enabling signal sharing among multiple modules; bus signal lines are parallel sets of multiple lines of the same type, capable of efficiently transmitting large amounts of data or multiple sets of related signals, connected according to the rule of "continuous or segmented".

[0136] In the technical solution provided in this application embodiment, firstly, multiple modules are sorted according to the arrangement direction and coordinates of the modules in the DDRPHY layout to obtain a module order list; then, corresponding schematic symbols are set according to the module type and arrangement direction in the module order list; next, the signal line direction is determined according to the pin direction of the schematic symbols; wherein, the signal line includes wires connecting each schematic symbol; finally, the schematic symbols are connected according to the signal line direction and signal line type to generate the schematic corresponding to the DDRPHY layout; wherein, different signal line types correspond to different schematic symbol connection methods. Thus, the module order list can be obtained according to the arrangement direction and coordinates of the modules in the DDRPHY layout, realizing the automatic reverse generation of the schematic corresponding to the layout, eliminating the need for manual verification and connection of schematic symbols, thereby avoiding problems such as misalignment, missing connections, and layout errors that are prone to occur during manual operation, ensuring that the generated schematic and layout are highly consistent in module order, signal connection, and layout logic, significantly improving the consistency between the layout and the schematic. Figure 1 The accuracy and pass rate of consistency verification.

[0137] In one embodiment of this application, the method of generating a schematic diagram may further include: dividing the signal lines into a first signal line and a second signal line according to the signal line name; generating corresponding labels for the first signal line and the second signal line respectively; and connecting schematic diagram symbols according to the connection rules corresponding to the labels to generate a schematic diagram corresponding to the DDRPHY layout.

[0138] Specifically, the signal line name of the first signal line contains a specific character, while the signal line name of the second signal line does not contain this specific character. Labels are used to indicate the signal line type, and setting labels allows designers to intuitively distinguish between different signal line types.

[0139] For example, a specific character can be the character "PAD", that is, the first signal line is a PAD signal line and the second signal line is a non-PAD signal line. The second signal line can include a power signal line, a ground signal line, a common signal line, etc.

[0140] Figure 8A and Figure 8B A flowchart illustrating the generation of a schematic diagram according to an embodiment of this application is shown schematically. Figure 8A and Figure 8B As shown, if the module arrangement direction is EW direction, the process of generating the schematic diagram includes:

[0141] Step 801: Initialize variables a, padInt, and netInt. Variable a is the parameter for the first preset coordinate (a, 0) and the second preset coordinate (a, -15) when setting the schematic symbol, with an initial value of 0. Variable padInt is used for naming and managing PAD signal lines, with an initial value of 1. When processing a PAD signal, the characters "PAD_" are combined with padInt to generate the PAD signal name (e.g., if padInt is currently 1, the generated PAD signal name is PAD_1). Subsequently, after each PAD signal is generated, the value of padInt is incremented by 1 to ensure that each PAD signal line has a unique and continuous identifier, avoiding naming confusion between PAD signal lines. Variable netInt is used for segmented management of common signal lines (Bus lines), with an initial value of 1.

[0142] Step 802: Traverse the pairing list namelist. The pairing list namelist includes the first pairing list and the second pairing list.

[0143] Step 803: Obtain the left coordinate lx, right coordinate rx, bottom coordinate ly, and top coordinate ry of the schematic symbol bBox using the skill language API and coordinate operations.

[0144] Step 804: Traverse all pins in the target schematic symbol dbsymbol. If the pin name pinName is in the signal line list PathNet, determine the pin direction (left, right, top, or bottom) of the schematic symbol symbol by using the pin coordinates of the pin boundary parameter pinbBox.

[0145] Step 805: If the pin is to the left of the schematic symbol, use the APIschCreateWire algorithm combined with coordinate calculations to create a wire signal line of a specified length from the geometric center point of the pin to the left; if the pin is to the right of the schematic symbol, use the APIschCreateWire algorithm combined with coordinate calculations to create a wire signal line of a specified length from the geometric center point of the pin to the right; if the pin is above the schematic symbol, use the APIschCreateWire algorithm combined with coordinate calculations to create a wire signal line of a specified length upward from the geometric center point of the pin; if the pin is below the schematic symbol, use the APIschCreateWire algorithm combined with coordinate calculations to create a wire signal line of a specified length downward from the geometric center point of the pin.

[0146] Step 806: Determine the signal line type and handle different cases accordingly. Based on whether the signal name contains the character "PAD", classify the signal lines into first signal lines that include the character "PAD" and second signal lines that do not.

[0147] Step 807: Combine the character “PAD_” with the variable padInt. For example, if the current variable padInt is 1, then the name of the PAD signal is PAD_1. Use the schCreateWireLabel algorithm to generate a label on the wire signal line. Then, use the schCreatePin algorithm to generate the pin of PAD_1 at the end of the wire signal line. After generation, increment the variable padInt by 1. Thus, the name of the next PAD signal is PAD_2.

[0148] Step 808: Divide the second signal line, which does not include the character "PAD", into a power signal line and a common signal line.

[0149] Step 809: Use the schCreateWireLabel algorithm to generate the corresponding label on the power signal line; combine the current value of the variable netInt and the name of the pin to form a new label; at the same time, use the schCreateWireLabel algorithm to generate the corresponding label BusLabel on the common signal line.

[0150] Step 810: If the current signal line has been processed, determine whether the current signal line is one of the bus cut module lists (BusCutCellList). If it is, the current variable netInt is the result of incrementing netInt by 1.

[0151] Step 811: Generate the corresponding pins at the specified locations of all power and ground lines in the power and ground signal list PgNet.

[0152] Step 812: Generate a schematic diagram by connecting the signal lines to the schematic symbols. In the schematic diagram, signal lines with the same name are considered as the same line.

[0153] It should be noted that although the steps of the method in this application are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0154] The following describes an apparatus embodiment of this application, which can be used to execute the method for generating schematic diagrams based on DDRPHY layout in the above embodiments of this application. Figure 9 A schematic block diagram of the control device structure provided in an embodiment of this application is shown. Figure 9 As shown, the control device provided in this application embodiment includes:

[0155] The list generation module 910 is used to sort multiple modules according to the arrangement direction and coordinates of the modules in the DDRPHY layout to obtain a module order list;

[0156] Symbol setting module 920 is used to set corresponding schematic symbols according to the module type and the arrangement direction in the module order list;

[0157] The direction determination module 930 is used to determine the signal line direction based on the pin direction of the schematic symbols; wherein, the signal line includes wires connecting each schematic symbol;

[0158] The schematic generation module 940 is used to connect the schematic symbols according to the signal line direction and signal line type to generate the schematic corresponding to the DDRPHY layout; wherein, different signal line types correspond to different schematic symbol connection methods.

[0159] In one embodiment of this application, the list generation module 910 is specifically used for:

[0160] Obtain the boundary parameters of the module in the DDRPHY layout, the boundary parameters including the coordinates of the lower left corner and the upper right corner of the module;

[0161] Calculate the coordinates of the center point of the module based on the boundary parameters of the module;

[0162] The coordinates of the center points of the multiple modules are sorted according to the arrangement direction to obtain a coordinate order list;

[0163] The module order list is generated based on the coordinate order list.

[0164] In one embodiment of this application, the list generation module 910 is specifically used for:

[0165] If the arrangement direction is the first direction, then the first preset coordinate values ​​of the center point coordinates of the multiple modules are sorted according to preset rules to obtain the coordinate order list; the coordinate axis direction corresponding to the first preset coordinate value is perpendicular to the first direction;

[0166] If the arrangement direction is the second direction, then the second preset coordinate values ​​of the center point coordinates of the multiple modules are sorted according to preset rules to obtain the coordinate order list; the coordinate axis direction corresponding to the second preset coordinate value is perpendicular to the second direction;

[0167] If the arrangement direction includes a first direction and a second direction, then the first preset coordinate values ​​among the coordinates of the center points of multiple modules arranged in the first direction are sorted according to preset rules to obtain a coordinate order list for the first direction; and the second preset coordinate values ​​among the coordinates of the center points of multiple modules arranged in the second direction are sorted according to preset rules to obtain a coordinate order list for the second direction; the coordinate order list for the first direction and the coordinate order list for the second direction are concatenated according to a preset format to obtain the coordinate order list; wherein, the first direction is perpendicular to the second direction, the first direction is perpendicular to the first preset coordinate axis direction, and the second direction is perpendicular to the second preset coordinate axis direction.

[0168] In one embodiment of this application, the list generation module 910 is specifically used for:

[0169] Traverse the coordinate order list to obtain the current center point coordinates from the coordinate order list;

[0170] For the current center point coordinates, iterate through the center point coordinates of each module in the DDRPHY layout. If the center point coordinates of a module match the current center point coordinates, add the name of that module to the module order list.

[0171] In one embodiment of this application, the symbol setting module 920 is specifically used for:

[0172] Traverse the module names in the ordered list and divide the modules into a first module and a second module according to the module names; wherein the module name of the first module does not include the specified string, and the module name of the second module includes the specified string;

[0173] Pair the module name of the first module with the name of the first schematic symbol library to generate a first pairing list; pair the module name of the second module with the name of the second schematic symbol library to generate a second pairing list;

[0174] According to the first pairing list, the schematic symbol corresponding to the first module is obtained from the first schematic symbol library corresponding to the first schematic symbol library name; and according to the second pairing list, the schematic symbol corresponding to the second module is obtained from the second schematic symbol library corresponding to the second schematic symbol library name.

[0175] The schematic symbols corresponding to the first module and the second module are set according to the arrangement direction.

[0176] In one embodiment of this application, the symbol setting module 920 is specifically used for:

[0177] If the arrangement direction is the first direction, then starting from the first preset coordinate, multiple schematic symbols corresponding to the modules are set sequentially according to the preset interval value.

[0178] If the arrangement direction is the second direction, then starting from the second preset coordinates, multiple schematic symbols corresponding to the modules are sequentially set according to preset interval values.

[0179] If the arrangement direction includes a first direction and a second direction, then starting from the first preset coordinate, the schematic symbols corresponding to the multiple modules with the first direction are set sequentially according to a preset interval value; and starting from the second preset coordinate, the schematic symbols corresponding to the multiple modules with the second direction are set sequentially according to a preset interval value.

[0180] In one embodiment of this application, the direction determination module 930 is specifically used for:

[0181] Obtain the boundary parameters of the schematic symbol and the pin coordinates of each pin in the schematic symbol; the boundary parameters of the schematic symbol include the coordinates of the lower left corner and the upper right corner of the schematic symbol;

[0182] The pin orientation is determined based on the boundary parameters and the pin coordinates; wherein the pin orientation represents the arrangement direction of the pins in the schematic symbol.

[0183] The direction of the signal line is determined based on the direction of the pin.

[0184] In one embodiment of this application, the schematic generation module 940 is specifically used for:

[0185] The signal lines are classified according to the parameters configured in the second parameter configuration interface to determine the signal line type, and the corresponding signal line types are obtained.

[0186] Obtain the corresponding signal line connection rules according to the signal line type; the signal line connection rules include the connection method between the signal line and the schematic symbol, and different signal line types correspond to different signal line connection rules;

[0187] The schematic symbols are connected according to the signal line direction and the signal line connection rules to generate the schematic corresponding to the DDRPHY layout.

[0188] In one embodiment of this application, the control device provided in this application further includes an interface generation module, which is specifically used for:

[0189] In response to a trigger operation that enters the first parameter configuration interface, the configuration options for the first parameter are displayed in the first parameter configuration interface; the first parameter includes at least the arrangement direction of the modules.

[0190] In one embodiment of this application, the interface generation module is further configured to:

[0191] In response to a trigger operation that enters the second parameter configuration interface, the configuration options for the second parameter are displayed in the second parameter configuration interface; the second parameter includes at least a parameter for determining the signal line type.

[0192] The specific details of the control device provided in the various embodiments of this application have been described in detail in the corresponding method embodiments, and will not be repeated here.

[0193] Figure 10 A schematic diagram of the computer system architecture used to implement the technical solution of this application is shown.

[0194] It should be noted that, Figure 10 The computer system 1000 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0195] like Figure 10As shown, the computer system 1000 includes a central processing unit (CPU) 1001, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 1002 or programs loaded from storage section 1007 into random access memory (RAM). The RAM 1003 also stores various programs and data required for system operation. The CPU 1001, ROM 1002, and RAM 1003 are interconnected via a bus 1004. An input / output interface 1005 (I / O interface) is also connected to the bus 1004.

[0196] The following components are connected to the input / output interface 1005: an input section 1006 including a keyboard, mouse, etc.; an output section 1007 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a local area network card, modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the input / output interface 1005 as needed. A removable medium 1011, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 1010 as needed so that computer programs read from it can be installed into the storage section 1008 as needed.

[0197] It should be noted that the computer-readable medium shown in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such transmitted data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0198] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0199] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of this application, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0200] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the method according to the embodiments of this application.

[0201] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0202] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for generating schematic diagrams based on DDRPHY layout, characterized in that, include: Based on the arrangement direction and coordinates of the modules in the DDRPHY layout, a module order list is obtained. The process of obtaining the module order list includes: if the arrangement direction is a first direction, sorting the center point coordinates of the multiple modules according to a preset rule to obtain a coordinate order list; the coordinate axis corresponding to the first preset coordinate value is perpendicular to the first direction; if the arrangement direction is a second direction, sorting the center point coordinates of the multiple modules according to a preset rule to obtain the coordinate order list; the coordinate axis corresponding to the second preset coordinate value is perpendicular to the second direction; if the arrangement direction includes both a first direction and a second direction... Then, according to preset rules, the first preset coordinate values ​​of the center point coordinates of multiple modules arranged in the first direction are sorted to obtain a coordinate order list in the first direction; and according to preset rules, the second preset coordinate values ​​of the center point coordinates of multiple modules arranged in the second direction are sorted to obtain a coordinate order list in the second direction; the coordinate order list in the first direction and the coordinate order list in the second direction are concatenated according to a preset format to obtain the coordinate order list; the module order list is generated based on the coordinate order list; the first direction is perpendicular to the second direction, the first direction is perpendicular to the coordinate axis direction corresponding to the first preset coordinate value, and the second direction is perpendicular to the coordinate axis direction corresponding to the second preset coordinate value; Set the schematic symbol corresponding to the module according to the module type in the module sequence list and the arrangement direction; The signal line direction is determined according to the pin direction of the schematic symbols; wherein, the signal line includes wires connecting the various schematic symbols; The schematic symbols are connected according to the signal line direction and signal line type to generate the schematic corresponding to the DDRPHY layout; wherein, different signal line types correspond to different schematic symbol connection methods.

2. The method for generating schematic diagrams based on DDRPHY layout according to claim 1, characterized in that, Before sorting the multiple modules according to the arrangement direction and coordinates of the modules in the DDRPHY layout, the method further includes: In response to a trigger operation that enters the first parameter configuration interface, the configuration options for the first parameter are displayed in the first parameter configuration interface; the first parameter includes at least the arrangement direction of the modules.

3. The method for generating schematic diagrams based on DDRPHY layout according to claim 1, characterized in that, The step of sorting multiple modules according to the arrangement direction and coordinates of the modules in the DDRPHY layout to obtain a module order list includes: Obtain the boundary parameters of the module in the DDRPHY layout, the boundary parameters including the coordinates of the lower left corner and the upper right corner of the module; Calculate the coordinates of the center point of the module based on the boundary parameters of the module; The coordinates of the center points of the multiple modules are sorted according to the arrangement direction to obtain a coordinate order list; The module order list is generated based on the coordinate order list.

4. The method for generating schematic diagrams based on DDRPHY layout according to claim 3, characterized in that, The step of generating the module order list based on the coordinate order list includes: Traverse the coordinate order list to obtain the current center point coordinates from the coordinate order list; For the current center point coordinates, iterate through the center point coordinates of each module in the DDRPHY layout. If the center point coordinates of a module match the current center point coordinates, add the name of that module to the module order list.

5. The method for generating schematic diagrams based on DDRPHY layout according to claim 1, characterized in that, Before connecting the schematic symbol according to the signal line direction and signal line type, the method further includes: In response to a trigger operation that enters the second parameter configuration interface, the configuration options for the second parameter are displayed in the second parameter configuration interface; the second parameter includes at least a parameter for determining the signal line type.

6. The method for generating schematic diagrams based on DDRPHY layout according to claim 1, characterized in that, The step of setting the schematic symbol corresponding to the module according to the module type in the module order list and the arrangement direction includes: Traverse the module names in the ordered list and divide the modules into a first module and a second module according to the module names; wherein the module name of the first module does not include the specified string, and the module name of the second module includes the specified string; Pair the module name of the first module with the name of the first schematic symbol library to generate a first pairing list; pair the module name of the second module with the name of the second schematic symbol library to generate a second pairing list; According to the first pairing list, the schematic symbol corresponding to the first module is obtained from the first schematic symbol library corresponding to the first schematic symbol library name; and according to the second pairing list, the schematic symbol corresponding to the second module is obtained from the second schematic symbol library corresponding to the second schematic symbol library name. The schematic symbols corresponding to the first module and the second module are set according to the arrangement direction.

7. The method for generating schematic diagrams based on DDRPHY layout according to claim 6, characterized in that, The step of setting the schematic symbols corresponding to the first module and the second module according to the arrangement direction includes: If the arrangement direction is the first direction, then starting from the first preset coordinate, multiple schematic symbols corresponding to the modules are set sequentially according to the preset interval value. If the arrangement direction is the second direction, then starting from the second preset coordinates, multiple schematic symbols corresponding to the modules are sequentially set according to preset interval values. If the arrangement direction includes a first direction and a second direction, then starting from the first preset coordinate, the schematic symbols corresponding to the multiple modules with the first direction are set sequentially according to a preset interval value; and starting from the second preset coordinate, the schematic symbols corresponding to the multiple modules with the second direction are set sequentially according to a preset interval value.

8. The method for generating schematic diagrams based on DDRPHY layout according to claim 1, characterized in that, Determining the signal line direction based on the pin direction of the schematic symbol includes: Obtain the boundary parameters of the schematic symbol and the pin coordinates of each pin in the schematic symbol; the boundary parameters of the schematic symbol include the coordinates of the lower left corner and the upper right corner of the schematic symbol; The pin orientation is determined based on the boundary parameters and the pin coordinates; wherein the pin orientation represents the arrangement direction of the pins in the schematic symbol. The direction of the signal line is determined based on the direction of the pin.

9. The method for generating schematic diagrams based on DDRPHY layout according to claim 1, characterized in that, The step of connecting the schematic symbols according to the signal line direction and signal line type to generate the schematic corresponding to the DDRPHY layout includes: The signal lines are classified according to the parameters configured in the second parameter configuration interface to determine the signal line type, and the corresponding signal line types are obtained. Obtain the corresponding signal line connection rules according to the signal line type; the signal line connection rules include the connection method between the signal line and the schematic symbol, and different signal line types correspond to different signal line connection rules; The schematic symbols are connected according to the signal line direction and the signal line connection rules to generate the schematic corresponding to the DDRPHY layout.

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