Chip serial number identification method for Bar wafers

Abstract

The invention discloses a chip serial number identification method for a Bar wafer, and relates to the technical field of chips, the method builds and trains a serial number identification model based on the idea of a neural network, and aims at the characteristics that the serial numbers of different chips on the Bar wafer conform to a predetermined format rule and are related to the coordinate information of the chips. Meanwhile, a surface image carrying serial number information and coordinate information of the chip are collected and input into a serial number recognition model, the serial number recognition model fuses image features of the surface image of the area where the serial number is located and position features of the coordinate information of the chip, and feature mapping and decoding are carried out to obtain a serial number recognition result; according to the method, the serial number identification accuracy and robustness are higher.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method for identifying chip serial numbers on bar-shaped wafers. Background Technology

[0002] Optical chips are a crucial type of chip in 5G fiber optic communication. In the manufacturing process of optical chips, especially light-emitting chips such as laser diodes and LEDs, the wafer is first diced into multiple long strips (Bars) for easier processing. Each Bar contains multiple chips arranged sequentially, and at this stage, the chips are not yet completely separated. The Bars are then attached to a blue film to form a Bar wafer. After Bar-level testing, the optical port faces of each Bar are coated. A typical approach is to have multiple chips arranged horizontally within each Bar, facilitating coating on the vertical optical port faces and allowing unobstructed light observation in the vertical direction. Similarly, another typical approach is to have multiple chips arranged vertically within each Bar, facilitating coating on the horizontal optical port faces and allowing unobstructed light observation in the horizontal direction. After completing the coating operation on the optical port end face of the Bar bar, each Bar bar is chip-level cut to further cut the multiple chips in each Bar bar, then chip-level testing is completed, and sorting and picking operations are performed.

[0003] To differentiate chips, each chip on the bar wafer is etched with a unique serial number (SN). To ensure accurate chip sorting and pickup, the bar wafer needs to be pre-scanned before sorting to determine the pre-scan information of each chip within each bar and associate it with the chip's serial number. Currently, the industry standard method is to use a moving camera to scan and acquire surface images of each chip and identify its serial number. However, due to the small size of the chips and the even smaller size of the etched serial numbers, coupled with the influence of image acquisition quality, identification errors are prone to occur, especially with easily confused characters like "B" and "8," leading to low accuracy in chip serial number identification and directly impacting the accuracy of subsequent chip sorting. Summary of the Invention

[0004] This application addresses the aforementioned problems and technical requirements by proposing a chip serial number identification method for Bar stripe wafers. The technical solution of this application is as follows:

[0005] A method for identifying chip serial numbers on bar-shaped wafers, the method comprising:

[0006] The process involves acquiring surface images of the regions where serial numbers are etched on the chip surfaces of each bar strip on a bar strip wafer, as well as the chip's coordinate information (x, y). The bar strip wafer contains multiple bar strips, and each bar strip contains multiple chips arranged sequentially. The x-coordinate of each chip indicates the bar strip to which it belongs, and the y-coordinate indicates the chip's arrangement order within its respective bar strip. The serial numbers of different chips on the bar strip wafer conform to a predetermined format and are related to the chip's coordinate information (x, y).

[0007] The surface image and coordinate information (x,y) of the chip are input into a pre-trained serial number recognition model. The serial number recognition model includes a feature extraction layer, a sequence modeling layer and a prediction layer. The feature extraction layer is used to extract the image features of the surface image and the position features of the coordinate information and then fuse them to obtain the chip fusion features. The sequence modeling layer maps the chip fusion features into a probability distribution sequence and then decodes and outputs the chip serial number recognition result through the prediction layer.

[0008] A further technical solution is that the chip serial number identification method also includes:

[0009] Select at least three chips in the Bar as index chips, and use the serial number recognition model to determine the serial number recognition result of the index chip based on the surface image and coordinate information of each index chip;

[0010] Based on the serial number recognition results of each index chip, a predetermined format rule is determined, and the serial number recognition results of other chips in the Bar are deduced according to the predetermined format rule.

[0011] The further technical solution is that the predetermined format rules that the serial numbers of different chips on the Bar strip wafer conform to include: the serial numbers of all chips in the same Bar strip are of the same length, the serial number of each chip includes a prefix string and a suffix string concatenated in sequence, the prefix strings of all chips in the same Bar strip are the same, and the suffix strings of each chip in the same Bar strip are different and related to the y coordinate of the chip.

[0012] The deduction yielded the following serial number identification results for the other chips in the Bar:

[0013] Based on the serial number identification results of each index chip, determine the prefix string of the chip in the corresponding Bar bar, and the relationship between the suffix string of the chip in the Bar bar and the chip's y-coordinate;

[0014] Based on the relationship between the suffix string of the chip in the Bar bar and the chip's y-coordinate, and combined with the y-coordinates of the other chips in the Bar bar, determine the suffix strings of the other chips;

[0015] By concatenating the prefix string of the chip in the Bar with the suffix string corresponding to each chip, the serial number identification result of the other chips in the Bar is obtained.

[0016] A further technical solution involves determining the suffix string of each chip within the same bar as a numeric string that monotonically changes with the chip's y-coordinate; and determining the prefix string of the chip within its bar based on the serial number identification result of each index chip, as well as the relationship between the suffix string of the chip within the bar and the chip's y-coordinate, including:

[0017] Extract the strings with the same high-order part from the serial number recognition results of each index chip in the Bar bar as candidate prefixes, and extract the strings other than the candidate prefixes from the serial number recognition results of each index chip as candidate suffixes;

[0018] Based on the candidate suffixes of each index chip and the y-coordinate of each index chip, determine the relationship between the suffix string of the chip in the Bar bar and the chip y-coordinate;

[0019] Based on the relationship between the suffix string of the chip in the Bar and the chip's y-coordinate, and combined with the total number of chips contained in the Bar, the prefix string of the chip in the corresponding Bar is determined.

[0020] The further technical solution involves determining the prefix string of the chip within the corresponding Bar bar, including:

[0021] Based on the relationship between the suffix string of the chip in the Bar and the chip's y-coordinate, and the total number of chips contained in the current Bar, determine the number of digits k1 occupied by the suffix string, and correspondingly determine the number of digits k2 occupied by the prefix string; where T is the number of characters contained in the serial number recognition result of a single index chip, k1, k2 and T are all integer parameters, and T≥3;

[0022] Extract the highest k2-bit string from the candidate prefixes to obtain the prefix string of the chip in the corresponding Bar.

[0023] A further technical solution involves selecting at least three chips as index chips within the bar, including:

[0024] At least three chips are randomly selected within the bar as index chips. These three index chips are arranged consecutively or alternately with other chips within the same bar.

[0025] A further technical solution is that the feature extraction layer in the serial number recognition model includes an image feature extractor and two location embedding layers. The chip fusion features output by the feature extraction layer include:

[0026] The surface image of the chip is extracted by multi-layer convolution and pooling using an image feature extractor. The feature map is compressed to 1 in the height direction by adaptive pooling and then divided into N time steps in the width direction. The P-dimensional image features of each time step in the channel dimension are output.

[0027] Two position embedding layers are used to convert the x and y coordinates in the chip's coordinate information into dense vectors. The two dense vectors are concatenated to obtain the Q-dimensional position feature. The Q-dimensional position feature is then copied and expanded in the time step dimension to output the Q-dimensional position feature for N time steps.

[0028] The P-dimensional image features and Q-dimensional position features of N time steps are concatenated along the feature dimension to output the (P+Q)-dimensional chip fusion features of N time steps.

[0029] Its further technical solution is that the sequence modeling layer in the sequence number recognition model includes a bidirectional LSTM, a sequence position attention mechanism, and a fully connected layer connected in sequence.

[0030] Bidirectional LSTM is used to perform sequence modeling of (P+Q) dimensional chip fusion features at N time steps and output the hidden features at N time steps;

[0031] The sequence position attention mechanism aggregates the hidden features of N time steps in the time step dimension to obtain the feature vector of N time steps;

[0032] The fully connected layer is used to map the feature vectors of N time steps into a probability distribution sequence. The probability distribution sequence includes the probability distribution result obtained by mapping the feature vectors at each time step. The probability distribution result at each time step includes the probability distribution of all R categories. The number of categories R is the total number of characters in the character set plus the number of whitespace characters.

[0033] A further technical solution is that the prediction layer performs CTC decoding on the probability distribution sequence output by the sequence modeling layer using greedy decoding or beam search methods to obtain the sequence number recognition result.

[0034] A further technical solution is that the chip serial number identification method also includes:

[0035] Obtain the surface image, coordinate information, and serial number label of the sample chip;

[0036] The surface image and coordinate information of the sample chip are input into the serial number recognition model to obtain the serial number prediction result of the sample chip;

[0037] The CTC loss is calculated based on the serial number label and serial number prediction results of the sample chip, and the model parameters of the serial number recognition model are adjusted according to the CTC loss until the serial number recognition model is trained.

[0038] The beneficial technical effects of this application are:

[0039] This application discloses a chip serial number recognition method for bar wafers. This method is based on the idea of ​​neural networks to realize serial number recognition. Taking advantage of the fact that the serial numbers of different chips on the bar wafer conform to a predetermined format and are related to the coordinate information of the chip, the method integrates the image features of the surface image of the area where the serial number is located and the position features of the chip's coordinate information, and performs feature mapping and decoding to obtain the serial number recognition result. This method has higher accuracy and robustness in serial number recognition.

[0040] Based on the format characteristics of the serial numbers of different chips on the Bar strip wafer, this method also proposes a serial number deduction method. Through the deduction mechanism, only a limited number of index chips need to be selected within the Bar strip to obtain surface images and use a serial number recognition model to identify the serial numbers. Then, based on the serial number recognition results of the highly accurate index chips, the serial number recognition results of other chips can be directly deduced. Compared with the method of sequentially taking surface images of each chip and inputting them into the serial number recognition model for recognition, this method further improves the recognition speed and efficiency and has good prospects for industrial application. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the structure of a Bar strip wafer.

[0042] Figure 2 This is a network structure diagram of a serial number recognition model in one embodiment of this application.

[0043] Figure 3 This is a flowchart illustrating the process of determining the serial number identification result of the chip within the Bar in one embodiment of this application. Detailed Implementation

[0044] The specific embodiments of this application will be further described below with reference to the accompanying drawings.

[0045] This application discloses a chip serial number identification method for Bar strip wafers. The structure of the Bar strip wafer is first described below; please refer to [link / reference]. Figure 1A bar wafer has multiple bar strips 10 arranged in an array and attached to a blue film 20 to form a bar wafer. That is, multiple bar strip groups are arranged at intervals along a first direction on the bar wafer. Each bar strip group includes multiple bar strips 10 arranged at intervals along a second direction. Each bar strip 10 includes multiple chips 11 arranged sequentially along the first direction. The number of chips 11 contained in a single bar strip is commonly 36, 46, 57, etc. Here, the first and second directions are perpendicular to each other and are two perpendicular directions of the plane on which the bar wafer is located. Figure 1 Taking the first direction as horizontal and the second direction as vertical as an example.

[0046] The lengths of the bars on the bar wafer are not exactly the same, but they are basically consistent within the tolerance range. Therefore, the typical length L of the bar along the first direction on the bar wafer can be predetermined. For ease of subsequent operations, multiple bar bars 10 arranged along the second direction in the same bar bar group are aligned, and multiple bar bars 10 arranged along the first direction in different bar bar groups are aligned to form an array. Similarly, due to the arrangement deviation when arranging the bar bars on the blue film, the orientation of the bar bars themselves may be deviated. In addition, due to the specification deviation between the bar bars, this alignment is not perfect, but it can be considered aligned within the tolerance range.

[0047] There is a gap between two bars spaced along the first direction. The gap between different bars may vary slightly, but it remains generally consistent within the error range. Therefore, the typical gap length d between bars along the first direction on a bar wafer can be predetermined. Similarly, there is a gap between two bars spaced along the second direction. The gap between different bars may vary slightly, but it remains generally consistent within the error range. Therefore, the typical gap length t between bars along the second direction on a bar wafer can also be predetermined. The bars on the bar wafer can be arranged in a rectangular array or a circular array, meaning that different bar groups may contain the same or different numbers of bars. Figure 1 The diagram shows a circular array arrangement, which makes full use of the space on the bar wafer to arrange more bars, thus improving chip manufacturing efficiency.

[0048] Each chip 11 has its serial number (SN) etched on its surface. This serial number is a string containing multiple characters, uniquely identifying each chip and facilitating chip tracking. To simplify design and avoid serial number duplication, the serial numbers are not randomly encoded. The industry standard practice is to assign serial numbers to each chip according to a predetermined format, and each chip's serial number is associated with its coordinate information (x, y). The coordinate information (x, y) indicates the chip's position within the bar wafer. The x-coordinate indicates the bar to which the chip belongs, while the y-coordinate indicates the chip's order within that bar. The x-coordinate of each bar is predetermined. For example, the coordinates of the chips arranged sequentially in one bar of a wafer are (0,0), (0,1), (0,2), (0,3)... while the coordinates of the chips arranged sequentially in another bar are (5,0), (5,1), (5,2), (5,3)...

[0049] Against this backdrop, the chip serial number identification method includes the following steps:

[0050] The process involves acquiring surface images of the chips within each bar on the bar-strip wafer, along with the chip's coordinate information (x, y). The chip surface image is the image of the area where the serial number is etched on the chip surface. The method for acquiring the chip surface image is similar to existing serial number recognition methods, using a camera to scan the chip. The chip's coordinate information (x, y) can already be determined during the preceding bar-strip wafer pre-scanning stage.

[0051] Then, the chip's surface image and coordinate information (x, y) are input into the pre-trained serial number recognition model. Please refer to [reference needed]. Figure 2 The serial number recognition model includes a feature extraction layer, a sequence modeling layer, and a prediction layer. The feature extraction layer extracts image features from the surface image and positional features of coordinate information (x, y) and then fuses them to obtain chip fusion features. The sequence modeling layer maps the chip fusion features into a probability distribution sequence and decodes and outputs the chip serial number recognition result through the prediction layer.

[0052] Since the serial number of each chip on the Bar wafer is related to the chip's coordinate information (x,y) and conforms to a predetermined format, the chip's coordinate information (x,y) also carries the relevant features of the chip's serial number. Based on this, this application fuses image features and position features, and performs mapping recognition based on the chip's fused features. Compared with the approach of using only image features, it can obtain more accurate serial number recognition results.

[0053] In one embodiment, please refer to Figure 2The feature extraction layer in the serial number recognition model includes an image feature extractor and two location embedding layers. The feature extraction layer extracts features from the chip's surface image and coordinate information and outputs the chip's fused features, including:

[0054] (1) The surface image of the chip is extracted using a multi-layer convolution and pooling method by an image feature extractor to obtain a feature map. The input surface image is an RGB image, which includes data in the channel, height, and width directions. Therefore, the extracted feature map includes features in the channel, height, and width directions. Then, the feature map is compressed to 1 in the height direction by adaptive pooling, and divided into N time steps in the width direction. The P-dimensional image features in the channel dimension of each time step are output. Here, N and P are both integer parameters.

[0055] (2) The x and y coordinates in the chip's coordinate information are converted into dense vectors using two position embedding layers respectively. Then, the two dense vectors are concatenated to obtain the Q-dimensional position feature, where Q is an integer parameter. The Q-dimensional position feature is copied and extended along the time step dimension to output the Q-dimensional position feature for N time steps.

[0056] Finally, the P-dimensional image features and Q-dimensional position features from N time steps are concatenated along the feature dimension to output the (P+Q)-dimensional chip fusion features from N time steps.

[0057] In one embodiment, the sequence modeling layer includes a bidirectional LSTM, a sequence position attention mechanism, and a fully connected layer, which are sequentially connected in series:

[0058] A bidirectional LSTM is used to perform sequence modeling on the (P+Q) dimensional chip fusion features across N time steps, and outputs hidden features at N time steps. A sequence position attention mechanism aggregates the hidden features at the N time steps, resulting in feature vectors at N time steps. The bidirectional LSTM captures the dependencies between preceding and following characters, and then the sequence position attention mechanism further focuses on key features, thereby outputting a sequence representation of context-aware feature vectors.

[0059] Finally, the fully connected layer maps the feature vectors of N time steps to a probability distribution sequence. The output probability distribution sequence includes the probability distribution results of N time steps. The probability distribution result of each time step is obtained by mapping the feature vector of the corresponding time step, and the probability distribution result of each time step includes the probability distribution of all R categories. The number of categories R is the total number of characters in the character set plus the number of whitespace characters. The character set is the total number of characters used in the serial number of the chip on the bar wafer. Due to the limited chip surface size, considering the etching difficulty, complex characters are not used in the serial number. The characters used in the character set include numbers and / or English letters. For example, in one instance, when the character set contains all 26 letters and the numbers 0-9, the number of characters in the character set is 36, and with the addition of whitespace characters, the number of categories R = 37. However, in practice, for a bar wafer, the character set used may only contain some letters and numbers. Based on the pre-determined character set, the number of categories can be determined accordingly.

[0060] Finally, the prediction layer uses greedy decoding or beam search to perform CTC decoding on the probability distribution sequence output by the sequence modeling layer to obtain the serial number recognition result. The number of characters in the serial number of the chip on the bar wafer is not equal to the number of time steps N, that is, the length of the probability distribution sequence input to the prediction layer and the length of the output serial number recognition result are inconsistent. CTC decoding can handle this situation well.

[0061] The number of time steps, N, is greater than M*η*δ and is an integer. Here, M is the maximum number of characters in the chip's serial number on the bar wafer; currently, the serial number typically contains 3 to 6 characters, so M = 6. η is the character repetition coefficient; CTC decoding requires 2 to 3 time steps to represent one character, so η is set to 3. δ is the safety margin coefficient, used to consider character spacing and boundary conditions; δ ranges from 1.2 to 1.5, typically taking the middle value of 1.3. Therefore, when M = 5, N > 5 * 3 * 1.3, meaning the minimum value of N is 20. When M = 6, N > 6 * 3 * 1.3, meaning the minimum value of N is 24.

[0062] The value of the time step number N also affects recognition accuracy and efficiency. Assuming the above basic requirements are met, a smaller N value results in relatively lower recognition accuracy, while a larger N value leads to higher accuracy. In one embodiment, when the number of characters in the serial number of the chip on the Bar wafer is 3-6, a time step number of N=37 achieves a better performance balance in terms of both recognition accuracy and efficiency. For comparison, when N=32, the recognition accuracy decreases by 5%-8% compared to N=37, especially when the serial number is longer. When N=40, the computational load increases by 15% compared to N=37, but the improvement in recognition accuracy is less than 1%.

[0063] In one embodiment, the image feature extractor employs a CNN network, progressively extracting image features through multiple convolutional and pooling layers to reduce spatial dimensionality and increase the number of channels in the output feature map. The spatial dimensions (height and width) are compressed, while the number of channels increases. In one embodiment, the input surface image has dimensions (3, 100, 300) in the channel, height, and width directions. The image feature extractor sequentially includes seven convolutional modules, which are described below:

[0064] The first convolutional module consists of a first convolutional layer, a ReLU activation function, and a max-pooling layer connected in sequence. The first convolutional layer uses 64 3x3 convolutional kernels with a stride of 1 and padding of 1. The max-pooling layer is 2x2 with a stride of 2. The first convolutional module outputs a feature map of (64, 50, 150).

[0065] The second convolutional module consists of a second convolutional layer, a ReLU activation function, and a max-pooling layer connected in sequence. The second convolutional layer uses 128 3x3 convolutional kernels with a stride of 1 and padding of 1. The max-pooling layer is 2x2 with a stride of 2. The first convolutional module outputs a feature map of (128, 25, 75).

[0066] The third convolutional module consists of a third convolutional layer and a ReLU activation function connected in sequence. The third convolutional layer uses 256 3*3 convolutional kernels with a stride of 1 and padding of 1. The third convolutional module outputs a feature map of (256, 25, 75).

[0067] The fourth convolutional module consists of a fourth convolutional layer and a ReLU activation function connected in sequence. The fourth convolutional layer uses 256 3*3 convolutional kernels with a stride of 1 and padding of 1. The fourth convolutional module outputs a feature map of (256, 25, 75).

[0068] The fifth convolutional module consists of a fifth convolutional layer and a ReLU activation function connected sequentially. The fifth convolutional layer uses 512 3x3 convolutional kernels with a stride of 1 and padding of 1. The fifth convolutional module outputs a feature map of (512, 25, 75).

[0069] The sixth convolutional module consists of a sixth convolutional layer and a ReLU activation function connected sequentially. The sixth convolutional layer uses 512 3x3 convolutional kernels with a stride of 1 and padding of 1. The sixth convolutional module outputs a feature map of (512, 25, 75).

[0070] The seventh convolutional module consists of a seventh convolutional layer and a ReLU activation function connected sequentially. The seventh convolutional layer uses 512 2x2 convolutional kernels with a stride of 2 and padding of 2, equivalent to pooling. The seventh convolutional module outputs a feature map of (512, 12, 37).

[0071] The image feature extractor uses a small 3x3 convolutional kernel to preserve detailed features and adapts to different scales through spatial pyramid pooling. Then, the (512, 12, 37) feature map is compressed to 1 in the height direction through adaptive pooling to obtain a (512, 1, 37) feature map. Further, the width direction is divided into 37 time steps, and the image features at each time step are output as 512-dimensional features in the channel dimension, resulting in a 37*512 image feature output.

[0072] Two location embedding layers convert the x and y coordinates into 32-dimensional dense vectors, respectively, which are then concatenated to obtain 64-dimensional location features. This is replicated and expanded to output 64-dimensional location features over 37 time steps, resulting in a 37*64 dimension output. Finally, the 37*512 image features are concatenated with the 37*64 location features along the feature dimension to obtain 37*576-dimensional chip fusion features. Then, a bidirectional LSTM with 256 hidden units outputs 512-dimensional hidden features over 37 time steps. A fully connected layer further maps the feature vectors from these 37 time steps to a 37*R probability distribution sequence, which is then decoded by CTC to obtain the sequence number recognition result.

[0073] The aforementioned chip serial number recognition relies on a serial number recognition model. Therefore, before using the model, it needs to be pre-trained. This includes building the network structure of the model according to the above-described structure, acquiring the surface image, coordinate information, and serial number label of the sample chip, and inputting the surface image and coordinate information into the model to obtain the serial number prediction result. Then, the CTC loss is calculated based on the serial number label and prediction result. The CTC loss allows for a variable-length correspondence between the aligned probability distribution sequence (N time steps) and the predicted serial number result (3-6 characters in length), without requiring precise character segmentation. The model parameters are then adjusted according to the CTC loss until the desired serial number recognition model is obtained.

[0074] In one embodiment, the surface image and coordinate information of each chip are acquired sequentially and input into the serial number recognition model to obtain the serial number recognition result of each chip.

[0075] Or in another embodiment, please refer to Figure 3The flowchart shown illustrates a method where at least three chips are selected as index chips within a bar. The surface image and coordinate information of each index chip are acquired and input into a serial number recognition model. The model then uses this information to determine the serial number of each index chip. Subsequently, there is no need to acquire surface images of other chips in the bar. Instead, the predetermined format rule for the serial numbers of different chips on the bar wafer is determined directly based on the serial number recognition results of each index chip. The serial number recognition results of other chips in the bar are then deduced according to this predetermined format rule. This method first uses a serial number recognition model to obtain the serial number recognition results of at least three index chips. Based on these accurate results, the serial number recognition results of other chips are deduced, saving the time spent on surface image acquisition and image processing, and improving the speed and efficiency of chip serial number recognition.

[0076] Typically, the serial numbers of different chips on a bar wafer follow a predetermined format: all chips within the same bar have serial numbers of the same length, and each chip's serial number includes a prefix and a suffix string concatenated sequentially. The prefix string in the chip's serial number identifies the bar to which the chip belongs and the chip's manufacturing process; therefore, the chip's prefix string is related to the chip's manufacturing process and its x-coordinate. Since the bars on the same bar wafer are often cut from the same wafer, the manufacturing processes of the chips on the same bar wafer are usually the same. Notably, chips in different bars may use different manufacturing processes, but regardless, all chips within the same bar use the same manufacturing process. Since all chips within the same bar have the same x-coordinate, the prefix strings of all chips within the same bar are the same, while the prefix strings of chips in different bars are different. The suffix string in the chip's serial number is used to distinguish different chips. Therefore, the suffix strings of each chip in the same bar are different, and the suffix string of the chip is related to the chip's arrangement order in the bar, which is also related to the chip's y-coordinate.

[0077] In the above process, the arrangement of the index chips in the bar is not limited. That is, at least three chips can be randomly selected in the bar as index chips. These at least three index chips are arranged continuously or alternately with other chips in the same bar.

[0078] Although the serial number recognition results obtained by this application using the serial number recognition model have high accuracy, errors are still unavoidable. Therefore, in one embodiment, after obtaining the serial number recognition results of multiple index chips, if it is determined that the number of characters contained in the serial number recognition results of multiple index chips is different, a recognition error is determined. In this case, an index chip is reselected within the Bar bar, and the above process is repeated. When the serial number recognition results of multiple index chips contain the same number of characters and are all T, the following deduction process is performed, including:

[0079] Based on the serial number identification results of each index chip, the prefix string of the chip in its respective Bar bar is determined, as well as the relationship between the suffix string of the chip in the Bar bar and the chip's y-coordinate. Specifically:

[0080] Because the chip's prefix string needs to identify the chip's manufacturing process, it typically contains numbers and English letters. The chip's suffix string, on the other hand, is mainly used to distinguish different chips; therefore, it only uses numbers. For ease of design, the common marking method is that the suffix string of each chip in the same bar is a numeric string that monotonically changes with the chip's y-coordinate, usually a multi-digit numeric string that monotonically increases with the y-coordinate. For example, in... Figure 1 In this example, a bar contains 46 chips arranged sequentially. Each chip's serial number consists of 5 characters. The highest 3 characters are a prefix string, A50, where A5 identifies the chip's manufacturing process, and 0 indicates the bar to which the chip belongs. The lowest 2 characters are a suffix string, a numeric string that monotonically changes according to the chip's order within the bar (i.e., the chip's y-coordinate), such as... Figure 2 The suffix strings of the 46 chips arranged sequentially are 00 to 45, thus... Figure 2 As shown, the serial numbers of the 46 chips in the Bar are A5000, A5001, A5002...A5044, A5045.

[0081] Based on this, we first extract the strings with the same high-order part from the serial number recognition results of each index chip in the Bar bar as candidate prefixes, and then extract the strings from the serial number recognition results of each index chip other than the candidate prefixes as candidate suffixes.

[0082] However, the candidate prefixes and suffixes extracted in this way are not accurate prefix and suffix strings. For example, in one instance, assuming the first three chips in the bar are selected as index chips, the serial numbers of these three index chips can be identified as A5000, A5001, and A5002, respectively. The extracted candidate prefix is ​​the high 4 bits of A500, while the candidate suffix for each index chip is the lowest character, which is clearly inconsistent with reality. In another instance, assuming the serial numbers of the three index chips are identified as A5010, A5032, and A5033, the extracted candidate prefix is ​​the high 3 bits of A50, while the candidate suffix for each index chip is the low 2 characters, which is consistent with reality. Therefore, it can be seen that due to the randomness of index chip selection, the extracted candidate prefixes and suffixes may be accurate or inaccurate, thus requiring further processing.

[0083] As seen in the examples above, inaccurate extraction of candidate prefixes and suffixes often occurs because the high-order bits of the suffix strings of multiple index chips are identical. This leads to the erroneous attribution of some high-order bits of the suffix string to the prefix string, resulting in a longer candidate prefix and a shorter candidate suffix. However, even if the extracted candidate suffix is ​​not necessarily the same as the actual suffix string, it still reflects the variation of the actual suffix string with the chip's y-coordinate. Therefore, based on the candidate suffixes and y-coordinates of each index chip, the relationship between the suffix string of the chip in the bar and its y-coordinate can be determined. For example, in the example above, when the first three chips in the bar are selected as index chips, the extracted candidate suffixes for these three chips are 0, 1, and 2, and their y-coordinates are also 0, 1, and 2, respectively. This confirms that the chip's suffix string matches its y-coordinate. This is just a common and typical example; the actual variation can be more complex.

[0084] After determining the relationship between the suffix string of the chips in a bar and the chip's y-coordinate, the prefix string of the chips in that bar can be further determined by combining this with the total number of chips contained within the bar. The total number of chips contained within a bar is a pre-known parameter; for example, as mentioned above, typical total numbers of chips are 36, 46, and 57. Specifically:

[0085] Based on the relationship between the suffix string of the chip in the Bar and the y-coordinate of each chip, as well as the total number of chips contained in the current Bar, the number of digits occupied by the suffix string, k1, can be determined. Then, the number of digits occupied by the prefix string, k2 = T - k1, can be determined accordingly. Here, T is the number of characters contained in the serial number recognition result of a single index chip, and k1, k2, and T are all integer parameters, with T ≥ 3.

[0086] Due to the limited chip size, the chip's serial number will not have redundant bits. Therefore, the number of bits (k1) occupied by the chip's suffix string is the minimum number of bits required to satisfy the requirements when the suffix string changes according to its relationship with the y-coordinates of each chip. For example, in the above example, if we determine that the chip's suffix string matches the chip's y-coordinate and that the Bar contains 46 chips, we can determine that the number of bits occupied by the suffix string (k1) is 2. The same logic applies to other cases. Based on the fact that the serial number recognition result of the three index chips contains 5 characters, we can further determine that the number of bits occupied by the prefix string (k2) is 3. Then, extracting the high 3 bits of the string from the candidate prefix A500 yields the prefix string A50.

[0087] Similarly, although the serial number recognition result obtained by the serial number recognition model in this application is highly accurate, errors are still unavoidable. Therefore, when k1=0 or k2=0 is detected, that is, when the prefix string and the prefix string cannot be extracted, it is determined that there is an error in the serial number recognition of the index chip, and the index chip is reselected in the Bar bar.

[0088] After extracting the prefix string and determining the relationship between the suffix string and the chip's y-coordinate, the suffix string of each chip in the Bar can be determined based on the relationship between the suffix string of the chip in the Bar and the chip's y-coordinate, combined with the y-coordinate of each other chip in the Bar. Finally, the prefix string of the chip in the Bar and the corresponding suffix string of each chip are concatenated sequentially to obtain the serial number recognition result of each other chip in the Bar.

[0089] The above descriptions are merely preferred embodiments of this application, and this application is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of this application should be considered to be included within the protection scope of this application.

Claims

1. A method for identifying chip serial numbers on Bar strip wafers, characterized in that, The chip serial number identification method includes: The surface image of the region where the serial number is etched on the chip surface in each bar bar on the bar bar wafer is obtained, as well as the chip's coordinate information (x, y). The bar bar wafer has multiple bar bars arranged on it, and multiple chips are arranged sequentially in each bar bar. The x-coordinate of each chip indicates the bar bar to which the chip belongs, and the y-coordinate of the chip indicates the arrangement order of the chip in its bar bar. The serial numbers of different chips on the bar bar wafer conform to a predetermined format and are related to the chip's coordinate information (x, y). The surface image and coordinate information (x, y) of the chip are input into a pre-trained serial number recognition model. The serial number recognition model includes a feature extraction layer, a sequence modeling layer, and a prediction layer. The feature extraction layer is used to extract the image features of the surface image and the position features of the coordinate information and then fuse them to obtain the chip fusion features. The sequence modeling layer maps the chip fusion features into a probability distribution sequence and decodes and outputs the serial number recognition result of the chip through the prediction layer.

2. The chip serial number identification method according to claim 1, characterized in that, The chip serial number identification method further includes: At least three chips are selected from the Bar as index chips, and the serial number recognition model is used to determine the serial number recognition result of the index chip based on the surface image and coordinate information of each index chip. The predetermined format rule is determined based on the serial number recognition results of each index chip, and the serial number recognition results of other chips in the Bar are deduced according to the predetermined format rule.

3. The chip serial number identification method according to claim 2, characterized in that, The predetermined format rules that the serial numbers of different chips on the Bar wafer conform to include: the serial numbers of all chips in the same Bar are of the same length; the serial number of each chip includes a prefix string and a suffix string concatenated in sequence; the prefix strings of all chips in the same Bar are the same; and the suffix strings of each chip in the same Bar are different and related to the y-coordinate of the chip. The deduction yielded the following serial number identification results for the other chips in the Bar bar: Based on the serial number identification results of each index chip, determine the prefix string of the chip in the corresponding Bar bar, and the relationship between the suffix string of the chip in the Bar bar and the chip's y-coordinate; Based on the relationship between the suffix string of the chip in the Bar bar and the chip's y-coordinate, and combined with the y-coordinates of the other chips in the Bar bar, determine the suffix strings of the other chips; By concatenating the prefix string of the chip in the Bar with the suffix string corresponding to each chip, the serial number identification result of the other chips in the Bar is obtained.

4. The chip serial number identification method according to claim 3, characterized in that, The suffix string of each chip in the same bar is a numeric string that changes monotonically with the chip's y-coordinate; the prefix string of the chip in the corresponding bar is determined based on the serial number identification result of each index chip, and the relationship between the suffix string of the chip in the bar and the chip's y-coordinate includes: Extract the strings with the same high-order part from the serial number recognition results of each index chip in the Bar bar as candidate prefixes, and extract the strings other than the candidate prefixes from the serial number recognition results of each index chip as candidate suffixes; Based on the candidate suffixes of each index chip and the y-coordinate of each index chip, determine the relationship between the suffix string of the chip in the Bar bar and the chip y-coordinate; Based on the relationship between the suffix string of the chip in the Bar and the chip's y-coordinate, and combined with the total number of chips contained in the Bar, the prefix string of the chip in the corresponding Bar is determined.

5. The chip serial number identification method according to claim 4, characterized in that, The prefix string for determining the chip in the corresponding Bar bar includes: Based on the relationship between the suffix string of the chip in the Bar and the chip's y-coordinate, and the total number of chips contained in the current Bar, determine the number of digits k1 occupied by the suffix string, and correspondingly determine the number of digits k2 occupied by the prefix string; where T is the number of characters contained in the serial number recognition result of a single index chip, k1, k2 and T are all integer parameters, and T≥3; Extract the highest k2-bit string from the candidate prefixes to obtain the prefix string of the chip in the corresponding Bar.

6. The chip serial number identification method according to claim 2, characterized in that, Select at least three chips from the bar as index chips, including: At least three chips are randomly selected within the bar as index chips. These three index chips are arranged consecutively or alternately with other chips within the same bar.

7. The chip serial number identification method according to claim 1, characterized in that, The feature extraction layer in the serial number recognition model includes an image feature extractor and two location embedding layers. The chip fusion features output by the feature extraction layer include: The surface image of the chip is extracted by multi-layer convolution and pooling using an image feature extractor. The feature map is compressed to 1 in the height direction by adaptive pooling and then divided into N time steps in the width direction. The P-dimensional image features of each time step in the channel dimension are output. Two position embedding layers are used to convert the x and y coordinates in the chip's coordinate information into dense vectors. The two dense vectors are concatenated to obtain the Q-dimensional position feature. The Q-dimensional position feature is then copied and expanded in the time step dimension to output the Q-dimensional position feature for N time steps. The P-dimensional image features and Q-dimensional position features of N time steps are concatenated along the feature dimension to output the (P+Q)-dimensional chip fusion features of N time steps.

8. The chip serial number identification method according to claim 7, characterized in that, The sequence modeling layer in the sequence number recognition model includes a bidirectional LSTM, a sequence position attention mechanism, and a fully connected layer, which are connected in series. Bidirectional LSTM is used to perform sequence modeling of (P+Q) dimensional chip fusion features at N time steps and output the hidden features at N time steps; The sequence position attention mechanism aggregates the hidden features of N time steps in the time step dimension to obtain the feature vector of N time steps; The fully connected layer is used to map the feature vectors of N time steps into a probability distribution sequence. The probability distribution sequence includes the probability distribution result obtained by mapping the feature vectors at each time step. The probability distribution result at each time step includes the probability distribution of all R categories. The number of categories R is the total number of characters in the character set plus the number of whitespace characters.

9. The chip serial number identification method according to claim 8, characterized in that, The prediction layer performs CTC decoding on the probability distribution sequence output by the sequence modeling layer using greedy decoding or beam search methods to obtain the sequence number recognition result.

10. The chip serial number identification method according to claim 1, characterized in that, The chip serial number identification method further includes: Obtain the surface image, coordinate information, and serial number label of the sample chip; The surface image and coordinate information of the sample chip are input into the serial number recognition model to obtain the serial number prediction result of the sample chip; The CTC loss is calculated based on the serial number label and serial number prediction result of the sample chip, and the model parameters of the serial number recognition model are adjusted according to the CTC loss until the serial number recognition model is trained.

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