Data storage device and method for predictive read threshold calibration

Abstract

The invention provides a predictive read threshold calibration method, wherein a dedicated hardware module is used for read threshold calibration. The hardware module uses a tree-based inference model to generate a tree that produces corresponding inference results based on a plurality of read thresholds. An inferred read threshold is obtained by summing the inferred results of the trees, and the memory is read using the inferred read threshold. Other embodiments are provided herein.

Description

Background Technology

[0001] One of the main challenges brought about by NAND process shrinkage and 3D stacking is maintaining process consistency. Additionally, data storage devices may need to support various operating conditions (e.g., different program / erase cycles, hold times, and temperatures), which can lead to increased variability between memory dies, blocks, and pages under different operating conditions. Due to these variations, the read threshold (RT) used to read memory pages in some data storage devices is not fixed and can vary significantly with physical location and operating conditions, especially for less mature memory nodes. Attached Figure Description

[0002] Figure 1A This is a block diagram of a data storage device for an implementation scheme.

[0003] Figure 1B This is a block diagram illustrating a storage module in one implementation scheme.

[0004] Figure 1C This is a block diagram illustrating a hierarchical storage system implementation.

[0005] Figure 2A This is an example based on an implementation plan. Figure 1A A block diagram of the components of the controller for the data storage device shown.

[0006] Figure 2B This is an example based on an implementation plan. Figure 1A A block diagram of the components of the data storage device is shown.

[0007] Figure 3 This is a block diagram of the host and data storage devices in an implementation scheme.

[0008] Figure 4 This is a diagram of a storage controller in one implementation scheme.

[0009] Figure 5 This is a flowchart of the implementation method executed after the read threshold calibration operation is initiated.

[0010] Figure 6 This is a flowchart of a method for implementing predictive read threshold calibration.

[0011] Figure 7 It is a diagram of an implementation of a Failed Bit Count (FBC) Sigma graph as a function of the number of trees. Detailed Implementation

[0012] The following embodiments typically relate to data storage devices and methods for predictive read threshold calibration. In one embodiment, a data storage device including memory and one or more processors is provided. The one or more processors are configured individually or in combination to: generate multiple trees using a tree-based inference model, wherein each tree produces an inference result based on multiple read thresholds; obtain an inference read threshold by summing the inference results of the multiple trees; and use the inference read threshold to read memory.

[0013] In another embodiment, a method is provided to be performed in a data storage device including memory. The method includes: analyzing the operational status and / or available resources of the data storage device; determining the number of individual read threshold operations based on the analysis; operating the number of times determined by the read threshold calibration unit to provide a read threshold calibration result; and using the read threshold calibration result to read the memory.

[0014] In yet another embodiment, a data storage device is provided, including a memory and means for: repeatedly operating a read threshold calibration unit of the data storage device to provide a read threshold calibration result, wherein the repeated operation is based on the operating status and / or available resources of the data storage device; and using the read threshold calibration result to read the memory.

[0015] Other implementation schemes are feasible, and each of these schemes can be used individually or in combination. Therefore, various implementation schemes will now be described with reference to the accompanying drawings.

[0016] Implementation Plan

[0017] The following implementation relates to a data storage device (DSD). As described herein, a "data storage device" refers to a non-volatile device that stores data. Examples of DSDs include (but are not limited to) hard disk drives (HDDs), solid-state drives (SSDs), tape drives, hybrid drives, etc. Details of an example DSD are provided below.

[0018] exist Figures 1A to 1C Examples of data storage devices suitable for implementing various aspects of these implementation schemes are shown. It should be understood that these are merely examples and other specific implementations may be used. Figure 1A This is a block diagram illustrating a data storage device 100 according to one implementation scheme. (See reference) Figure 1AIn this example, the data storage device 100 includes a controller 102 coupled to non-volatile memory, which may consist of one or more non-volatile memory dies 104. As described herein, the term die refers to a collection of non-volatile memory cells formed on a single semiconductor substrate, and the associated circuitry for managing the physical operations of those non-volatile memory cells. The controller 102 interacts with a host system and transmits sequences of commands for read, program, and erase operations to the non-volatile memory die 104. Furthermore, as used herein, the phrases “communicating with” or “coupled with” can mean directly communicating / coupling with or indirectly communicating / coupling with or through one or more components, which may or may not be shown or described herein. The communication / coupling can be wired or wireless.

[0019] Controller 102 (which may be a non-volatile memory controller (e.g., a flash memory, resistive random access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random access memory (MRAM) controller)) may include one or more components, individually or in combination, configured to perform certain functions, including but not limited to those described herein and illustrated in the flowcharts. For example, such as Figure 2A As shown, controller 102 may include one or more processors 138, which are individually or in combination configured to perform functions, such as, but not limited to, the functions described herein and illustrated in the flowcharts, by executing computer-readable program code stored within and / or outside controller 102 in one or more non-transitory memories 139 (e.g., in random access memory (RAM) 116 or read-only memory (ROM) 118). As another example, one or more components may include circuitry, such as, but not limited to, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0020] In one exemplary embodiment, a nonvolatile memory controller 102 is a device that manages data stored on nonvolatile memory and communicates with a host (such as a computer or electronic device) having any suitable operating system. In addition to the specific functionalities described herein, the nonvolatile memory controller 102 may have various functionalities. For example, the nonvolatile memory controller may format the nonvolatile memory to ensure that the memory is operating correctly, identify bad nonvolatile memory cells, and allocate spare cells to replace future failed cells. Some portions of the spare cells may be used to house firmware (and / or other metadata for management and tracking) to operate the nonvolatile memory controller and implement other features. In operation, when the host needs to read data from or write data to the nonvolatile memory, it may communicate with the nonvolatile memory controller. If the host provides a logical address to read / write data, the nonvolatile memory controller may translate the logical address received from the host into a physical address in the nonvolatile memory. The non-volatile memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (allocating writes to specific memory blocks to avoid wear that would otherwise be repeatedly written to) and garbage collection (moving only valid data pages to a new block after a block is full, so that the entire block can be erased and reused).

[0021] The non-volatile memory die 104 may comprise any suitable non-volatile memory medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may be in the form of solid-state (e.g., flash memory) memory cells and may be programmable once, programmable multiple times, or programmable many times. The memory cells may also be single-level cells (SLC), multi-level cells (MLC) (e.g., two-level cells, three-level cells (TLC), four-level cells (QLC)), or utilize other memory cell-level technologies now known or developed thereafter. Furthermore, the memory cells may be fabricated in a two-dimensional or three-dimensional manner.

[0022] The interface located between the controller 102 and the non-volatile memory die 104 can be any suitable flash memory interface, such as switching modes 200, 400, or 800. In one embodiment, the data storage device 100 can be a card-based system, such as a Secure Digital (SD) card or a Micro Secure Digital (Micro SD) card. In another embodiment, the data storage device 100 can be part of an embedded data storage device.

[0023] Although Figure 1AIn the illustrated example, data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between controller 102 and non-volatile memory die 104; however, the subject matter described herein is not limited to having a single memory channel. For example, in some storage system architectures (such as...) Figure 1B and Figure 1C In the architecture shown, there can be two, four, eight, or more memory channels between the controller and the memory device, depending on the controller's capabilities. In any of the embodiments described herein, even if a single channel is shown in the figures, there can be more than one single channel between the controller and the memory die.

[0024] Figure 1B An example is illustrated of a storage module 200 comprising multiple non-volatile data storage devices 100. Thus, the storage module 200 may include a storage controller 202 that interacts with a host and a data storage device 204 comprising the multiple data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA), a Peripheral Component Rapid Interconnect (PCIe) interface, a Double Data Rate (DDR) interface, or a Serial Attached Small Compute Interface (SAS / SCSI). In one embodiment, the storage module 200 may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), such as those found in server PCs or portable computing devices such as laptops and tablets.

[0025] Figure 1C This is a block diagram illustrating a hierarchical storage system. The hierarchical storage system 250 includes a plurality of storage controllers 202, each of which controls a corresponding data storage device 204. A host system 252 can access the memory within the storage system 250 via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Fast (NVMe) or Fibre Channel Ethernet (FCoE) interface. In one embodiment, Figure 1C An example system could be a rack-mountable mass storage system that can be accessed by multiple host computers, such as in a data center or other locations where mass storage is required.

[0026] Refer again Figure 2AThe controller 102 in this example also includes a front-end module 108 that interfaces with the host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other components or modules, such as, but not limited to, a buffer manager / bus controller module that manages buffers in RAM 116 and controls the internal bus arbitration of controller 102. As described above, modules may include one or more processors or components. ROM 118 may store system boot code. Although Figure 2A In this embodiment, the RAM 116 and ROM 118 are illustrated as being located separately from the controller 102, but in other embodiments, one or both of them may be located within the controller 102. In still other embodiments, portions of the RAM 116 and ROM 118 may be located both inside and outside the controller 102.

[0027] Front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide an electrical interface to the host or next-level storage controller. The type of host interface 120 can be selected depending on the type of memory used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, Serial Attached Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. Host interface 120 is typically used for transmitting data, control signals, and timing signals.

[0028] Backend module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and error-corrects data bytes read from the non-volatile memory. Command sequencer 126 generates command sequences, such as programming and erasing command sequences, to be transmitted to the non-volatile memory die 104. RAID (Redundant Array of Independent Drives) module 128 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data written to memory device 104. In some cases, RAID module 128 may be part of ECC engine 124. Memory interface 130 provides command sequences to and receives status information from the non-volatile memory die 104. In one embodiment, memory interface 130 may be a double data rate (DDR) interface, such as a switching mode 200, 400, or 800 interface. The controller 102 in this example also includes a media management layer 137 and a flash control layer 132, which controls the overall operation of the back-end module 110.

[0029] The data storage device 100 also includes other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interact with the controller 102. In an alternative embodiment, one or more of the physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller are optional components that are not required in the controller 102.

[0030] Figure 2B This is a block diagram illustrating the components of a non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells for storing data. The non-volatile memory cells can be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The non-volatile memory die 104 also includes a data cache 156 that caches data and address decoders 148, 150. The peripheral circuitry 141 in this example includes a state machine 152 that provides state information to the controller 102. The peripheral circuitry 141 may also include one or more components that are individually or in combination configured to perform certain functions, including but not limited to those described herein and shown in the flowcharts. For example, as... Figure 2B As shown, memory die 104 may include one or more processors 168, which are individually or in combination configured to execute computer-readable program code stored in one or more non-transitory memories 169, in memory array 142, or external to memory die 104. As another example, one or more components may include circuitry, such as, but not limited to, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0031] In addition to or replacing one or more processors 138 (or more generally, components) in controller 102 and one or more processors 168 (or more generally, components) in memory die 104, data storage device 100 may include another set of one or more processors (or more generally, components). Generally, regardless of location and number, one or more processors (or more generally, components) in data storage device 100 may be configured individually or in combination to perform various functions, including but not limited to those described herein and illustrated in the flowcharts. For example, one or more processors (or components) may be located in other locations within controller 102, memory device 104, and / or data storage device 100. Furthermore, different processors (or components) or combinations of processors (or components) may be used to perform different functions. Additionally, means for performing functions may be implemented using a controller that includes one or more components (e.g., processors or other components described above).

[0032] Refer again Figure 2A The flash control layer 132 (hereinafter referred to as the flash translation layer (FTL)) handles flash errors and interacts with the host. Specifically, the FTL (which may be an algorithm in the firmware) is responsible for the internal memory management and translates writes from the host into writes to memory 104. An FTL may be necessary because memory 104 may have limited endurance, may only have a few pages written, and / or may not be written to at all (unless it is erased as a block). The FTL understands these potential limitations of memory 104, which may not be visible to the host. Therefore, the FTL attempts to translate writes from the host into writes to memory 104.

[0033] The FTL may include a logical-to-physical address (L2P) mapping (sometimes referred to herein as a table or data structure) and allocated cache memory. In this way, the FTL translates logical block addresses (“LBAs”) from the host into physical addresses in memory 104. The FTL may include other features such as, but not limited to, power-off recovery (enabling the FTL’s data structures to recover in the event of a sudden power loss) and wear leveling (ensuring wear is evenly distributed across memory blocks to prevent some blocks from becoming excessively worn, which would lead to a greater chance of failure).

[0034] Returning to the attached diagram, Figure 3This is a block diagram of a host 300 and a data storage device 100 according to one embodiment. The host 300 can take any suitable form, including but not limited to a computer, mobile phone, tablet, wearable device, digital video recorder, surveillance system, etc. In this embodiment, the host 300 (here, a computing device) includes one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in one or more memories 340 configures one or more processors 330 to perform actions described herein as being performed by the host 300. Therefore, actions performed by the host 300 are sometimes referred to herein as being performed by an application (computer-readable program code) running on the host 300. For example, the host 300 can be configured to send data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the memory 104 of the data storage device.

[0035] As mentioned above, one of the main challenges brought about by NAND process shrinkage and 3D stacking is maintaining process consistency. Additionally, data storage devices may need to support various operating conditions (e.g., different program / erase cycles, hold times, and temperatures), which can lead to increased variability between memory dies, blocks, and pages under different operating conditions. Due to these variations, the read threshold (RT) used to read memory pages in some data storage devices is not fixed and can vary significantly with physical location and operating conditions, especially for newer, less mature memory nodes.

[0036] Reading with inaccurate read thresholds can lead to high bit error rates (BER), potentially degrading performance and Quality of Service (QoS) due to decoding failures. This may necessitate invoking high-latency recovery streams, resulting in latency and poor performance. Maintaining optimal read thresholds is particularly challenging for enterprise memory systems with stringent QoS requirements, as well as mobile, Internet of Things (IoT), and automotive memory systems, given the wide range of operating conditions and the high frequency of condition changes (e.g., temperature). This problem becomes even more difficult to address when migrating to newer, less mature memory nodes.

[0037] Current read threshold calibration solutions, such as BER estimation scan (BES) and valley search (VS), are high-latency operations designed to optimize read thresholds for specific word lines. While useful for rare read recovery processes when decoding data fails, they may not be suitable for frequent operations when read thresholds change frequently. Therefore, to address this issue, flash memory systems can implement read threshold management schemes that attempt to track read threshold changes in the background through a maintenance process to ensure that an appropriate read threshold is used when the host issues a read command.

[0038] One approach is to track read thresholds for each block group that shares the same conditions. More specifically, blocks written at roughly the same time and temperature are grouped into time-temperature (TT) groups. The read thresholds for each time-temperature group are typically derived from a representative word line of a block within that group. When the host performs a read operation, the read threshold associated with the time-temperature group corresponding to the read block is used, with additional adjustments made to the read threshold based on a pre-calibrated word line partitioning table, depending on the specific read word line.

[0039] Some read threshold management schemes may fail to adequately track read thresholds under frequently changing conditions and large variations between memory pages. For example, U.S. Patent Application No. 17 / 838,481, filed June 13, 2022, describes a read threshold calibration method applying a machine learning (ML) predictive model, which is incorporated herein by reference. More specifically, it describes a system and method for inferring the optimal read threshold from all available information, including time and temperature group information, temperature information, BER information, program / erase count (PEC) information, and physical page location.

[0040] As another example, U.S. Patent Application No. 17 / 899,073, filed August 30, 2022; U.S. Patent Application No. 18 / 220,363, filed July 11, 2023; and U.S. Patent Application No. 18 / 242,061, filed September 5, 2023, describe a method that allows for the implementation of an inference engine to obtain read thresholds faster and more accurately, all of which are incorporated herein by reference in their entirety. This method uses a binary tree model to efficiently store only a subset of the relevant calibration data. Furthermore, this method does not require direct reading from NAND memory to perform threshold calibration. Therefore, this method is significantly faster than BES / VS-based calibration. The unique structure of binary trees allows for the implementation of fast, small-area, and low-power solutions, and can be implemented in hardware. However, hardware implementations of tree-based prediction models may not allow for the flexibility of read threshold calibration engines and may therefore be unsuitable for use cases requiring faster and lower power consumption.

[0041] The following embodiments can solve this problem by providing a modular design that uses dedicated hardware (e.g., a pure hardware implementation) to calibrate the read threshold. Generally speaking, these embodiments can be used to provide a modular binary tree hardware module for read threshold calibration. The modular design allows for flexible use of different parts of the hardware engine in order to be able to adaptively use and optimize the trade-off between the read threshold accurately provided on the one hand and the latency and power consumption on the other hand. A pure hardware implementation means implementation only in hardware (e.g., in an application-specific integrated circuit (ASIC)) rather than by executing software.

[0042] The basic hardware engine described in the above patent application is based on a non-linear function that uses multiple inputs reflecting the current memory and data conditions. Previously, each operation of the hardware module required sequential operations on a set of trees that make up the entire model (e.g., 15 consecutive operations on a set of four trees at each step). The following embodiments allow for flexible operation on only a part of these sets of trees according to user constraints (e.g., power and / or time / latency).

[0043] One embodiment is based on the construction nature of a random forest gradient boosting prediction model. These models are based on successive corrections of the prediction. At each new step of model training, a new tree is added with the criterion of minimizing the error residuals of the previous set of trees. Thus, in one example, a hardware model with M = 60 trees - the set of each subgroup of m < M trees {1, 2,.., m} will provide a more accurate read threshold by itself. As m becomes larger and includes more trees, the finally predicted read threshold will be more accurate.

[0044] Therefore, these implementations offer flexible use of hardware modules, where the number of operated trees can be adaptively set according to user requirements, or automatically set by tracking system conditions and available resources (e.g., current power consumption, PEC value, system temperature, etc.). These implementations allow for more accurate thresholds but require more time and effort in inference engine operation. For example, at high system temperatures, performance throttling can be applied to prevent further heating, allowing more bandwidth / tuning for read threshold inference operations that can use a full tree-based model (e.g., 60 trees). Simultaneously, under such high temperatures, the Xtemp effect can lead to increased BER, which may necessitate more accurate read thresholds to maintain lower BER levels and avoid higher error correction code (ECC) decoding latency and power consumption, which can further increase system temperature or even cause ECC decoding failures. Therefore, at high system temperatures, using the full inference model to obtain accurate read thresholds may be beneficial. In fact, due to performance limitations, the system allows for latency when applying the full inference model. At normal system temperatures, the data storage device can perform inference based on a reduced / more limited model (e.g., a smaller number of trees, such as <60) in order to perform inference at a rate that does not limit the overall system performance (utilizing small / low-complexity inference hardware) while providing a sufficiently good read threshold under normal temperature conditions.

[0045] In one implementation, the hardware module enables the simultaneous computation of a tree-based inference model across k trees. Each tree produces inference results for all read thresholds. In this implementation, if the storage design operates on a quad-level cell (QLC) memory, the number of calibrated read thresholds in the hardware unit will be 2. 4 -1 = 15. If the memory design is running on a three-level cell (TLC) memory, the number of calibration read thresholds will be 2. 3 -1 = 7, and so on. The final reasoning result can be obtained by adding the results of each tree.

[0046] The hardware module can be activated once to produce an inference result based on k trees with minimal latency. Alternatively, the hardware module can be activated twice to produce a more accurate inference result based on 2*k trees, but at the cost of twice the latency. Alternatively, the hardware module can be activated m times to produce a more accurate inference result based on m*k trees, but at the cost of m times the latency. The number of read threshold calibration hardware operations affects the accuracy of the entire calibration operation. The number of operations can depend on various system factors, such as, but not limited to, PEC, environmental conditions, performance requirements, available resources, and system temperature. When higher accuracy is required, the data storage device can perform more hardware operations. When accuracy requirements are low or resources are scarce, only a single operation may be performed.

[0047] Please refer to the attached diagram again. Figure 4 This is a diagram of a storage controller 102 in one implementation scheme. (See diagram) Figure 4 As shown, in this embodiment, the storage controller 102 includes a read threshold calibration activation control unit 400 and a single read threshold calibration unit 410, both of which can be implemented by one or more processors of the controller 102, as described above. The read threshold calibration activation control unit 400 can operate the single read threshold calibration unit 410 according to its considerations.

[0048] Figure 5 This is a flowchart 500 of the implementation method executed after initiating the read threshold calibration operation. (e.g.) Figure 5 As shown, in this method, the read threshold calibration activation control unit 400 analyzes the operating status and available resources (action 510), and then determines the number of times a single read threshold operation is performed (action 520). Next, the single read threshold calibration unit 410 operates the indicated number of times and provides the read threshold calibration result (action 530).

[0049] In another implementation, the read threshold activation control unit 400 can determine the number of activations before the entire calibration operation, or it can determine the number of activations on the fly based on feedback from the read threshold calibration unit 410. For example, if the change in the read threshold is large (i.e., above a certain threshold), it may be more necessary to activate the calibration unit to correct the result because the optimal read threshold differs significantly from the current read threshold. More specifically, a tree-based model can be trained such that each tree corrects the residual error of the inference model based on previous trees. In this case, the correction applied to each consecutive tree is expected to have a low magnitude. Therefore, the determination of the number of trees applied in a particular inference operation can be dynamic, based on the correction magnitude introduced by the last set of k trees computed in the previous round. Once the correction magnitude falls below a predefined threshold, the inference operation can be considered sufficiently accurate and terminated. Additionally, this scheme provides the ability to terminate or reduce the number of operations if conditions or available resources change during the calibration operation.

[0050] Figure 6 This is a flowchart 600 of a method for an implementation scheme executed after initiating a read threshold calibration operation. In this method, after each iteration of the read threshold calibration unit 410, the read threshold calibration control unit 400 can decide to terminate the operation or resume another calibration unit iteration. More specifically, as... Figure 6 As shown, in this method, the read threshold calibration activation control unit 400 analyzes the operating status, available resources, and feedback from the read threshold calibration unit 410 (action 610). If the read threshold calibration activation control unit 400 concludes based on this analysis that the read threshold calibration operation has been completed, it provides the calibration result to the system (action 620). However, if the read threshold calibration activation control unit 400 determines that another read threshold calibration operation needs to be performed, the read threshold calibration unit 410 performs a single calibration operation and provides the read threshold calibration result.

[0051] In another implementation, the read threshold operation unit may consist of a single read threshold calibration. The logic behind this implementation is that, due to the larger Vt shift of the read threshold, some read thresholds may require more operations (e.g., more calibration iterations), while others may require fewer calibration iterations. For example, in TLC memory, the FG threshold is known to cause a larger Vt offset compared to other read thresholds due to external conditions such as Xtemp or DR. Using this implementation, the FG RT calibration can run more iterations than the AB RT calibration because a finer result is required. Exemplary results of the operation are shown in... Figure 7 The graph shows a comparison between operating on 60 trees and a shorter model. Therefore, Figure 7The effect of the number of trees used in the model on the Failed Bit Count (FBC) level is shown. This figure is based on a BiCS5 memory; see the next page for the figure.

[0052] When using BES for each point, one line represents the FBC level. Another line represents the FBC level when using certain read thresholds. All the lines in between depict various models that vary with the number of trees. These lines show that even shorter models are effective. This is an expected result, as each additional tree improves the model. Specifically, the graph shows that halving the number of trees has a small impact on FBC but can significantly reduce power consumption and latency.

[0053] These implementation schemes offer several advantages. For example, they allow for modular and flexible use of invested resources, thereby optimizing the trade-off between the accuracy threshold provided on one hand and the latency and power consumption on the other.

[0054] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in a NAND configuration or a NOR configuration.

[0055] The memory device can be formed from passive and / or active components in any combination. By way of non-limiting example, a passive semiconductor memory element includes a ReRAM device element, which in some embodiments includes resistivity-switching storage elements such as antifuse, phase-change materials, etc., and optionally includes guiding elements such as diodes. Further by way of non-limiting example, an active semiconductor memory element includes EEPROM and flash memory device elements, which in some embodiments include elements having charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0056] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND memory array can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, for example, in a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0057] Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional or three-dimensional memory structures.

[0058] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in the xz plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of the memory elements are formed, or it may be a carrier substrate attached to the memory elements after they have been formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0059] Memory elements can be arranged in a single memory device level in an ordered array (such as in multiple rows and / or columns). However, memory elements can be arranged in unconventional or non-orthogonal configurations. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0060] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y and z directions, where the y direction is substantially perpendicular to the main surface of the substrate, and the x and z directions are substantially parallel to the main surface of the substrate).

[0061] As a non-limiting example, a three-dimensional memory structure can be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), wherein each column has multiple memory elements. The columns can be arranged in a two-dimensional configuration, for example, in the xz plane, resulting in a three-dimensional arrangement of the memory elements, where the elements are on multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0062] As a non-limiting example, in a three-dimensional NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0063] Typically, in a monolithic three-dimensional memory array, one or more memory device classes are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers that are at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layer constituting each memory device class of the array is typically formed on the layer of the underlying memory device class of the array. However, the layers of adjacent memory device classes in a monolithic three-dimensional memory array may be shared or may have intervening layers between memory device classes.

[0064] Two-dimensional arrays can then be formed individually and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0065] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0066] Those skilled in the art will recognize that the present invention is not limited to the described two-dimensional and three-dimensional structures, but covers all relevant memory structures as described herein and as understood by those skilled in the art to be of the spirit and scope of the invention.

[0067] The foregoing detailed description is intended to be understood as an illustration of selected forms in which the invention may take place, and not as a definition of the invention. The scope of the claimed invention is intended to be defined only by the following claims (including all equivalents). Finally, it should be noted that any aspect of any embodiment described herein may be used alone or in combination with each other.

Claims

1. A data storage device, the data storage device comprising: Memory; and One or more processors, wherein the one or more processors are configured individually or in combination to: A tree-based inference model is used to generate multiple trees, each of which produces inference results based on multiple read thresholds; The reading threshold for reasoning is obtained by summing the reasoning results of the multiple trees; as well as The memory is read using the read threshold determined by the inference.

2. The data storage device of claim 1, wherein the one or more processors are further configured individually or in combination to generate additional trees using the tree-based inference model, wherein the read threshold of the inference is obtained by summing the inference results of the plurality of trees and the additional trees, which provides higher accuracy.

3. The data storage device of claim 2, wherein the number of trees in the additional tree is based on a program-erase count.

4. The data storage device of claim 2, wherein the number of trees in the additional tree is based on environmental conditions.

5. The data storage device of claim 2, wherein the number of trees in the additional tree is based on performance requirements.

6. The data storage device of claim 2, wherein the number of trees in the additional tree is based on available resources.

7. The data storage device of claim 2, wherein the number of trees in the additional tree is based on temperature.

8. The data storage device of claim 2, wherein the number of trees in the additional trees is based on power consumption.

9. The data storage device of claim 1, wherein the one or more processors are further configured individually or in combination to apply performance limits to allow additional bandwidth to be used to obtain the read threshold for the inference using the full tree-based model.

10. The data storage device according to claim 1, wherein the tree-based inference model includes a random forest gradient boosting prediction model.

11. The data storage device of claim 1, wherein the one or more processors are implemented entirely in hardware.

12. The data storage device according to claim 1, wherein the memory includes a three-dimensional memory.

13. In a data storage device including a memory, a method includes: Analyze the operating status and / or available resources of the data storage device; Based on the analysis, the number of individual read threshold operations is determined; The number of operations determined by the read threshold calibration unit is used to provide read threshold calibration results; as well as The memory is read using the read threshold calibration result.

14. The method of claim 13, wherein the determination is performed before the calibration operation is performed.

15. The method of claim 13, wherein the determination is performed in real time based on feedback from the read threshold calibration unit.

16. The method according to claim 13, further comprising: After each iteration of the read threshold calibration unit, it is determined whether to terminate the operation or perform another calibration unit iteration, wherein the read threshold calibration result is provided in response to determining the termination operation.

17. The method of claim 16, wherein determining whether to terminate the operation or perform another calibration unit iteration is based on operating status, available resources, and / or feedback from the read threshold calibration unit.

18. The method of claim 13, wherein the read threshold calibration unit comprises a single read threshold calibration unit.

19. The method of claim 13, wherein the method is performed in a dedicated hardware module in the data storage device.

20. A data storage device, the data storage device comprising: Memory; and Devices for the following purposes: The read threshold calibration unit of the data storage device is operated multiple times to provide a read threshold calibration result, wherein the multiple operations are based on the operating status and / or available resources of the data storage device; as well as The memory is read using the read threshold calibration result.

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