Semiconductor bonding method, semiconductor bonding structure and packaging structure

Abstract

The invention relates to the technical field of semiconductors, and discloses a semiconductor bonding method, a semiconductor bonding structure and a packaging structure.The semiconductor bonding method comprises the steps that a first semiconductor structure and a second semiconductor structure are formed, the first semiconductor structure is provided with a first groove, and a first bonding pad is formed in the first groove; the first bonding pad comprises a first magnetic conductive material layer located on at least part of the groove surface of the first groove and a first conductive layer filling the remaining space in the first groove, the magnetization intensity of the first magnetic conductive material layer is larger than that of the first conductive layer, and the conductivity of the first conductive layer is larger than that of the first magnetic conductive material layer; a second bonding pad is formed on the second semiconductor structure, and the material of the second bonding pad comprises a second magnetic conductive material; aligning the first bonding pad with the second bonding pad by using an attractive force between the first bonding pad and the second bonding pad; and bonding the first semiconductor structure with the second semiconductor structure. The magnetic alignment mode is beneficial to meeting the requirement of smaller pitch bonding on accurate focusing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor bonding method, a semiconductor bonding structure and a packaging structure. BACKGROUND

[0002] Bonding technology is a key technology for realizing three-dimensional integration of semiconductor and plays an important role in integrated circuits. The bonding technology includes a plurality of semiconductor structure longitudinal stacking, alignment and bonding steps in sequence, so as to obtain a semiconductor bonding structure, wherein the alignment step is mainly used for aligning a plurality of pads on the semiconductor structures, so that the plurality of pads on the semiconductor structures after bonding can be connected one by one, thereby realizing the electrical connection of the plurality of semiconductor structures. Higher alignment accuracy can avoid problems such as series connection and short circuit of lines after bonding caused by misplacement of the plurality of pads.

[0003] At present, optical alignment method is usually used for the alignment of semiconductor structures. The optical alignment method needs to form a plurality of alignment marks on the bonding surface of the semiconductor structure, capture the image or signal of the alignment mark through an optical system, calculate the offset through an image processing algorithm, and adjust the position through a driving system until the target accuracy is reached. The alignment mark is usually located at the edge region of the bonding surface of the semiconductor structure. As can be seen, the optical alignment method needs to reserve part of the area of the bonding surface of the semiconductor structure to form the alignment mark, which limits the further reduction of the size of the semiconductor structure and the semiconductor bonding structure. SUMMARY

[0004] Therefore, the present application provides a semiconductor bonding method, a semiconductor bonding structure and a packaging structure to further reduce the size of the semiconductor bonding structure.

[0005] In a first aspect, the present application provides a semiconductor bonding method, comprising:

[0006] forming a first semiconductor structure, one side surface of the first semiconductor structure having a plurality of first grooves, a first pad being formed in each of the first grooves, the first pad comprising a first magnetic conductive material layer located at least part of the groove surface of the first groove, and a first conductive layer filling the remaining space in the first groove, the magnetization intensity of the first magnetic conductive material layer being greater than the magnetization intensity of the first conductive layer, and the electrical conductivity of the first conductive layer being greater than the electrical conductivity of the first magnetic conductive material layer;

[0007] forming a second semiconductor structure, one side surface of the second semiconductor structure having a plurality of second pads, the material of the second pad comprising a second magnetic conductive material, the polarity of the second magnetic conductive material being opposite to that of the first magnetic conductive material;

[0008] aligning the first pad with the second pad using an attractive force between the first pad and the second pad;

[0009] bonding the first semiconductor structure with the second semiconductor structure.

[0010] The semiconductor bonding method can realize the alignment of the first pad with the second pad using the attractive force between the first pad and the second pad. The magnetic alignment method can avoid forming alignment marks on the surfaces of the first semiconductor structure and the second semiconductor structure, which is conducive to further reducing the lateral size of the formed semiconductor bonding structure, and the magnetic alignment method is conducive to meeting the requirement of accurate focusing of smaller pitch bonding pairs.

[0011] In an optional embodiment, the forming of the first semiconductor structure comprises: forming a plurality of first grooves on a side surface of the first semiconductor structure; forming a first magnetic conductive material layer on at least part of the groove surface of the first grooves, and forming a first conductive layer in the remaining space of the first grooves; and magnetizing the first magnetic conductive material layer using a first magnetic field.

[0012] In an optional embodiment, the forming of the second semiconductor structure comprises: forming a plurality of second grooves on a side surface of the second semiconductor structure; forming a second magnetic conductive material layer on at least part of the groove surface of the second grooves, and forming a second conductive layer in the remaining space of the second grooves; magnetizing the second magnetic conductive material layer using a second magnetic field, the magnetization intensity of the second magnetic conductive material layer being greater than the magnetization intensity of the second conductive layer, and the electrical conductivity of the second conductive layer being greater than the electrical conductivity of the second magnetic conductive material layer; or, filling the second magnetic conductive material in all the space of the second grooves, and magnetizing the second magnetic conductive material using a second magnetic field, the direction of the second magnetic field being opposite to that of the first magnetic field.

[0013] In an optional embodiment, the first magnetic conductive material layer is magnetized using a first magnetic field after the forming of the first magnetic conductive material layer and before the forming of the first conductive layer; and / or, the second magnetic conductive material layer is magnetized using a second magnetic field after the forming of the second magnetic conductive material layer and before the forming of the second conductive layer.

[0014] In an optional embodiment, the first magnetic conductive material layer is located at least at the groove bottom of the first grooves; and / or, the second magnetic conductive material layer is located at least at the groove bottom of the second grooves.

[0015] In an optional embodiment, the material of the first magnetic conductive material layer comprises one or more of cobalt, nickel, cobalt-nickel alloy, and iron-cobalt alloy.

[0016] In an alternative embodiment, the second magnetic conductive material comprises one or more of cobalt, nickel, cobalt-nickel alloy, iron-cobalt alloy.

[0017] In an alternative embodiment, the material of the first conductive layer comprises one or more of copper, tungsten, molybdenum.

[0018] In an alternative embodiment, the material of the second conductive layer comprises one or more of copper, tungsten, molybdenum.

[0019] In an alternative embodiment, the ratio of the thickness of the first magnetic conductive material layer to the depth of the first recess is 1:(3-100).

[0020] In an alternative embodiment, the ratio of the thickness of the second magnetic conductive material layer to the depth of the second recess is 1:(3-100).

[0021] In an alternative embodiment, the forming of the first recesses on the side surface of the first semiconductor structure comprises: forming a first dielectric layer on the side surface of the first semiconductor substrate; and patterning the first dielectric layer to form first through holes penetrating the first dielectric layer, the first through holes constituting the first recesses in the first semiconductor structure.

[0022] In an alternative embodiment, the forming of the first magnetic conductive material layer on at least part of the side surface of the first recess and the forming of the first conductive layer in the remaining space of the first recess comprises: forming a first initial magnetic conductive material layer on the side surface of the first recess and the side surface of the first dielectric layer away from the first semiconductor substrate, the thickness of the first initial magnetic conductive material layer being less than the depth of the first recess; forming a first initial conductive layer on the side surface of the first initial magnetic conductive material layer away from the first semiconductor substrate, the sum of the thicknesses of the first initial magnetic conductive material layer and the first initial conductive layer being greater than or equal to the depth of the first recess; and planarizing the first initial magnetic conductive material layer and the first initial conductive layer to remove the first initial magnetic conductive material layer and the first initial conductive layer outside the first recess.

[0023] In an alternative embodiment, the forming the first magnetic conductive material layer on at least part of the sidewall of the first recess and the forming the first conductive layer in the remaining space of the first recess comprises: forming a first initial magnetic conductive material layer on the sidewall of the first recess and a side surface of the first dielectric layer away from the first semiconductor substrate, the first initial magnetic conductive material layer having a thickness less than the depth of the first recess; patterning the first initial magnetic conductive material layer to form the first magnetic conductive material layer on part of the sidewall of the first recess; forming a first initial conductive layer on the side surface of the first dielectric layer away from the first semiconductor substrate, the first initial conductive layer extending into the first recess and covering the first magnetic conductive material layer, the first magnetic conductive material layer and the first initial conductive layer having a combined thickness greater than or equal to the depth of the first recess; and planarizing the first initial conductive layer to remove the first initial conductive layer outside the first recess.

[0024] In an alternative embodiment, the forming the first semiconductor structure further comprises: forming a first barrier layer on the sidewall of the first recess before forming the first magnetic conductive material layer on at least part of the sidewall of the first recess, the first barrier layer having a first opening on at least part of the area of the bottom of the first recess.

[0025] In an alternative embodiment, the forming the plurality of second recesses on a side surface of the second semiconductor structure comprises: forming a second dielectric layer on a side surface of the second semiconductor substrate; and patterning the second dielectric layer to form a plurality of second through holes through the second dielectric layer, the second through holes constituting the second recesses in the second semiconductor structure.

[0026] In an alternative embodiment, the forming the second magnetic conductive material layer on at least part of the sidewall of the second recess and the forming the second conductive layer in the remaining space of the second recess comprises: forming a second initial magnetic conductive material layer on the sidewall of the second recess and a side surface of the second dielectric layer away from the second semiconductor substrate, the second initial magnetic conductive material layer having a thickness less than the depth of the second recess; forming a second initial conductive layer on the side surface of the second initial magnetic conductive material layer away from the second semiconductor substrate, the second initial magnetic conductive material layer and the second initial conductive layer having a combined thickness greater than or equal to the depth of the second recess; and planarizing the second initial magnetic conductive material layer and the second initial conductive layer to remove the second initial magnetic conductive material layer and the second initial conductive layer outside the second recess.

[0027] In an alternative embodiment, the forming the second magnetic conductive material layer on at least part of the sidewall of the second recess and forming the second conductive layer in the remaining space of the second recess comprises: forming a second initial magnetic conductive material layer on the sidewall of the second recess and the side surface of the second dielectric layer away from the second semiconductor substrate, the thickness of the second initial magnetic conductive material layer being less than the depth of the second recess; patterning the second initial magnetic conductive material layer to form the second magnetic conductive material layer on part of the sidewall of the second recess; forming a second initial conductive layer on the side surface of the second dielectric layer away from the second semiconductor substrate, the second initial conductive layer extending into the second recess and covering the second magnetic conductive material layer, the sum of the thicknesses of the second magnetic conductive material layer and the second initial conductive layer being greater than or equal to the depth of the second recess; and planarizing the second initial conductive layer to remove the second initial conductive layer outside the second recess.

[0028] In an alternative embodiment, the filling the entire space in the second recess with the second magnetic conductive material comprises: forming a second initial magnetic conductive material layer on the sidewall of the second recess and the side surface of the second dielectric layer away from the second semiconductor substrate, the thickness of the second initial magnetic conductive material layer being greater than or equal to the depth of the second recess; and planarizing the second initial magnetic conductive material layer to remove the second initial magnetic conductive material layer outside the second recess.

[0029] In an alternative embodiment, the forming the second semiconductor structure further comprises: before forming the second magnetic conductive material layer on at least part of the sidewall of the second recess, forming a second barrier layer on the sidewall of the second recess, the second barrier layer having a second opening on at least part of the area of the bottom of the second recess.

[0030] In an alternative embodiment, the semiconductor bonding method further comprises: before aligning the first pad with the second pad by the attractive force between the first pad and the second pad, coarsely aligning the first pad with the second pad by an optical alignment process.

[0031] In an alternative embodiment, the forming the plurality of first recesses on the side surface of the first semiconductor structure comprises: forming a first dielectric layer on the side surface of the first semiconductor substrate; and patterning the first dielectric layer to form a plurality of first through holes through the first dielectric layer, the first through holes constituting the first recesses in the first semiconductor structure.

[0032] The forming of the plurality of second grooves on the side surface of the second semiconductor structure comprises: forming a second dielectric layer on a side surface of a second semiconductor substrate; and performing a patterning process on the second dielectric layer to obtain a plurality of second through holes penetrating through the second dielectric layer, the second through holes constituting the second grooves in the second semiconductor structure.

[0033] The bonding of the first semiconductor structure and the second semiconductor structure comprises: performing a first compression process on the first semiconductor structure and the second semiconductor structure to preliminarily combine the first dielectric layer and the second dielectric layer through intermolecular forces; and performing a second compression process on the first semiconductor structure and the second semiconductor structure, the temperature of the second compression process being greater than the temperature of the first compression process, so that alloying occurs at the interface of the first pad and the second pad, and the first dielectric layer and the second dielectric layer are combined through covalent bonds.

[0034] In a second aspect, the present application provides a semiconductor bonding structure, comprising a first semiconductor structure and a second semiconductor structure, a side surface of the first semiconductor structure having a plurality of first grooves, a first pad being arranged in each of the first grooves, the first pad comprising a first magnetic conductive material layer on at least part of the groove surface of the first groove, and a first conductive layer filling the remaining space in the first groove, the magnetic intensity of the first magnetic conductive material layer being greater than the magnetic intensity of the first conductive layer, and the electrical conductivity of the first conductive layer being greater than the electrical conductivity of the first magnetic conductive material layer; a side surface of the second semiconductor structure being provided with a plurality of second pads, the material of the second pad comprising a second magnetic conductive material, the polarity of the second magnetic conductive material being opposite to that of the first magnetic conductive material; the first semiconductor structure and the second semiconductor structure being oppositely arranged and bonded.

[0035] In an optional embodiment, a side surface of the second semiconductor structure has a plurality of second grooves, the second pad comprising a second magnetic conductive material layer on at least part of the groove surface of the second groove, and a second conductive layer filling the remaining space in the second groove, the magnetic intensity of the second magnetic conductive material layer being greater than the magnetic intensity of the second conductive layer, and the electrical conductivity of the second conductive layer being greater than the electrical conductivity of the second magnetic conductive material layer; or the second pad is composed of a second magnetic conductive material filling all the space in the second groove.

[0036] In a third aspect, the present application provides a packaging structure, comprising the semiconductor bonding structure obtained by the semiconductor bonding method of the first aspect or the semiconductor bonding structure of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the specific embodiments or the related art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the related art description. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0038] Figure 1 is a process flow chart of a semiconductor bonding method according to an embodiment of the present application.

[0039] Figure 2 is a structural schematic diagram of a first semiconductor structure according to an embodiment of the present application.

[0040] Figure 3 is a structural schematic diagram of a second semiconductor structure according to an embodiment of the present application.

[0041] Figure 4 is a structural schematic diagram of another second semiconductor structure according to an embodiment of the present application.

[0042] Figure 5 is a schematic diagram of an alignment step of a first semiconductor structure and a second semiconductor structure according to an embodiment of the present application.

[0043] Figure 6 is a schematic diagram of a semiconductor bonding structure according to an embodiment of the present application.

[0044] Figure 7 is a schematic diagram of another semiconductor bonding structure according to an embodiment of the present application.

[0045] Legend of reference signs:

[0046] 1 - first semiconductor structure; 11 - first pad; 111 - first magnetic conductive material layer; 112 - first conductive layer; 12 - first semiconductor substrate; 121 - first vertical interconnection structure; 122 - first horizontal interconnection structure; 13 - first dielectric layer; 2, 2' - second semiconductor structure; 21, 21' - second pad; 211 - second magnetic conductive material layer; 212 - second conductive layer; 22 - second semiconductor substrate; 221 - second vertical interconnection structure; 222 - second horizontal interconnection structure; 23 - second dielectric layer. DETAILED DESCRIPTION

[0047] The present application will be further described below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present application, and not to limit the present application. In addition, it should be noted that, for the purpose of description, only the parts related to the present application are shown in the drawings, not all the structures.

[0048] In the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present application. Various structural diagrams according to embodiments of the present application are shown in the accompanying drawings. These diagrams are not drawn to scale, in which certain details are shown in a somewhat exaggerated manner for the purpose of clarity and understanding, and certain details can be omitted. The shapes of various regions, layers, and the relative sizes and positional relationships between them shown in the drawings are merely exemplary, and in actuality can be deviated due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed according to actual needs by those skilled in the art.

[0049] Referring to Figure 1 In a first aspect, the present application provides a semiconductor bonding method, comprising:

[0050] Step S1, forming a first semiconductor structure, a side surface of the first semiconductor structure having a plurality of first grooves, a first pad being formed in each of the first grooves, the first pad comprising a first magnetic conductive material layer on at least part of a groove surface of the first groove, and a first conductive layer filling a remaining space in the first groove, a magnetization intensity of the first magnetic conductive material layer being greater than a magnetization intensity of the first conductive layer, and a conductivity of the first conductive layer being greater than a conductivity of the first magnetic conductive material layer;

[0051] Step S2, forming a second semiconductor structure, a side surface of the second semiconductor structure having a plurality of second pads, a material of the second pad comprising a second magnetic conductive material, a polarity of the second magnetic conductive material being opposite to a polarity of the first magnetic conductive material;

[0052] Step S3, aligning the first pad with the second pad by using an attractive force between the first pad and the second pad;

[0053] Step S4, bonding the first semiconductor structure with the second semiconductor structure.

[0054] The first pad formed by the above semiconductor bonding method comprises a first magnetic conductive material layer and a first conductive layer, and a material of the second pad comprises a second magnetic conductive material, a polarity of the second magnetic conductive material being opposite to a polarity of the first magnetic conductive material, which makes the first pad and the second pad have an attractive ability to each other, so that the alignment of the first pad with the second pad can be achieved by using the attractive force between the first pad and the second pad. By using the above magnetic alignment method, the alignment marks formed on the surfaces of the first semiconductor structure and the second semiconductor structure can be avoided, which is beneficial to further reducing the lateral size of the semiconductor bonding structure formed.

[0055] Meanwhile, the magnetization intensity of the first magnetic conductive material layer is greater than the magnetization intensity of the first conductive layer, and the electrical conductivity of the first conductive layer is greater than the electrical conductivity of the first magnetic conductive material layer, which is conducive to the first pad having better magnetism and better electrical conductivity, and is conducive to the electrical performance of the semiconductor bonding structure.

[0056] In addition, due to the limitations of wavelength and numerical aperture, and the problem of focal plane drift, the optical alignment method is difficult to meet the requirement of accurate focusing for smaller pitch bonding pairs. However, the magnetic alignment method of the present application is conducive to meeting the requirement of accurate focusing for smaller pitch bonding pairs.

[0057] In addition, in order to ensure the bonding effect, it is usually necessary to use a polishing liquid to perform a planarization treatment on the bonding surface of the semiconductor structure between the bonding. If the magnetic material is used to form the alignment mark independent of the pad on the bonding surface of the semiconductor structure, due to the difference in materials between the alignment mark and the pad, the etching selectivity of the polishing liquid to the pad and the alignment mark is different during the planarization treatment, so that the etching degree of the polishing end point to the pad and the alignment mark is different, which may cause a void in the position of the alignment mark, and adversely affect the yield and stability of the semiconductor bonding structure.

[0058] In the present application, the first magnetic conductive material layer and the first conductive layer jointly constitute the first pad, and the first magnetic conductive material layer is formed on at least part of the groove surface of the first groove. This results in two results of the planarization treatment: one is that the first magnetic conductive material layer is completely covered by the first conductive layer and is not exposed on the bonding surface of the first semiconductor structure, so that the polishing liquid is only used to remove the first conductive layer during the planarization treatment, and no void is formed on the bonding surface due to the removal of the first magnetic conductive material layer; the other is that the edge of the first magnetic conductive material layer is exposed on the bonding surface of the first semiconductor structure, and the polishing liquid removes the first conductive layer and the first magnetic conductive material layer during the planarization treatment, so that a void may be formed at the edge of the first magnetic conductive material layer. However, since the size of the magnetic material layer exposed on the bonding surface is small, the size of the void formed is small, and the influence on the yield and stability of the semiconductor bonding structure can be ignored.

[0059] In the present application, the groove surface of the groove refers to the surface area inside the groove, which can include the groove bottom and the sidewall of the groove. The sequence of steps S1 and S2 is not limited, and step S1 can be performed first, followed by step S2, or step S2 can be performed first, followed by step S1, or steps S1 and S2 can be performed simultaneously.

[0060] The steps S1-S4 will be described in detail below.

[0061] Step S1

[0062] ReferenceFigure 2 Forming the first semiconductor structure 1 can include:

[0063] Step S11, forming a plurality of first recesses on a side surface of the first semiconductor structure 1.

[0064] For example, forming a plurality of first recesses on a side surface of the first semiconductor structure 1 can include:

[0065] Step S111, forming a first dielectric layer 13 on a side surface of the first semiconductor substrate 12.

[0066] The first dielectric layer 13 can be a low dielectric constant material, such as one or more of silicon oxide, silicon nitride, silicon carbon nitride, and silicon carbon oxide. The thickness of the first dielectric layer 13 can be 50 nm to 3 μm, such as 50 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1500 nm, 2000 nm, 2500 nm, 3000 nm, or any range between any two of the aforementioned values, and is preferably 500 nm to 1 μm. The first dielectric layer 13 can be formed using a chemical vapor deposition (such as PECVD) process.

[0067] The first semiconductor substrate 12 includes a first interconnection structure, and the first dielectric layer 13 can be formed on a side of the first interconnection structure. The first interconnection structure includes a first vertical interconnection structure 121 (such as a through-silicon via, TSV) and / or a first horizontal interconnection structure 122 (such as a redistribution structure), and the first pad 11 is electrically connected to the first interconnection structure.

[0068] The first semiconductor substrate 12 can also include at least one first device (not shown), and the first device is electrically connected to the first interconnection structure. The function of the first semiconductor structure 1 corresponds to the function of the first device.

[0069] Step S112, performing a patterning process on the first dielectric layer 13 to obtain a plurality of first through-holes penetrating the first dielectric layer 13, and the first through-holes constitute the first recesses in the first semiconductor structure 1. For example, a photoresist layer can be coated on a side surface of the first dielectric layer 13 facing away from the first semiconductor substrate 12. The formed photoresist layer is sequentially subjected to exposure and development to transfer the pattern of the first pad 11 to the photoresist layer. The first dielectric layer 13 is etched using the photoresist layer as a mask to form the first through-holes. The photoresist layer is removed.

[0070] Step S12, forming a first magnetic conductive material layer 111 on at least part of the groove surface of the first groove, and forming a first conductive layer 112 in the remaining space of the first groove, and magnetizing the first magnetic conductive material layer by using a first magnetic field.

[0071] The first magnetic conductive material layer can be magnetized by using a first magnetic field after the first magnetic conductive material layer is formed and before the first conductive layer is formed, or the first magnetic conductive material layer can be magnetized by using a first magnetic field after the first conductive layer is formed. Preferably, the first magnetic conductive material layer is magnetized by using a first magnetic field after the first magnetic conductive material layer is formed and before the first conductive layer is formed, which is beneficial to obtain a good magnetization effect.

[0072] In an embodiment, step S12 can include:

[0073] Step S121, forming a first initial magnetic conductive material layer on the groove surface of the first groove and the side surface of the first dielectric layer 13 away from the first semiconductor substrate 12, the thickness of the first initial magnetic conductive material layer being less than the depth of the first groove; the first initial magnetic conductive material layer can be formed by electrochemistry, electroplating, physical vapor deposition (PVD) or the like.

[0074] Step S122, forming a first initial conductive layer on the side surface of the first initial magnetic conductive material layer away from the first semiconductor substrate 12, the sum of the thicknesses of the first initial magnetic conductive material layer and the first initial conductive layer being greater than or equal to the depth of the first groove.

[0075] The first initial conductive layer can be formed by the following steps: forming a first seed layer on the side surface of the first initial magnetic conductive material layer away from the first semiconductor substrate 12 by using a physical vapor deposition (PVD) or atomic layer deposition (ALD) process, the thickness of the first seed layer being 10 nm-50 nm, such as 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm or any range formed by the above values; depositing a first conductive material on the side surface of the first seed layer away from the first semiconductor substrate 12 by using an electroplating process until the first groove is filled, the first seed layer and the first conductive material constituting the first initial conductive layer.

[0076] Step S123, performing a planarization process on the first initial magnetic conductive material layer and the first initial conductive layer, removing the first initial magnetic conductive material layer and the first initial conductive layer outside the first recess, the first pad 11 obtained is flush or substantially flush with the side surface of the first dielectric layer 13 away from the first semiconductor substrate 12, and the first magnetic conductive material layer 111 is formed on the entire groove surface of the first recess. The planarization process can be performed by chemical mechanical polishing (CMP). The first initial magnetic conductive material layer can be magnetized by a first magnetic field after the first initial magnetic conductive material layer is formed and before the first initial conductive layer is formed; or the first magnetic conductive material layer formed can be magnetized by a first magnetic field after the planarization process.

[0077] In another embodiment, step S12 can include:

[0078] Step S121', forming a first initial magnetic conductive material layer on the groove surface of the first recess and the side surface of the first dielectric layer 13 away from the first semiconductor substrate 12, the thickness of the first initial magnetic conductive material layer being less than the depth of the first recess; the first initial magnetic conductive material layer can be formed by electrochemistry, electroplating, physical vapor deposition (PVD), etc.

[0079] Step S122', patterning the first initial magnetic conductive material layer to form the first magnetic conductive material layer 111 on part of the groove surface of the first recess; for example, photoresist can be coated on the side surface of the first initial magnetic conductive material layer away from the first semiconductor substrate 12; the formed photoresist layer is sequentially subjected to exposure and development to transfer the pattern of the first magnetic conductive material layer 111 to the photoresist layer; etching the first initial magnetic conductive material layer with the photoresist layer as a mask, retaining the first magnetic conductive material only on part of the groove surface of the first recess, removing the first magnetic conductive material outside the part of the groove surface; removing the photoresist layer.

[0080] Step S123', forming a first initial conductive layer on the side surface of the first dielectric layer 13 away from the first semiconductor substrate 12, the first initial conductive layer extending into the first recess and covering the first magnetic conductive material layer 111, the sum of the thicknesses of the first magnetic conductive material layer 111 and the first initial conductive layer being greater than or equal to the depth of the first recess.

[0081] The first initial conductive layer can be formed by the following steps: forming a first seed layer on the side surface of the first dielectric layer 13 away from the first semiconductor substrate 12 by a physical vapor deposition (PVD) or atomic layer deposition (ALD) process, the first seed layer extending into the first recess and covering the first magnetic conductive material layer 111; and depositing a first conductive material on the side surface of the first seed layer away from the first semiconductor substrate 12 by an electroplating process until the first recess is filled, the first seed layer and the first conductive material constituting the first initial conductive layer.

[0082] In step S124', the first initial conductive layer is planarized to remove the first initial conductive layer outside the first recess, the resulting first pad 11 being flush or substantially flush with the side surface of the first dielectric layer 13 away from the first semiconductor substrate 12, and the first magnetic conductive material layer 111 being formed in part of the surface of the first recess. The planarization can be performed by chemical mechanical polishing (CMP). The first magnetic conductive material layer can be magnetized by a first magnetic field after being patterned to obtain the first magnetic conductive material layer and before forming the first initial conductive layer; or the first magnetic conductive material layer can be magnetized by a first magnetic field after the planarization.

[0083] Specifically, the ratio of the thickness of the first magnetic conductive material layer 111 to the depth of the first recess in step S12 can be 1:(3-100), such as 1:100, 1:90, 1:80, 1:70, 1:60, 1:50, 1:40, 1:30, 1:20, 1:10, 1:5, 1:3, etc., or a range consisting of any of the above values. By limiting the ratio of the thickness of the first magnetic conductive material layer 111 to the depth of the first recess to the above range, the first pad 11 has good magnetic properties and good electrical conductivity. The ratio of the thickness of the first magnetic conductive material layer to the depth of the first recess is preferably 1:(25-50).

[0084] Illustratively, the thickness of the first magnetic conductive material layer 111 can be 10-100 nm, such as 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc., or a range consisting of any of the above values, and the thickness of the first magnetic conductive material layer 111 is preferably 20-50 nm. The depth of the first recess can be 500 nm-1 μm, such as 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, etc., or a range consisting of any of the above values.

[0085] The material of the first magnetic conductive material layer 111 includes, but is not limited to, one or more of cobalt, nickel, cobalt-nickel alloy, iron-cobalt alloy, and other magnetic materials, and the above-mentioned magnetic materials can be nanowires; the material of the first conductive layer 112 includes, but is not limited to, one or more of copper, tungsten, and molybdenum.

[0086] In step S1, forming the first semiconductor structure 1 can further include:

[0087] In step S115, before forming the first magnetic conductive material layer 111 on at least part of the groove surface of the first recess, a first barrier layer (not shown) is formed on the groove surface of the first recess, and the first barrier layer has a first opening located in at least part of the area of the groove bottom of the first recess. Specifically, the first barrier layer is formed before forming the first initial magnetic conductive material layer on the groove surface of the first recess and the side surface of the first dielectric layer 13 away from the first semiconductor substrate 12. The first barrier layer is used to prevent the material of the first pad 11 from diffusing into the first dielectric layer 13 or the first semiconductor substrate 12 to adversely affect the function of the first semiconductor structure 1, and to enhance the adhesion of the first pad 11 to the first dielectric layer 13, while ensuring electrical connection between the first pad 11 and the first interconnection structure. The material of the first barrier layer includes, but is not limited to, one or more of titanium nitride, tantalum nitride, and tantalum; the thickness of the first barrier layer can be 5 nm-30 nm, such as 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, or a range consisting of any of the above values.

[0088] Forming the first barrier layer can include the following steps: using a physical vapor deposition (such as magnetron sputtering, vacuum evaporation) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process to form a first initial barrier layer on the groove surface of the first recess and the side surface of the first dielectric layer 13 away from the first semiconductor substrate 12; coating photoresist on the side surface of the first initial barrier layer away from the first semiconductor substrate 12; sequentially exposing and developing the formed photoresist layer to transfer the pattern of the first barrier layer to the photoresist layer; etching the first initial barrier layer with the photoresist layer as a mask to remove the first barrier material on the side surface of the first dielectric layer 13 away from the first semiconductor substrate 12 and at the first opening, forming the first barrier layer; and removing the photoresist layer.

[0089] Step S2

[0090] Forming the second semiconductor structure 2 can include:

[0091] In step S21, a plurality of second recesses are formed on the side surface of the second semiconductor structure 2;

[0092] In step S22, referring to Figure 3In at least part of the groove surface of the second groove, a second magnetic conductive material layer 211 is formed, and in the remaining space of the second groove, a second conductive layer 212 is formed. The second magnetic conductive material layer 211 is magnetized by a second magnetic field, and the magnetization intensity of the second magnetic conductive material layer 211 is greater than the magnetization intensity of the second conductive layer 212. The electrical conductivity of the second conductive layer 212 is greater than the electrical conductivity of the second magnetic conductive material layer 211. Alternatively, Figure 4 In all the space in the second groove, the second magnetic conductive material is filled, and the second magnetic conductive material is magnetized by a second magnetic field, and the direction of the second magnetic field is opposite to that of the first magnetic field.

[0093] The second magnetic conductive material layer 211 and the second conductive layer 212 jointly constitute the second pad 21, and the second magnetic conductive material layer 211 is formed in at least part of the groove surface of the second groove. This makes the planarization process produce two results: one is that the second magnetic conductive material layer 211 is completely covered by the second conductive layer 212 and is not exposed on the bonding surface of the second semiconductor structure 2. Therefore, during the planarization process, the abrasive liquid is only used to remove the second conductive layer 212, and the second magnetic conductive material layer 211 is not removed, so that no cavity is formed on the bonding surface. The other is that the edge of the second magnetic conductive material layer 211 is exposed on the bonding surface of the second semiconductor structure 2. During the planarization process, the abrasive liquid is used to remove the second conductive layer 212 and the second magnetic conductive material layer 211, so that a cavity may be formed at the edge of the second magnetic conductive material layer 211. However, since the size of the magnetic material layer exposed on the bonding surface is small, the size of the cavity formed is also small, and the influence of the cavity on the yield and stability of the semiconductor bonding structure can be ignored.

[0094] All the space in the second groove is filled with the second magnetic conductive material, and the second magnetic conductive material constitutes the second pad 21. During the planarization process, the abrasive liquid is only used to remove the second magnetic conductive material, so that the risk of forming a cavity on the bonding surface can also be reduced.

[0095] The second magnetic conductive material layer can be magnetized by a second magnetic field after the second magnetic conductive material layer is formed and before the second conductive layer is formed. Alternatively, the second magnetic conductive material layer can be magnetized by a second magnetic field after the second conductive layer is formed. Preferably, the second magnetic conductive material layer is magnetized by a second magnetic field after the second magnetic conductive material layer is formed and before the second conductive layer is formed, which is beneficial to obtaining a good magnetization effect.

[0096] In step S21, forming a plurality of second grooves on one side surface of the second semiconductor structure 2 can include:

[0097] Step S211, forming a second dielectric layer 23 on one side surface of the second semiconductor substrate 22;

[0098] The material of the second dielectric layer 23 can be a low dielectric constant material, such as one or more of silicon oxide, silicon nitride, silicon carbon nitride, silicon carbon oxide; the thickness of the second dielectric layer 23 can be 50 nm-3 μm, such as 50 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1500 nm, 2000 nm, 2500 nm, 3000 nm, etc., or a range consisting of any of the above values, and is preferably 500 nm-1 μm; the second dielectric layer 23 can be formed by a chemical vapor deposition (such as PECVD) process.

[0099] The second semiconductor substrate 22 includes a second interconnection structure, and the second dielectric layer 23 can be formed on one side of the second interconnection structure. The second interconnection structure includes a second vertical interconnection structure 221 (such as a through-silicon via TSV) and / or a second horizontal interconnection structure 222 (such as a redistribution structure), and the second pad 21 is electrically connected to the second interconnection structure.

[0100] The second semiconductor substrate 22 can further include at least one second device (not shown), which is electrically connected to the second interconnection structure, and the function of the second semiconductor structure 2 corresponds to the function of the second device.

[0101] Step S212, performing a patterning process on the second dielectric layer 23 to obtain a plurality of second through holes penetrating through the second dielectric layer 23, and the second through holes constitute a second recess in the second semiconductor structure 2. For example, a photoresist can be coated on the side surface of the second dielectric layer 23 away from the second semiconductor substrate 22; the formed photoresist layer is sequentially subjected to exposure and development to transfer the pattern of the second pad 21 to the photoresist layer; the second dielectric layer 23 is etched with the photoresist layer as a mask to form the second through hole; and the photoresist layer is removed.

[0102] Reference Figure 3 In an embodiment, step S22 can include:

[0103] Step S221, forming a second initial magnetic conductive material layer on the groove surface of the second recess and the side surface of the second dielectric layer 23 away from the second semiconductor substrate 22, and the thickness of the second initial magnetic conductive material layer is less than the depth of the second recess; the second initial magnetic conductive material layer can be formed by an electrochemical, electroplating, physical vapor deposition (PVD) or the like process.

[0104] Step S222, forming a second initial conductive layer on the side surface of the second initial magnetic conductive material layer away from the second semiconductor substrate 22, the sum of the thicknesses of the second initial magnetic conductive material layer and the second initial conductive layer being greater than or equal to the depth of the second groove;

[0105] The second initial conductive layer can be formed by the following steps: forming a second seed layer on the side surface of the second initial magnetic conductive material layer away from the second semiconductor substrate 22 by a physical vapor deposition (PVD) process, the thickness of the second seed layer being 10 nm-50 nm, such as 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, or a range derived from any of the above values; and depositing a second conductive material on the side surface of the second seed layer away from the second semiconductor substrate 22 by an electroplating process until the second groove is filled, the second seed layer and the second conductive material constituting the second initial conductive layer.

[0106] Step S223, performing a planarization process on the second initial magnetic conductive material layer and the second initial conductive layer to remove the second initial magnetic conductive material layer and the second initial conductive layer outside the second groove, the obtained second pad 21 being flush or substantially flush with the side surface of the second dielectric layer 23 away from the second semiconductor substrate 22, and the second magnetic conductive material layer 211 being formed on the entire groove surface of the second groove. The planarization process can be performed by chemical mechanical polishing (CMP). The second initial magnetic conductive material layer can be magnetized by a second magnetic field after the second initial magnetic conductive material layer is formed and before the second initial conductive layer is formed; or the formed second magnetic conductive material layer can be magnetized by a second magnetic field after the planarization process.

[0107] Reference Figure 3 In another embodiment, step S22 can include:

[0108] Step S221', forming a second initial magnetic conductive material layer on the groove surface of the second groove and the side surface of the second dielectric layer 23 away from the second semiconductor substrate 22, the thickness of the second initial magnetic conductive material layer being less than the depth of the second groove; the second initial magnetic conductive material layer can be formed by electrochemistry, electroplating, physical vapor deposition (PVD), etc.

[0109] Step S222', the second initial magnetic conductive material layer is patterned to form the second magnetic conductive material layer 211 on the partial groove surface of the second groove; for example, photoresist can be coated on the side surface of the second initial magnetic conductive material layer away from the second semiconductor substrate 22; the formed photoresist layer is subjected to exposure and development in sequence to transfer the pattern of the second magnetic conductive material layer 211 to the photoresist layer; the second initial magnetic conductive material layer is etched with the photoresist layer as a mask, only the second magnetic conductive material on the partial groove surface of the second groove is reserved, and the second magnetic conductive material outside the partial groove surface is removed; and the photoresist layer is removed.

[0110] Step S223', a second initial conductive layer is formed on the side surface of the second dielectric layer 23 away from the second semiconductor substrate 22, the second initial conductive layer extends into the second groove and covers the second magnetic conductive material layer 211, and the sum of the thicknesses of the second magnetic conductive material layer 211 and the second initial conductive layer is greater than or equal to the depth of the second groove.

[0111] The second initial conductive layer can be formed by the following steps: a second seed layer is formed on the side surface of the second dielectric layer 23 away from the second semiconductor substrate 22 by a physical vapor deposition (PVD) process, the second seed layer extends into the second groove and covers the second magnetic conductive material layer 211; and a second conductive material is deposited on the side surface of the second seed layer away from the second semiconductor substrate 22 by an electroplating process until the second groove is filled, and the second seed layer and the second conductive material constitute the second initial conductive layer.

[0112] Step S224', the second initial conductive layer is subjected to a planarization treatment to remove the second initial conductive layer outside the second groove, the obtained second pad 21 is flush or substantially flush with the side surface of the second dielectric layer 23 away from the second semiconductor substrate 22, and the second magnetic conductive material layer 211 is formed on the partial area of the groove surface of the second groove. The planarization treatment can be performed by chemical mechanical polishing (CMP). The second magnetic conductive material layer can be magnetized by a second magnetic field after the second initial magnetic conductive material layer is patterned to obtain the second magnetic conductive material layer and before the second initial conductive layer is formed; or the second magnetic conductive material layer can be magnetized by a second magnetic field after the planarization treatment.

[0113] Reference Figure 4 In still another embodiment, step S22 can include:

[0114] Step S221”, a second initial magnetic conductive material layer is formed on the side surface of the second dielectric layer 23 facing away from the second semiconductor substrate 22 and the groove surface of the second groove, and the thickness of the second initial magnetic conductive material layer is greater than or equal to the depth of the second groove; the second initial magnetic conductive material layer can be formed by electrochemistry, electroplating, physical vapor deposition (PVD), etc.

[0115] Step S222”, the second initial magnetic conductive material layer is planarized to remove the second initial magnetic conductive material layer outside the second groove, and the obtained second pad 21 is flush or substantially flush with the side surface of the second dielectric layer 23 facing away from the second semiconductor substrate 22. Chemical mechanical polishing (CMP) can be used for planarization.

[0116] Step S223”, the second magnetic conductive material is magnetized by a second magnetic field.

[0117] Specifically, the ratio of the thickness of the second magnetic conductive material layer 211 to the depth of the second groove in step S22 can be 1:(3-100), such as 1:100, 1:90, 1:80, 1:70, 1:60, 1:50, 1:40, 1:30, 1:20, 1:10, 1:5, 1:3, etc., or a range consisting of any of the above values. By limiting the ratio of the thickness of the second magnetic conductive material layer 211 to the depth of the second groove to the above range, the second pad 21 has good magnetic properties and good electrical conductivity. The ratio of the thickness of the second magnetic conductive material layer to the depth of the second groove is preferably 1:(25-50).

[0118] For example, the thickness of the second magnetic conductive material layer can be 10nm-100nm, such as 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc., or a range consisting of any of the above values, and the thickness of the second magnetic conductive material layer is preferably 20nm-50nm. The depth of the second groove can be 500nm-1μm, such as 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, etc., or a range consisting of any of the above values.

[0119] The second magnetic conductive material includes but is not limited to one or more of cobalt, nickel, cobalt-nickel alloy, iron-cobalt alloy, etc. The above magnetic material can be a nanowire. The material of the second conductive layer 212 includes but is not limited to one or more of copper, tungsten, molybdenum.

[0120] In step S2, forming the second semiconductor structure 2 can further include:

[0121] Step S215, before forming the second magnetic conductive material layer 211 on at least part of the groove surface of the second groove, a second barrier layer (not shown) is formed on the groove surface of the second groove, the second barrier layer has a second opening on at least part of the area of the groove bottom of the second groove. Specifically, the second barrier layer is formed before forming the second initial magnetic conductive material layer on the groove surface of the second groove and the side surface of the second dielectric layer 23 away from the second semiconductor substrate 22. The second barrier layer is used to prevent the material of the second pad 21 from diffusing into the second dielectric layer 23 or the second semiconductor substrate 22 to adversely affect the function of the second semiconductor structure 2, and to enhance the adhesion of the second pad 21 and the second dielectric layer 23, while ensuring that the second pad 21 is electrically connected to the second interconnection structure. The material of the second barrier layer includes but is not limited to one or more of titanium nitride, tantalum nitride, and tantalum; the thickness of the second barrier layer can be 5nm-30nm, such as 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, etc., or a range consisting of any of the above values.

[0122] Forming the second barrier layer can include the following steps: using a physical vapor deposition (such as magnetron sputtering, vacuum evaporation) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process to form a second initial barrier layer on the groove surface of the second groove and the side surface of the second dielectric layer 23 away from the second semiconductor substrate 22; coating photoresist on the side surface of the second initial barrier layer away from the second semiconductor substrate 22; sequentially exposing and developing the formed photoresist layer to transfer the pattern of the second barrier layer to the photoresist layer; etching the second initial barrier layer with the photoresist layer as a mask to remove the second barrier material on the side surface of the second dielectric layer 23 away from the second semiconductor substrate 22 and at the second opening, forming the second barrier layer; and removing the photoresist layer.

[0123] Step S3

[0124] In some optional embodiments, referring to Figure 5 The first pad 11 and the second pad 21 can be aligned directly using the attractive force between the first pad 11 and the second pad 21.

[0125] In another alternative embodiment, the semiconductor bonding method further comprises: before the first pad 11 is aligned with the second pad 21 by using the attractive force between the first pad 11 and the second pad 21, the first pad 11 and the second pad 21 are coarsely aligned by using an optical alignment process. That is, the optical alignment process is used for coarse alignment, and then the first pad 11 and the second pad 21 are finely aligned by using the attractive force between the first pad 11 and the second pad 21, so as to effectively realize the alignment of the corresponding pads in the first semiconductor structure 1 and the second semiconductor structure 2, and effectively avoid the short circuit and series connection of the circuit after bonding caused by the misalignment of the pads. Since the optical alignment process does not have high accuracy requirement for alignment, the semiconductor structure does not need to form an alignment mark, and the image or signal of the pad is obtained by using an optical system to perform the alignment operation.

[0126] Optionally, before the first pad 11 and the second pad 21 are aligned, the first semiconductor structure 1 and the second semiconductor structure 2 can also be subjected to surface pretreatment to remove contaminants on the bonding surface. For example, the bonding surface is treated by using plasma (such as argon or hydrogen plasma); and the pad surface oxide layer is removed by reduction treatment.

[0127] Step S4

[0128] In an alternative embodiment, the first semiconductor structure 1 comprises a first dielectric layer 13 located on one side surface of a first semiconductor substrate 12, and a plurality of first through holes in the first dielectric layer 13 form first grooves in the first semiconductor structure 1; the second semiconductor structure 2 comprises a second dielectric layer 23 located on one side surface of a second semiconductor substrate 22, and a plurality of second through holes in the second dielectric layer 23 form second grooves in the second semiconductor structure 2; and the bonding of the first semiconductor structure 1 and the second semiconductor structure 2 comprises:

[0129] Step S41, the first semiconductor structure 1 and the second semiconductor structure 2 are subjected to first compression treatment, so that the first dielectric layer 13 and the second dielectric layer 23 are preliminarily combined by intermolecular force; the temperature of the first compression treatment can be less than 200°C.

[0130] Step S42, the first semiconductor structure 1 and the second semiconductor structure 2 are subjected to second compression treatment, the temperature of the second compression treatment is greater than that of the first compression treatment, alloying occurs at the interface of the first pad 11 and the second pad 21, and the first dielectric layer 13 and the second dielectric layer 23 are combined by covalent bond, so as to obtain higher bonding strength by the synergistic effect of metal bonding and dielectric bonding. The temperature of the second compression treatment can be 300°C-400°C. After the first semiconductor structure 1 and the second semiconductor structure 2 are bonded, a semiconductor structure 3 is obtainedFigure 6 or Figure 7 the semiconductor bonding structure shown in the figure.

[0131] The bonding of the first semiconductor structure 1 and the second semiconductor structure 2 in step S4 is mainly used to connect the first pad 11 and the second pad 21 to realize the direct electrical connection of the semiconductor structure. Therefore, the bonding mode of the first semiconductor structure 1 and the second semiconductor structure 2 includes but is not limited to the bonding mode described in steps S41-S42, and other bonding modes that can realize the connection of the first pad 11 and the second pad 21 are also applicable.

[0132] The semiconductor bonding method provided by the application has simple process and very good realizability, and can be applied to a computing chip (such as a CPU or a GPU) or a storage chip to realize three-dimensional stacking.

[0133] Reference Figure 7 In a second aspect, the application provides a semiconductor bonding structure, comprising a first semiconductor structure 1 and a second semiconductor structure 2; one side surface of the first semiconductor structure 1 is provided with a plurality of first grooves, and a first pad 11 is arranged in the first grooves; the first pad 11 comprises a first magnetic conductive material layer 111 located on at least part of the groove surface of the first groove, and a first conductive layer 112 filling the remaining space in the first groove; the magnetization intensity of the first magnetic conductive material layer 111 is greater than that of the first conductive layer 112, and the electrical conductivity of the first conductive layer 112 is greater than that of the first magnetic conductive material layer 111; one side surface of the second semiconductor structure 2 is provided with a plurality of second pads 21, and the material of the second pad 21 comprises a second magnetic conductive material; the polarity of the second magnetic conductive material is opposite to that of the first magnetic conductive material; the first semiconductor structure 1 and the second semiconductor structure 2 are oppositely arranged and bonded, and the first pad 11 and the second pad 21 are oppositely arranged and bonded.

[0134] Optionally, the first magnetic conductive material layer 111 is located at least at the groove bottom of the first groove.

[0135] It should be noted that when the first groove has no other functional layer except the first magnetic conductive material layer 111 and the first conductive layer 112, the "remaining space in the first groove" corresponds to the space in the first groove except the first magnetic conductive material; when the first groove has other functional layers in addition to the first magnetic conductive material layer 111 and the first conductive layer 112, the "remaining space in the first groove" corresponds to the space in the first groove except the first magnetic conductive material and other functional layers. That is, the meaning of "remaining space in the first groove" in the application is not limited to the space in the first groove except the first magnetic conductive material.

[0136] In an alternative embodiment, referring to Figure 6 , the side surface of the second semiconductor structure 2 has a plurality of second grooves, the second pad 21 comprises a second magnetic conductive material layer 211 located on at least part of the groove surface of the second grooves, and a second conductive layer 212 filling the remaining space in the second grooves, the magnetization intensity of the second magnetic conductive material layer 211 is greater than that of the second conductive layer 212, and the electrical conductivity of the second conductive layer 212 is greater than that of the second magnetic conductive material layer 211. Optionally, the second magnetic conductive material layer 211 is located at least on the groove bottom of the second grooves.

[0137] In another alternative embodiment, referring to Figure 7 , the second pad 21 is composed of a second magnetic conductive material filling all the space of the second grooves. The first pad 11 and the second pad 21 are bonded, that is, the second conductive layer 212 or the second magnetic conductive material is bonded with the first conductive layer 112.

[0138] It should be noted that the features and effects described for the semiconductor bonding method are also applicable to the semiconductor bonding structure, which will not be described again.

[0139] In a third aspect, the present application provides a packaging structure comprising the semiconductor bonding structure obtained by the semiconductor bonding method of the first aspect or the semiconductor bonding structure of the second aspect.

[0140] In the description of the present application, the description of the terms "the present embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present description, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, different embodiments or examples described in the present description and the features of different embodiments or examples can be combined and combined by those skilled in the art without contradiction. In addition, the terms "first", "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0141] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, etc. of the desired shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0142] The above are only the preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described above, and those skilled in the art can make various obvious changes, re-adjustments, mutual combinations and substitutions without departing from the scope of protection of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of protection of the present application is determined by the scope of the appended claims.

Claims

1. A semiconductor bonding method, characterized in that, include: A first semiconductor structure is formed, wherein one side surface of the first semiconductor structure has a plurality of first grooves, and a first pad is formed in the first groove. The first pad includes a first magnetic conductive material layer located on at least a portion of the groove surface of the first groove, and a first conductive layer filling the remaining space in the first groove. The magnetization intensity of the first magnetic conductive material layer is greater than the magnetization intensity of the first conductive layer, and the conductivity of the first conductive layer is greater than the conductivity of the first magnetic conductive material layer. A second semiconductor structure is formed, and a plurality of second pads are formed on one side surface of the second semiconductor structure. The material of the second pads includes a second magnetically conductive material, and the polarity of the second magnetically conductive material is opposite to that of the first magnetically conductive material. Align the first pad and the second pad using the attraction between them; The first semiconductor structure is bonded to the second semiconductor structure.

2. The semiconductor bonding method according to claim 1, characterized in that, The formation of the first semiconductor structure includes: forming a plurality of first grooves located on one side surface of the first semiconductor structure; forming a first magnetically conductive material layer on at least a portion of the groove surface of the first grooves; forming a first conductive layer in the remaining space of the first grooves; and magnetizing the first magnetically conductive material layer using a first magnetic field; and / or, The formation of the second semiconductor structure includes: forming a plurality of second grooves located on one side surface of the second semiconductor structure; forming a second magnetically conductive material layer on at least a portion of the groove surface of the second grooves; forming a second conductive layer in the remaining space of the second grooves; magnetizing the second magnetically conductive material layer using a second magnetic field, wherein the magnetization intensity of the second magnetically conductive material layer is greater than the magnetization intensity of the second conductive layer, and the conductivity of the second conductive layer is greater than the conductivity of the second magnetically conductive material layer; or, filling the entire space within the second grooves with the second magnetically conductive material; magnetizing the second magnetically conductive material using a second magnetic field, wherein the direction of the second magnetic field is opposite to that of the first magnetic field. Preferably, the first magnetic conductive material layer is magnetized using a first magnetic field after the first magnetic conductive material layer is formed and before the first conductive layer is formed; and / or, the second magnetic conductive material layer is magnetized using a second magnetic field after the second magnetic conductive material layer is formed and before the second conductive layer is formed. Preferably, the first magnetically conductive material layer is located at least at the bottom of the first groove; and / or, the second magnetically conductive material layer is located at least at the bottom of the second groove.

3. The semiconductor bonding method according to claim 2, characterized in that, One or more of the following conditions must be met: The material of the first magnetically conductive material layer includes one or more of cobalt, nickel, cobalt-nickel alloy, and iron-cobalt alloy; The second magnetic conductive material includes one or more of cobalt, nickel, cobalt-nickel alloy, and iron-cobalt alloy; The material of the first conductive layer includes one or more of copper, tungsten, and molybdenum; The material of the second conductive layer includes one or more of copper, tungsten, and molybdenum; The ratio of the thickness of the first magnetic conductive material layer to the depth of the first groove is 1:(3-100); The ratio of the thickness of the second magnetic conductive material layer to the depth of the second groove is 1:(3-100).

4. The semiconductor bonding method according to claim 2, characterized in that, The formation of a plurality of first grooves located on one side surface of the first semiconductor structure includes: forming a first dielectric layer on one side surface of the first semiconductor substrate; and patterning the first dielectric layer to obtain a plurality of first vias penetrating the first dielectric layer, wherein the first vias constitute the first grooves in the first semiconductor structure. Preferably, forming a first magnetically conductive material layer on at least a portion of the groove surface of the first groove and forming a first conductive layer in the remaining space of the first groove includes: forming a first initial magnetically conductive material layer on the groove surface of the first groove and on the side of the first dielectric layer facing away from the first semiconductor substrate, wherein the thickness of the first initial magnetically conductive material layer is less than the depth of the first groove; forming a first initial conductive layer on the side of the first initial magnetically conductive material layer facing away from the first semiconductor substrate, wherein the sum of the thicknesses of the first initial magnetically conductive material layer and the first initial conductive layer is greater than or equal to the depth of the first groove; and planarizing the first initial magnetically conductive material layer and the first initial conductive layer, thereby removing the first initial magnetically conductive material layer and the first initial conductive layer located outside the first groove. Preferably, forming a first magnetically conductive material layer on at least a portion of the groove surface of the first groove and forming a first conductive layer in the remaining space of the first groove includes: forming a first initial magnetically conductive material layer on the groove surface of the first groove and on the side surface of the first dielectric layer opposite to the first semiconductor substrate, wherein the thickness of the first initial magnetically conductive material layer is less than the depth of the first groove; patterning the first initial magnetically conductive material layer to form the first magnetically conductive material layer on a portion of the groove surface of the first groove; forming a first initial conductive layer on the side surface of the first dielectric layer opposite to the first semiconductor substrate, wherein the first initial conductive layer extends into the first groove and covers the first magnetically conductive material layer, wherein the sum of the thicknesses of the first magnetically conductive material layer and the first initial conductive layer is greater than or equal to the depth of the first groove; and planarizing the first initial conductive layer to remove the first initial conductive layer located outside the first groove. Preferably, the formation of the first semiconductor structure further includes: forming a first barrier layer on the surface of the first groove before forming a first magnetically conductive material layer on at least a portion of the groove surface of the first groove, the first barrier layer having a first opening located in at least a portion of the bottom of the first groove.

5. The semiconductor bonding method according to claim 2, characterized in that, The method of forming a plurality of second grooves located on one side surface of the second semiconductor structure includes: forming a second dielectric layer on one side surface of the second semiconductor substrate; and patterning the second dielectric layer to obtain a plurality of second vias penetrating the second dielectric layer, wherein the second vias constitute the second grooves in the second semiconductor structure. Preferably, forming a second magnetically conductive material layer on at least a portion of the groove surface of the second groove, and forming a second conductive layer in the remaining space of the second groove, includes: A second initial magnetic conductive material layer is formed on the groove surface of the second groove and on the side of the second dielectric layer opposite to the second semiconductor substrate, wherein the thickness of the second initial magnetic conductive material layer is less than the depth of the second groove. A second initial conductive layer is formed on the surface of the second initial magnetic conductive material layer away from the second semiconductor substrate, and the sum of the thicknesses of the second initial magnetic conductive material layer and the second initial conductive layer is greater than or equal to the depth of the second groove; the second initial magnetic conductive material layer and the second initial conductive layer are planarized, and the second initial magnetic conductive material layer and the second initial conductive layer located outside the second groove are removed; Preferably, forming a second magnetically conductive material layer on at least a portion of the groove surface of the second groove and forming a second conductive layer in the remaining space of the second groove includes: forming a second initial magnetically conductive material layer on the groove surface of the second groove and on the side of the second dielectric layer facing away from the second semiconductor substrate, wherein the thickness of the second initial magnetically conductive material layer is less than the depth of the second groove; patterning the second initial magnetically conductive material layer to form the second magnetically conductive material layer on a portion of the groove surface of the second groove; forming a second initial conductive layer on the side of the second dielectric layer facing away from the second semiconductor substrate, wherein the second initial conductive layer extends into the second groove and covers the second magnetically conductive material layer, wherein the sum of the thicknesses of the second magnetically conductive material layer and the second initial conductive layer is greater than or equal to the depth of the second groove; and planarizing the second initial conductive layer to remove the second initial conductive layer located outside the second groove. Preferably, filling the entire space within the second groove with a second magnetically conductive material includes: forming a second initial magnetically conductive material layer on the groove surface of the second groove and on the side of the second dielectric layer facing away from the second semiconductor substrate, wherein the thickness of the second initial magnetically conductive material layer is greater than or equal to the depth of the second groove; planarizing the second initial magnetically conductive material layer; and removing the second initial magnetically conductive material layer located outside the second groove. Preferably, the formation of the second semiconductor structure further includes: forming a second barrier layer on the surface of the second groove before forming a second magnetically conductive material layer on at least a portion of the groove surface of the second groove, the second barrier layer having a second opening located in at least a portion of the bottom of the second groove.

6. The semiconductor bonding method according to claim 1, characterized in that, Also includes: Before aligning the first pad and the second pad using the attraction between them, a coarse alignment process is used to align the first pad and the second pad.

7. The semiconductor bonding method according to claim 1, characterized in that, The formation of a plurality of first grooves located on one side surface of the first semiconductor structure includes: forming a first dielectric layer on one side surface of the first semiconductor substrate; and patterning the first dielectric layer to obtain a plurality of first vias penetrating the first dielectric layer, wherein the first vias constitute the first grooves in the first semiconductor structure. The method of forming a plurality of second grooves located on one side surface of the second semiconductor structure includes: forming a second dielectric layer on one side surface of the second semiconductor substrate; and patterning the second dielectric layer to obtain a plurality of second vias penetrating the second dielectric layer, wherein the second vias constitute the second grooves in the second semiconductor structure. The bonding of the first semiconductor structure to the second semiconductor structure includes: The first semiconductor structure and the second semiconductor structure are subjected to a first pressing process, so that the first dielectric layer and the second dielectric layer are initially bonded together by intermolecular forces. The first semiconductor structure and the second semiconductor structure are subjected to a second lamination process, the temperature of the second lamination process being higher than the temperature of the first lamination process, so that alloying occurs at the interface between the first pad and the second pad, and the first dielectric layer and the second dielectric layer are bonded by covalent bonds.

8. A semiconductor bonding structure, characterized in that, include: A first semiconductor structure has a plurality of first grooves on one side surface. A first pad is disposed in the first groove. The first pad includes a first magnetic conductive material layer located on at least a portion of the groove surface of the first groove and a first conductive layer filling the remaining space in the first groove. The magnetization intensity of the first magnetic conductive material layer is greater than the magnetization intensity of the first conductive layer, and the conductivity of the first conductive layer is greater than the conductivity of the first magnetic conductive material layer. A second semiconductor structure has a plurality of second pads disposed on one side surface of the second semiconductor structure. The material of the second pads includes a second magnetically conductive material, and the polarity of the second magnetically conductive material is opposite to that of the first magnetically conductive material. The first semiconductor structure and the second semiconductor structure are disposed opposite to each other and bonded together, and the first pad and the second pad are disposed opposite to each other and bonded together.

9. The semiconductor bonding structure according to claim 8, characterized in that, The second semiconductor structure has a plurality of second grooves on one side surface. The second pad includes a second magnetic conductive material layer located on at least a portion of the groove surface of the second groove, and a second conductive layer filling the remaining space in the second groove. The magnetization of the second magnetic conductive material layer is greater than the magnetization of the second conductive layer, and the conductivity of the second conductive layer is greater than the conductivity of the second magnetic conductive material layer. Alternatively, the second pad is composed of a second magnetic conductive material that fills the entire space of the second groove.

10. A packaging structure, characterized in that, The semiconductor bonding structure obtained by the semiconductor bonding method according to any one of claims 1-7 or the semiconductor bonding structure according to claim 8 or 9.

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