Surface treatment method of protective sealing cover for wafer level packaging

Abstract

The invention discloses a surface treatment method for a protective sealing cover of wafer level packaging. The surface treatment method comprises the following steps of S1, performing flatness optimization treatment on the surface of the protective sealing cover; s2, the surface roughness of the protective sealing cover is regulated and controlled; s3, carrying out optimization treatment on a thermal interface of the protective sealing cover; s4, designing a laser sensitive interface layer of the protective sealing cover; s5, the optical performance of the surface of the protective sealing cover is regulated and controlled; s6, a mechanical weakening structure is arranged; and S7, performing thermal management optimization. According to the surface treatment process for the protective sealing cover for wafer level packaging, the problem that the sealing cover possibly blocks light rays from entering or affects the sensitivity of the sensor can be effectively solved, meanwhile, through the multi-dimensional surface engineering scheme, on the premise that an existing packaging structure is not changed, a laser debonding process window can be enlarged by 2-3 times, and the yield of the sensor is improved. And meanwhile, the risk of thermal mechanical damage to the chip is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wafer level packaging protective cover processing, in particular to a wafer level packaging protective cover surface treatment method. BACKGROUND

[0002] Wafer level packaging generally needs to perform interconnection processes on the back of the wafer, including thinning, grinding, etching and cutting processes, which can easily damage the front area of the wafer. Therefore, before wafer level packaging, a protective cover such as a glass is bonded to the front of the wafer, which serves to protect the front of the wafer and provide a load for subsequent grinding and cutting processes.

[0003] For the current wafer level packaging protective cover, a common problem is that it has a large negative impact on the chip, such as the bonding process before the cover, and the cover may hinder the light from entering or affect the sensitivity of the sensor, thereby affecting the normal working ability of the chip. In the final process of packaging, the die and the cover need to be separated, but due to the high laser energy, direct irradiation to the high-sensitivity sensing area will cause irreparable damage. Therefore, when debonding, the area of the cover with glue needs to be able to transmit laser, while protecting the sensing area from the influence of laser.

[0004] Therefore, in order to correct the above-mentioned defects, we propose a wafer level packaging protective cover surface treatment method. SUMMARY

[0005] The present application solves the technical problem of providing a wafer level packaging protective cover surface treatment method.

[0006] To achieve the above-mentioned purpose, the present application provides the following technical scheme: a wafer level packaging protective cover surface treatment method, comprising the following steps:

[0007] S1, performing flatness optimization treatment on the surface of the protective cover;

[0008] S2, performing protective cover surface roughness control;

[0009] S3, performing thermal interface optimization treatment on the protective cover;

[0010] S4, designing a laser-sensitive interface layer for the protective cover;

[0011] S5, performing surface optical performance control treatment on the protective cover;

[0012] S6, setting a mechanical weakening structure;

[0013] S7, performing thermal management optimization.

[0014] Further, in the step S1, the crystal flatness optimization process adopts one of chemical mechanical polishing and local laser planarization.

[0015] Further, in the step S2, the surface roughness regulation adopts dry treatment and wet treatment.

[0016] Further, in the step S3, the thermal interface optimization process includes a metallized coating and a thermally conductive filler coating.

[0017] The metallized coating: sputtering Ti / Ni / Ag multilayer structure on the surface of the protective cover, then embedding the copper column in the cover for direct connection with the heat sink, wherein Ti is an adhesion layer and Ag is a high thermal conductivity layer.

[0018] The thermally conductive filler coating: spraying epoxy resin containing nanodiamond or boron nitride (BN).

[0019] Further, in the step S4, the laser-sensitive interface layer is designed to introduce a material sensitive to laser response at the bonding interface, and the laser-sensitive interface layer includes a light-absorbing conversion layer and a thermal decomposition type adhesive layer.

[0020] Further, the light-absorbing conversion layer: depositing a laser-absorbing material between the cover and the chip, the laser-absorbing material being one of TiN, Ta, and carbon nanotube film.

[0021] The thermal decomposition type adhesive layer adopts one of an adhesive containing azobenzene or a metal-organic framework.

[0022] Further, in the step S5, the surface optical performance regulation process is to set a gradient refractive index coating on the outer surface of the cover, and then set a laser anti-reflection microstructure.

[0023] The gradient refractive index coating is a SiO2 / TiO2 gradient refractive index prepared on the outer surface of the cover.

[0024] The laser anti-reflection microstructure is a moth-eye structure with a period of 600 nm and a height of 200 nm.

[0025] Further, in the step S6, the mechanical weakening structure is a micro-crack network made by laser stealth cutting on the edge of the cover, the crack depth is controlled at 20-30% of the thickness of the cover, and then 10-20 vol% hollow glass microspheres with a diameter of 5-10 μm are implanted in the bonding glue.

[0026] Further, in the step S7, the thermal management optimization includes setting a thermal barrier layer on the surface of the cover and setting a micro heat dissipation channel in the cover.

[0027] Further, the thermal barrier layer is an AlN thermal insulation layer, and the micro heat dissipation channel is a copper micro column array with a diameter of 50 microns integrated in the cover.

[0028] Compared with the prior art, the surface treatment process of the protective cover of the wafer-level package in the application can effectively solve the problem that the cover may hinder the light from entering or affect the sensitivity of the sensor, and through the multi-dimensional surface engineering scheme, the laser debonding process window can be expanded by 2-3 times without changing the existing packaging structure, and the risk of thermal mechanical damage to the chip is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 The figure is a process flow diagram of the application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the application.

[0031] The application provides a technical solution:

[0032] Please refer to Figure 1 A surface treatment method of a protective cover of a wafer-level package, comprising the following steps:

[0033] S1, performing flatness optimization treatment on the surface of the protective cover;

[0034] S2, performing protective cover surface roughness control;

[0035] S3, performing thermal interface optimization treatment on the protective cover;

[0036] S4, designing a laser sensitive interface layer of the protective cover;

[0037] S5, performing surface optical performance control treatment on the protective cover;

[0038] S6, setting a mechanical weakening structure;

[0039] S7, performing thermal management optimization.

[0040] Among the above, flatness optimization can reduce interfacial thermal resistance and improve bonding quality. Chemical mechanical polishing (CMP) can be used for silicon / glass cover, and the surface roughness can be controlled to <1 nm. The polishing liquid formula needs to be optimized (such as SiO2 slurry for silicon and CeO2 for glass). Local laser flattening can also be used to repair micro-protrusions of metal covers (such as copper) and avoid bonding cavities.

[0041] After processing, the surface morphology is monitored by white light interferometer (WLI) or atomic force microscope (AFM).

[0042] Protective cover surface roughness regulation is used to balance adhesion and signal loss;

[0043] Increase adhesion:

[0044] Dry treatment: oxygen plasma or nitrogen plasma bombardment (increase surface energy, suitable for organic cover).

[0045] Wet treatment: HF solution (glass cover) or alkaline etching (silicon cover) to form a micron-level rough structure.

[0046] Reduce signal loss:

[0047] Super smooth surface (after CMP + low damage cleaning) reduces high-frequency signal transmission loss (suitable for RF packaging).

[0048] Thermal interface optimization processing can maximize the improvement of heat dissipation efficiency, which includes:

[0049] Metalized coating:

[0050] Silicon cover surface sputtering Ti / Ni / Ag multilayer structure (Ti as adhesion layer, Ag as high thermal conductivity layer).

[0051] Electroplated copper pillar (Cu pillar) embedded in cover, directly connected to heat sink.

[0052] Thermal conductive filler coating:

[0053] Spray epoxy resin containing nanodiamond or boron nitride (BN) with thermal conductivity >5 W / mK.

[0054] After processing, infrared thermal imager can be used to measure interfacial thermal resistance (TIM test) for verification.

[0055] Among the above, the laser-sensitive interface layer of the protective cover is designed, and the core strategy is to introduce a material sensitive to laser response at the bonding interface, which is:

[0056] Light absorption conversion layer:

[0057] Depositing 50-200nm laser absorption material (such as TiN, Ta, carbon nanotube film) between the cover and the chip can increase the 1064nm laser absorption rate to more than 90%;

[0058] Process: low-temperature sputtering (<150℃) or spraying process to avoid affecting the existing structure;

[0059] Thermal decomposition type adhesive layer:

[0060] Adhesive containing azobenzene or metal organic framework (MOF);

[0061] Photothermal dissociation occurs when laser irradiation occurs, and the required energy can be reduced to 1 / 3 of the conventional epoxy resin;

[0062] The decomposition temperature can be controlled in the range of 180-220℃.

[0063] The above-mentioned surface optical performance regulation and processing of the protective cover can improve the utilization rate of laser energy, specifically:

[0064] Gradient refractive index coating:

[0065] Preparation of SiO2 / TiO2 gradient refractive index film (n=1.46→2.4) on the outer surface of the cover;

[0066] Can reduce the 1064nm laser reflectivity from 8% to 0.5%;

[0067] Process: ion beam assisted deposition (IAD), thickness accuracy ±2nm.

[0068] Laser antireflection microstructure:

[0069] Surface making moth-eye structure with a period of 600nm and a height of 200nm;

[0070] Wide band (900-1100nm) transmittance >99%;

[0071] Process: nanoimprint + reactive ion etching.

[0072] Setting mechanical weakening structure to reduce the energy required for mechanical separation, specifically:

[0073] Preset separation channel:

[0074] The cover edge is made of laser stealth dicing (Stealth Dicing) to make a microcrack network;

[0075] The crack depth is controlled at 20-30% of the cover thickness;

[0076] Can reduce the peeling force by 40-60%;

[0077] Porous interface layer:

[0078] 10-20vol% hollow glass microspheres (5-10μm in diameter) are contained in the bonding glue;

[0079] The microspheres are broken when laser irradiation, and stress concentration points are generated.

[0080] In the above, heat management optimization is performed, and the purpose is to prevent the spread of thermal damage, specifically:

[0081] Thermal barrier layer:

[0082] 100nm AlN thermal insulation layer (thermal conductivity↓80%) is arranged below the light absorption layer;

[0083] The heat-affected zone can be reduced from 200μm to 50μm;

[0084] Miniature heat dissipation channel:

[0085] A copper micro-column array with a diameter of 50μm is integrated in the cover, and the heat diffusion speed is increased by 3 times.

[0086] Although embodiments of the present application have been shown and described, it is to be understood that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for surface treatment of a protective cap of a wafer level package, characterized by: The method comprises the following steps: S1, performing flatness optimization treatment on the surface of the protective cover; S2, performing surface roughness control on the protective cover; S3, performing thermal interface optimization treatment on the protective cover; S4, designing a laser-sensitive interface layer on the protective cover; S5, performing surface optical performance control treatment on the protective cover; S6, setting a mechanical weakening structure; S7, performing thermal management optimization.

2. The surface treatment method of a protective cap of a wafer level package according to claim 1, characterized by: In the step S1, the crystal flatness optimization treatment adopts one of chemical mechanical polishing and local laser flattening.

3. The surface treatment method of a protective cap of a wafer level package according to claim 1, characterized by: In the step S2, the surface roughness control adopts dry treatment and wet treatment.

4. The surface treatment method of a protective cap of a wafer level package according to claim 1, characterized by: In the step S3, the thermal interface optimization treatment includes a metallized coating layer and a thermal conductive filler coating layer. The metallized coating layer is a Ti / Ni / Ag multilayer structure sputtered on the surface of the protective cover, and then a copper column is embedded in the cover to directly connect the heat sink, wherein Ti is an adhesion layer and Ag is a high thermal conductivity layer. The thermal conductive filler coating layer is an epoxy resin containing nanodiamond or boron nitride (BN) sprayed.

5. The surface treatment method of a protective cap of a wafer level package according to claim 1, wherein: In the step S4, the laser-sensitive interface layer is designed to introduce a material sensitive to laser response at the bonding interface, and the laser-sensitive interface layer includes a light-absorbing conversion layer and a thermal decomposition type adhesive layer.

6. The surface treatment method of a protective cap of a wafer level package according to claim 5, wherein: The light-absorbing conversion layer is a laser-absorbing material deposited between the cover and the chip, and the laser-absorbing material is one of TiN, Ta, and carbon nanotube film. The thermal decomposition type adhesive layer adopts one of an adhesive containing azobenzene or a metal-organic framework.

7. The wafer level packaged protective cover surface treatment method of claim 1, wherein: In the step S5, the surface optical performance control treatment is to set a gradient refractive index coating on the outer surface of the cover, and then set a laser anti-reflection microstructure. The gradient refractive index coating is a SiO2 / TiO2 gradient refractive index prepared on the outer surface of the cover. The laser anti-reflection microstructure is a moth-eye structure with a period of 600 nm and a height of 200 nm.

8. The wafer level packaged protective cover surface treatment method of claim 1, wherein: In the step S6, the mechanical weakening structure is a micro-crack network made by laser stealth cutting on the edge of the cover, and the crack depth is controlled at 20-30% of the thickness of the cover, and then 10-20 vol% hollow glass microspheres with a diameter of 5-10 μm are implanted in the bonding glue.

9. The wafer level packaged protective cover surface treatment method of claim 1, wherein: In the step S7, the thermal management optimization includes setting a thermal resistance layer on the surface of the cover and setting a micro heat dissipation channel in the cover.

10. The surface treatment method of a protective cap of a wafer level package according to claim 9, wherein: The thermal resistance layer is an AlN thermal resistance layer, and the micro heat dissipation channel is a copper micro column array with a diameter of 50 μm integrated in the cover.

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