Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises a semiconductor substrate, and a plurality of fin structures are formed on the surface of the semiconductor substrate; the first opening is located in the fin structure; the protection layer is located on the side wall of the first opening; the second opening is located in the fin structure at the bottom of the first opening and communicated with the first opening, the width of the second opening is larger than that of the first opening, and the first opening and the second opening form an SDB isolation groove. The invention provides a semiconductor structure and a forming method thereof, which can reduce the difficulty of an SDB process and improve the isolation performance of an SBD isolation structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the progress of semiconductor technology, the demand for higher storage capacity, faster processing system, higher performance and lower cost is increasing. In order to meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, and the design of three-dimensional structures such as FinFET has become a hot spot in the semiconductor field.

[0003] With the continuous miniaturization of devices, in order to make smaller and more densely distributed fins, new technologies for manufacturing isolation structures have also emerged, such as a manufacturing technology of single diffusion break isolation structures (SDB isolation structures). The SDB isolation structures are generally distributed along the length direction of the fins, and one or more SDB isolation trenches are formed in the fins by etching some regions of the fins, which can separate the fins into multiple small fins, thereby preventing leakage current between two adjacent fins and avoiding source-drain bridge in the fins. The manufacturing process of SDB isolation structure and its forming structure will affect the isolation performance of SDB isolation structure, and even cause defects to the fins and gate structures around it, thereby affecting the performance of FinFET device.

[0004] However, due to the small size of the SDB isolation structure, especially the narrow bottom, the insulation effect is not good. If the size is increased, the growth of the source and drain regions will be affected. Moreover, with the continuous reduction of the size, the process difficulty of the SDB increases, and the isolation effect becomes worse.

[0005] Therefore, it is necessary to provide a more effective and reliable technical solution to reduce the process difficulty of SDB and improve the isolation performance of SBD isolation structure. SUMMARY

[0006] The present application provides a semiconductor structure and a forming method thereof, which can reduce the process difficulty of SDB and improve the isolation performance of SBD isolation structure.

[0007] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate having a plurality of fin structures formed on a surface thereof; performing a first etching process to form a first opening in the fin structures; forming a protective layer on sidewalls of the first opening; and performing a second etching process to continue etching the fin structures at a bottom of the first opening along the protective layer to form a second opening, the second opening having a width greater than that of the first opening, the first opening and the second opening forming an SDB isolation trench.

[0008] In some embodiments of the present application, the first opening has a depth of 50-90% of a height of the fin structures.

[0009] In some embodiments of the present application, the second opening has a depth of 10-50% of the height of the fin structures.

[0010] In some embodiments of the present application, a ratio of the width of the first opening to that of the second opening is 1:(1-6).

[0011] In some embodiments of the present application, the protective layer has a thickness of 3-50% of the width of the first opening.

[0012] Another aspect of the present application provides a semiconductor structure, comprising: a semiconductor substrate having a plurality of fin structures formed on a surface thereof; a first opening in the fin structures; a protective layer on sidewalls of the first opening; and a second opening in the fin structures at a bottom of the first opening and in communication with the first opening, the second opening having a width greater than that of the first opening, the first opening and the second opening forming an SDB isolation trench.

[0013] In some embodiments of the present application, the first opening has a depth of 50-90% of a height of the fin structures.

[0014] In some embodiments of the present application, the second opening has a depth of 10-50% of the height of the fin structures.

[0015] In some embodiments of the present application, a ratio of the width of the first opening to that of the second opening is 1:(1-6).

[0016] In some embodiments of the present application, the protective layer has a thickness of 3-50% of the width of the first opening.

[0017] The present application provides a semiconductor structure and a method for forming the same, which can reduce the difficulty of SDB process and improve the isolation performance of SDB isolation structure. BRIEF DESCRIPTION OF DRAWINGS

[0018] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0019] in:

[0020] Figures 1 to 5 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation

[0021] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0022] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0023] Figures 1 to 5 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0024] refer to Figure 1 and Figure 2 As shown, where, Figure 1 This is a top view. Figure 2 For along Figure 1 A longitudinal cross-sectional view at the dashed line AA. A semiconductor substrate 100 is provided, and a plurality of fin structures 110 are formed on the surface of the semiconductor substrate 100.

[0025] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.

[0026] In some embodiments of this application, reference is made to Figure 1 As shown, the semiconductor substrate 100 includes mutually perpendicular x-squares and y-squares. The plurality of fin structures 110 extend along the x-direction.

[0027] In some embodiments of the present application, the fin structure 110 is integrally connected with the semiconductor substrate 100, and the fin structure 110 is formed by etching the semiconductor substrate 100.

[0028] In some embodiments of the present application, referring to Figure 2 As shown, the top surface of the fin structure 110 is further formed with a mask layer 120 and an oxide layer 130 in sequence. The mask layer 120 and the oxide layer 130 are masks for etching the semiconductor substrate 100 to form the fin structure 110. Figure 1 In some embodiments of the present application, the mask layer 120 and the oxide layer 130 are omitted for the purpose of showing the fin structure 110.

[0029] In some embodiments of the present application, the material of the mask layer 120 includes silicon nitride or the like.

[0030] In some embodiments of the present application, the material of the oxide layer 130 includes silicon oxide or the like.

[0031] Referring to Figure 3 As shown, a first etching process is performed to etch the oxide layer 130 and the mask layer 120 into the fin structure 110 to form a first opening 140 in the fin structure 110.

[0032] In some embodiments of the present application, the depth of the first opening 140 in the fin structure 110 is 50%-90%, for example, 60%, 70% or 80% of the height of the fin structure 110. Specifically, for example, the height of the fin structure 110 is 80-120 nanometers. The depth of the first opening 140 in the fin structure 110 is 40-100 nanometers.

[0033] In some embodiments of the present application, the fin structure 110 on both sides of the first opening 140 will be formed with a source region and a drain region subsequently. The depth of the first opening 140 in the fin structure 110 is greater than the depth of the source region and the drain region.

[0034] In some embodiments of the present application, the first etching process is an anisotropic dry etching process.

[0035] Referring to Figure 4 As shown, a protection layer 150 is formed on the sidewall of the first opening 140. On the one hand, the protection layer 150 protects the fin structure 110 on the sidewall of the first opening 140 from being etched subsequently; on the other hand, the protection layer 150 narrows the width of the first opening 140, increases the aspect ratio of the first opening 140, and reduces the difficulty of subsequently filling the first opening 140 to seal it.

[0036] In some embodiments of this application, the thickness of the protective layer 150 is 3%-50% of the width of the first opening 140, for example, 10%, 20%, 30%, or 40%. The thickness of the protective layer 150 is, for example, 2-4 nanometers. The width of the first opening 140 is, for example, 25 to 35 nanometers. The width refers to the horizontal dimension shown in the figures.

[0037] In some embodiments of this application, the material of the protective layer 150 includes silicon oxide.

[0038] In some embodiments of this application, the method of forming the protective layer 150 includes: depositing a protective material layer on the bottom and sidewalls of the first opening 140 and on the surface of the oxide layer 130; etching away the protective material layer located at the bottom of the first opening 140 and on the surface of the oxide layer 130; and forming the protective layer 150 on the sidewalls of the first opening 140.

[0039] refer to Figure 5 As shown, a second etching process is performed to continue etching the fin structure 110 at the bottom of the first opening 140 along the protective layer 150 to form a second opening 160. The width of the second opening 160 is greater than the width of the first opening 140. The first opening 140 and the second opening 160 constitute an SDB isolation trench 170. The SDB isolation trench 170 is used to isolate adjacent active regions.

[0040] In some embodiments of this application, the depth of the second opening 160 in the fin structure 110 is 10%-50% of the height of the fin structure 110, for example, 20%, 30%, or 40%. Specifically, for example, the depth of the second opening 160 is 10 to 50 nanometers. The depth of the SDB isolation trench 170 is the sum of the depths of the first opening 140 and the second opening 160 in the fin structure 110.

[0041] In some embodiments of this application, the ratio of the width of the first opening 140 to the width of the second opening 160 is 1:(1-6), for example, 1:1, 1:2, 1:3, 1:4, or 1:5. Specifically, for example, the width of the first opening 140 is 25 to 35 nanometers, and the width of the second opening 160 is 25 to 100 nanometers.

[0042] In some embodiments of this application, the second etching process is isotropic wet etching.

[0043] In the technical solution of this application, the SDB isolation trench 170 has a structure that is narrow at the top and wide at the bottom. Without increasing the width of the first opening 140, the isolation performance of the SDB isolation trench 170 can be improved.

[0044] In some embodiments of the present application, the method for forming the semiconductor structure further comprises: forming an SDB isolation structure in the SDB isolation trench 170.

[0045] In some embodiments of the present application, the method for forming the SDB isolation structure in the SDB isolation trench 170 comprises: filling insulating material in the SDB isolation trench 170, the insulating material in the first opening 140 and the second opening 160 collectively form the SDB isolation structure.

[0046] In some other embodiments of the present application, the method for forming the SDB isolation structure in the SDB isolation trench 170 comprises: depositing insulating material in the first opening 140, the insulating material seals the second opening 160 so that the second opening 160 is a gas gap structure. The insulating material in the first opening 140 and the gas gap structure of the second opening 160 collectively form the SDB isolation structure.

[0047] In some embodiments of the present application, the method for forming the semiconductor structure further comprises: forming a gate structure above the SDB isolation structure; forming a source region and a drain region in the fin structure 110 on both sides of the gate structure respectively. The depth of the source region and the drain region is higher than the bottom of the first opening 140.

[0048] The present application provides a method for forming a semiconductor structure, which can reduce the difficulty of SDB process and improve the isolation performance of the SDB isolation structure.

[0049] Embodiments of the present application also provide a semiconductor structure, which refers to Figure 5 as shown, comprising: a semiconductor substrate 100, a plurality of fin structures 110 are formed on the surface of the semiconductor substrate 100; a first opening 140 located in the fin structure 110; a protective layer 150 located on the sidewall of the first opening 140; a second opening 160 located in the fin structure 110 at the bottom of the first opening 140 and communicating with the first opening 140, the width of the second opening 160 is greater than the width of the first opening 140, and the first opening 140 and the second opening 160 constitute an SDB isolation trench 170.

[0050] In some embodiments of the present application, the material of the semiconductor substrate 100 comprises (i) elemental semiconductor, such as silicon or germanium, etc.; (ii) compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide, etc.; or (iv) a combination of the above.

[0051] In some embodiments of the present application, referring to Figure 1As shown, the semiconductor substrate 100 includes x direction and y direction perpendicular to each other. The fin structures 110 extend along the x direction.

[0052] In some embodiments of the present application, the fin structures 110 are integrally connected with the semiconductor substrate 100, and the fin structures 110 are formed by etching the semiconductor substrate 100.

[0053] In some embodiments of the present application, referring to Figure 5 As shown, the top surface of the fin structure 110 is further formed with a mask layer 120 and an oxide layer 130 in sequence. The mask layer 120 and the oxide layer 130 are masks for etching the semiconductor substrate 100 to form the fin structure 110.

[0054] In some embodiments of the present application, the material of the mask layer 120 includes silicon nitride or the like.

[0055] In some embodiments of the present application, the material of the oxide layer 130 includes silicon oxide or the like.

[0056] In some embodiments of the present application, the depth of the first opening 140 in the fin structure 110 is 50%-90% of the height of the fin structure 110, for example, 60%, 70% or 80%. Specifically, for example, the height of the fin structure 110 is 80-120 nanometers. The depth of the first opening 140 in the fin structure 110 is 40-100 nanometers.

[0057] In some embodiments of the present application, the fin structure 110 on both sides of the first opening 140 further includes a source region and a drain region. The depth of the first opening 140 in the fin structure 110 is greater than the depth of the source region and the drain region.

[0058] In some embodiments of the present application, the thickness of the protective layer 150 is 3%-50% of the width of the first opening 140, for example, 10%, 20%, 30% or 40%, etc. The thickness of the protective layer 150 is, for example, 2-4 nanometers. The width of the first opening 140 is, for example, 25-35 nanometers. The width refers to the horizontal dimension in the drawing.

[0059] In some embodiments of the present application, the material of the protective layer 150 includes silicon oxide.

[0060] In some embodiments of the present application, the second opening 160 has a depth in the fin structure 110 of 10-50%, for example 20%, 30% or 40%, etc. of the height of the fin structure 110. Specifically, for example, the depth of the second opening 160 is 10-50 nm. The depth of the SDB isolation trench 170 is the sum of the depths of the first opening 140 and the second opening 160 in the fin structure 110.

[0061] In some embodiments of the present application, the ratio of the width of the first opening 140 to the width of the second opening 160 is 1:(1-6), for example 1:1, 1:2, 1:3, 1:4 or 1:5, etc. Specifically, for example, the width of the first opening 140 is 25-35 nm, and the width of the second opening 160 is 25-100 nm.

[0062] In the technical solutions of the present application, the SDB isolation trench 170 has a structure of being narrow at the top and wide at the bottom, and the width of the second opening 160 can be increased without increasing the first opening 140, so as to improve the isolation performance of the SDB isolation trench 170.

[0063] In some embodiments of the present application, the semiconductor structure further comprises an SDB isolation structure in the SDB isolation trench 170.

[0064] In some embodiments of the present application, the SDB isolation structure is formed by an insulating material filled in the first opening 140 and the second opening 160.

[0065] In some other embodiments of the present application, the SDB isolation structure is formed by an insulating material filled in the first opening 140 and an air gap structure of the second opening 160.

[0066] In some embodiments of the present application, the semiconductor structure further comprises a gate structure above the SDB isolation structure, and a source region and a drain region in the fin structure 110 on both sides of the gate structure, respectively. The depths of the source region and the drain region are higher than the bottom of the first opening 140.

[0067] The present application provides a semiconductor structure and a forming method thereof, which can reduce the difficulty of SDB process and improve the isolation performance of the SDB isolation structure.

[0068] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing content of the present application can be presented only in an exemplary manner and can not be limiting. Although not explicitly stated herein, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of the present application.

[0069] It will be understood that the term "and / or," as used herein in the specification and in the claims, can connote any or all possible combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can also be present.

[0070] Similarly, it will be understood that, when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, the term "directly on" means that there are no intervening elements present. It will also be understood that the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, has, contains, contains one or more of a list of features can not only comprise, have, or contain the features but can also comprise, have, or contain additional features not expressly listed or inherent to such process, method, article, or apparatus.

[0071] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed but not necessarily described below could be later described as a second element, component, region, layer or section. The same reference numbers or symbols in the drawings represent the same elements, components, regions, layers and / or sections.

[0072] In addition, the specification of the present application describes exemplary embodiments by reference to idealized illustrative cross-sectional and / or plan and / or elevation views. Consequently, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, the exemplary embodiments should not be construed as limited to the precise shapes and regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, wherein a plurality of fin structures are formed on the surface of the semiconductor substrate; A first etching process is performed to form a first opening in the fin structure; A protective layer is formed on the sidewall of the first opening; A second etching process is performed to continue etching the fin structure at the bottom of the first opening along the protective layer to form a second opening. The width of the second opening is greater than the width of the first opening. The first opening and the second opening constitute an SDB isolation trench.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The depth of the first opening is 50%-90% of the height of the fin structure.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The depth of the second opening is 10%-50% of the height of the fin structure.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The ratio of the width of the first opening to the width of the second opening is 1:(1-6).

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the protective layer is 3%-50% of the width of the first opening.

6. A semiconductor structure, characterized in that, include: A semiconductor substrate, wherein a plurality of fin structures are formed on the surface of the semiconductor substrate; The first opening is located within the fin structure; A protective layer is located on the sidewall of the first opening; The second opening is located in the fin structure at the bottom of the first opening and communicates with the first opening. The width of the second opening is greater than the width of the first opening. The first opening and the second opening constitute an SDB isolation trench.

7. The semiconductor structure as described in claim 6, characterized in that, The depth of the first opening is 50%-90% of the height of the fin structure.

8. The semiconductor structure as described in claim 6, characterized in that, The depth of the second opening is 10%-50% of the height of the fin structure.

9. The semiconductor structure as described in claim 6, characterized in that, The ratio of the width of the first opening to the width of the second opening is 1:(1-6).

10. The semiconductor structure as described in claim 6, characterized in that, The thickness of the protective layer is 3%-50% of the width of the first opening.

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