Preparation method of semiconductor structure and stacked structure

Abstract

The embodiment of the invention provides a preparation method of a semiconductor structure and a stacked structure, and the method comprises the steps: providing a first wafer which comprises a substrate, the substrate comprises a first surface and a second surface which are opposite to each other, and a chip region and a cutting region are located on the first surface; bonding the surface of one side, far away from the substrate, of the chip area with a slide glass; performing a first thinning process on the second surface of the substrate; a first segmentation process is performed from the second surface of the substrate to form a plurality of first segmentation grooves. A second segmentation process is executed along the position of the first segmentation groove to form a second segmentation groove, the second segmentation groove penetrates through the segmentation area between the adjacent chip areas, and the first wafer is separated into a plurality of chips based on the first segmentation groove and the second segmentation groove; wherein the edge of the part, located on the substrate, of the chip deviates outwards relative to the edge of the substrate, and the included angle between the side wall of the second segmentation groove and the direction parallel to the plane of the substrate is larger than a preset value; and removing the slide glass.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and a stacking structure. Background Technology

[0002] With the development of large-scale integrated circuits, the feature size of circuits continues to shrink, and chips are evolving towards three dimensions, entering the post-Moore's Law era to meet the demands for high integration, high transmission speed, and low power consumption. The three-dimensional direction mainly includes wafer-to-wafer (W2W), chip-to-wafer (C2W), and chip-to-chip (C2C). In this context, interconnecting wafers or chips with the same or different functions offers advantages such as high performance, low cost, and high integration.

[0003] However, there are still many problems in the above process that need to be improved. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure, including:

[0005] A first wafer is provided, the first wafer including a substrate, a plurality of chip regions and a dicing region located on the substrate, the dicing region being located between adjacent chip regions, the substrate including a first surface and a second surface disposed opposite to each other, the chip regions and the dicing region being located on the first surface;

[0006] Bond the surface of the chip region away from the substrate to the carrier wafer;

[0007] A first thinning process is performed on the second surface of the substrate;

[0008] A first dicing process is performed from the second surface of the substrate to form a plurality of first dicing grooves, the first dicing grooves penetrating the substrate and exposing the location of the dicing area;

[0009] A second dicing process is performed along the location of the first dicing groove to form a second dicing groove, the second dicing groove penetrating the dicing area between adjacent chip areas, the first wafer being separated into multiple chips based on the first dicing groove and the second dicing groove; wherein, the edge of the portion of the chip located on the substrate is offset outward relative to the edge of the substrate, and the angle between the sidewall of the second dicing groove and the direction parallel to the substrate plane is greater than a preset value;

[0010] Remove the substrate.

[0011] In some embodiments, a first segmentation process is performed from the second surface of the substrate to form a plurality of first segmentation grooves, the first segmentation grooves penetrating the substrate; including:

[0012] A mask layer is formed, the mask layer covering the second surface of the substrate;

[0013] The mask layer is patterned to form a mask pattern that exposes the location of the orthographic projection of the cut area onto the substrate;

[0014] The substrate is etched using the mask pattern as a mask to form the first segmentation groove.

[0015] In some embodiments, after forming the first dividing groove, the method further includes:

[0016] Remove the mask layer and perform a first cleaning process on the remaining structure after removing the mask layer.

[0017] In some embodiments, a second segmentation process is performed along the location of the first segmentation groove to form the second segmentation groove, including:

[0018] A protective layer is formed, which at least covers the second surface of the substrate located around the first dividing groove;

[0019] The second dividing groove is formed by laser cutting. The width of the second dividing groove is smaller than the width of the first dividing groove, and the angle between the sidewall of the second dividing groove and the direction parallel to the substrate plane is greater than a preset value.

[0020] In some embodiments, a second process is performed along the location of the first dividing groove to form the second dividing groove, including:

[0021] A protective layer is formed that covers a second surface of the substrate surrounding the first dividing groove and covers the sidewalls of the first dividing groove, and exposes the middle region of the first dividing groove in the direction extending along the first dividing groove.

[0022] The second dividing groove is formed by laser cutting. The width of the second dividing groove is smaller than the width of the first dividing groove, and the angle between the sidewall of the second dividing groove and the direction parallel to the substrate plane is greater than a preset value.

[0023] In some embodiments, after forming the second dividing groove, the method further includes:

[0024] Remove the protective layer and perform a second cleaning process on the remaining structure after the protective layer has been removed.

[0025] In some embodiments, after performing the second segmentation process, the method further includes:

[0026] A second thinning process is performed on the second surface of the substrate;

[0027] A support structure is formed on the second surface of the thinned substrate.

[0028] In some embodiments, removing the carrier includes:

[0029] After the support structure is formed, the carrier located above the chip is removed.

[0030] In some embodiments, after removing the substrate, the method further includes:

[0031] The bonding surface of the chip is exposed.

[0032] This disclosure also provides a stacking structure, the stacking structure comprising:

[0033] The second wafer includes multiple chip structures, and dicing channels are provided between adjacent chip structures;

[0034] Multiple chips located on the second wafer, wherein the active surfaces of the chips are connected to the chip structure in a one-to-one correspondence, and the active surfaces are the sides of the chips where the device layer is formed;

[0035] A filler layer, the filler layer being located on the dicing area and between adjacent chips;

[0036] Wherein, the edge of the portion of the chip near the second wafer is offset outward relative to the edge of the portion of the chip away from the wafer structure, and the angle between the sidewall of the filling layer away from the second wafer portion and the direction parallel to the plane of the second wafer is greater than a preset value.

[0037] The semiconductor structure fabrication method and stacking structure disclosed herein include the following steps: providing a first wafer, the first wafer including a substrate, a plurality of chip regions and dicing regions located on the substrate, the dicing regions being located between adjacent chip regions, the substrate including a first surface and a second surface disposed opposite to each other, the chip regions and the dicing regions being located on the first surface; bonding the surface of the chip region away from the substrate to a carrier wafer; performing a first thinning process on the second surface of the substrate; performing a first dicing process from the second surface of the substrate to form a plurality of first dicing grooves, the first dicing grooves penetrating the substrate and exposing the locations of the dicing regions; performing a second dicing process along the locations of the first dicing grooves to form second dicing grooves, the second dicing grooves penetrating the dicing regions between adjacent chip regions, the first wafer being separated into a plurality of chips based on the first dicing grooves and the second dicing grooves; wherein the edges of the portions of the chips located on the substrate are offset outward relative to the edges of the substrate, and the angle between the sidewalls of the second dicing grooves and the direction parallel to the plane of the substrate is greater than a preset value; and removing the carrier wafer. In this embodiment, a first dicing process is performed on the side of the substrate where the chip area is not located, forming a relatively wide first dicing groove. Then, a second dicing process is performed based on the first dicing groove to form a relatively narrow second dicing groove. This multi-stage dicing process helps reduce the difficulty and time of dicing the structure on the substrate during the process of obtaining the chip structure from the first wafer. It also reduces the thickness and amount of protective layer and other materials used in the second dicing process, thus reducing production costs. Simultaneously, the wider first dicing groove provides a larger process window for the subsequent formation of the second dicing groove, facilitating its smooth execution. Furthermore, the narrower width of the second dicing groove compared to the first dicing groove further reduces the amount and thickness of protective layer and other materials, effectively reducing dicing difficulty and time. The larger angle between the sidewall of the second dicing groove and the substrate plane facilitates the bonding of the chip obtained from the dicing process with other structures. During the process of filling the area between adjacent chips with a material layer, this material layer exhibits good filling performance, reducing voids, holes, and other defects. In addition, performing the dicing operation on the side of the substrate where the chip area is not located and removing the carrier after the dicing process helps to remove the slag and other debris located at the bottom of the dicing groove in a timely manner, which can effectively improve the bonding quality of the bonding structure obtained based on the chip.

[0038] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and drawings. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0041] Figures 2 to 12 This is a schematic diagram of the semiconductor structure corresponding to the method for fabricating the semiconductor structure provided in the embodiments of this disclosure; wherein, Figure 7 Figure (1) is a schematic diagram of the structure during the formation of a protective layer according to an embodiment of this disclosure. Figure 7 Figure (2) is a structural schematic diagram of the process of forming a protective layer provided in another embodiment of this disclosure;

[0042] Figure 13 This is a schematic diagram of the stacked structure provided in an embodiment of the present disclosure. Detailed Implementation

[0043] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0044] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0045] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0047] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] Wafer-to-wafer bonding to achieve multi-wafer or multi-chip connectivity is a method used to increase packaging density. Before bonding, pre-processing operations are usually performed on the wafers, such as separating the wafer into multiple separate chips, and material formation operations are performed on the resulting structure after bonding. These processes are prone to contamination or poor filling, affecting the yield of the bonded structure.

[0050] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0051] This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 The preparation method includes the following steps:

[0052] Step S101: Provide a first wafer, the first wafer including a substrate, a plurality of chip regions located on the substrate and a dicing region, the dicing region being located between adjacent chip regions, the substrate including a first surface and a second surface disposed opposite to each other, the chip regions and the dicing region being located on the first surface;

[0053] Step S102: Bond the surface of the chip region away from the substrate to the carrier.

[0054] Step S103: Perform a first thinning process on the second surface of the substrate;

[0055] Step S104: Perform a first dicing process from the second surface of the substrate to form a plurality of first dicing grooves, the first dicing grooves penetrating the substrate and exposing the location of the dicing area;

[0056] Step S105: Perform a second dicing process along the location of the first dicing groove to form a second dicing groove. The second dicing groove penetrates the cutting area between adjacent chip areas. The first wafer is separated into multiple chips based on the first and second dicing grooves. The edge of the chip located on the substrate is offset outward relative to the edge of the substrate, and the angle between the sidewall of the second dicing groove and the direction parallel to the substrate plane is greater than a preset value.

[0057] Step S106: Remove the substrate.

[0058] In this embodiment, a first dicing process is performed on the side of the substrate where the chip area is not located, forming a relatively wide first dicing groove. Then, a second dicing process is performed based on the first dicing groove to form a relatively narrow second dicing groove. This multi-stage dicing process helps reduce the difficulty and time of dicing the structure on the substrate during the process of obtaining the chip structure from the first wafer. It also reduces the thickness and amount of protective layer and other materials used in the second dicing process, thus reducing production costs. Simultaneously, the wider first dicing groove provides a larger process window for the subsequent formation of the second dicing groove, facilitating its smooth execution. Furthermore, the narrower width of the second dicing groove compared to the first dicing groove further reduces the amount and thickness of protective layer and other materials, effectively reducing dicing difficulty and time. The larger angle between the sidewall of the second dicing groove and the substrate plane facilitates the bonding of the chip obtained from the dicing process with other structures. During the process of filling the area between adjacent chips with a material layer, this material layer exhibits good filling performance, reducing voids, holes, and other defects. In addition, performing the dicing operation on the side of the substrate where the chip area is not located and removing the carrier after the dicing process helps to remove the slag and other debris located at the bottom of the dicing groove in a timely manner, which can effectively improve the bonding quality of the bonding structure obtained based on the chip.

[0059] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0060] Figures 2 to 12 A schematic diagram of the semiconductor structure corresponding to the semiconductor structure fabrication method provided in this embodiment of the present disclosure; wherein... Figure 7 Figure (1) is a schematic diagram of the structure during the formation of a protective layer according to an embodiment of this disclosure. Figure 7 Figure (2) is a structural schematic diagram of the process of forming a protective layer provided in another embodiment of this disclosure.

[0061] The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0062] First, execute step S101, as follows: Figure 2As shown, a first wafer W1 is provided. The first wafer W1 includes a substrate 10, a plurality of chip regions Ca and a dicing region Q located on the substrate 10. The dicing region Q is located between adjacent chip regions Ca. The substrate 10 includes a first surface S1 and a second surface S2 disposed opposite to each other. The chip regions Ca and the dicing region Q are located on the first surface S1.

[0063] Here, the first wafer W1 can be, but is not limited to, a wafer structure with any suitable function, such as storage function, logic function, integrated circuit, etc. The substrate 10 can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor materials (e.g., silicon (Si) substrate, germanium (Ge) substrate, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In one specific embodiment, the substrate 10 is a silicon substrate.

[0064] In some embodiments, the chip region Ca further includes an interconnect structure 11, which may include interconnect lines distributed on multiple layers and via structures connecting interconnect lines of different layers.

[0065] In some embodiments, a bonding dielectric layer L1 and a bonding contact 12 are disposed above the interconnect structure 11, and the surface of the bonding dielectric layer L1 and the bonding contact 12 away from the substrate 10 can be referred to as the bonding surface S3.

[0066] In some embodiments, the material of the bonding dielectric layer may include, but is not limited to, silicon nitride or silicon carbonitride, and the material of the bonding contact 12 may include, but is not limited to, conductive metals, such as copper. Specifically, the materials can be flexibly selected according to the requirements, and no specific limitations are made here.

[0067] In some embodiments, a debonding layer L is also formed on the bonding surface S3. The debonding layer L is removed after the second segmentation process is completed. The presence of the debonding layer L ensures that the materials or tools used in the subsequent first and second segmentation processes do not directly contact the bonding surface S3, thus providing good protection for the bonding surface S3. This helps to ensure the smooth progress of the subsequent bonding process and results in a highly reliable structure after the bonding process is completed.

[0068] Next, proceed to step S102, as follows: Figure 3 As shown, the surface of the chip region Ca away from the substrate 10 is bonded to the carrier 20.

[0069] In some embodiments, the material of the carrier 20 may include, but is not limited to, silicon wafers, glass, or ceramic materials.

[0070] Understandably, during the subsequent dicing process of the first wafer W1, the process operations will begin on the second surface S2 of the substrate 10. During the process, as multiple chip regions Ca and multiple regions in the substrate 10 are separated from each other, many impurities Z will be generated (see details). Figure 8 These impurities Z may include, but are not limited to, the removed material layer such as molten metal slag (mainly slag generated from laser cutting of metal), or dielectric layer or process byproducts, or any other substances that may be generated during the execution of the splitting process, without specific limitations.

[0071] Currently, the most common wafer dicing technology involves laser cutting the front side of the wafer to obtain chips (dies). However, this process requires cutting a relatively thick layer of material, necessitating a thicker laser protective solution. Furthermore, impurities (Z) remain on the wafer surface, such as molten metal residue. Additionally, there is often "grass-like" growth at the bottom of the dicing groove (i.e., uncleaned molten metal accumulates in this area), affecting the quality of the chips obtained after dicing. If bonding is subsequently performed, this further impacts the quality of the chip-wafer bonded structure. These impurities (Z) (see [reference needed]) Figure 8 For example, molten metal slag is difficult to remove effectively even after rigorous or repeated cleaning operations.

[0072] In conventional technology, during the dicing operation of the first wafer W1, which begins on the surface of the chip region Ca, the dicing of the chip region Ca ends on the first surface S1 of the substrate. Metal slag residue is easily generated at this location. Since the substrate is usually part of the chip and supports the chip, it cannot be removed arbitrarily. This can easily lead to the phenomenon of bottom slag growth during the subsequent etching and dicing process of the substrate 10. The bottom slag may be cleaned out in subsequent processes, but it will also affect the bonding quality of the chip to the wafer (D2W) (there is a bubble).

[0073] In this embodiment, the dicing operation of the first wafer W1 begins on the surface of the substrate 10 away from the chip region Ca, and ends at the location of the carrier 20. This ensures that after the dicing operation and a series of subsequent processing operations, the aforementioned impurity Z appears on the surface of the carrier 20. Since the carrier 20 is not a necessary component of the chip obtained after dicing the first wafer W1, it can be removed after the process is complete. This allows impurities Z and the like generated during the dicing operation of the first wafer W1 to be removed along with the carrier 20, improving the quality and cleanliness of the chip obtained after dicing.

[0074] Next, proceed to step S103, as follows: Figure 4 As shown, a first thinning process is performed on the second surface S2 of the substrate 10.

[0075] In some embodiments, the first thinning process on the second surface S2 of the substrate 10 may include, but is not limited to, backside grinding and chemical mechanical polishing (CMP). This can reduce the thickness of the substrate 10 to a certain extent, thereby reducing the difficulty of the subsequent first slitting process.

[0076] In some embodiments, after performing the first thinning process, the thickness of the remaining substrate 10 can range from 40 micrometers to 110 micrometers (inclusive), such as 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, etc.

[0077] Next, proceed to step S104, as follows: Figure 5 and Figure 6 As shown, a first dicing process is performed on the second surface S2 of the substrate 10 to form a plurality of first dicing grooves T1. The first dicing grooves T1 penetrate the substrate 10 and expose the location of the dicing area Q.

[0078] In some embodiments, a first segmentation process is performed from the second surface S2 of the substrate 10 to form a plurality of first segmentation grooves T1, the first segmentation grooves T1 penetrating the substrate 10; including:

[0079] A mask layer Ma is formed, which covers the second surface S2 (not shown) of the substrate 10;

[0080] The patterned mask layer Ma is used to form a mask pattern M, which exposes the location of the orthographic projection of the cutting region Q onto the substrate 10 (see details). Figure 5 );

[0081] Using the mask pattern M as the mask, the substrate 10 is etched to form the first segmentation groove T1 (see details). Figure 6 ).

[0082] In some embodiments, the process for forming the first dividing groove T1 can be an etching process.

[0083] In some embodiments, the material of the mask layer Ma may include, but is not limited to, photoresist.

[0084] In some embodiments, the width of the mask pattern M can be between 40 micrometers and 100 micrometers (including endpoint values) along a direction perpendicular to the extension of the mask pattern M, for example, 45 micrometers, 50 micrometers, 55 micrometers, 60 micrometers, 65 micrometers, 70 micrometers, 75 micrometers, 80 micrometers, 85 micrometers, 90 micrometers, 95 micrometers, etc.

[0085] In some embodiments, after forming the first dividing groove T1, the method further includes:

[0086] Remove the mask layer Ma and perform a first cleaning process on the remaining structure after removing the mask layer Ma.

[0087] In some embodiments, an ashing process may be used to remove the mask layer Ma.

[0088] Understandably, after removing the mask layer Ma, the remaining structure, i.e. Figure 6 The structure shown helps improve the operation of the first cleaning process. Figure 6 The cleanliness of the structure shown is to prevent impurities Z such as powder, excess material cut off, or other products generated during the aforementioned process from adversely affecting subsequent processes or contaminating the final structure.

[0089] Then, proceed to step S105, as follows: Figure 8 As shown, a second dicing process is performed along the location of the first dicing groove T1 to form a second dicing groove T2. The second dicing groove T2 penetrates the cutting area Q between adjacent chip areas Ca. The first wafer W1 is separated into multiple chips C based on the first dicing groove T1 and the second dicing groove T2. The edge of the portion of chip C located on the substrate 10 is offset outward relative to the edge of the substrate 10, and the angle between the sidewall of the second dicing groove T2 and the direction parallel to the plane of the substrate 10 is greater than a preset value.

[0090] Here, the angle between the sidewall of the second dividing groove T2 and the direction parallel to the plane of the substrate 10 is greater than a preset value. This can also be understood as the angle between the edge of the part of the chip C located on the substrate 10 and the direction parallel to the plane of the substrate 10 is greater than a preset value.

[0091] In some embodiments, the size range of the second dividing groove T2 perpendicular to the extension direction, i.e. the width range, can be between 30 micrometers and 80 micrometers (including the endpoint values), for example, 35 micrometers, 40 micrometers, 45 micrometers, 50 micrometers, 55 micrometers, 60 micrometers, 65 micrometers, 70 micrometers, 75 micrometers, etc.

[0092] In some embodiments, the width ratio of the first dividing groove T1 to the second dividing groove T2 can be between 1.33 and 3.6 (including the endpoint values), such as 1.375, 1.5, 1.7, 1.8, 2, 2.2, 2.5, 2.8, 3, 3.2, 3.5, etc.

[0093] Understandably, the outward offset of the edge of the portion of chip C on substrate 10 relative to the edge of substrate 10 means that the width of the second dividing groove T2 has a certain degree of abrupt change compared to the width of the first dividing groove T1. This reduction in the width of the second dividing groove T2 can, on the one hand, reduce the thickness and amount of materials such as protective layers used in the second dividing process, thus helping to reduce production costs. Simultaneously, the wider first dividing groove T1 provides a larger process window for the subsequent formation of the second dividing groove T2, facilitating its smooth execution. Furthermore, the smaller width of the second dividing groove T2 compared to the first dividing groove T1 helps to further reduce the amount and thickness of materials such as protective layers, effectively reducing dividing difficulty and time, and resulting in a larger numerical angle between the sidewall of the second dividing groove T2 and the plane of substrate 10.

[0094] In some embodiments, the angle between the sidewall of the second dividing groove T2 and the direction parallel to the plane of the substrate 10 is greater than a preset setting. This may include an angle greater than 70°, such as 75°, 80°, 85°, 90°, etc. It can also be understood that in the structure of the second dividing groove T2, if the width difference between the surface away from the substrate 10 and the surface close to the substrate 10 is small, the filling effect of the filling layer between adjacent chips C during the bonding process will not be affected by the large difference between the two.

[0095] In some embodiments, such as Figure 7 Figure (1) in the middle and Figure 8 As shown, a second dividing process is performed along the position of the first dividing groove T1 to form the second dividing groove T2, including:

[0096] A protective layer P is formed, which at least covers the second surface S2 of the substrate 10 located around the first dividing groove T1;

[0097] The second dividing groove T2 is formed by laser cutting. The width of the second dividing groove T2 is smaller than the width of the first dividing groove T1, and the angle between the sidewall of the second dividing groove T2 and the direction parallel to the plane of the substrate 10 is greater than a preset value.

[0098] In this embodiment, the presence of the protective layer P can provide the necessary protection or encapsulate the substances generated during the laser cutting process, while also providing a larger process window for the execution of the second segmentation process.

[0099] In other embodiments, such as Figure 7 Figure (2) in the middle and Figure 8 As shown, a second process is performed along the location of the first dividing groove T1 to form the second dividing groove T2, including:

[0100] A protective layer P is formed, which covers the second surface S2 of the substrate 10 located around the first dividing groove T1 and covers the sidewall of the first dividing groove T1. In the direction extending along the first dividing groove T1, the protective layer P exposes the middle region of the first dividing groove T1.

[0101] The second dividing groove T2 is formed by laser cutting. The width of the second dividing groove T2 is smaller than the width of the first dividing groove T1, and the angle between the sidewall of the second dividing groove T2 and the direction parallel to the plane of the substrate 10 is greater than a preset value.

[0102] In this embodiment, the presence of the protective layer P provides the necessary protection or encapsulates the substances generated during the laser cutting process. It also provides a certain degree of coverage to the sidewalls of the substrate exposed by the first dividing groove T1. This helps to reduce the adhesion and residue of metal slag, by-products, or other materials generated during the laser cutting process around the substrate. This helps to obtain a chip structure with higher cleanliness after the subsequent removal of the protective layer P or the cleaning process, thereby improving the quality and reliability of the bonded structure obtained after bonding with other structures.

[0103] In some embodiments, the material of the protective layer P may include, but is not limited to, a laser protective liquid. The laser protective liquid helps to protect the wafer surface circuit from laser ablation or plasma sputtering contamination during the second dicing process. Secondly, it controls the thermal effect during the cutting process. Thirdly, it assists in debris management, that is, it wraps around the metal slag or other materials removed at the cutting position during the laser cutting process.

[0104] In some embodiments, the thickness of the protective layer P can be less than 5 micrometers, such as 2 micrometers, 3 micrometers, 3.5 micrometers, 4 micrometers, and 4.5 micrometers.

[0105] Compared to the embodiment of this disclosure, where an etching operation is first used to form the first dividing groove T1, and then a laser cutting operation is used to cut a thinner material layer to form the second dividing groove T2, the conventional process first performs a laser cutting process on the side where the chip area is located to form a cutting groove that stops on the first surface of the substrate, and then performs the substrate cutting operation. The entire cutting process is completed under the protection of the laser protective fluid. The thickness of the laser cutting operation in conventional technology is relatively large, and the thickness of the laser protective fluid required is also relatively large, usually in the range of greater than 10 micrometers. This not only increases the material cost of the laser protective fluid (a thicker laser protective fluid is required to protect the bonding interface, resulting in high consumable costs) and the coating time, but also, because the laser protective fluid is thicker, the metal slag and other materials generated during the cutting process are more likely to be encapsulated in the laser protective fluid, making it difficult to remove the impurities generated during the cutting process even after subsequent cleaning operations. Slag residue may remain on the surface, affecting the D2W bonding quality (creating a bubble).

[0106] In addition, during the chip dicing process in conventional processes, there is a high probability that there will be residual metal slag at the bottom of the laser grooving, which is the first surface of the substrate. When the silicon substrate is etched later, it may cause the phenomenon of "grass growing at the bottom". This can be understood as these residual metal and other materials re-attaching and accumulating at the bottom and near the dicing groove. These materials (grass growing at the bottom) may be cleaned out in subsequent processes, which will also have a certain impact on the D2W bonding quality (the presence of a bubble).

[0107] Furthermore, in conventional processes, due to the relatively thick thickness requiring laser cutting, the dicing groove at the initial cutting position may have a large width. However, as the cutting depth increases, the width of the dicing groove at the bottom of the cutting position decreases to some extent compared to the initial dicing groove width. This phenomenon becomes more pronounced with increasing cutting depth. In some cases, the angle between the sidewall of the dicing groove and the substrate plane on the resulting chip after the cutting process may be small, such as less than 70°. This small angle can lead to poor filling of the gaps between the chips after die-to-wafer (D2W) bonding, resulting in incomplete filling such as voids, thus affecting the integrity and reliability of the final bonded structure.

[0108] In some embodiments, after forming the second dividing groove T2, the method further includes:

[0109] The protective layer P is removed, and a second cleaning process is performed on the remaining structure after the protective layer P is removed.

[0110] In some embodiments, such as Figure 10 As shown, after performing the second segmentation process, the method further includes:

[0111] A second thinning process is performed on the second surface S2 of the substrate 10;

[0112] A support structure 30 is formed on the second surface S2 of the thinned substrate 10.

[0113] In some embodiments, the process operation of performing the second thinning process on the second surface S2 of the substrate 10 may include, but is not limited to, buffer chemical mechanical polishing (Buffer CMP) and wet cleaning processes.

[0114] In some embodiments, the thickness of the substrate 10 removed after the second thinning process is completed is between 5 and 10 μm (inclusive), for example, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, 9.5 μm, etc.

[0115] In some embodiments, after the second thinning process is completed, the thickness of the remaining substrate 10 is between 35 and 100 μm (including the endpoint values), for example, 40 μm, 45 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, etc.

[0116] In some embodiments, the presence of the support structure 30 allows the chips C obtained after the second dicing process to maintain or closely approximate their original relative positions before dicing, even after the carrier 20 is removed, so that they do not become scattered after the carrier 20 is removed.

[0117] Finally, proceed with step S106, as follows: Figure 11 As shown, remove slide 20.

[0118] In some embodiments, removing the carrier 20 includes:

[0119] After the support structure 30 is formed, the carrier 20 located above the chip is removed.

[0120] Understandably, in this embodiment, performing the dicing operation on the first wafer W1 in two stages, with the first dicing operation not being a laser process, effectively reduces the cutting thickness when using a laser process for dicing. Furthermore, the addition of a first cleaning process between the two dicing operations significantly reduces the adhesion or aggregation of impurities Z. Further, the second thinning process on the substrate 10 in the previous step, followed by wet cleaning, and the removal of the carrier 20 in this step allow these multiple settings to work together to reduce or prevent the residue of impurities Z, such as molten metal slag. Specifically, the second thinning process on the substrate 10 effectively removes impurities Z, such as molten metal slag, located on the opposite side of the carrier 20. The subsequent wet cleaning removes any locations in the structure where impurities Z, such as molten metal slag, might remain. The operation on the carrier 20 effectively removes impurities Z, such as molten metal slag, located at the bottom of the second dicing groove T2 at the end of the second dicing operation. As can be seen, in this embodiment of the disclosure, multiple operation methods and steps work together to form an inseparable whole, so that the final obtained chip C can have high cleanliness and good reliability.

[0121] In some embodiments, such as Figure 12 As shown, after removing the carrier 20, the method further includes:

[0122] Remove the debonding layer L to expose the bonding surface of chip C.

[0123] In some embodiments, the removal of the unbonding layer L can be performed using a laser process.

[0124] In some embodiments, after removing the unbonding layer L, the preparation method further includes:

[0125] A third cleaning process is performed to achieve a high level of cleanliness in the chip.

[0126] This disclosure also provides a stacking structure, such as Figure 13 As shown, the stacking structure includes:

[0127] The second wafer W2 includes multiple chip structures C1, and a dicing channel Q1 is provided between adjacent chip structures C1.

[0128] Multiple chips C are located on the second wafer W2. The active surface of chip C (the side of the chip where the device layer is formed) is connected to chip structure C1 in a one-to-one correspondence. The active surface is the side of chip C where the device layer is formed.

[0129] Filling layer L2 is located on the dicing channel area Q1 and between adjacent chips C;

[0130] In this case, the edge of the portion of chip C near the second wafer W2 is offset outward relative to the edge of the portion of chip C away from the wafer structure, and the angle between the sidewall of the portion of the filling layer away from the second wafer W2 and the direction parallel to the plane of the second wafer W2 is greater than a preset value.

[0131] In some embodiments, the second wafer W2 includes a connection structure layer 21 and a contact structure 22. The connection structure layer 21 includes multiple interconnect layers and via structures connecting the multiple interconnect layers. The contact structure 22 is located on the connection structure layer 21 and connected to bonding contacts in the chip C.

[0132] In some embodiments, chip C may be manufactured using the methods provided in any of the above embodiments.

[0133] Because the chip C obtained in the method provided in this embodiment has a high degree of cleanliness. Meanwhile, the edge of the portion of chip C located on substrate 10 is offset outward relative to the edge of substrate 10, and the angle between the edge of the portion of chip C located on substrate 10 and the direction parallel to the plane of substrate 10 is greater than a preset value. This setting allows the filling layer L2, which fills the space between adjacent chips C after chip C is bonded to chip structure C1 in the second wafer W2, to have a good contact interface with the surrounding chips C. This results in a sidewall morphology that is essentially consistent with the edge morphology of chip C, and a filling effect where voids and holes are virtually non-existent in the region within the filling layer L2. This helps to improve the bonding quality and reliability of the final bonded structure.

[0134] The technical features described in the embodiments provided in this disclosure can be arbitrarily combined without conflict.

[0135] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A first wafer is provided, the first wafer including a substrate, a plurality of chip regions and a dicing region located on the substrate, the dicing region being located between adjacent chip regions, the substrate including a first surface and a second surface disposed opposite to each other, the chip regions and the dicing region being located on the first surface; Bond the surface of the chip region away from the substrate to the carrier wafer; A first thinning process is performed on the second surface of the substrate; A first dicing process is performed from the second surface of the substrate to form a plurality of first dicing grooves, the first dicing grooves penetrating the substrate and exposing the location of the dicing area; A second dicing process is performed along the location of the first dicing groove to form a second dicing groove, the second dicing groove penetrating the dicing area between adjacent chip areas, the first wafer being separated into multiple chips based on the first dicing groove and the second dicing groove; wherein, the edge of the portion of the chip located on the substrate is offset outward relative to the edge of the substrate, and the angle between the sidewall of the second dicing groove and the direction parallel to the substrate plane is greater than a preset value; Remove the substrate.

2. The method according to claim 1, characterized in that, A first segmentation process is performed from the second surface of the substrate to form a plurality of first segmentation grooves, the first segmentation grooves penetrating the substrate; including: A mask layer is formed, the mask layer covering the second surface of the substrate; The mask layer is patterned to form a mask pattern that exposes the location of the orthographic projection of the cut area onto the substrate; The substrate is etched using the mask pattern as a mask to form the first segmentation groove.

3. The method according to claim 2, characterized in that, After forming the first dividing groove, the method further includes: Remove the mask layer and perform a first cleaning process on the remaining structure after removing the mask layer.

4. The method according to claim 1, characterized in that, Performing a second segmentation process along the location of the first segmentation groove to form the second segmentation groove includes: A protective layer is formed, which at least covers the second surface of the substrate located around the first dividing groove; The second dividing groove is formed by laser cutting. The width of the second dividing groove is smaller than the width of the first dividing groove, and the angle between the sidewall of the second dividing groove and the direction parallel to the substrate plane is greater than a preset value.

5. The method according to claim 1, characterized in that, Performing a second process along the location of the first dividing groove to form the second dividing groove includes: A protective layer is formed that covers a second surface of the substrate surrounding the first dividing groove and covers the sidewalls of the first dividing groove, and exposes the middle region of the first dividing groove in the direction extending along the first dividing groove. The second dividing groove is formed by laser cutting. The width of the second dividing groove is smaller than the width of the first dividing groove, and the angle between the sidewall of the second dividing groove and the direction parallel to the substrate plane is greater than a preset value.

6. The method according to claim 4 or 5, characterized in that, After forming the second dividing groove, the method further includes: Remove the protective layer and perform a second cleaning process on the remaining structure after the protective layer has been removed.

7. The method according to any one of claims 1-5, characterized in that, After performing the second segmentation process, the method further includes: A second thinning process is performed on the second surface of the substrate; A support structure is formed on the second surface of the thinned substrate.

8. The method according to claim 7, characterized in that, Removing the substrate includes: After the support structure is formed, the carrier located above the chip is removed.

9. The method according to claim 8, characterized in that, After removing the substrate, the method further includes: The bonding surface of the chip is exposed.

10. A stacked structure, characterized in that, The stacked structure includes: The second wafer includes multiple chip structures, and dicing channels are provided between adjacent chip structures; Multiple chips located on the second wafer, wherein the active surfaces of the chips are connected to the chip structure in a one-to-one correspondence, and the active surfaces are the sides of the chips where the device layer is formed; A filler layer, the filler layer being located on the dicing area and between adjacent chips; Wherein, the edge of the portion of the chip near the second wafer is offset outward relative to the edge of the portion of the chip away from the wafer structure, and the angle between the sidewall of the filling layer away from the second wafer portion and the direction parallel to the plane of the second wafer is greater than a preset value.

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